JP4556747B2 - Software defined radio communication device and hardware design language program - Google Patents

Description

  The present invention relates to a software defined radio communication device and a hardware design language program.

  Conventionally, a wireless device is configured using a dedicated IC called an ASIC (Application Specific Integrated Circuit). Since this is dedicated to a specific communication method, downsizing, low power consumption, and cost reduction are possible. However, in order to cope with different communication methods, a plurality of wireless devices are required for each communication method, leading to an increase in size, power consumption, and cost. Moreover, in order to cope with a new communication system, a separate radio is required, and flexibility is also lacking.

  For such a problem, there is a technique called “software radio” (see, for example, Non-Patent Documents 1 and 2). This is a technique in which wireless processing is described by software and can be changed according to a user's request. A DSP (Digital Signal Processor) or an FPGA (Field Programmable Gate Array) is used as a device to be mounted on the software defined radio arithmetic processing unit. According to the FPGA, each processing unit is realized by executing a hardware design language program using an installed processor. Therefore, the function change of the processing unit to support a new communication method or a plurality of communication methods can be handled only by changing the program.

  FIG. 1 is a functional configuration diagram of a software defined radio arithmetic processing unit in the prior art.

  The software radio processing unit 1 in FIG. 1 processes a mobile phone IF (intermediate frequency) signal and a wireless LAN IF signal. For this purpose, the software defined radio processing unit 1 includes a mobile phone module 11 and a wireless LAN module 12. The mobile phone module 11 includes an ADC (Analog Digital Converter) unit 111 for a mobile phone IF signal, a filter unit 112, a despreading unit 113, a PN code generation unit 114, a demodulation unit 115, a deinterleaver, Unit 116, descrambling unit 117, and error correction decoding unit 118. On the other hand, the wireless LAN module 12 includes an ADC unit 121 for a wireless LAN IF signal, a filter unit 122, a despreading unit 123, a PN code generation unit 124, a demodulation unit 125, and a descrambling unit 127. Have Data output from the ADC unit is continuous, and the processing unit sequentially processes the continuous data. As described above, the software radio communication apparatus according to the related art constitutes a module according to the radio frequency band to be processed.

Araki Junmichi, “Software Radio”, IEICE Journal, Vol. 83, no. 3, pp. 183-190, March 2000 Joe Mitola, “The Software Radio Architecture”, IEEE Communications Magazine, Vol. 33, no. 5, pp 26-38, May 1995

  According to the prior art in FIG. 1, each module has the same arithmetic processing unit for each communication method. This means that a plurality of the same logic gate groups are provided in one software-defined radio arithmetic processing unit, and resources are wasted.

  On the other hand, when signal processing of different communication methods is actually assumed, the processing itself is often similar even if there is a difference in parameters. In addition, the flow of signal processing can be limited to some extent by limiting the communication system to be implemented to some extent.

  Therefore, an object of the present invention is to provide a software defined radio communication device and a hardware design language program that can increase the use efficiency of the number of logic gates.

According to the present invention, a software defined radio apparatus having a software defined radio operation processing unit,
For each different type of radio frequency band that is input, a packet configuration means for generating a packet that includes the type identifier in the header;
A plurality of modules having an arithmetic processing unit and a header determination unit that switches whether the packet is processed and output by the arithmetic processing unit or output without processing according to an identifier included in the header of the input packet; ,
A packet disassembling means for outputting only the data of the packet at an output port corresponding to the identifier included in the header of the packet;
The plurality of modules are connected in one direction.

According to another embodiment of the software defined radio of the present invention,
The header determination means can be switched to further discard the packet according to the identifier included in the packet header,
It is also preferable that some of the modules are connected in parallel.

According to another embodiment of the software defined radio apparatus of the present invention,
When the module outputs a packet, output switching means for switching whether the packet is finally output as a software radio arithmetic processing unit or output to the next module according to the identifier included in the header of the packet Further comprising
It is also preferable that the plurality of modules are connected in a ring shape.

  Furthermore, according to another embodiment of the software defined radio apparatus of the present invention, the software defined radio operation processing unit is preferably an FPGA.

According to the present invention, there is provided a hardware design language program in a software radio arithmetic processing unit configured by an FPGA,
For each different type of radio frequency band that is input, a packet configuration means for generating a packet that includes the type identifier in the header;
A plurality of modules having an arithmetic processing unit and a header determination unit that switches whether the packet is processed and output by the arithmetic processing unit or output without processing according to an identifier included in the header of the input packet; ,
Causing the FPGA to function as a packet disassembling means for outputting only the data of the packet to the output port corresponding to the identifier included in the header of the packet;
The plurality of modules make the FPGA function so as to be connected in one direction.

According to another embodiment of the hardware design language program of the present invention,
The header determination means causes the FPGA to switch to further discard the packet according to the identifier included in the header of the packet,
It is also preferable for the FPGA to function so that a plurality of modules are connected in parallel in part.

According to another embodiment of the hardware design language program of the present invention,
When the module outputs a packet, output switching means for switching whether the packet is finally output as a software radio arithmetic processing unit or output to the next module according to the identifier included in the header of the packet To make the FPGA work,
It is also preferable that the FPGA functions so that the plurality of modules are connected in a ring shape.

  According to the present invention, since the same arithmetic processing unit can be shared in different radio frequency bands, the use efficiency of the number of logic gates can be increased as compared with the prior art. Further, according to the present invention, since the modules are basically connected in one direction, switching between the modules is not necessary, and the operation delay can be reduced.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a first functional configuration diagram of a module according to the present invention.

  A “module” refers to an arithmetic processing block that processes a signal. The module 2 in the present invention inputs a packet composed of a header and data, and outputs a packet including the processed data. In particular, according to the present invention, data is transferred between modules in units of packets.

  The header includes a signal identifier assigned to each radio frequency band input to the software defined radio operation processing unit. The data part includes digital data to be processed. The length of the packet may be fixed or variable. However, in an FPGA, it is preferable to realize with a fixed length.

  The module 2 includes a header determination unit 21 and a processing unit 22. The header determination unit 21 determines the header of the input packet and switches the packet to “processing”, “through”, and “discard”. That is, the header determination unit 21 stores, for example, the following table in advance, and determines a signal identifier to be “processed”, a signal identifier to be “through”, and a signal identifier to be “discarded”.

  When the header determination unit 21 determines that the packet should be “processed”, the header determination unit 21 notifies the processing unit 22 of the packet. When it is determined that the packet should be “through”, the packet is output as it is without being notified to the processing unit 22 and without performing any processing on the data unit. If it is determined that the packet should be “discarded”, the input packet is discarded and nothing is output.

  Module 2 has at least one input port and output port. According to the structure of this invention, it is 1 input 1 output fundamentally, and is connected to one direction. One direction means that the output port of one module is connected to the input port of the other module. In particular, a plurality of modules are connected in series, and some of them may be connected in parallel. Further, it may further include a final output port (an output port to the packet disassembling unit), which is connected in a ring shape with one input and two outputs. Another embodiment of the module 2 may be a multi-input one-output type such as a mixer. In this case, a plurality of header determination units 21 are provided for each input port. The output ports of the plurality of header determination units 21 are input to the plurality of input ports of the processing unit 22.

  The processing unit 22 receives a packet determined as “processing” by the header determination unit 21, performs signal processing, and outputs a packet including the processed data. The signal processing of the processing unit 22 may be a fixed process for all packets, or may be a different process by switching parameters necessary for the process.

  FIG. 3 is a first functional configuration diagram of the software defined radio operation processing unit according to the present invention.

  The software defined radio processing unit 1 is preferably composed of an FPGA. Therefore, each arithmetic processing unit is realized by the FPGA executing the hardware design language program. Here, the hardware design language program means reconfiguration data or wiring arrangement information described in a hardware description language called Verilog HDL (Veriware Hardware Description Language) or VHDL. A logic circuit is configured (or reconfigured) in the FPGA based on the reconfiguration data or the wiring arrangement information.

  The software wireless calculation processing unit 1 in FIG. 3 inputs the mobile phone IF signal and the wireless LAN IF signal. The software radio processing unit 1 includes an ADC unit 111 for mobile phone IF signals, an ADC unit 121 for wireless LAN IF signals, a packet configuration unit 131, a filter module 132, a despreading module 133, A demodulation module 135, a deinterleaver module 136, a descrambling module 137, and an error correction decoding module 138. According to the module configuration of FIG. 3, the plurality of modules 132 to 138 are connected in one direction, and particularly connected in series.

  The ADC unit 111 for the mobile phone IF signal and the ADC unit 121 for the wireless LAN IF signal have separate functional units as in the existing configuration of FIG. The data digitized by the ADC units 111 and 121 is input to the packet configuration unit 131. Here, the ADC unit does not always exist for each different type of input radio frequency band. For example, one ADC unit may sample and digitize different radio frequency bands (for example, FM radio signal and AM radio signal) or a plurality of channels of the same system at the same time. Even when the processing is performed by one ADC unit, an identifier included in a header of a packet to be described later differs for each radio band.

  The packet configuration unit 131 generates a packet including a header and data. A mobile phone identifier header is added to the data received from the ADC unit 111. A header of a wireless LAN identifier is added to the data received from the ADC unit 121. The packet configuration unit 131 notifies the filter module 132 of the generated packet.

  For example, according to the prior art of FIG. 1, the data output from the ADC unit is not composed of packets, and the processing unit sequentially processes and outputs the input continuous data. On the other hand, according to the present invention, data output from the ADC unit is configured into packets, and transfer between modules is performed in units of packets.

  Filter processing is necessary for both mobile phone packets and wireless LAN packets. The filter module 132 processes both packets by the filter unit. A packet including data processed by the filter unit is notified to the despreading module 133.

  The despreading processing unit is required for both mobile phone packets and wireless LAN packets. The despreading module 133 processes both packets by the despreading unit. A packet including data processed by the despreading unit is notified to the demodulation module 135.

  Demodulation is required for both mobile phone packets and wireless LAN packets. The demodulation module 135 processes both packets by the demodulation unit. A packet including data processed by the demodulation unit is notified to the deinterleaver module 136.

  The deinterleaver process is necessary for the mobile phone packet, but not for the wireless LAN packet. The deinterleaver module 136 determines that the mobile phone packet should be “processed” and processes the packet by the deinterleaver unit. On the other hand, it is determined that the wireless LAN packet should be “through” and is output as it is without performing any processing on the data portion. The packet output from the deinterleaver module 136 is notified to the descrambling module 137.

  The descrambling process is required for both the mobile phone packet and the wireless LAN packet. The descrambling module 137 processes both packets by the descrambling unit. The packet including the data processed by the descrambling unit is notified to the error correction decoding module 138.

  The error correction decoding process is necessary for the mobile phone packet, but not for the wireless LAN packet. The error correction decoding module 138 determines that the mobile phone packet should be “processed” and processes it by the error correction decoding unit. On the other hand, it is determined that the wireless LAN packet should be “through” and is output as it is without performing any processing on the data portion. The data output from the error correction decoding module 138 is notified to the packet decomposing unit 139.

  The packet decomposing unit 139 removes the header of the packet and outputs only data for each header. Data is transferred in packet format only within the software defined radio processing unit.

  According to the present invention, only the data of the packet is output to the output port corresponding to the identifier included in the packet header. According to the module configuration of FIG. 3, an output port is provided for each different radio frequency band. However, according to other embodiments, one output port may be provided for different radio frequency bands. For example, when processing is performed by switching between an FM radio signal and an AM radio signal, the output data is the same audio data (analog signal to be input to the speaker), and it is sufficient to have one output port. That is, the software defined radio processing unit 1 according to the present invention includes at least one or more input ports and output ports, and the numbers of input ports and output ports do not need to match.

  FIG. 4 is a first module configuration diagram according to the present invention.

  According to the module configuration of FIG. 4, the plurality of modules 41 to 47 are connected in one direction. In particular, they are generally connected in series, but are partially connected in parallel from the module 42 to the module 43 and the module 45. In this case, for example, the first packet is “discarded” by the module 45 and is “processed” or “through” by the module 43. On the other hand, the second packet is “discarded” by the module 43 and is “processed” or “through” by the module 45. In this way, modules can be configured in parallel by the header determination unit “discarding” the packet.

  FIG. 5 is a second module configuration diagram in the present invention.

  According to the module configuration of FIG. 5, the plurality of modules 51 to 58 are connected in one direction. In particular, it is generally formed in a ring shape. In this case, for example, a packet including the first identifier is input from the module 51 and output from the module 54. A packet including the second identifier is input from the module 52 and output from the module 56. As described above, the input module and the output module may be different for each packet having a different signal identifier. Further, since the modules are configured in a ring shape, a packet can be processed multiple times by the same module.

  FIG. 6 is a second functional configuration diagram of the module according to the present invention.

  The module in FIG. 6 further includes an output switching unit 61 in the output stage as compared with the module in FIG. The module has a final output port for final output from the software defined radio processing unit 1 and an output port for output to the next module. When the output switching unit 61 determines that the module is an output module according to the identifier included in the header of the packet, the output switching unit 61 outputs the packet to the final output port. The packet is notified to the packet decomposing unit 139.

  Such a module is effective, for example, when the module is configured in a ring shape as shown in FIG. For example, the module 54 in FIG. 5 outputs a packet including the first identifier to the packet decomposing unit 139 as a final output, and outputs a packet including the second identifier to the next module 55. 5 outputs the packet including the second identifier to the packet decomposing unit 139 as a final output.

  According to the present invention, since the same arithmetic processing unit can be shared in different radio frequency bands, the use efficiency of the number of logic gates can be increased as compared with the prior art. Further, according to the present invention, since the modules are basically connected in one direction, switching between the modules is not necessary, and the operation delay can be reduced.

  According to the above-described various embodiments of the present invention, those skilled in the art can easily make various changes, modifications, and omissions in the technical idea and scope of the present invention. The above description is merely an example, and is not intended to be restrictive. The invention is limited only as defined in the following claims and the equivalents thereto.

It is a functional block diagram of the software radio | wireless arithmetic processing part in a prior art. It is a 1st function block diagram of the module in this invention. It is a 1st functional block diagram of the software defined radio | wireless arithmetic processing part in this invention. It is a 2nd function block diagram of the software defined radio | wireless arithmetic processing part in this invention. It is a 3rd function block diagram of the software defined radio | wireless arithmetic processing part in this invention. It is a 2nd function block diagram of the module in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Software radio | wireless arithmetic processing part 11 Module for mobile phones 12 Module for wireless LAN 111, 121 ADC part 112, 122 Filter part 113, 123 Despreading part 114, 124 PN code generation part 115, 125 Demodulation part 116 Deinterleaver part 117, 127 Descramble unit 118 Error correction decoding unit 131 Packet component unit 132 Filter module 133 Despreading module 135 Demodulation module 136 Deinterleaver module 137 Descramble module 138 Packet decomposing unit 2 Module 21 Header determining unit 22 Processing units 41 to 47, 51 to 51 58 modules 401, 402, 501, 502 ADC section

Claims (7)

A software defined radio apparatus having a software defined radio processing unit,
For each different type of radio frequency band that is input, a packet configuration means for generating a packet that includes the type identifier in the header;
A plurality of modules having arithmetic processing means and header determination means for switching whether the packet is processed and output by the arithmetic processing means or output without processing according to an identifier included in the header of the input packet When,
Packet disassembling means for outputting only the data of the packet to an output port corresponding to the identifier included in the header of the packet;
The software defined radio device characterized in that the plurality of modules are connected in one direction. The header determination means can be switched to further discard the packet according to an identifier included in the header of the packet,
The software radio apparatus according to claim 1, wherein some of the plurality of modules are connected in parallel. When the module outputs the packet, whether the packet is finally output as the software defined radio operation processing unit or output to the next module according to the identifier included in the header of the packet It further has an output switching means for switching,
The software wireless device according to claim 1, wherein the plurality of modules are connected in a ring shape.   The software defined radio device according to any one of claims 1 to 3, wherein the software defined radio operation processing unit is an FPGA. A hardware design language program in a software defined radio processing unit configured by an FPGA,
For each different type of radio frequency band that is input, a packet configuration means for generating a packet that includes the type identifier in the header;
A plurality of modules having arithmetic processing means and header determination means for switching whether to output the packet processed by the arithmetic processing means or output without processing according to an identifier included in the header of the input packet When,
Causing the FPGA to function as a packet decomposing means for outputting only the data of the packet to an output port corresponding to an identifier included in the header of the packet;
A hardware design language program characterized by causing the FPGA to function so that the plurality of modules are connected in one direction. The header determination means causes the FPGA to switch to further discard the packet according to an identifier included in a header of the packet;
The hardware design language program according to claim 5, wherein the FPGA functions so that the plurality of modules are connected in parallel in part. When the module outputs the packet, whether the packet is finally output as the software defined radio operation processing unit or output to the next module according to the identifier included in the header of the packet It further has an output switching means for switching,
6. The hardware design language program according to claim 5, wherein the plurality of modules cause the FPGA to function so as to be connected in a ring shape.

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