JP4553014B2 - Information code reading apparatus and information code reading method - Google Patents

Description

  The present invention relates to an information code reader for optically reading and decoding an information code, and an information code reading method.

  At present, information codes such as barcodes and two-dimensional codes are widely used for merchandise sales management, for example. Then, as disclosed in, for example, Patent Document 1, the conventional information code reading device temporarily stores the data read by the light receiving sensor in the image memory, and when the reading is completed, the processor stores the data in the image memory. Data is read and decoded.

Patent Document 1 stores two-dimensional image data in a plurality of memories in advance for each frame for the purpose of minimizing time loss and enabling high-speed reading in the case where re-reading of image data occurs. I try to let them.
JP-A-10-198753

  However, the configuration of Patent Document 1 has a problem in terms of cost because an extra memory capacity is required for a reader having a general configuration. For example, in the case of the number of pixels of the VGA (Video Graphic Array) class, it takes about several tens of ms to read data once. Accordingly, assuming that the number of pixels of the light receiving sensor is increased for the purpose of improving the reading accuracy in the information code reading device, it is inevitable that the time required for reading is increased in the configuration of Patent Document 1.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an information code reading apparatus and an information code reading method capable of reducing the time required for reading and decoding an information code with a low-cost configuration. There is to do.

According to the information code reader of the first aspect, the image signal data of the information code read by the light receiving sensor and A / D converted is first input to the feature detection circuit, and the feature pattern included in the information code is read. Detection is performed. When the feature detection circuit determines that the code pattern of the information code is out of the allowable value, the re-execution unit stops reading the information code by the light receiving sensor at that time and starts a new reading operation. .
That is, if an attempt is made to read an information code other than the information code to be read or an attempt to read an unclear and unreadable information code, the reading operation is stopped and the next reading operation is executed. The operator can perform the reading operation more efficiently without the unnecessary reading operation being continued.

  According to the information code reading apparatus of the second aspect, the feature detection circuit determines the type of the information code according to the detected feature pattern and transmits the determined type to the decoding unit. Decoding processing according to the type of information code transmitted from the beginning can be performed. Therefore, it is not necessary for the decoding means itself to perform the process for determining the type of information code, so that the decoding process can be completed more quickly.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a functional block diagram mainly showing the configuration of the data processing system in the information code reader. A CCD sensor (light receiving sensor) 1 is an area sensor for optically reading an information code irradiated by a light source such as an LED, and the reading is synchronized with a clock signal output by a timing generator (TG) 2. Done.

  Image data read and output by the CCD sensor 1 is amplified by an amplifier 3 and A / D converted by an A / D conversion circuit (ADC) 4. The A / D converted digital data is supplied to the feature detection gate array 5. The feature detection gate array 5 includes a data buffer 6, a signal output unit (signal output circuit) 7, and a feature detection unit (feature detection circuit) 8.

  The data buffer 6 is configured as a first-in first-out FIFO (First In First Out). The signal output unit 7 outputs a detection timing signal each time the data written in the data buffer 6, that is, the image data read and output by the CCD sensor 1 reaches a predetermined amount, for example, one scanning line. It is configured. The feature detector 8 detects the presence or absence of a feature pattern included in the information code read by the CCD sensor 1 based on the data written in the data buffer 6.

  For example, as shown in FIG. 4, in a QR code (registered trademark) which is a kind of two-dimensional code, a light / dark pattern ratio is set to 1: 1: 3: 1: 1 as a reference positioning symbol for reading data. Finder pattern is arranged. The feature detection unit 8 is configured to output a detection signal when a feature pattern such as the finder pattern is detected based on a light / dark pattern of data written in the data buffer 6.

  Also, if the information code is PDF417, which is a kind of barcode or two-dimensional code, as shown in FIG. 5, the fixed number of bars and the arrangement ratio of these bars are obtained. Recognize as a code. In the example shown in FIG. 5, a quaternary code is assumed, and a narrow / wide ratio of up to 4 is allowed for 5 bars. Also, the bar thickness is allowed to 20%. As an example, a bar code is recognized when the ratio of 1,2,1,4,2,1,1,1 can be clearly detected under the above conditions.

In the case of PDF417, since a two-dimensional code pattern is combined with a barcode similar to the above format, it is recognized as PDF417 when a two-dimensional code pattern is detected following the barcode pattern.
Further, if the information code is a data matrix that is a kind of two-dimensional code, as shown in FIG. 6, when either the vertical or horizontal bar of the L-shaped pattern is detected, any one of them will be captured at the next capture. It is detected whether or not the other bar following the one end side exists. Then, it is determined as a data matrix when detection is performed up to a place where an L-shaped pattern can be estimated to some extent.

  The feature detection gate array 5 is connected to the system bus 9. The system bus 9 includes a CPU (decoding means, notifying means) 10 for controlling the information code reader, an S (Synchronous) DRAM 11 as an image memory, a flash memory 12 in which a control program and the like are stored, and peripheral processing of the CPU 10. A gate array 13 and a DMA (Direct Memory Access) controller (DMAC, data transfer circuit) 14 are connected.

The gate array 13 includes an interrupt control circuit 15 therein. The interrupt control circuit 15 is configured so that an interrupt can be generated by the feature detection gate array 5. That is, as described with reference to FIGS. 4 to 6, when the type is determined based on the feature pattern of the information code detected by the feature detector 8, the feature detection gate array 5 determines whether the interrupt control circuit corresponds to the type. By setting a bit corresponding to 15, the CPU 10 can generate an interrupt (INT).
When the CPU 10 recognizes the occurrence of the interrupt, the CPU 10 can read the register of the interrupt control circuit 15 and recognize the type of information code determined by the feature detection gate array 5 based on the set bit.

The gate array 13 is connected to a buzzer (notification means) 16 for the CPU 10 to perform notification processing, and the CPU 10 writes to a buzzer driving register (not shown) in the gate array 13. Thus, the buzzer 16 can be sounded via a drive circuit (not shown). Similarly, an LED 17 serving as an exposure light source is connected to the gate array 13, and drive control is performed by the CPU 10.
The DMA controller 14 transfers data written in the data buffer 6 of the feature detection gate array 5 to the SDRAM 11, and executes cycle steal while the CPU 10 performs resource access via the system bus 9. Data transfer.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 2 is a flowchart showing the processing contents of the feature detection gate array 5. Note that the feature detection gate array 5 is pure hardware composed only of logic, and therefore indicates processing by the hardware.

  When the reading of the information code is started, the light emitted from the LED 17 is applied to the information code to be read (“Exposure”, see FIG. 7A), and the CCD sensor 1 determines the brightness of the light applied to the information code. Are read two-dimensionally to generate charge data. Subsequently, the CCD sensor 1 outputs the generated charge data to the amplifier 3 (“capture”) in synchronization with the clock signal of the timing generator 2. Then, since the data A / D converted by the A / D conversion circuit 4 is given to the feature detection gate array 5, the feature detection gate array 5 writes the data in the data buffer 6 (step A1).

When the timing signal is output from the signal output unit 7 (step A2, “YES”), the feature detection unit 8 starts the feature detection process (step A3). If a feature pattern corresponding to any information code is detected (step A4, "YES"), the type of information code is determined based on the feature pattern (step A5).
If the information code is a two-dimensional code, the feature pattern cannot be detected with only one scanning line of the CCD sensor 1 (step A4, "NO"), so the limit for detection is set to a predetermined number of lines. If the detection limit has not been reached ("NO"), the process returns to step A1 and continues to take in data. If the detection limit is exceeded in Step A11 ("YES"), an interrupt is generated in the CPU 10 so as to perform a notification process for the user, and an instruction is output (Step A12).

  When the feature detection unit 8 determines the type of the information code, the feature detection unit 8 instructs the CPU 10 to start decoding according to the type (step A6). That is, as described above, a bit is set in the interrupt control circuit 15 of the gate array 13. Subsequently, the feature detection gate array 5 determines whether or not the data written in the data buffer 6 has reached a predetermined amount (full) based on the value of the write pointer (step A7), and reaches the predetermined amount. If not ("NO"), the data buffer 6 continues to take in data (step A8).

On the other hand, if it is determined in step A7 that the data written in the data buffer 6 has reached a predetermined amount (“YES”), the feature detection gate array 5 activates the DMA controller 14 (step A9). Then, the DMA controller 14 starts data transfer from the data buffer 6 to the SDRAM 11. If the data capture has not been completed (step A10, “NO”), the feature detection gate array 5 proceeds to step A8 and continues the capture.
Even during the processing of steps A7 to A10, the signal output unit 7 outputs a timing signal each time the data written in the data buffer 6 reaches one scanning line. In this embodiment, a predetermined amount for determining whether the buffer is full is set to be equal to one scanning line.

FIG. 3 is a flowchart showing the processing contents on the CPU 10 side. The CPU 10 first turns on the LED 17 to perform exposure (step B0), and then instructs to start taking in data read by the CCD sensor 1 (step B0a). That is, the timing generator 2 starts outputting the clock signal.
Then, the CPU 10 stands by until there is a decoding start instruction (step B1) or a notification processing instruction (step B2) by the feature detection gate array 5. When an interrupt to the CPU 10 occurs and the CPU 10 recognizes that a decoding start instruction has been generated by performing the interrupt processing (step B1, “YES”), the CPU 10 sets the information code by setting the bit of the interrupt control circuit 15. Is determined (step B4).

Then, the CPU 10 waits until the timing signal is output by the feature detection gate array 5 (step B5). When the timing signal is output ("YES"), the SDRAM 11 is accessed to read out the image data (step B6). ). Here, the timing signal is also generated as an interrupt to the CPU 10. The interrupt control circuit 15 is set so that the interrupt is permitted at the same time that the feature detection gate array 5 issues a decode start instruction.
Therefore, when the timing signal is output in step B5, the first data transfer to the SDRAM 11 by the DMA controller 14 is completed, and the CPU 10 can read the image data from the SDRAM 11.

Next, the CPU 10 performs a decoding process according to the type of information code determined in step B4 (step B7). If the decoding of the data amount corresponding to the type of information code is completed (step B8, “YES”), the process is terminated. If the decoding is not completed (“NO”), the process returns to step B5.
On the other hand, when the CPU 10 recognizes that the notification processing instruction by the feature detection gate array 5 has occurred (step B2, “YES”), the CPU 10 sounds the buzzer 16 to notify the user that the reading processing has failed. (Step B3).

FIG. 7A is a timing chart showing the flow of processing in this embodiment. That is, the feature detection process in the feature detection unit 8 is performed in parallel with the process of fetching the data read by the CCD sensor 1 in “exposure” into the data buffer 6 of the gate array 5 for feature detection in the subsequent “fetch”. Further, the data in the data buffer 6 is transferred to the SDRAM 11, and the decoding process by the CPU 10 is also performed in parallel with the data fetching.
FIG. 7B shows the flow of processing in an information code reading device having a conventional general configuration. That is, in the general conventional configuration, after all the data is written in the image memory, the feature detection process and the decoding process are performed serially, so that it takes a long time to complete all the processes. .

  As described above, according to the present embodiment, the image signal data of the information code read and A / D converted by the CCD sensor 1 is first input to the feature detection gate array 5 and included in the information code by the feature detection unit 8. The detected feature pattern is detected. Then, the image data is transferred to the SDRAM 11, and the CPU 10 decodes the data stored in the SDRAM 11 in accordance with the timing signal output from the signal output unit 7.

  That is, while the image data is sequentially read, the feature pattern detection of the information code in the feature detection gate array 5 is performed first, and then the decoding by the CPU 10 is performed. Therefore, unlike the prior art, a plurality of frames of image memory is not required to perform different processes in parallel, and can be configured at low cost. Since reading of image data and feature detection processing and decoding processing are performed in parallel, decoding of the information code can be completed more quickly.

Since the signal output unit 7 outputs a timing signal every time the CCD sensor 1 outputs an image signal for one scanning line, for example, when the information code is a bar code arranged one-dimensionally, Decoding can be performed faster.
The feature detection unit 8 detects a finder pattern as a feature pattern when the information code is a QR code, and detects the number of bars and a bar interval ratio when the information code is a barcode or PDF417. When the code is a data matrix, an L-shaped pattern is detected. Therefore, it is possible to detect features corresponding to each information code.

Further, the DMA controller 14 is activated when the feature detection gate array 5 detects a feature pattern, and transfers the digital data input to the data buffer 6 to the SDRAM 11, so that the CPU 10 can reliably read the information code. When it is determined that the decoding has been performed, decoding is started, and unnecessary decoding processing can be avoided.
In addition, the feature detection gate array 5 determines the type of the information code according to the detected feature pattern and transmits the determined type to the CPU 10. Therefore, the CPU 10 determines the type of the information code transmitted from the beginning. It is possible to perform a decoding process according to the above. Accordingly, since the CPU 10 itself does not need to perform processing for determining the type of information code, the decoding processing can be completed more quickly.

(Second embodiment)
8 and 9 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only different parts will be described below. In FIG. 8, which is a diagram corresponding to FIG. 3, when the decoding process is completed and “YES” is determined in step B8, the CPU 10 stops the data acquisition to the timing generator 2, the feature detection gate array 5 and the DMA controller 14. An instruction for making it output is output (step B9).

Then, the timing generator 2 stops outputting the clock signal to the CCD sensor 1. Further, the feature detection gate array 5 stops writing data to the data buffer 6 (at that time, it is determined as “YES” in step A10), and the DMA controller 14 determines that the data transfer process is being executed. The transfer is stopped at the time (see FIG. 9).
Subsequently, the CPU 10 performs processing for notifying the user that decoding has been completed (step B10). This notification process is performed by sounding the buzzer 16 as in step B3 described above.

  As described above, according to the second embodiment, when the decoding is completed, the CPU 10 stops capturing the information code by the CCD sensor 1 at that time, so that unnecessary data is not captured and power consumption is reduced. Can do. Further, the CPU 10 sounds the buzzer 16 when the decoding is completed and performs a notification operation for the user, so that the user can recognize that the decoding is completed by the notification.

(Third embodiment)
10 and 11 show a third embodiment of the present invention. The same parts as those in the first or second embodiment are denoted by the same reference numerals, and the description thereof is omitted. Only different parts will be described below. In FIG. 10 corresponding to FIG. 3, when the CPU (re-execution means) 10 is notified of the failure of feature detection from the feature detection gate array 5 and executes step B3, step B9 similar to the second embodiment is executed. Execute to stop reading data. Then, the process returns to step B0, and an exposure operation for immediately performing the next reading is started. The operation timing chart in this case is as shown in FIG.

  As described above, according to the third embodiment, when the feature pattern detection of the information code by the feature detection gate array 5 fails, the CPU 10 stops reading the information code by the CCD sensor 1 at that time and starts a new reading. The operation was started. That is, when an attempt is made to read a code other than the information code to be read, or to read an unclear and unreadable information code, the reading operation is stopped and the next reading operation is executed. Therefore, the operator can perform the reading operation more efficiently without continuing the unnecessary reading operation.

(Fourth embodiment)
12 and 13 show a fourth embodiment of the present invention, and only the parts different from the second embodiment will be described. In the fourth embodiment, it is assumed that information codes are read continuously. When the decoding process is completed for one information code (step B8, “YES”), steps B9 and B10 are executed as in the second embodiment. Then, the CPU (state changing means) 10 changes the time required for data capture in step B0a according to the type of information code determined in step B4 (step B11).

  That is, depending on the type of information code, since the stored data capacity is small, the time required for data capture may be short. For example, the time required to read a barcode is shorter than that of a QR code. Therefore, when the capture time set as the initial state is set together with the QR code and the actually read data is barcode data, the capture time is shortened accordingly in step B11. Reset as follows. Then, the process proceeds to step B0 and the next reading operation is performed.

  As described above, according to the fourth embodiment, the CPU 10 determines the type of the information code based on the feature pattern detected by the feature detection gate array 5, and the information code by the CCD sensor 1 according to the determined type. The data acquisition time, that is, the reading state was changed. Therefore, when the information code reading apparatus supports reading of various types of information codes, if the reading state is changed according to the determined type, it is possible to perform appropriate reading according to each information code. The reading process can be made efficient.

(5th Example)
14 and 15 show a fifth embodiment of the present invention. In the fifth embodiment, the clock rate of the timing generator 2 is set sufficiently high, and the data transfer processing by the DMA controller 14 is performed at a sufficiently high speed, so that the feature detection gate array 5 detects the feature pattern. A case is assumed in which the transfer of data to be decoded to the SDRAM 11 is completed during the period.

In FIG. 14, which corresponds to FIG. 2, the feature detection gate array 5 performs the determination in step A7 when it is determined “NO” in step A11, and starts the DMA controller 14 at that time when it is determined “YES”. (Step A9). Then, the process returns to step A1.
When the feature pattern is normally detected (step A4, "YES"), the stop of data capture is instructed (step A13). The processing here is the same processing as step B9 performed by the CPU 10 in the second embodiment, and the feature detection gate array 5 executes in place of the CPU 10 in the fifth embodiment. Then, steps A5 and A6 are executed and the process is terminated.

  That is, the process in this case is represented by the timing chart of FIG. The CPU 10 reads the data from the SDRAM 11 and performs a decoding process after the data capturing is stopped.

  As described above, according to the fifth embodiment, when the feature detection gate array 5 completes the detection of the feature pattern, the CCD sensor 1 stops taking in the information code. In other words, if the transfer process of the data to be decoded by the DMA controller 14 is completed while the feature pattern is being detected, the CPU 10 only needs to perform the decoding process thereafter. Accordingly, it is possible to prevent excessive data capture and reduce power consumption.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
For example, in the first embodiment, without performing the process of transmitting the discriminated information code type from the feature detection gate array 5 to the CPU 10, the CPU 10 receives the information code in the decoding process when instructed to start decoding. You may make it discriminate | determine the kind of.
The information code reader does not necessarily need to support a plurality of types of information codes, and may be configured to support only one of the types, or may be configured to perform correspondence switching externally by switch setting, for example. You may do it.
The timing signal from the signal output unit 7 is not necessarily output for each scanning line. The timing signal used by the feature detection unit 8 inside the feature detection gate array 5 and the timing signal output to the CPU 10 may be output at different timings.

Further, the signal output unit 7 may be deleted, and the CPU 10 may perform the decoding process based on its own processing timing.
If there is no problem in cost, the function of the feature detection gate array 5 may be realized by software by using a separate CPU.
In the second embodiment, when the data capture is stopped, the power supply to the CCD sensor 1 and the timing generator 2 may be stopped.
In the fifth embodiment, the reading resolution by the CCD sensor 1 may be changed in addition to or instead of changing the data capture time. For example, when the initial setting is a QR code and the actual reading is a micro QR code or a bar code, the resolution is lowered or only a part of the reading area of the CCD sensor 1 is activated. It may be switched as follows.

1 is a functional block diagram showing a configuration of a data processing system in an information code reader according to a first embodiment of the invention. Flow chart showing the processing contents by hardware of the gate array for feature detection Flow chart showing processing contents of CPU The figure explaining the feature pattern detected when an information code is a QR code FIG. 4 equivalent diagram when the information code is a barcode or PDF417 FIG. 4 equivalent diagram when the information code is a data matrix (A) is a timing chart showing the flow of processing in this embodiment, and (b) is a timing chart showing the flow of processing in the conventional information code reader. FIG. 3 equivalent view showing a second embodiment of the present invention. Fig. 7 (a) equivalent diagram FIG. 3 equivalent view showing a third embodiment of the present invention. Fig. 7 (a) equivalent diagram FIG. 3 equivalent view showing a fourth embodiment of the present invention. Fig. 7 (a) equivalent diagram FIG. 2 equivalent diagram showing a fifth embodiment of the present invention. Fig. 7 (a) equivalent diagram

Explanation of symbols

  1 is a CCD sensor (light receiving sensor), 4 is an A / D conversion circuit, 5 is a feature detection gate array, 7 is a signal output unit (signal output circuit), 8 is a feature detection unit (feature detection circuit), and 10 is a CPU. (Decoding means, notification means, re-execution means, state change means), 11 is an SDRAM (image memory), 14 is a DMA controller (data transfer circuit), and 16 is a buzzer (notification means).

Claims (6)

A light receiving sensor for optically reading an information code and outputting an image signal;
An A / D conversion circuit for A / D converting the image signal;
A feature detection circuit that receives digital data output from the A / D conversion circuit and detects a feature pattern included in the information code;
A data transfer circuit for transferring digital data input to the feature detection circuit to an image memory;
Decoding means for decoding data stored in the image memory;
Re-execution means for stopping the reading of the information code by the light receiving sensor and starting a new reading operation at that time when the code pattern of the information code is determined to be out of an allowable value by the feature detection circuit; An information code reading device comprising:   2. The information according to claim 1, wherein the feature detection circuit is configured to determine a type of an information code in accordance with a detected feature pattern and to transmit the determined type to the decoding unit. Code reader. 3. The information code reading apparatus according to claim 2, wherein an information code capturing time is changed in accordance with the determined type. A process of optically reading an information code by a light receiving sensor and outputting an image signal;
A / D converting the image signal;
A feature detection circuit detecting a feature pattern included in the information code based on the A / D converted digital data;
Transferring the digital data from the feature detection circuit to an image memory;
Decoding the data stored in the image memory;
When the feature detection circuit determines that the code pattern of the information code is out of an allowable value, the process includes a process of stopping reading of the information code by the light receiving sensor and starting a new reading operation at that time. An information code reading method characterized by the above . The feature detection circuit determines the type of information code according to the detected feature pattern,
5. The information code reading method according to claim 4, wherein the information code is decoded according to the determined type. 6. The information code reading method according to claim 5, wherein an information code fetch time is changed in accordance with the determined type.

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