JP4420033B2 - Information reader - Google Patents

Description

The present invention relates to an information reading apparatus that reads optical information such as a barcode and a QR code (registered trademark) attached to a product or the like conveyed on a production line.

Optical information such as a bar code is used to identify a product by optically reading it by attaching it to a product conveyed on a production line in addition to a POS system. Here, when two barcodes are attached to the product and read at the same time, two information readers are provided together. Patent Document 1 discloses a composite image generation imaging system that captures and combines two images with two cameras.
JP 2004-297283 A

When two information readers are installed, the introduction cost is doubled. If you always read two barcodes at the same time, the increase in installation cost is acceptable. However, when one barcode is read and two barcodes are read on the production line, it is not desirable to provide two information readers. On the other hand, although it is conceivable to attach two cameras to one information reading apparatus, the time required for reading is doubled and rapid reading cannot be performed.

In order to achieve the above object, an object of the present invention is to provide an information reading apparatus capable of reading a plurality of information codes in a short time by an internal camera and an external camera.

In order to achieve the above object, the invention of claim 1 is an information reading apparatus capable of decoding an image captured by the internal camera 12 and decoding an image captured by the connected external camera 112,
First image data storage means 22 for storing image data sent from the internal camera 12 in a first buffer 22b:
Second image data storage means 26 for storing image data sent from the external camera 112 in the second buffer 26b:
Image data transfer means for intermittently sending the image data stored in the first buffer 22b and the second buffer 26b via the bus line 28 and holding them in the image memory 24:
Decoding means for acquiring and decoding the image data held in the image memory 24 via the bus line 28;
The capacity of the first buffer 22b and the second buffer 26b is set so that the decoding process by the decoding unit is divided for each block, and the first image is processed even in the longest processing time for processing the divided blocks. a buffer capacity adjusting means for storing the image data is adjusted so as to be continued from the due data storage means and the second image data storage means within the camera 12 and the external camera 112:
First notification means for notifying the decoding means when the buffer size set in advance before the image data from the internal camera 12 in the first buffer 22b reaches the maximum buffer capacity;
A second notifying unit for notifying the decoding unit when image data from the external camera 112 in the second buffer reaches a buffer size set in advance before reaching the maximum buffer capacity;
The decoding means interrupts decoding after processing at least one of the divided blocks constituting the decoding processing after receiving the notification from the first notification means and the second notification means And
By transferring the image data stored in the first buffer 22b and the second buffer 26b during the interruption to the image memory 24 via the bus line 28, the image data is transferred to the image memory 24 via the bus line 28. Start within the time of maximum buffer capacity;
The decoding means is technically characterized by restarting decoding after the transfer is completed.

The invention of claim 2 is an information reading apparatus capable of decoding an image captured by the internal camera 12 and decoding an image captured by the connected external camera 112,
First image data storage means for storing image data sent from the internal camera 12 in the first buffer 22b:
Second image data storage means for storing image data sent from the external camera 112 in the second buffer 26b:
Image data transfer means for intermittently sending the image data stored in the first buffer 22b and the second buffer 26b via the bus line 28 and holding them in the image memory 24:
Decoding means for acquiring and decoding the image data held in the image memory 24 via the bus line 28;
First notification means for notifying the decoding means when the buffer size set in advance before the image data from the internal camera 12 in the first buffer 22b reaches the maximum buffer capacity;
Second notification means for notifying the decoding means when the buffer size set in advance before the image data from the external camera 112 in the second buffer 26b reaches the maximum buffer capacity;
The decoding means interrupts decoding after processing at least one of the divided blocks constituting the decoding process after receiving the notification from the first notification means and the second notification means;
Processing for transferring image data to the image memory 24 via the bus line 28 by sending the image data stored in the first buffer 22b and the second buffer 26b to the image memory 24 via the bus line 28. Starts within the maximum buffer capacity time;
A technical feature of the decoding means is that the decoding is resumed after the transfer is completed.

In the information reading apparatus according to claim 1, by decoding the image data stored in the first buffer and the second buffer intermittently to the image memory via the bus line, the decoding is performed from the internal camera and the external camera. It is possible to simultaneously store and decode the image data to be sent to the first buffer and the second buffer, and to shorten the time for capturing and decoding the images from the internal camera and the external camera. Here, it is possible to continue to store image data from the internal camera and the external camera even in the processing time that is the longest of the processing times for processing the divided blocks of the decoding process for the first buffer and the second buffer. Adjust as follows. Then, by interrupting the decoding after the processing of at least one of the divided blocks constituting the decoding process, the image data stored in the first buffer and the second buffer are intermittently transmitted via the bus line. The image data from the internal camera and the external camera is stored in the first buffer so that the intermittent transmission for holding the image data in the image memory via the bus line can be prevented. In this case, the capacity of the second buffer is exceeded and the first buffer and the second buffer are not held. Further, when the image data from the internal camera and external camera in the first buffer and the second buffer reach the preset buffer size before reaching the maximum buffer capacity, the storage means that the storage is almost complete is notified to the decoding means. To do. After receiving the notification, the decoding means interrupts the decoding after processing at least one block of the divided decoding blocks constituting the decoding processing, thereby storing the image data stored in the first buffer and the second buffer. Can be decoded during a pause time in which the image data is intermittently sent to the image memory via the bus line, and the intermittent feed for holding the image data in the image memory via the bus line can be prevented.

In the information reading apparatus according to claim 2, by decoding the image data stored in the first buffer and the second buffer intermittently to the image memory via the bus line, the decoding is performed from the internal camera and the external camera. It is possible to simultaneously store and decode the image data to be sent to the first buffer and the second buffer, and to shorten the time for capturing and decoding the images from the internal camera and the external camera. Here, when the image data from the internal camera and external camera in the first buffer and the second buffer reach a preset buffer size before reaching the maximum buffer capacity, the decoding means that the storage is almost complete. After receiving the notification, the decoding means interrupts the decoding after the processing of at least one block among the divided decoding blocks constituting the decoding process, thereby allowing the first buffer and the second buffer to The accumulated image data can be decoded during a pause time in which the image data is intermittently sent to the image memory via the bus line, and the intermittent feed for holding the image data in the image memory via the bus line can be prevented.

In the information reading apparatus according to claim 3 , since the second buffer for storing the image data from the external camera is composed of the gate array, the image data from the external camera is temporarily stored in the gate array and intermittently via the bus line. And stored in the image memory. For this reason, the image data stored in the gate array is decoded in the pause time when it is intermittently sent to the image memory via the bus line, so that the image data sent from the external camera can be stored in the gate array and decoded. Can be performed simultaneously, and the time required for image capture and decoding from an external camera can be shortened.

Hereinafter, an embodiment in which an information reading apparatus of the present invention is applied to an information code reading apparatus will be described with reference to the drawings. First, a configuration outline of the information code reading device 10 according to the first embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 is an explanatory diagram of an information code reader 10 according to the first embodiment. The information code reader 10 includes an internal camera 12, reads the QR code Q1 attached to the side surface of the product 200, and transmits the decoding result to the computer 120 side. The information code reader 10 can further be connected to a general-purpose external camera 112, and can output the decoding result of the QR code Q 2 on the upper surface of the product 200 captured by the external camera 112 to the computer 120.

FIG. 2 is a block diagram showing the configuration of the information code reading device 10. The information code reader 10 mainly includes an illumination light source 16, an imaging lens 14, a light receiving sensor 12 comprising a CCD, an A / D converter 32 for A / D converting analog output from the light receiving sensor 12, and A / D conversion. A main circuit 20 that processes the received image signal, a signal IF 34 that controls the exchange of signals with the computer 120, a control IF 36 that performs various controls, a buzzer 38 that outputs a read sound, and an external camera 112 It consists of a connector 40 and the like for connection. The external camera 112 connected via the cable 18 is provided with a dedicated illumination light source 116.

FIG. 3 shows signal outputs from the internal camera 12 made of a CCD and the external camera 112 made of a CMOS sensor. The internal camera 12 composed of a CCD is converted into an 8-bit digital signal by an A / D converter 32 in order to output an analog image signal, and is output to the main circuit 20 shown in FIG. The external camera 112 composed of a CMOS sensor outputs an 8-bit image signal directly to the main circuit 20. Here, a CCD is used for the internal camera 12, but a CMOS sensor can also be used, and a CCD can be used for the external camera 112.

FIG. 4 is a block diagram showing a circuit configuration of the main circuit 20.
The main circuit 20 that decodes the information code from the image data includes a CPU 22, an image memory 24 composed of DRAM, and a gate array 26. The CPU 22, the image memory 24, and the gate array 26 receive image signals. They are connected by a digital bus 28 for transfer. The CPU 22 includes a buffer 22b, and the gate array 26 also includes a buffer 26b. Here, the image memory 24 can also be configured by SDRAM, and the gate array 26 can also be configured by FPGA (Field Programmable Gate Array). The image signal converted from the internal camera 12 into a digital signal by an A / D converter (not shown in FIG. 4) is sent to the CPU 22 via the camera interface and temporarily stored in the buffer 22b of the CPU 22. When the data amount is stored to a certain level, it is transferred to the image memory 24 via the digital bus 28. On the other hand, the signal from the external camera 112 is sent via the external camera interface and temporarily stored in the buffer 26b of the gate array 26. When the data amount is stored to a certain level, it is transferred to the image memory 24 via the digital bus 28. The CPU 22 takes out the image data stored in the image memory 24 via the digital bus 28 and decodes the information code.

FIG. 5 is an explanatory diagram showing the connection of the D flip-flop 26f provided in the gate array 26 and detecting the connection of the external camera 112, and FIG. 6 is a chart showing the state transition of the D flip-flop 26f. A power supply voltage Vcc is applied to the D terminal of the D flip-flop 26f, an enable command from the CPU 22 is output to the CE input terminal, a control signal from the external camera 112 is output to the C input terminal, and the CLR terminal. The clear command from the CPU 22 is output. The Q output terminal outputs external camera detection to the CPU 22 side. That is, as shown in FIG. 6, when a control signal from the external camera 112 is applied, an external camera detection signal (1) is output from the Q output terminal to the CPU 22 side. As a clock source of the D flip-flop 26f, for example, a horizontal synchronization signal, a vertical synchronization signal from an external camera, a response to an input to the external camera, an image transfer clock output from the external camera, or the like can be used.

FIG. 7A is an explanatory diagram showing the allocation of the image memory when the image memory 24 is not connected to the external camera, and FIG. 7B is an explanatory diagram showing the allocation of the image memory when the external camera is connected. When the external camera is not connected, as shown in FIG. 7A, the image data of the first screen imaged by the internal camera is held from the start address 0XAAAA, and the image is captured by the internal camera from the start address 0XBBBB. The second screen image data is stored, the third screen image data captured by the internal camera is stored from the start address 0XCCCC, and the fourth screen image data captured by the internal camera is stored from the start address 0XDDDD. Thus, the image data of the internal camera for 4 screens is held.

On the other hand, when an external camera is connected, as shown in FIG. 7B, the image data of the first screen imaged by the internal camera is held from the start address 0XAAAA, and from the start address 0XBBBB by the external camera. Holds the image data of the first screen imaged, holds the image data of the second screen imaged by the internal camera from the start address 0XCCCC, and holds the image data of the second screen imaged by the external camera from the start address 0XDDDD By doing so, the image data of the internal camera for two screens and the image data of the external camera for two screens are held.

FIG. 8 is a flowchart showing the allocation processing of the image memory 24 by the CPU 22. The CPU 22 stores the image data sent from the internal camera in the buffer 22b, transfers the stored image data from the buffer 22b to the image memory 24, waits for a time (Xms) (S12), and refers to FIG. The CLR terminal of the D flip-flop 26f described above is reset from 1 to 0 (S14). Then, it is detected whether the output of the Q output terminal is 1, that is, whether an external camera is connected (S18). Here, when the external camera is connected (Q output terminal output 1) (S18: Yes), it is determined whether the external camera is not conventionally connected (Mode = 0) (S28). When the external camera is not conventionally connected (Mode = 0), that is, when the connection is detected in this processing (S28: Yes), the connection of the external camera is detected (S30), and FIG. As described above, the image memory is allocated (S32), and an image transfer process described later is started (S22). On the other hand, if an external camera has been conventionally connected and the image memory allocation has already been completed (S28: No), the image transfer process is immediately started (S22).

On the other hand, if the external camera is not connected (Q output terminal output 0) (S18: No), it is determined whether the external camera is conventionally connected (Mode = 1) (S20). When the external camera is conventionally connected (Mode = 1), that is, when removal of the external camera is detected in this processing (S20: Yes), removal of the external camera is detected (S24), and FIG. As described above with reference to (A), the image memory is allocated (S26), and the image transfer process is started (S22). On the other hand, if the external camera has not been connected conventionally and the image memory allocation has already been completed (S20: No), the image transfer process is immediately started (S22).

Subsequently, transfer of image data in the information code reader 10 of the first embodiment will be described with reference to FIGS. FIG. 9A shows transmission of an image signal from the internal camera 12 to the buffer 22b of the CPU 22, and FIG. 9B shows transfer of the image signal from the buffer 22b to the image memory 24 via the digital bus 28. FIG. 9 (3) shows transmission of image signals from the external camera 112 to the gate array 26, and FIG. 9 (4) shows transfer from the gate array 26 to the image memory 24 via the digital bus 28. It is a timing chart which shows. In the first embodiment, image data is transferred from the buffer 22b of the CPU 22 to the image memory 24 via the digital bus 28 in the idle time of the digital bus 28, and similarly, the image is transferred from the gate array 26 via the digital bus 28. Transfer to the memory 24.

With reference to FIG. 10, processing of image capture and decoding in the information code reader 10 of the first embodiment will be described. FIG. 10A is an explanatory diagram of processing of image capture and decoding in the prior art. In the prior art, after an image is captured by an internal camera and an external camera, the image of the internal camera and the image of the external camera are decoded.

FIG. 10B is an explanatory diagram for processing of image capture and decoding in the information code reader 10 of the first embodiment.
In the first embodiment, image capture and decoding are performed simultaneously. That is, the image captured by the external camera is decoded while the image is captured by the internal camera, and the image captured by the internal camera is decoded while the image is captured by the external camera. For this reason, the decoding time of the image of the internal camera can be shortened by T1 and the decoding time of the image from the external camera can be shortened by T2 with respect to the conventional method shown in FIG.

This processing timing will be further described with reference to FIGS.
FIG. 11A and FIG. 11B are timing charts showing the relationship between image data transfer and decoding.
In FIG. 11A, (3) shows transmission of the image signal from the internal camera to the buffer 22b of the CPU 22 and transmission of the image signal from the external camera to the gate array 26, and (4) shows the buffer 22b. FIG. 6 shows the transfer from the gate to the image memory 24 via the digital bus 28 and the transfer from the gate array 26 to the image memory 24 via (5). A decoding process in which an image is acquired from the memory 24 via the digital bus 28 is shown. In the first embodiment, as described above, the image data is continuously acquired, the image data is intermittently transferred to the image memory 24 via the digital bus 28, and the CPU 22 decodes using this idle time. I do. For this reason, acquisition of image data and decoding can be performed simultaneously.

In the first embodiment, in order to transfer image data intermittently to the image memory 24 and perform decoding using this idle time, the decoding is temporarily stopped (interrupted) before intermittent transfer, and decoded after transfer. To resume. Here, FIG. 11B shows a case where image transfer and decoding are shared. If decoding is temporarily stopped and decoding and data transfer overlap, that is, if the use of the digital bus 28 is shared, there is a possibility that image data may be lost.

FIG. 12 is a timing chart showing the relationship between the transfer period and transfer time of image data. In the figure, (3) shows the transfer of the image signal from the internal camera to the buffer 22b of the CPU 22 and the transfer of the image signal from the external camera to the gate array 26. (4) shows the digital bus 28 from the buffer 22b. And transfer to the image memory 24 via the digital bus 28 from the gate array 26. If the amount of image data stored in the buffer 22b and the gate array 26 is reduced and the transfer cycle is shortened, the transfer time is shortened. Conversely, the amount of image data stored in the buffer 22b and the gate array 26 is increased and the transfer cycle is extended. Then, the transfer time becomes long.

In the first embodiment, the decoding process is divided into blocks (steps) as shown in FIG. 13 in order to allow the decoding process to be interrupted. That is, it is divided for each process that can be interrupted (the minimum processing unit of the decoding process that can be divided). Then, the processing time at each step is stored, and the interruption timing is determined based on the processing at the longest step.

Furthermore, in the first embodiment, in order to interrupt the decoding process, a notification signal is output from the gate array 26 side to the CPU 22 side when the buffer size set in advance before the image data reaches the maximum buffer capacity, The CPU 22 detects the buffer size set in the buffer 22b. FIG. 14A shows the structure of the buffer 22 b of the CPU 22. When the buffer 22b composed of 32 bytes detects that the accumulation of image data has reached n1 (= 16 bytes), it sets a detection flag (setting the detection flag is called a notice from the CPU 22 to the CPU 22 for convenience) Decoding interruption processing is started. Similarly, FIG. 14B shows the structure of the buffer 26 b of the gate array 26. When the buffer 26b composed of 32 bytes detects that the accumulation of the image data has reached n2 (= 16 bytes), it outputs a notification for starting the decoding interruption process to the CPU 22 side.

Further, in the first embodiment, the above-described decoding takes the longest time, and even if the decoding is interrupted after the notification at n1 (= 16 bytes) and n2 (= 16 bytes), it takes the longest time. If the maximum buffer capacity (32 bytes) is reached before the process is interrupted, the buffer capacity is increased. That is, the capacity of the buffer 22b of the CPU 22 is increased from 32 bytes shown in FIG. 14A to 36 bytes as shown in FIG. 14C. Similarly, the capacity of the buffer 26b of the gate array 26 is shown in FIG. 14B. Increase from 32 bytes to 36 bytes as shown in FIG.

Image storage and transfer processing in the gate array 26 of the first embodiment described above will be described with reference to the flowchart of FIG. The image storage and transfer processing in the gate array 26 is similarly performed in the buffer 22b of the CPU 22, but only the gate array 26 will be described here.
First, accumulation of image data sent from the external camera 112 in the buffer 26b is started as described above with reference to FIG. 14B (S52). Then, it is determined whether a predetermined timing (n2 = 16 bytes) has been reached (S54). When the predetermined timing is reached (S54: Yes), a completion notice is notified to the CPU 22 side (S56). When the image data reaches 32 bytes and the accumulation is completed (S58: Yes), it is determined whether the digital bus 28 is used for image transfer of the buffer 22b from the CPU 22 side (S60), and the buffer from the CPU 22 side is determined. When the image transfer of 22b is in progress (S60: No), and when the image transfer of the buffer 22b from the CPU 22 side is not in progress (S60: Yes), the image data is as described above with reference to FIG. 9 (2). Then, the image data is transferred to the image memory 24 via the digital bus 28 (S62), and the completion of the transfer is notified to the CPU 22 side (S64).

Next, decoding processing on the CPU 22 side will be described with reference to the flowchart of FIG.
When the notification of the end of the image data transfer described above is received (S72: Yes), the decoding steps (Step A, Step B,... Step X) described above with reference to FIG. 13 are performed (S74). The time required for each step is stored (S76). For example, Step A = 3 ms, Step B = 6 ms,. Then, it is determined whether there is a notification of completion notice from the gate array 26 and in the internal processing of the CPU 22 (S78). Until there is a completion notice (S78: No), it is determined whether the decoding is completed (S82). Until the decoding is completed (S82: No), the process returns to S74 and the processing of each step is continued. Here, when there is a notice of completion notice from the gate array 26 or in the internal processing of the CPU 22 (S78: Yes), the decoding is interrupted when the step being processed is completed (S80), and the process returns to S72. Wait until the data transfer is completed, and resume decoding after the transfer is completed (S74).

When the above processing is repeated and decoding is completed (S82: Yes), the longest time step among the processing times of each step stored in S72 described above is specified (S84). Here, it is assumed that Step B is the longest in 6 ms. Whether or not the longest time (6 ms) is longer than the free time from the buffer transfer to the next transfer, specifically, with reference to FIGS. 14A and 14B. It is determined whether the transfer of the next image data is not hindered even if the decoding process is interrupted after completion of the processing of Step B, which has already been started, after the notice of notice at n1 and n2 is completed (S86). ). Here, if the longest time is longer than the free time from the buffer transfer to the next transfer (S86: Yes), as described above with reference to FIGS. 14C and 14D, the CPU 22 The capacities of the buffer 22b and the buffer 26b of the gate array 26 are increased (S88).

On the other hand, if the longest time is shorter than the free time until the next transfer (S86: No), it is determined whether the longest time is very short relative to the free time until the next transfer (S92). ). If it is not very short (S92: No), the process is terminated without adjusting the buffer capacity. On the other hand, if it is very short (S92: Yes), the buffer capacity is reduced (S94). Specifically, as described above with reference to FIGS. 14C and 14D, the capacity of the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26 is changed from 36 bytes to FIGS. Reduce to 32 bytes as shown in B).

In the first embodiment, the step of the longest time in the processing time is specified every time decoding is performed. The step of the longest time in the processing time differs depending on the reading condition, the type of information code, and the like. Because it changes itself. In the first embodiment, when the same information code type is read under the same conditions as the previous time, the processing can proceed smoothly.

In the information code reader 10 of the first embodiment, the image data stored in the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26 are decoded during the pause time during which they are intermittently sent to the image memory 24 via the digital bus 28. Thus, it is possible to simultaneously store and decode the image data sent from the internal camera 12 and the external camera 112 in the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26, and from the internal camera 12 and the external camera 112. The time required for capturing and decoding the image can be shortened. Here, even when the capacity of the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26 is the longest processing time for processing the divided blocks of the decoding process, the images from the internal camera 12 and the external camera 112 are used. Adjust so that data accumulation can continue. Further, when the image data from the internal camera 12 and the external camera 112 in the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26 reach a preset buffer size before reaching the maximum buffer capacity, the accumulation is almost complete. This is notified to the CPU 22. After receiving the notification, the CPU 22 interrupts the decoding after the processing of at least one block among the divided decoding blocks constituting the decoding process, thereby accumulating in the buffer 22b of the CPU 22 and the buffer 26b of the gate array 26. The image data is decoded during the pause time in which the image data is intermittently sent to the image memory 24 via the digital bus 28, so that the intermittent feed for holding the image data in the image memory 24 via the digital bus 28 is not hindered. it can.

In the information code reader 10 according to the first embodiment, since the gate array 26 stores the image data from the external camera 112 in the gate array 26, the image data from the external camera 112 is stored in the gate array 26. Can be temporarily stored and sent intermittently via the digital bus 28 and held in the image memory 24. For this reason, the image data stored in the gate array is decoded in the pause time during which the image data is intermittently sent to the image memory 24 via the digital bus 28, whereby the image data sent from the external camera 112 is stored in the gate array. Thus, decoding can be performed at the same time, and the time required for capturing and decoding an image from the external camera 112 can be shortened.

The information code reader 10 according to the first embodiment simultaneously performs image capturing and decoding even when an image from the internal camera 12 is processed without an external camera attached. This operation will be described with reference to FIG.
FIG. 17A is an explanatory diagram for the processing of image capture and decoding in the prior art. In the prior art, after an image is captured by the internal camera, the image of the internal camera is decoded. FIG. 17B is an explanatory diagram for processing of image capture and decoding in the information code reader 10 of the first embodiment. In the first embodiment, image capture and decoding are performed simultaneously. That is, while the image is captured by the internal camera, the image captured by the previous internal camera is decoded. For this reason, the decoding time of the image of the internal camera can be shortened as compared with the prior art method shown in FIG.

[Second Embodiment]
An information code reader 10 according to a second embodiment of the present invention will be described with reference to FIGS. Since the mechanical configuration of the information code reader 10 of the second embodiment is the same as that of the first embodiment, description thereof is omitted.
In the first embodiment described above, the buffer capacity is adjusted according to the longest time of the divided steps of decoding. On the other hand, in the second embodiment, the buffer capacity is fixed, and the timing of the notification signal (completion notice) is adjusted according to the longest step time. FIG. 18A shows the structure of the buffer 22 b of the CPU 22. For example, when it is detected that the accumulation of image data has reached n1 (= 16 bytes), the buffer 22b configured by 32 bytes sets a detection flag (setting the detection flag is referred to as a notice from the CPU 22 to the CPU 22 for convenience). The decoding interruption process is started. Similarly, FIG. 18B shows the structure of the buffer 26 b of the gate array 26. When the buffer 26b composed of 32 bytes detects that the accumulation of the image data has reached n2 (= 16 bytes), it outputs a notification for starting the decoding interruption process to the CPU 22 side.

In the second embodiment, in the above-described step that takes the longest time for decoding, even if the decoding is interrupted after the notification at n1 (= 16 bytes) and n2 (= 16 bytes), the processing in the longest step is interrupted. Before reaching the maximum buffer capacity (32 bytes), the timing of the notification signal (completion notice) is advanced. That is, as shown in FIG. 18C, when the accumulation of the image data in the buffer 22b of the CPU 22 reaches n1 (= 14 bytes), a notification signal (completion notice) is output. Similarly, as shown in FIG. 18D, when the accumulation of image data in the buffer 26b of the gate array 26 reaches n2 (= 14 bytes), a notification signal (completion notice) is output.

Decoding processing on the CPU 22 side of the second embodiment will be described with reference to the flowchart of FIG.
The processing from S72 to S80 is the same as that of the first embodiment described above with reference to FIG.
When the decoding is completed (S82: Yes), the step with the longest time is specified in the processing time of each step stored in S72 described above (S84). Here, it is assumed that Step B is the longest in 6 ms. Then, whether or not the longest time (6 ms) is longer than the free time from the buffer transfer to the next transfer, specifically, with reference to FIGS. 18 (A) and 18 (B). It is determined whether the transfer of the next image data is not hindered even if the decoding process is interrupted after completion of the processing of Step B, which has already been started, after the notice of notice at n1 and n2 is completed (S86). ). Here, when the longest time is longer than the free time from the buffer transfer to the next transfer (S86: Yes), the completion is completed as described above with reference to FIGS. 18C and 18D. The notification timing of the advance notice is advanced (S88).

On the other hand, if the longest time is shorter than the free time until the next transfer (S86: No), it is determined whether the longest time is very short relative to the free time until the next transfer (S92). ). If it is not very short (S92: No), the process ends without adjusting the notification timing of the completion notice. On the other hand, if it is very short (S92: Yes), the notification timing of the completion notice is delayed (S94). Specifically, as described above with reference to FIGS. 18C and 18D, when the accumulation of image data in the buffer 22b of the CPU 22 reaches n1 (= 14 bytes), a notification signal (completed) Assume that a notification signal (completion notice) is output when the accumulation of image data in the buffer 26b of the gate array 26 reaches n2 (= 14 bytes). As described above with reference to FIGS. 18 (A) and 18 (B), when n1 (= 16 bytes) is reached, a notification signal (completion notice) is reached when n2 (= 16 bytes) is reached. Adjust to output.

[Third embodiment]
An information code reader 10 according to a third embodiment of the present invention will be described.
In the first and second embodiments, when there is a notification signal (completion notice), the decoding is interrupted when the step process being executed is completed. On the other hand, in the third embodiment, the decoding process is continued within a range that does not hinder the transfer of image data.

Decoding processing on the CPU 22 side of the third embodiment will be described with reference to the flowchart of FIG.
The processes from S72 to S76 and S82 to S94 are the same as those in the first embodiment described above with reference to FIG.
Here, when the completion notice is made (S78: Yes), the processing of the next step is completed before the transfer of the image data following the step currently in progress based on the processing time of the step stored in S76. It is determined whether it can be performed (S102). Here, when the transfer can be completed before transfer (S102: Yes), the next step is performed (S104). Decoding is performed to the extent possible by repeating the processing of S102 and S104, and if the next step processing cannot be completed before transfer of image data (S102: No), decoding is completed by finishing the processing of the step in progress. The process is interrupted (S80).

In the third embodiment, there is an advantage that the decoding process can proceed using the digital bus to the maximum available time.

In the above-described embodiment, an example in which only one external camera is connected has been illustrated. However, the configuration in which image capturing and decoding are simultaneously performed according to the present invention can also be applied when two or more external cameras are attached.

It is explanatory drawing of the information code reader which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure outline | summary of the information code reader of 1st Embodiment. It is explanatory drawing of a structure of an internal camera and an external camera. It is a block diagram which shows the circuit structure of a main circuit. It is explanatory drawing which shows the connection of D flip-flop which detects the connection of an external camera. It is a graph which shows the state transition of D flip-flop. FIG. 7A is an explanatory diagram showing the allocation of the image memory when the external camera is not connected to the image memory, and FIG. 7B is an explanatory diagram showing the allocation of the image memory when the external camera is connected. It is a flowchart which shows the allocation process of the memory for images in CPU. FIG. 9 (1) is a timing chart showing transmission of an image signal from the internal camera to the CPU buffer, and FIG. 9 (2) is a timing showing transfer from the buffer to the image memory via the digital bus. FIG. 9 (3) is a timing chart showing transmission of image signals from the external camera to the gate array, and FIG. 9 (4) is a timing chart showing the image memory from the gate array to the image memory via the digital bus. It is a timing chart which shows transfer. FIG. 10A is a diagram for explaining processing of image capturing and decoding in the prior art, and FIG. 10B is a diagram for describing processing of image capturing and decoding in the information code reader 10 of the first embodiment. FIG. FIG. 11A and FIG. 11B are timing charts showing the relationship between image data transfer and decoding. 5 is a timing chart showing a relationship between a transfer period and transfer time of image data. It is explanatory drawing which shows the division | segmentation of the decoding process of 1st Embodiment. 14A and 14C are explanatory diagrams showing the structure of the CPU buffer, and FIGS. 14B and 14D are explanatory diagrams showing the structure of the gate array buffer. 4 is a flowchart showing image accumulation and transfer processing in the gate array and CPU of the first embodiment. It is a flowchart which shows the decoding process in CPU of the information code reading apparatus which concerns on 1st Embodiment. FIG. 17A is a diagram for explaining processing of image capturing and decoding in the prior art, and FIG. 17B is a diagram for explaining processing of image capturing and decoding in the information code reader 10 of the first embodiment. FIG. FIGS. 18A and 18C are explanatory views showing the structure of the CPU buffer in the information code reader of the second embodiment, and FIGS. 18B and 18D show the gate array. It is explanatory drawing which shows the structure of a buffer. It is a flowchart which shows the decoding process in CPU of the information code reader which concerns on 2nd Embodiment. It is a flowchart which shows the decoding process in CPU of the information code reader which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Information code reader 12 ... Internal camera 20 ... Main circuit 22 ... CPU
22b ... buffer 24 ... image memory 26 ... gate array 26b ... buffer 28 ... digital bus 112 ... external camera

Claims (3)

An information reading apparatus capable of decoding an image captured by an internal camera and decoding an image captured by a connected external camera,
First image data storage means for storing image data sent from the internal camera in a first buffer;
Second image data storage means for storing image data sent from the external camera in a second buffer;
Image data transfer means for intermittently sending the image data stored in the first buffer and the second buffer via the bus line and holding them in the image memory;
Decoding means for obtaining and decoding the image data held in the image memory via the bus line;
The capacity of the first buffer and the second buffer is divided into blocks for decoding processing by the decoding means, and the first image data storage is performed even in the longest processing time among the processing times for processing the divided blocks. Buffer capacity adjusting means for adjusting so that image data from the internal camera and the external camera can be continuously stored by the means and the second image data storage means :
First notification means for notifying the decoding means when image data from the internal camera in the first buffer reaches a preset buffer size before reaching the maximum buffer capacity;
Second notification means for notifying the decoding means when the buffer size set in advance before the image data from the external camera in the second buffer reaches the maximum buffer capacity is provided :
The decoding means interrupts decoding after processing at least one of the divided blocks constituting the decoding processing after receiving the notification from the first notification means and the second notification means And
The processing for transferring the image data to the image memory via the bus line by sending the image data stored in the first buffer and the second buffer to the image memory via the bus line during the interruption is the maximum buffer capacity. Start within
The information reading apparatus, wherein the decoding means resumes decoding after the transfer is completed. An information reading apparatus capable of decoding an image captured by an internal camera and decoding an image captured by a connected external camera,
First image data storage means for storing image data sent from the internal camera in a first buffer;
Second image data storage means for storing image data sent from the external camera in a second buffer;
Image data transfer means for intermittently sending the image data stored in the first buffer and the second buffer via the bus line and holding them in the image memory;
Decoding means for obtaining and decoding the image data held in the image memory via the bus line;
First notification means for notifying the decoding means when image data from the internal camera in the first buffer reaches a preset buffer size before reaching the maximum buffer capacity;
Second notification means for notifying the decoding means when the buffer size set in advance before the image data from the external camera in the second buffer reaches the maximum buffer capacity;
The decoding means interrupts decoding after processing at least one of the divided blocks constituting the decoding process after receiving the notification from the first notification means and the second notification means;
By sending the image data stored in the first buffer and the second buffer to the image memory via the bus line, the processing for transferring the image data to the image memory via the bus line becomes the maximum buffer capacity. Start in time;
The information reading apparatus characterized in that the decoding means restarts decoding after the transfer is completed. The first buffer is a buffer of a CPU constituting the decoding means;
3. The information reading apparatus according to claim 1, wherein the second buffer is configured by a gate array.

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