JP4548873B2 - Dry ashing method for ashing TiN layer without isotropic etching - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for ashing a via in a semiconductor device, and more particularly to a method for ashing a via without excessive etching of a via or via base layer.
[0002]
[Prior art]
The use of TiN as a base layer for vias used to interconnect tungsten plugs is becoming increasingly common. This via or via means a structure including a recess (hole or groove). However, one problem with using TiN is that after etching the vias, the resist must be removed from the periphery of the vias, and the polymer residues that occur along the via base and via sidewalls are removed. It is a point that must be done. Nevertheless, in a normal ashing process, the TiN layer is isotropically etched, so that the via resistance is undesirably high.
[0003]
In the process of solubilizing polymers formed from resists in vias, halogens (halogens such as fluorine or chlorine) are generally used in a plasma environment to halogenate metals and polymers. is necessary. However, TiN is rapidly isotropically etched in the presence of fluorine, especially at temperatures higher than 50 ° C. where the etching rate increases rapidly. This rapid etching occurs even when a small amount of fluorine gas is used. In processes where it is desired to solubilize the polymer and other residues resulting from etching, a substantial amount of fluorine-containing gas (eg, CF ₄ or NF ₃ ) is typically used. With the high concentration of fluorine generally required to solubilize the resist at high temperatures, the TiN etch rate is unacceptably high.
[0004]
[Problems to be solved by the invention]
The present invention provides a method of using a stripping / ashing process to remove polymer from the via base and sidewalls and to remove resist from the via periphery without penetrating and etching into the TiN base layer. The task is to do.
[0005]
[Means for Solving the Problems]
The present invention includes an ashing process that ashes resist and sidewall polymer during the RIE plasma ashing process using water vapor without isotropically etching the base layer in the via. To be included. This process preferably includes oxygen, fluorine gas (preferably NF ₃ ) and water vapor and optionally a forming gas such as N ₂ H ₂ .
The process is preferably used for vias having a titanium nitride (TiN) base layer. For such vias, the process makes the residue soluble in deionized (DI) water, so that after ashing, the wafer can be further cleaned using a rinse process. It has been found that water vapor suppresses the etching of the TiN layer during the ashing process, and the higher the temperature, the more water vapor is used. For example, at a temperature of about 200 ° C., about 12% water vapor was used to make the resist and residue soluble while etching about 40% or less of the TiN base layer in the via.
[0006]
According to the method of the present invention, ashing can be performed without using a wet chemical solvent that is costly to obtain and difficult to dispose, and provides good TiN selectivity, good contact resistance value, excessive TiN loss due to isotropic etching is eliminated and the polymer and resist can be completely removed. Other features and advantages will be apparent from the following detailed description, as well as from the drawings and claims.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, vias are etched after the stack 10 is formed. The laminated body 10 includes a conductive layer 12 such as aluminum, an antireflection film (ARC) 14 such as titanium nitride (TiN), a dielectric layer 16 such as TEOS, PSG or polyamide, and exposure and development. And a photoresist layer 18 having an opening 20 formed therein. An etching process, such as a commonly known fluorine-based etching process, was performed to form the via opening and form a via as shown in FIG. The etch depth can vary depending on the process used, the etching equipment and the control of the equipment. The TiN base layer has been etched away by a thickness of several hundred angstroms, or substantially no TiN has been etched away as shown, or the etching process penetrates the TiN into a conductive layer. It may have entered and perforated.
[0008]
As shown in FIG. 2, the etching process leaves contaminated resist 18a and sidewall polymer 22. The sidewall polymer 22 includes a photoresist contaminated with fluorine and possibly a small amount of titanium or aluminum, depending on the etch depth of the via etch process. In the case of etching through the TiN layer, the sidewall polymer has additional and more difficult to handle contaminants such as aluminum from the underlying conductive layer and the composite AlF ₄ .
[0009]
As noted above, wet (wet "wet") etching has considerable practical and environmental drawbacks, while typical dry ashing using fluorine is unacceptable for etching TiN layers, It is common to make the resist and residue soluble after removing all of the TiN layer in the via base.
[0010]
It has been found that when the RIE ashing process is performed by adding water vapor, the etching of the TiN layer can be greatly suppressed, but still a good ashing rate between the resist and the residue can be provided. FIG. 3 shows a gas flow with an O ₂ gas flow rate of 800 sccm, an NF ₃ gas flow rate of 120 sccm, and an H ₂ O flow rate of 150 sccm at a temperature of 200 ° C. of the table (on which the wafer is placed). The etching rate of TiN according to the process performed is shown. The vertical line in the graph indicates that the residue was substantially removed at 28 seconds. At fluorine concentrations where the polymer residue resulting from etching is readily achieved within 30 seconds, the etching rate is approximately 200 liters / min. In this example, it was observed that the loss of TiN was only about 80% in the time required to make the polymer residue completely soluble. Without adding water, a low concentration of NF ₃ can be used to make the residue completely soluble, but the TiN layer will be over-etched. Thus, according to this process, both stripping bulk surface resist and solubilizing the sidewall polymer in an RIE ashing process using O ₂ , fluorine, chemical gas and water vapor. It becomes possible.
[0011]
The above process does not eliminate etching of the entire TiN, but reduces such TiN etching to an acceptable level, for example, a loss of about 50% or less (and preferably a lower loss). If water vapor is not used, the resist and residue are made soluble with oxygen and fluorine gas after TiN is completely etched away.
[0012]
The ashing chamber may be used exclusively for the RIE process or it may be a microwave-RF combined device as described in US Pat. No. 5,226,056 (Kikuchi). The description of this US patent is specifically incorporated herein by reference for all purposes. Water vapor is supplied into the chamber through the inlet separately from the other gases. The water vapor should not be introduced in a single stream into the center of the wafer, but rather the water vapor is supplied around the chamber and preferably evenly distributed around the wafer being processed. It is preferable to avoid excessive concentrations of water vapor supplied at any location.
[0013]
In the above-described method, it was found by spectroscopic analysis that in the presence of H ₂ O, atomic fluorine is very little or not detected at all. However, there is a very strong H peak. This is considered to occur because fluorine released during discharge reacts with water to form HF, and means that an environment rich in HF exists by adding water. When a similar plasma is used without water present, a high concentration of fluorine atoms is detected. However, solubilization is performed by reaction with HF or F. This is because the fluorine atoms that are temporarily present in the plasma and in the region of the polymer residue react very rapidly, keeping very low and undetectable concentrations of fluorine atoms in the spectrum. Because. Although not wishing to be limited to any particular theory, it is believed that the added H ₂ O can suppress the etching of TiN because fluorine is thus converted to HF.
[0014]
The microwave discharge can occur simultaneously in a microwave applicator of a dual plasma capable process chamber of an apparatus of the type described above. In this case, a large amount of fluorine is observed in the spectrum. This is because the amount of additional fluorine atoms generated in the microwave discharge is higher than the water concentration, so that a sufficient amount of free fluorine is present in the dual plasma state. Suggests that HF can be adsorbed on the TiN surface, thereby inhibiting the TiN etching process.
[0015]
If the via etch process etches hundreds of angstroms of TiN and deposits TiF ₄ and sputtered TiN on the wafer surface, the sidewall polymer inside the via is completely water soluble. Nevertheless, the surface material reacts differently from RIE plasma, resulting in a residue that is not completely water soluble. To address such problems for the surface, the initial short RIE plasma ashing with O ₂ removes the surface polymer from the etching process and then a residual resist on the surface where a small amount of insoluble residue remains. It has been found that ashing becomes easier. The short RIE plasma process using O ₂ (preferably containing no halogen) is followed by a bulk RIE ashing process using O ₂ , halogen and water vapor as described above. The third ashing process in microwave mode then uses the same gas as the gas in the second bulk strip process, but a large amount of free fluorine is available for surface treatment to obtain complete surface cleanliness be able to. In this example, the bulk RIE ashing process succeeded in solubilizing the residue on the via sidewalls.
[0016]
The optimal process for any application also depends on the via configuration. For example, vias with high aspect ratios and small diameters tend to have lower energy and tend to have less intense ion bombardment on the polymer surface due to the charging effect on the wafer surface. When properly processing the sidewall polymer and the base polymer, the process pressure can be kept lower and the RF power can be higher, thereby increasing the ion energy and relative to the surface. The charging effect can be reduced. The lower part of the via contains a large amount of polymer and contains a large amount of sputtered TiN or Al derived from the base of the via, so the optimum plasma state for processing these lower parts is This is slightly different from the case near the via surface.
[0017]
In the stripping process of the present invention, it can be guaranteed that by adjusting the parameters, not only the residue on the entire inner surface of the via, but also the residue on the surface of the oxide will be completely soluble. it can.
[0018]
In a generalized example, the gas flow rate is in the following range.
[0019]
O _2: 400-800sccm
H ₂ N _2: 10-60sccm
NF _3: 100-300sccm
H ₂ O: 100-300sccm
Therefore, the percentage is as follows.
[0020]
O _2: 30-80%
H ₂ N ₂ : 1-10%
NF ₃ : 8-37%
H ₂ O: 8-37%
These combined steps are sensitive to via diameter dimensions and may therefore vary, and for specific vias and etching processes, pressure, power, temperature and You may adjust all the time. The temperature of the table on which the wafer is placed is around 240 ° C. If the temperature is higher, a greater amount of water vapor is used, whereas if the temperature is lower, a lower proportion of water vapor is used. Typically, the pressure is 1 Torr or less and the power is at least 100W.
[0021]
It is known to use various halogens such as CF ₄ and S ₂ F ₆ for plasma ashing, but by using NF ₃ , the required electric energy can be compared with other halogens. It was found that it can be reduced by 50%, and the ashing rate can be increased by 30% or more.
[0022]
【Example】
In this example, the first process was an O ₂ RIE ashing process, with power of 500 W, pressure of 0.2 Torr, time of 20 seconds, and O ₂ flow rate of 800 sccm. This process removed the polymerization residue on the resist surface and served as a partial strip that removed the surface material but did not reach the substrate. This partial strip avoids ion bombardment of the final residue with oxygen which forms undesirable oxides.
[0023]
The second RIE ashing process was performed by combining gases having the following gas flow rates.
[0024]
(1) O ₂ : 800 sccm (73%)
(2) NF ₃ : 135 sccm (12%)
(3) H ₂ O: 135 sccm (12%)
(4) H ₂ N ₂ : 30 sccm (3%)
The wafer stage was set to 50 ° C., the power was set to 500 W, the pressure was set to 0.45 Torr, and the time was 90 seconds.
[0025]
This particularly typical process is for 6 inch (150 mm) wafers, but can be modified for other wafer sizes such as 200 mm or 300 mm by increasing gas flow rate and power density. Can be used.
[0026]
Since the second step is performed in a high oxygen flow, it serves as a step of stripping the bulk resist at a relatively high strip rate (> 1 μ / min). This process is different from the process of first ashing and then making the remaining residue soluble without using an ashing step, because the resist and the residue are made ashable at the same time.
[0027]
The etching apparatus used in the process was poor in selectivity with respect to TiN having an initial thickness of about 1200 mm. About 500% of TiN was etched (about 40%). The above process succeeded in making all the residues water-soluble.
[0028]
Although the particular embodiment has been described and the method of the invention has been described by way of example, it is understood that modifications may be made without departing from the scope of the invention as defined by the appended claims. it is obvious. For example, as described above, other halogens such as CF ₄ and S ₂ F ₆ can be used, and other parameters can be varied for a particular process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a stacked body before a via is etched.
FIG. 2 is a cross-sectional view of an etched via.
FIG. 3 is a graph showing the TiN etching rate of one example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Laminated body 12 Conductive layer 14 Antireflection film 16 Dielectric layer 18 Resist layer 18a Contamination resist layer 20 Opening part 22 Polymer

Claims (14)

A laminate comprising a titanium nitride (TiN) base layer on a conductive base layer, a dielectric layer on the TiN layer, and a resist defining an opening for forming a via on the dielectric layer is formed by TiN. Using a plasma that etches to a layer and contains oxygen, a halogen-containing gas and water vapor, the amount of halogen being sufficient to render substantially all of the polymer in the via water soluble. Ashing the resist residue in the via by a reactive ion etching (RIE) ashing process , the ashing comprising ashing the resist residue while etching the TiN layer in a range not exceeding 50% dry ashing method to. 2. The dry ashing method according to claim 1 , wherein the etching includes etching until reaching the TiN layer, but etching so as not to enter the TiN layer. 2. The dry ashing method according to claim 1 , wherein the etching includes etching a part of the TiN layer instead of all of the TiN layer.   After the etching and before the ashing, the method further includes ashing the semiconductor device by performing an RIE ashing process without using water vapor and a halogen-containing gas, but using oxygen and a gas containing halogen. The dry ashing method according to claim 1. 5. The dry process according to claim 4 , further comprising the step of ashing the semiconductor device by performing a downstream microwave process using oxygen, water vapor and a halogen-containing gas after at least one of the ashing. Ashing method.   2. The dry ashing method according to claim 1, further comprising a step of ashing the semiconductor device by performing a downstream microwave process using oxygen, water vapor, and a halogen-containing gas after the ashing. A laminate comprising a titanium nitride (TiN) base layer on a conductive base layer, a dielectric layer on the TiN layer, and a resist defining an opening for forming a via on the dielectric layer. Etching the via and then ashing the via to remove residues from the via sidewalls of the semiconductor device, the ashing comprising 30-80% oxygen, 10-50% fluorine-containing gas, And forming a 10-50% water vapor RF plasma so that the ashing substantially completely solubilizes the residue while etching less than about 50% of the conductive base layer in the via. The dry ashing method is characterized by being performed. 8. The dry ashing method according to claim 7, wherein the ashing includes ashing using about 73% oxygen, 12% fluorine-containing gas, and 12% water vapor. 8. The dry ashing method according to claim 7, wherein the water vapor is distributed and introduced into the chamber. 8. The dry ashing method according to claim 7 , wherein oxygen is used before the ashing, but the RIE ashing process is performed without using a fluorine-containing gas and water vapor. The dry ashing method according to claim 10 , further comprising performing a downstream microwave ashing process after the second ashing process. 12. The dry ashing method according to claim 11 , wherein the downstream microwave process uses the same gas as in the second RIE ashing process. 8. The dry ashing method according to claim 7 , further comprising performing a downstream microwave ashing process after the ashing process. 14. The dry ashing method according to claim 13 , wherein oxygen, fluorine gas, water vapor and, if necessary, chemical gas are used in the downstream microwave ashing process.

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