JP4540735B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a MOS (Metal Oxide Semiconductor) type field effect transistor and a method for manufacturing the same.

  In a MOS field effect transistor (MOS transistor), increasing the drain current, which is a drive current, is one method for improving the performance of the MOS transistor. There are several factors that determine the drain current, one of which is carrier mobility. It is difficult to change the carrier mobility because it is roughly determined by the substrate material, but changing the lattice spacing of the substrate atoms changes the scattering probability and effective mass of the carrier, thereby changing the carrier mobility. I know that is possible.

  In a substrate in which Si is formed on SiGe, since the lattice spacing of SiGe is larger, the lattice spacing of Si in the upper layer is expanded due to the influence. A substrate having such a wide lattice spacing of silicon is called a “strained silicon substrate”. According to the strained silicon substrate, since the mobility of the channel is improved as compared with a normal silicon substrate, the drain current of the MOS transistor formed thereon increases (for example, Non-Patent Documents 1 and 2).

  However, the strained silicon substrate has a problem caused by using SiGe as a substrate material. For example, generation of crystal defects due to SiGe, deterioration of surface roughness, increase in substrate temperature due to poor thermal conductivity of SiGe, short-circuit in a p-channel MOS transistor via a band discontinuous surface at the interface between SiGe and Si. This is a process problem due to an increase in channel effect and inability to sufficiently perform heat treatment (non-adaptability to STI (Shallow Trench Isolation) process, inability to perform sufficient activation annealing, etc.). Therefore, there are still many problems to overcome in order to apply a strained silicon substrate to an actual LSI.

  There is also a technique for changing the lattice spacing of silicon in the channel region of the MOS transistor by applying stress to the silicon substrate without using SiGe (for example, Patent Document 1).

  For example, when a tensile stress is generated in the channel region, the driving current increases in the n-channel MOS transistor (nMOS transistor), but the driving current decreases in the p-channel MOS transistor (pMOS transistor). Conversely, when compressive stress is generated in the channel region, the driving current of the pMOS transistor increases and the driving current of the nMOS transistor decreases.

JP 2002-93921 A (page 3-6, FIG. 1-19)

T.A. T. Welser et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon / Relaxed Silicon-Germanium Structures”, International Electron Device Meeting 1992, 1992 , P. 1000 T.A. T. Mizuno et al., “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology ”, International Electron Device Meeting 1999, 1999, p. 934

  As described above, since there are still many problems in using a strained silicon substrate using SiGe in order to improve the performance of a MOS transistor, a simpler method is desired.

  On the other hand, according to Patent Document 1, the channel performance of the MOS transistor can be improved without using a strained silicon substrate by generating stress in the gate electrode and applying the stress to the channel region of the silicon substrate. .

  As described above, when a tensile stress is applied to the channel region, the driving current of the nMOS transistor increases, but conversely, the driving current of the pMOS transistor decreases. On the other hand, when compressive stress is applied to the channel region, the driving current of the pMOS transistor increases, and conversely, the driving current of the nMOS transistor decreases. Therefore, it is necessary to make the stress generated at least different between the nMOS transistor and the pMOS transistor.

  Therefore, in Patent Document 1, it is necessary to make the material of the gate electrode and the film formation temperature different between the nMOS transistor and the pMOS transistor. As a result, the gate electrode of the nMOS transistor and the gate electrode of the pMOS transistor cannot be formed in the same process, which complicates the manufacturing process.

  The present invention has been made to solve the above-described problems, and applies a tensile stress only to the channel region of a desired MOS transistor to improve carrier mobility, and to complicate the manufacturing process. An object of the present invention is to provide a semiconductor device that can be suppressed and a manufacturing method thereof.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including at least an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate, and includes the following steps. A step of preparing a semiconductor substrate. Forming a gate insulating film on the semiconductor substrate; Forming a non-single-crystal silicon film on the gate insulating film; The non-single crystal silicon film was patterned to form a first gate electrode and the second gate electrode of the p-channel type MOS transistor of the n-channel type MOS transistor. Implanting n-type dopant ions having a mass number of 70 or more into the first gate electrode ; Implanting B ions into the second gate electrode; An insulating film is formed on the n-channel MOS transistor and the p-channel MOS transistor, and the first gate electrode made amorphous by the implantation of the n-type dopant ions and the B ions are implanted. Forming an insulating film covering the second gate electrode which has been made amorphous . Wherein while covering said an insulating film a first gate electrode and said second gate electrode, and facilities the heat treatment of the temperatures above 550 ° C. in a semiconductor substrate, by recrystallizing the first gate electrode, A compressive stress is left as internal stress in the first gate electrode, and a tensile stress of 3 × 10 ⁹ dyn / cm ² or more is applied to the channel region below the first gate electrode by the residual compressive stress. Recrystallizing the second gate electrode. Wherein after the heat treatment step, the first gate electrode and removing the insulating film formed on the second gate electrode. It said rear insulating layer is removed, the first gate electrode and forming a silicide layer on said second gate electrode surface.

According to the method for manufacturing a semiconductor device of the present invention, compressive stress can be left as internal stress on the gate electrode of an n-channel MOS transistor (nMOS transistor) , and tensile stress can be applied to the underlying silicon substrate. Therefore, the lattice spacing of that portion of the silicon substrate Ri spread, can improve the performance of the nMOS transistor improves carrier mobility definitive the nMOS transistor. Moreover, even when formed in the same process of the gate electrode of the gate electrode and the p-channel type MOS transistor of the nMOS transistor (pMOS transistor), in Rukoto with a difference in the mass of the ions implanted in accordance with the type of the gate electrode A strong compressive stress can be generated only in the gate electrode of the nMOS transistor , and the manufacturing process can be prevented from becoming complicated. In addition, since the insulating film over the gate electrode is removed after the heat treatment step, a silicide layer can be formed on the surface of the gate electrode.

6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. FIG. 6 is a stress distribution diagram in the cross section in the channel length direction of the nMOS transistor and the conventional nMOS transistor in the semiconductor device according to the first embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment.

<Embodiment 1>
The present inventors have found that when a heat treatment is applied to amorphous silicon into which a large amount of ions have been implanted, the volume of the silicon expands when the silicon is recrystallized and becomes polycrystalline silicon (polysilicon) by the heat treatment. I found it. Further, it was found that the expansion amount greatly depends on the mass of the implanted ions, and that the larger the mass (especially the mass number 70 or more), the greater the expansion. It was also confirmed that the larger the dose of implanted ions, the greater the expansion.

  1 to 9 are diagrams showing manufacturing steps of the semiconductor device according to the first embodiment. In these drawings, it is assumed that the left side in the drawing is a region where an nMOS transistor is formed (hereinafter “nMOS region”), and the right side in the drawing is a region where a pMOS transistor is formed (hereinafter referred to as “pMOS region”). To do.

  First, the element isolation film 11, the p well 12, and the n well 22 are formed on the silicon substrate 10 by a conventional method. Thereafter, a silicon oxide film 31 as a gate insulating film material is formed on them. Next, a non-single crystal (including amorphous and polycrystalline) silicon film 32 is formed as a gate electrode material on the silicon oxide film 31 (FIG. 1).

  Next, by patterning the non-single crystal silicon film 32 using a photolithography technique, the gate electrode 14 is formed on the p well 12 and the gate electrode 24 is formed on the n well 22 (FIG. 2).

  Thereafter, a resist mask 33 having an opening in the pMOS region is formed by using a photolithography technique. Then, using the resist mask 33 and the gate electrode 24 as a mask, a p-type dopant having a relatively small mass number such as B ions is implanted to form a p-type source / drain extension layer 26 a at a relatively shallow position in the n-well 22. (Figure 3). At this time, since ions are also implanted into the gate electrode 24, a part of the non-single-crystal silicon forming the gate electrode 24 becomes amorphous. However, since the mass number of the ions is relatively small, it becomes amorphous. The degree of is small.

  Next, a resist mask 34 having an nMOS region opened is formed by using a photolithography technique. Then, using the resist mask 34 and the gate electrode 14 as a mask, an n-type dopant having a mass number of 70 or more, such as As ions or Sb ions, is implanted into a relatively shallow position in the p-well 12. An n-type source / drain extension layer 16a is formed (FIG. 4). At this time, since ions having a relatively large mass number are also implanted into the gate electrode 14, part of the non-single-crystal silicon forming the gate electrode 14 becomes amorphous.

  Further, sidewalls 15 and 25 are formed on the side surfaces of the gate electrodes 14 and 24, and the silicon oxide film 31 is etched to form gate insulating films 13 and 23 under the gate electrodes 14 and 24, respectively (FIG. 5). ). At this time, the film formation temperature of the sidewalls 15 and 25 is set to be equal to or lower than the temperature (about 550 ° C.) at which recrystallization of silicon is started.

Subsequently, a resist mask 35 having an opening in the pMOS region is formed again. Then, using the resist mask 35, the gate electrode 24 and the sidewall 25 as a mask, a p-type dopant having a relatively small mass number such as B ions is implanted at a dose of 4 × 10 ¹⁵ / cm ² or more, and the comparison in the n-well 22 is performed. A p-type source / drain diffusion layer 26b is formed at a deep position (FIG. 6). Thereby, a p-type source / drain region 26 composed of the p-type source / drain extension layer 26a and the p-type source / drain diffusion layer 26b is formed. At this time, ions are also implanted into the gate electrode 24, and a part of the non-single-crystal silicon forming the gate electrode 24 becomes amorphous. The degree of conversion is small.

  Next, a resist mask 36 having an opening in a region for forming an nMOS transistor is formed. Then, using the resist mask 36, the gate electrode 14 and the sidewall 15 as a mask, an n-type dopant having a relatively large mass number such as As ion or Sb ion is implanted, and the n-type dopant is implanted at a relatively deep position in the p-well 12. A source / drain diffusion layer 16b is formed (FIG. 7). As a result, an n-type source / drain region 16 including the n-type source / drain extension layer 16a and the n-type source / drain diffusion layer 16b is formed. Again, since ions having a relatively large mass number are implanted into the gate electrode 14, the non-single-crystal silicon forming the gate electrode 14 is further amorphized.

  Thereafter, a silicon oxide film 40 is formed on the gate electrodes 14 and 24 and the sidewalls 15 and 25 at a film formation temperature equal to or lower than the temperature at which silicon recrystallization is started (about 550 ° C.) (FIG. 8).

  Then, with the gate electrodes 14 and 24 and the sidewalls 15 and 25 covered with the silicon oxide film 40, heat treatment at about 950 to 1100 ° C. (for example, RTA (Rapid Thermal Annealing) for 0 to 30 seconds (0 seconds is spike annealing). ) To repair the damage caused by ion irradiation and activate the dopant. At the same time, recrystallization of amorphous silicon occurs, and the gate electrodes 14 and 24 become polysilicon.

  At this time, the gate electrode 14 of the nMOS transistor tends to expand because a large amount of ions having a relatively large mass number (mass number 70 or more) such as As ions and Sb ions are implanted. However, since the surfaces of the gate electrode 14 and the sidewalls 15 are covered with the silicon oxide film 40, they can hardly expand. Therefore, a strong compressive stress remains as internal stress in the gate electrode 14 due to the force to expand. Along with this, tensile stress is applied to the channel region below the gate electrode 14.

  On the other hand, the gate electrode 24 of the pMOS transistor is hardly expanded because only ions having a relatively small mass number are implanted, and almost no stress remains in the gate electrode 24. Therefore, almost no stress is applied to the channel region below the gate electrode 24.

  For example, when the upper portions of the gate electrodes 14 and 24 and the source / drain regions 16 and 26 are silicided, the silicon oxide film 40 is removed, and a metal film of Co or the like is formed on the entire surface by sputtering, and 350 to 550 is formed. By applying heat treatment at a relatively low temperature of 0 ° C., the metal film reacts with the gate electrodes 14 and 24 and the source / drain regions 16 and 26. Then, the metal film left unreacted on the element isolation film 11 and the sidewalls 15 and 25 is selectively removed. Subsequently, by applying a higher temperature heat treatment, silicide layers 14a, 24a, 16c and 26c are formed on the gate electrodes 14 and 24 and on the source / drain regions 16 and 26, respectively (FIG. 9).

  Thereafter, predetermined interlayer insulating films, contacts, wirings, and the like are formed to complete the manufacture of the semiconductor device.

  FIG. 10A is a stress distribution diagram in the cross section in the channel length direction of the nMOS transistor according to the present embodiment, and FIG. 10B shows a conventional nMOS transistor (that is, the gate electrode 14 having a relatively mass number). It is a stress distribution diagram in a cross section in the channel length direction of an nMOS transistor in which only small ions are implanted. In the nMOS transistor according to the present embodiment, it can be seen that strong compressive stress remains in the gate electrode 14 and tensile stress is applied in the channel region. Accordingly, since the silicon lattice spacing in the channel region of the nMOS transistor is widened, the carrier mobility is improved, which can contribute to the performance improvement of the MOS transistor.

  On the other hand, since almost no stress remains in the gate electrode 24 of the pMOS transistor, almost no stress is applied to the channel region below the gate electrode 24. As described above, applying a tensile stress to the channel region of the pMOS transistor is not effective because the drain current of the pMOS transistor is reduced. That is, in a device having both a pMOS transistor and an nMOS transistor, it is desirable that the tensile stress is applied only to the channel region of the nMOS transistor. According to this embodiment, since no tensile stress is applied to the channel region of the pMOS transistor, it is possible to improve the characteristics of the nMOS transistor while suppressing a decrease in the drain current of the pMOS transistor.

  Further, according to the present embodiment, ions having a relatively large mass number are used as ions to be implanted into the gate electrode 14 (ions for forming the n-type source / drain region 16), and ions to be implanted into the gate electrode 24 are used. A strong tensile stress can be applied only to the channel region of the nMOS transistor by using an ion for forming the p-type source / drain region 26 having a relatively small mass number. In other words, even if the gate electrode 14 and the gate electrode 24 are formed in the same process, the nMOS transistor and the pMOS transistor are obtained by making a difference in mass number between the n-type dopant and the p-type dopant implanted thereafter. Thus, the stresses applied to the channel regions can be made different from each other. That is, it is not necessary to form the nMOS transistor and the pMOS transistor in different processes, and the complexity of the manufacturing process is suppressed.

As described above, when amorphous silicon into which a large amount of ions are implanted is recrystallized to change into polysilicon, the larger the mass of the implanted ions, the greater the expansion. Therefore, the larger the dose amount and mass number of ions implanted into the gate electrode 14, the greater the compressive stress remaining in the gate electrode 14. Then, the tensile stress applied to the channel region below the gate electrode 14 increases, and the effect of the present embodiment is improved. Similarly, the compressive stress remaining in the gate electrode 14 increases as the dose of ions implanted into the gate electrode 14 increases. In the above example, the n-type source / drain diffusion layer 16b is formed by ion implantation with a dose amount of 4 × 10 ¹⁵ / cm ² or more. This is a standard for forming the n-type source / drain diffusion layer 16b. This is a dose amount and does not limit the application of the present invention. Of course, the effect of the present invention can be sufficiently obtained even at a dose of about 4 × 10 ¹⁵ / cm ² , but the effect of the present invention is further enhanced if a larger dose is implanted. However, the compressive stress itself of the gate electrode 14 is generated even when the dose is smaller than 4 × 10 ¹⁵ / cm ² .

  Further, in the process shown in FIG. 8, the silicon oxide film 40 is formed as a predetermined film formed on the gate electrodes 14 and 24, but the temperature is less than the temperature (about 550 ° C.) at which the recrystallization of silicon is started. As long as the film can be formed under the above conditions, it may be a film of another material. For the purpose of leaving compressive stress in the gate electrode 14, the insulating film is not necessarily required. For example, a metal, silicide, or a laminated film thereof may be used. However, in that case, after compressive stress is generated in the gate electrode 14 by heat treatment, the film is once removed, and an insulating film such as a silicon oxide film is formed again.

  Also, when the predetermined film 40 has a characteristic that it shrinks by the heat treatment (the silicon oxide film has the characteristic), the compressive stress remaining in the gate electrode 14 becomes large. Furthermore, the compressive stress remaining in the gate electrode 14 increases as the temperature of the heat treatment for recrystallizing amorphous silicon increases and as the thickness of the predetermined film 40 increases, and the effect of improving the carrier mobility increases. It has been confirmed by the present inventors.

  In the present embodiment, the substrate on which the MOS transistor is formed is described as a normal silicon substrate, but the above-described “strained silicon substrate” may be used. In that case, it is clear that the channel mobility in the channel region of the nMOS transistor can be further improved.

<Embodiment 2>
As described in the first embodiment, since ions having a relatively small mass number are implanted into the gate electrode 24, even if the silicon oxide film 40 exists on the gate electrode 24, almost no stress remains. However, when a large amount of ions are implanted, even if ions having a small mass number are implanted, compressive stress may remain.

  Hereinafter, a manufacturing process of the semiconductor device according to the second embodiment will be described. First, an nMOS transistor and a pMOS transistor are formed by a process similar to that shown in FIGS. 1 to 8 in the first embodiment, and a silicon oxide film 40 is formed thereon. Then, as shown in FIG. 11, the silicon oxide film 40 on the pMOS region is removed and opened.

  Thereafter, heat treatment at about 950 to 1100 ° C. is performed to repair damage caused by ion irradiation and activate the dopant. At the same time, recrystallization of amorphous silicon occurs, and the gate electrodes 14 and 24 become polysilicon.

  At this time, since the surfaces of the gate electrode 14 and the sidewall 15 of the nMOS transistor are covered with the silicon oxide film 40, a strong compressive stress remains as an internal stress in the gate electrode 14 due to the force of expansion. Along with this, tensile stress is applied to the channel region below the gate electrode 14.

  On the other hand, since the surface of the gate electrode 24 and the sidewall 25 of the pMOS transistor is exposed without being covered with the silicon oxide film 40, even if the gate electrode 24 is slightly expanded, the gate electrode 24 is almost completely expanded. No stress remains. That is, the tensile stress is further suppressed from being applied to the channel region of the pMOS transistor than in the first embodiment.

<Embodiment 3>
In the first embodiment and the second embodiment, ion implantation for forming the n-type source / drain diffusion layer 16b is used for ion implantation for expanding the gate electrode 14 of the nMOS transistor. However, in order to implant ions into the gate electrode 14, an ion implantation different from the ion implantation step for forming the n-type source / drain diffusion layer 16b may be performed.

Hereinafter, a manufacturing process of the semiconductor device according to the third embodiment will be described. First, nMOS transistors and pMOS transistors are formed in the same process as that shown in FIGS. 1 to 6 in the first embodiment. Then, as shown in FIG. 12, a resist mask 36 having an opening over the nMOS region is formed, and prior to the formation of the n-type source / drain diffusion layer 16b in the nMOS region, it is electrically inactive and has a relatively large mass number. (Mass number 70 or more) For example, Ge ions are implanted into the entire surface by 4 × 10 ¹⁵ / cm ² or more. At this time, ions are implanted not only into the gate electrode 14 but also into the source / drain region of the nMOS transistor. However, since ions implanted in this step are electrically inactive, they do not work as dopants.

  Then, as shown in FIG. 7, an n-type dopant is implanted to form an n-type source / drain diffusion layer 16b. The n-type dopant at this time may be ions having a relatively small mass number, such as P ions.

  Thereafter, as in the first embodiment, a silicon oxide film 40 is formed on the gate electrodes 14 and 24 and the sidewalls 15 and 25 as shown in FIG. 8, and heat treatment is performed at about 950 to 1100 ° C. Thereby, recrystallization of amorphous silicon occurs, and the gate electrodes 14 and 24 become polysilicon.

  At this time, a large amount of ions that are electrically inactive and have a relatively large mass number are implanted into the gate electrode 14 of the nMOS transistor by the above process, and the surfaces of the gate electrode 14 and the sidewall 15 are formed on the silicon oxide film 40. Therefore, compressive stress remains as internal stress in the gate electrode 14 due to the force of expansion. Along with this, tensile stress is applied to the channel region below the gate electrode 14.

  On the other hand, since only ions having a relatively small mass number are implanted into the gate electrode 24 of the pMOS transistor, almost no stress remains. Therefore, almost no stress is applied to the channel region below the gate electrode 24.

<Embodiment 4>
Generally, crystal defects are likely to occur in a silicon substrate subjected to strong stress, and in a transistor formed on a silicon substrate having crystal defects, leakage current such as junction leakage current, gate current, and subthreshold leakage current increases. Resulting in. That is, in the nMOS transistor according to the present invention, it is conceivable that a crystal defect is generated by the tensile stress applied to the channel region, and the possibility that the leakage current is increased is higher than that of the conventional one.

  For example, a logic unit of a general semiconductor device is mainly intended for high-speed operation and response, and high-speed operation is given priority even if there is some leakage current. On the other hand, for example, a memory unit such as SRAM or DRAM, In the logic part of the LSI for mobile communication devices, it is necessary to suppress a slight increase in power consumption due to leakage current. Therefore, the MOS transistor according to the present invention is effective for a circuit portion where high-speed operation is prioritized (hereinafter referred to as “high-speed circuit portion”), but a circuit portion for which power consumption is to be suppressed (hereinafter referred to as “low-power consumption circuit portion”). It can be said that it is unsuitable for. In other words, it is desirable to apply the MOS transistor according to the present invention only to the high-speed circuit portion of the semiconductor device and to apply the conventional MOS transistor to the low power consumption circuit portion.

  13 to 16 are views showing the manufacturing steps of the semiconductor device according to the fourth embodiment. In these figures, as shown in FIG. 13, the left side is a high-speed circuit unit in which high-speed operation is prioritized, and the right side is a low-power consumption circuit unit that wants to suppress power consumption. Further, it is assumed that each of the high-speed circuit unit and the low power consumption circuit unit has an nMOS region in which an nMOS transistor is formed and a pMOS region in which a pMOS transistor is formed. Hereinafter, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to these drawings.

  First, the element isolation film 11, the p wells 12 and 52, and the n wells 22 and 62 are formed on the silicon substrate 10 by a conventional method. Thereafter, the gate insulating film 13, the gate electrode 14, the sidewall 15 and the n-type source / drain extension layer 16a are formed in the nMOS region of the high-speed circuit portion in the same process as that shown in FIGS. The gate insulating film 23, the gate electrode 24, the sidewall 25 and the p-type source / drain extension layer 26a are formed in the pMOS region of the high-speed circuit portion, and the gate insulating film 53, the gate electrode 54 and the sidewall are formed in the nMOS region of the low power consumption circuit portion. 55 and an n-type source / drain extension layer 56a, and a gate insulating film 63, a gate electrode 64, sidewalls 65, and a p-type source / drain extension layer 66a are formed in the pMOS region of the low power consumption circuit portion, respectively.

Subsequently, a resist mask 71 having openings in the pMOS regions of the high speed circuit portion and the low power consumption circuit portion is formed. Then, using the resist mask 71, the gate electrodes 24 and 64, and the sidewalls 25 and 65 as masks, a p-type dopant having a relatively small mass number such as B ions is implanted at a dose of 4 × 10 ¹⁵ / cm ² or more. A type source / drain diffusion layer 26b and a p type source / drain diffusion layer 66b are formed (FIG. 13). Thus, the p-type source / drain region 26 composed of the p-type source / drain extension layer 26a and the p-type source / drain diffusion layer 26b, and the p-type composed of the p-type source / drain extension layer 66a and the p-type source / drain diffusion layer 66b. A source / drain region 66 is formed. At this time, the ions are also implanted into the gate electrodes 24 and 64.

  Next, a resist mask 72 having openings in the nMOS regions of the high speed circuit portion and the low power consumption circuit portion is formed. Then, using the resist mask 72, the gate electrodes 14 and 54, and the sidewalls 15 and 55 as a mask, an n-type dopant having a relatively large mass number such as As ion or Sb ion is implanted, and the n-type source / drain diffusion layer 16b and An n-type source / drain diffusion layer 56b is formed (FIG. 14). Thereby, the n-type source / drain region 16 composed of the n-type source / drain extension layer 16a and the n-type source / drain diffusion layer 16b, and the n-type composed of the n-type source / drain extension layer 56a and the n-type source / drain diffusion layer 56b. A source / drain region 56 is formed. At this time, the ions are also implanted into the gate electrodes 14 and 54.

  Thereafter, silicon recrystallization is started on the gate electrodes 14 and 24 and the side walls 15 and 25 of the high-speed circuit portion, with the silicon oxide film 80 covering the high-speed circuit portion and opening the low-power consumption circuit portion. The film is formed under conditions of temperature (about 550 ° C.) or less (FIG. 15).

  Then, heat treatment is performed at about 950 to 1100 ° C. with the gate electrodes 14 and 24 and the side walls 15 and 25 covered with the silicon oxide film 80. At this time, recrystallization of amorphous silicon occurs, and the gate electrodes 14, 24, 54, and 64 become polysilicon.

  Here, a large amount of ions having a relatively large mass number (mass number of 70 or more) such as As ions and Sb ions are implanted into the gate electrode 14 of the nMOS transistor in the high-speed circuit section, and the gate electrode 14 and the sidewall 15 Since the surface is covered with the silicon oxide film 80, a strong compressive stress remains as internal stress in the gate electrode. Along with this, tensile stress is applied to the channel region below the gate electrode 14.

  On the other hand, a large amount of ions having a relatively large mass number, such as As ions and Sb ions, are implanted into the gate electrode 54 of the nMOS transistor of the low power consumption circuit portion, but the surfaces of the gate electrode 54 and the sidewall 55 are exposed. Therefore, almost no stress remains in the gate electrode 54. Therefore, almost no stress is applied to the channel region below the gate electrode 54.

  Further, since only ions having a relatively small mass number are implanted into the gate electrodes 24 and 64 of the pMOS transistor in the high-speed circuit portion and the low power consumption circuit portion, almost no stress remains in the inside. Therefore, almost no stress is applied to the channel region below the gate electrodes 24 and 64.

  As described above, according to the manufacturing process according to the present embodiment, it is possible to improve performance by applying a strong tensile stress only to the channel region of the nMOS transistor in the high-speed circuit section. At the same time, almost no stress is applied to the channel regions of the pMOS transistor in the high-speed circuit portion, the pMOS in the low power consumption circuit portion, and the nMOS transistor, so that an increase in leakage current due to the occurrence of crystal defects can be suppressed.

  For example, when siliciding the gate electrode and the source / drain region of a predetermined MOS transistor, a metal film such as Co is formed by sputtering, and a heat treatment at a relatively low temperature of 350 to 550 ° C. is performed. Reacts with silicon. Then, the metal film left unreacted on the insulating film is selectively removed. Subsequently, a higher temperature heat treatment is applied.

  For example, in an LSI for mobile communication devices, the gate electrode and source / drain region of a MOS transistor in a low power consumption circuit section are often silicided. In that case, the silicon oxide film 80 formed in the above process and covering the high-speed circuit part and opening the low-power consumption circuit part can be used as it is as a mask. Thereby, silicide layers 54a, 64a, 56c, and 66c are formed on the gate electrodes 54 and 64 and the source / drain regions 56 and 66, respectively, in the low power consumption circuit portion (FIG. 16).

  According to the present embodiment, when amorphous silicon is recrystallized, the silicon oxide film 80 is strong only in the channel region of the nMOS transistor in the high-speed circuit portion by opening the low power consumption circuit portion. A tensile stress can be applied. That is, even if all the gate electrodes 14, 24, 54, and 64 are formed in the same process, a tensile stress can be applied only to the channel region of a predetermined nMOS transistor. Therefore, the complexity of the manufacturing process is suppressed.

<Embodiment 5>
In this embodiment, as in the fourth embodiment, another method for applying the MOS transistor according to the present invention only to the high-speed portion of the semiconductor device and applying the conventional MOS transistor to the low power consumption portion will be described. To do.

  17 to 20 are views showing the manufacturing steps of the semiconductor device according to the fifth embodiment. Also in these drawings, as in FIG. 13, the left side is a high-speed circuit unit in which high-speed operation is prioritized, and the right side is a low-power consumption circuit unit in which power consumption is to be suppressed. ing.

  Hereinafter, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to these drawings. First, as in the fourth embodiment, the element isolation film 11, the p wells 12 and 52, and the n wells 22 and 62 are formed on the silicon substrate 10, and the gate insulating film 13 and the gate electrode are formed in the nMOS region of the high-speed circuit portion. 14, the sidewall 15 and the n-type source / drain extension layer 16a, the gate insulating film 23, the gate electrode 24, the sidewall 25 and the p-type source / drain extension layer 26a in the pMOS region of the high-speed circuit portion, and the low-power consumption circuit portion. The gate insulating film 53, gate electrode 54, sidewall 55 and n-type source / drain extension layer 56a are formed in the nMOS region, and the gate insulating film 63, gate electrode 64, sidewall 65 and p-type source are formed in the pMOS region of the low power consumption circuit portion. Drain extension layers 66a are formed respectively. However, when forming the n-type source / drain extension layer 16a and the n-type source / drain extension layer 56a, an n-type dopant having a relatively low mass number such as P ions is implanted.

Subsequently, a resist mask 71 having openings in the pMOS regions of the high speed circuit portion and the low power consumption circuit portion is formed. Then, using the resist mask 71, the gate electrodes 24 and 64, and the sidewalls 25 and 65 as masks, a p-type dopant having a relatively small mass number such as B ions is implanted at a dose of 4 × 10 ¹⁵ / cm ² or more. A type source / drain diffusion layer 26b is formed (FIG. 13). Thus, the p-type source / drain region 26 composed of the p-type source / drain extension layer 26a and the p-type source / drain diffusion layer 26b, and the p-type composed of the p-type source / drain extension layer 66a and the p-type source / drain diffusion layer 66b. A source / drain region 66 is formed. At this time, the ions are also implanted into the gate electrodes 24 and 64.

  Next, a resist mask 73 having an opening in the nMOS region of the low power consumption circuit portion is formed. Then, using the resist mask 73, the gate electrode 54, and the sidewall 55 as a mask, an n-type dopant having a relatively small mass number such as P ions is implanted to form an n-type source / drain diffusion layer 56b (FIG. 17). As a result, an n-type source / drain region 56 composed of the n-type source / drain extension layer 56a and the n-type source / drain diffusion layer 56b is formed. At this time, the ions are also implanted into the gate electrode 54.

  Thereafter, a resist mask 74 having an opening in the nMOS region of the high speed circuit portion is formed. Then, using the resist mask 74, the gate electrode 14 and the sidewall 15 as a mask, an n-type dopant having a relatively large mass number such as As ions or Sb ions is implanted to form an n-type source / drain diffusion layer 16b (FIG. 18). As a result, an n-type source / drain region 16 including the n-type source / drain extension layer 16a and the n-type source / drain diffusion layer 16b is formed. At this time, the ions are also implanted into the gate electrode 14.

  Then, recrystallization of silicon starts so that the silicon oxide film 81 covers the gate electrodes 14, 24, 54, 64 and the sidewalls 15, 25, 55, 65 on the high-speed circuit portion and the low power consumption circuit portion. It is formed under the condition of the temperature (about 550 ° C.) or less (FIG. 19).

  Then, heat treatment is performed at about 950 to 1100 ° C. with the gate electrodes 14, 24, 54, 64 and the sidewalls 15, 25, 55, 65 covered with the silicon oxide film 81. At this time, recrystallization of amorphous silicon occurs, and the gate electrodes 14, 24, 54, and 64 become polysilicon.

  Here, a large amount of ions having a relatively large mass number (mass number of 70 or more) such as As ions and Sb ions are implanted into the gate electrode 14 of the nMOS transistor in the high-speed circuit section, and the gate electrode 14 and the sidewall 15 Since the surface is covered with the silicon oxide film 81, strong compressive stress remains as internal stress in the gate electrode. Along with this, tensile stress is applied to the channel region below the gate electrode 14.

  On the other hand, since only ions having a relatively small mass number are implanted into the gate electrode 54 of the nMOS transistor in the low power consumption circuit portion, almost no stress remains in the inside. Therefore, almost no stress is applied to the channel region below the gate electrode 54.

  Further, since only ions having a relatively small mass number are implanted into the gate electrodes 24 and 64 of the pMOS transistor in the high-speed circuit portion and the low power consumption circuit portion, almost no stress remains in the inside. Therefore, almost no stress is applied to the channel region below the gate electrodes 24 and 64.

  As described above, according to the manufacturing process according to the present embodiment, it is possible to improve performance by applying a strong tensile stress only to the channel region of the nMOS transistor in the high-speed circuit section. At the same time, almost no stress is applied to the channel regions of the pMOS transistor in the high-speed circuit portion, the pMOS in the low power consumption circuit portion, and the nMOS transistor, so that an increase in leakage current due to the occurrence of crystal defects can be suppressed.

  For example, when siliciding the gate electrode and the source / drain region of a MOS transistor of a low power consumption circuit unit such as an LSI for mobile communication devices, an opening is formed on the low power consumption circuit unit of the silicon oxide film 81 as a mask. Perform salicide processing. Thereby, silicide layers 54a, 64a, 56c, 66c are formed on the gate electrodes 54, 64 and the source / drain regions 56, 66 of the low power consumption circuit section, respectively (FIG. 20).

  According to the present embodiment, by applying a mass number difference between the n-type dopant of the high-speed circuit unit and the n-type dopant of the low power consumption circuit unit, strong pulling is performed only on the channel region of the nMOS transistor of the high-speed circuit unit. Stress can be applied. That is, even if all the gate electrodes 14, 24, 54, and 64 are formed in the same process, a tensile stress can be applied only to the channel region of a predetermined nMOS transistor.

<Embodiment 6>
As described above, in the nMOS transistor according to the present invention, crystal defects are likely to occur, and leakage current such as junction leakage current, gate current, and subthreshold leakage current in the MOS transistor increases. There is a problem that the possibility of increasing the leakage current is higher than that of the conventional one. Therefore, in this embodiment, a method for solving the problem is shown.

  That is, for example, after forming the gate electrodes 14 and 24 of non-single crystal silicon in the step shown in FIG. 2 in the first embodiment, the surfaces of the gate electrodes 14 and 24 and the silicon substrate 10 are oxidized (at this time, silicon Since the silicon oxide film 31 remains on the substrate 10, the oxide film is accurately oxidized again). As a result, as shown in FIG. 21, a silicon oxide film 90 is formed on the surfaces of the gate electrodes 14 and 24. At this time, bird's beaks 90a of silicon oxide film are formed on the edge portions of the gate electrodes 14 and 24. The subsequent steps are the same as those shown in FIGS.

  By forming the bird's beak 90a, the insulating film thickness at the edge portions of the gate electrodes 14 and 24 is increased, so that the tunnel current is suppressed and the gate electric field is relaxed, so that the subthreshold leakage current can be reduced, and the MOS transistor Increase in leakage current is suppressed. Therefore, this is particularly effective for a MOS transistor in which an increase in leakage current is a concern, such as an nMOS transistor according to the present invention in which a tensile stress is applied to the channel region.

  Further, when the heat treatment in the subsequent process is performed while the gate electrodes 14 and 24 are covered with the silicon oxide film 90, it is possible to suppress the variation in the resistance value of the polysilicon gate electrode in the non-silicide region. be able to.

  10 silicon substrate, 11 element isolation film, 12, 52 p-well, 13, 23, 53, 63 gate insulating film, 14, 24, 54, 64 gate electrode, 15, 25, 55, 65 sidewall, 16, 56 n Type source / drain region, 16a, 56a n type source / drain extension layer, 16b, 56b n type source / drain diffusion layer, 22, 62 n well, 26, 66 p type source / drain region, 26a, 66a p type source / drain extension layer, 26b, 66b p-type source / drain diffusion layer, 31 silicon oxide film, 32 non-single crystal silicon film, 40, 80, 81 silicon oxide film, 90 silicon oxide film, 90a bird's beak.

Claims (5)

In a method for manufacturing a semiconductor device including at least an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate,
Preparing the semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Forming a non-single crystal silicon film on the gate insulating film;
Patterning the non-single-crystal silicon film to form a first gate electrode of the n-channel MOS transistor and a second gate electrode of the p-channel MOS transistor,
Implanting n-type dopant ions having a mass number of 70 or more into the first gate electrode;
Implanting B ions into the second gate electrode;
An insulating film is formed on the n-channel MOS transistor and the p-channel MOS transistor, and the first gate electrode made amorphous by the implantation of the n-type dopant ions and the B ions are implanted. Forming an insulating film covering the second gate electrode that has been made amorphous;
In a state where the first gate electrode and the second gate electrode are covered with the insulating film, the semiconductor substrate is subjected to a heat treatment at a temperature of 550 ° C. or more to recrystallize the first gate electrode, Compressive stress remains as internal stress in the first gate electrode, and 3 × 10 3 in the channel region below the first gate electrode due to the residual compressive stress. ⁹ dyn / cm ² Applying the above tensile stress and recrystallizing the second gate electrode;
Removing the insulating film formed on the first gate electrode and the second gate electrode after the heat treatment step;
Forming a silicide layer on the surfaces of the first gate electrode and the second gate electrode after removing the insulating film;
A method of manufacturing a semiconductor device including: In a method for manufacturing a semiconductor device including at least an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor substrate,
Forming a gate insulating film on the semiconductor substrate;
Forming a non-single crystal silicon film on the gate insulating film;
Patterning the non-single-crystal silicon film to form a first gate electrode of the n-channel MOS transistor and a second gate electrode of the p-channel MOS transistor,
Implanting n-type dopant ions having a mass number of 70 or more into the surface of the semiconductor substrate located on both sides of the first gate electrode and the first gate electrode;
Implanting B ions into the surface of the semiconductor substrate located on both sides of the second gate electrode and the second gate electrode;
An insulating film is formed on the n-channel MOS transistor and the p-channel MOS transistor, and the first gate electrode made amorphous by the implantation of the n-type dopant ions and the B ions are implanted. Forming an insulating film covering the second gate electrode made amorphous and the surface of the semiconductor substrate;
In a state where the first gate electrode and the second gate electrode are covered with the insulating film, the semiconductor substrate is subjected to a heat treatment at a temperature of 550 ° C. or more to recrystallize the first gate electrode, Compressive stress remains as internal stress in the first gate electrode, and 3 × 10 3 in the channel region below the first gate electrode due to the residual compressive stress. ⁹ dyn / cm ² Applying the above tensile stress and recrystallizing the second gate electrode;
Removing the insulating film formed on the first gate electrode and the second gate electrode after the heat treatment step;
Forming a silicide layer on the surfaces of the first gate electrode and the second gate electrode after removing the insulating film;
A method of manufacturing a semiconductor device including: The semiconductor according to claim 1, wherein the insulating film is formed at a temperature of 550 ° C. or less.
Device manufacturing method. 4. The insulating film according to claim 1, wherein the insulating film is contracted by the heat treatment process. 5.
The manufacturing method of the semiconductor device described. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film.

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