JP4539732B2 - Flip-flop circuit - Google Patents

Description

  The present invention relates to a flip-flop circuit, and more particularly to a circuit suitable for a true signal phase clock type D-type flip-flop circuit.

  In a clock synchronization system, a clock generator typified by a phase locked loop (hereinafter referred to as “PLL”), a delay locked loop (hereinafter referred to as “DLL”), and the like is external data. (External clock) is an indispensable element circuit for maintaining the synchronization between the internal clock and the clock generator to construct a stable clock synchronization system in which the phase relationship between the external clock and the internal clock is accurately adjusted by the clock generator. It has become very important.

FIG. 7 is a block diagram illustrating the configuration of a digital DLL as an example of a clock generator. In this DLL, a phase comparator 1 that compares the phase difference between the external clock CLK _EXT and the internal clock CLK _INT, and an up / down counter that controls the delay time by output signals UP and DN from the phase comparator 1 (hereinafter referred to as “ It is referred to as a “counter”.) 2. It comprises a delay line 3 and a clock driver 4 for adjusting the delay time.

  FIG. 8 is a circuit diagram showing an example of a delay unit that constitutes a delay line, and includes inverters INV1, INV2, INV3, switches SW1, SW2, and capacitors C1, C2. In this delay line, switching between whether or not the capacitors C1 and C2 are connected to the delay line is performed according to the level of the output signal n bit from the counter 2 shown in FIG. 7, thereby realizing the adjustment of the delay amount. .

FIG. 9 is a timing chart of the digital DLL. The operation principle of phase adjustment will be described based on this timing chart. That is, when the internal clock CLK _INT is later than the external clock CLK _EXT (period 1 shown in FIG. 9), the signal DN becomes “H” level, and the counter 2 shown in FIG. The delay adjustment capacitors (capacitors C1 and C2 shown in FIG. 8) are successively disconnected from the delay line, and the phase difference between the external clock CLK _EXT and the internal clock CLK _INT is reduced.

On the other hand, when the internal clock CLK _INT exceeds the external clock CLK _EXT (period 2 shown in FIG. 9), the signal UP becomes “H” level, and the counter 2 shown in FIG. The delay adjusting capacitors (capacitors C1 and C2 shown in FIG. 8) are connected to the delay line one after another, and the phase difference between the external clock CLK _EXT and the internal clock CLK _INT is reduced.

With the configuration / operation as described above, the phase difference between the external clock CLK _EXT and the internal clock CLK _INT appears to approach zero, but the accuracy greatly depends on the accuracy of the phase comparator 1. become. That is, in order to design a high-accuracy clock generator, it is necessary to design the phase comparator 1 that can detect the phase difference between the external clock CLK _EXT and the internal clock CLK _INT with high accuracy.

FIG. 10 is a diagram for explaining a conventional phase comparator, and FIG. 11 is a diagram for explaining input / output waveforms of the conventional phase comparator. As shown in FIG. 10, the conventional phase comparator uses a D-type flip-flop (hereinafter referred to as “DFF”), and the internal clock CLK _INT is used as the data signal D and the external clock is used as the clock signal CK. CLK _EXT is connected, signal UP is connected to positive phase output Q, and signal DN is connected to negative phase output Qb.

As shown in FIG. 11, when the internal clock CLK _INT is delayed from the external clock CLK _{EXT, the} signal DN becomes “H” level, and when the internal clock CLK _INT is advanced from the external clock CLK _EXT. Since the signal UP is at the “H” level, it can be seen that the function as the phase comparator is realized. In this configuration, narrowing the dead zone of the DFF directly leads to higher accuracy of phase difference detection. Therefore, it is possible to increase the accuracy of phase detection by using a dynamic DFF that responds at high speed and has a narrow dead zone. .

  FIG. 12 is a circuit diagram illustrating an example of a dynamic DFF. This circuit is a True Signal Phase Clock (hereinafter referred to as “TSPC”) DFF, which realizes a high speed and narrow dead band by operating only with a positive phase clock.

  The DFF includes a first latch circuit L1, a third p-channel transistor P3, and a second n-channel composed of a first p-channel transistor P1, a second p-channel transistor P2, and a first n-channel transistor N1. A second latch circuit L2 composed of a transistor N2, a third n-channel transistor N3, a fourth p-channel transistor P4, a fourth n-channel transistor N4, and a fifth n-channel transistor N5. 3 latch circuits L3 and an inverter INV4.

  The data signal D is connected to the gates of the first p-channel transistor P1 and the first n-channel transistor N1, and the clock signal CK is the second p-channel transistor P2, the third p-channel transistor P3, and the third n-channel transistor. The channel transistor N3 is connected to the gates of the fourth n-channel transistor N4.

  The output signal NC of the first latch circuit L1 is applied to the gate of the second n-channel transistor N2, and the output signal X of the second latch circuit L2 is applied to the fourth p-channel transistor P4 and the fifth n-channel transistor N5. Are connected to each gate.

  FIG. 13 is a timing chart when the “L” level of the DFF data signal is captured. When the data signal D and the clock signal CK become “L” level, the internal node NC becomes “H” level. As a result, the second n-channel transistor N2 is turned on, and the internal node A is also set to "H" level.

  Next, when the clock signal CK becomes “H” level, the internal node NC enters a floating state. Since the third n-channel transistor N3 is turned on at this timing, the internal node A changes to the “L” level, and is affected by the coupling due to the gate capacitance of the second n-channel transistor N2, so that the floating The level of the internal node NC which has become lowers. For this reason, the gm (mutual conductance) of the second n-channel transistor N2 is lowered, the signal change of the internal node X is delayed, and a delay occurs from the rising timing of the clock signal CK to the “L” output.

  Further, in response to the rising edge of the data signal D, the internal node NC changes to “L” level, and the time until the second n-channel transistor N2 is turned off and the rising edge of the clock signal CK changes the internal node X to “L” level. Since the difference from the time until this is considered as the margin of the data hold time, the internal node NC falling to the intermediate level in response to the rising edge of the clock signal CK as described above impairs the margin of the data hold time. End up. In other words, the high speed and narrow dead zone performance are impaired due to the presence of the floating node inside.

  Conventionally, as an example of improving TSPC-DFF, a technique has been disclosed in which an n-channel transistor for pull-down is connected to an internal node NC, and the gate level is controlled by a signal obtained by delaying a clock signal CK (Patent Document 1). reference).

JP 2005-318479 A

  However, even if the technique disclosed in Patent Document 1 is used, the internal node NC eventually becomes a floating state during the time when the clock signal CK is delayed, so that the problem of impairing the high speed performance and the performance of the narrow dead zone is the problem. It is not solved.

  That is, in the flip-flop circuit disclosed in Patent Document 1, although a delay clock is input to the sixth n-channel transistor N6, a normal clock (non-delayed clock) is input to the second p-channel transistor P2. As a result, the node N1 remains floating during the time period from when the clock changes from “L” level to “H” level to when the delayed clock changes from “L” level to “H” level. End up.

  Here, it is conceivable that a delayed clock is also input to the second p-channel transistor P2, but in this case, the precharge of the node N1 when the normal clock changes from the “H” level to the “L” level. Since time is reduced, precharge becomes irregular when operated at a higher frequency, which may cause malfunction.

  An object of the present invention is to provide a flip-flop circuit suitable for a phase comparator that can operate at high speed with little dead zone.

  The present invention inputs a data signal and a rising delay clock signal delayed only by the rising edge of the clock signal, and rises the signal of the first node by the falling edge of the rising delay clock signal while the data signal is falling. The first latch circuit for lowering the signal of the first node by the rise of the rising delay clock signal, the signal of the first node and the clock signal are input, and the signal of the first node is rising. The second latch circuit that causes the signal at the second node to fall at the timing when the clock signal falls, the second node signal and the clock signal are input, and the data signal in the state where the clock signal is raised is held. A third latch circuit for generating an output signal to be output and a signal at the first node to rise the delay clock. A flip-flop circuit and a pull-down circuit that pulls down the signal.

  In the present invention, since the pull-down circuit is provided at the first node, the occurrence of the floating period of the first node can be suppressed, and a signal that delays only the rising edge is supplied to the pull-down circuit and the first latch circuit. Therefore, the fall of the first node is not delayed, and the loss of the precharge time of the first node can be suppressed.

  The present invention is also a flip-flop circuit in which a clocked inverter circuit is connected to the second node. Thereby, the floating of the second node can be prevented.

  Here, the first latch circuit includes a configuration in which a first p-channel transistor, a second p-channel transistor, and a first n-channel transistor are connected in series. A data signal is input to the gate of one n-channel transistor, and a rising delay clock signal is input to the gate of the second p-channel transistor.

  The second latch circuit includes a configuration in which a third p-channel transistor, a second n-channel transistor, and a third n-channel transistor are connected in series, the gate of the third p-channel transistor, A clock signal is input to the gate of the third n-channel transistor, and a signal of the first node is input to the gate of the second n-channel transistor.

  The third latch circuit includes a configuration in which a fourth p-channel transistor, a fourth n-channel transistor, and a fifth n-channel transistor are connected in series, and the gate of the fourth p-channel transistor and The signal of the second node is input to the gate of the fifth n-channel transistor, and the clock signal is input to the gate of the fourth n-channel transistor.

  The pull-down circuit includes a sixth n-channel transistor, a rising delay clock signal is input to the gate of the sixth n-channel transistor, and the first node is connected to the source of the sixth n-channel transistor. It is what is done.

  The clocked inverter circuit has a configuration in which a fifth p-channel transistor, a sixth p-channel transistor, a seventh n-channel transistor, and an eighth n-channel transistor are connected in series. The first node signal is input to the gate of the p-channel transistor, the second node signal is input to the gates of the sixth p-channel transistor and the seventh n-channel transistor via the inverter, and the eighth node A clock signal is input to the gate of the n-channel transistor.

  According to the present invention, the flip-flop circuit can be operated at high speed with little dead zone, and a phase comparator capable of stable operation can be configured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Flip-flop circuit>
The flip-flop circuit according to the present embodiment is applied as, for example, the phase comparator 1 in the digital DLL shown in FIG. That is, in the DLL, the phase comparator 1 that compares the phase difference between the external clock CLK _EXT and the internal clock CLK _INT , the counter 22 that controls the delay time by the output signals UP and DN from the phase comparator 1, and the adjustment of the delay time The delay line 3 and the clock driver 4 for performing

  The delay line is constituted by a delay unit composed of inverters INV1, INV2, INV3, switches SW1, SW2, and capacitors C1, C2 as shown in FIG. 8, and a capacitor C1 according to the level of the output signal n bit from the counter 2 shown in FIG. The delay amount is adjusted by switching whether or not C2 is connected to the delay line.

In the DLL, when the internal clock CLK _INT is delayed from the external clock CLK _EXT , the signal DN becomes “H” level, the counter 2 counts down, and a delay adjusting capacity (capacitance shown in FIG. 8). C1 and C2) are successively disconnected from the delay line, and the phase difference between the external clock CLK _EXT and the internal clock CLK _INT is reduced.

On the other hand, when the internal clock CLK _INT exceeds the external clock CLK _EXT , the signal UP goes to “H” level, the counter 2 goes up, and the delay adjustment capacitance (capacitance C1 shown in FIG. 8). And C2) are successively connected to the delay line, and the phase difference between the external clock CLK _EXT and the internal clock CLK _INT is reduced.

As shown in FIG. 10, when the phase comparator used in the DLL is configured by DFF, the internal clock CLK _INT is connected to the data input section (data signal D), and the external clock CLK _EXT is connected to the clock input section. The signal UP is connected to the phase output Q, and the signal DN is connected to the reverse phase output Qb. The flip-flop circuit of the present embodiment is used in such a DLL phase comparator and has the following configuration.

  FIG. 1 is a circuit diagram illustrating a flip-flop circuit according to this embodiment. This flip-flop circuit is mainly a TSPC type DFF. That is, the flip-flop circuit of the present embodiment receives the data signal D and the rising delay clock signal CKd delayed only by the rising edge of the clock signal CK, and the rising delay clock signal CKd while the data signal D is falling. The first latch circuit L1 that raises the signal of the internal node NC, which is the first node, at the falling edge of the signal, and the signal of the internal node NC, which causes the signal at the internal node NC to fall at the rising edge of the rising delay clock signal CKd. The second latch circuit L2 which receives the signal CK and causes the signal of the internal node X which is the second node to fall at the timing when the clock signal CK falls while the signal of the internal node NC is rising, the internal node Input X signal and clock signal CK, clock signal A third latch circuit L3 for generating an output signal Q holding the data signal D in a state where K is rising; and a pull-down circuit PD for pulling down the signal of the internal node NC by the rising delay clock signal CKd. ing.

  Here, the rising delay clock signal CKd is generated by the rising delay circuit DC. FIG. 2 is a circuit diagram showing an example of a rise delay circuit. In the input stage, the gm (transconductance) of the p-channel transistor P7 is set large and the gm of the n-channel transistor N9 is set small, and the next stage is reversed. By setting, the propagation delay of the rising edge of the input signal (here, the clock signal) is set large, and the propagation delay of the falling edge is set small.

  In the flip-flop circuit of this embodiment, the first latch circuit L1 has a configuration in which a first p-channel transistor P1, a second p-channel transistor P2, and a first n-channel transistor N1 are connected in series. The data signal D is input to the gates of the first p-channel transistor P1 and the first n-channel transistor N1, and the rising delay clock signal CKd is input to the gate of the second p-channel transistor P2.

  The second latch circuit L2 has a configuration in which a third p-channel transistor P3, a second n-channel transistor N2, and a third n-channel transistor N3 are connected in series, and the third p-channel transistor The clock signal CK is input to the gate of P3 and the gate of the third n-channel transistor N3, and the signal of the internal node NC is input to the gate of the second n-channel transistor N2.

  The third latch circuit L3 has a configuration in which a fourth p-channel transistor P4, a fourth n-channel transistor N4, and a fifth n-channel transistor N5 are connected in series, and the fourth p-channel transistor The signal of the internal node X is input to the gate of P4 and the gate of the fifth n-channel transistor N5, and the clock signal CK is input to the gate of the fourth n-channel transistor N4.

  The pull-down circuit PD includes a sixth n-channel transistor N6. The rising delay clock signal CKd is input to the gate of the sixth n-channel transistor N6, and the internal node is connected to the source of the sixth n-channel transistor N6. NC is connected.

  By connecting this pull-down circuit PD to the internal node NC, the internal node NC can be prevented from floating during operation. In other words, the pull-down sixth n-channel transistor N6 is added to the internal node NC, and the gate potential and the gate potential of the second p-channel transistor P2 forming the latch circuit L1 are controlled by the rising delay clock signal CKd. Thus, the internal node NC is prevented from being in a floating level during the operation period.

  In the present embodiment, a clocked inverter circuit CINV is connected to the internal node X. The clocked inverter circuit CINV receives the clock signal CK and the signal of the internal node NC, and prevents the internal node X from floating by the signal of the internal node NC when the clock signal CK rises.

  Specifically, the clocked inverter circuit CINV includes a fifth p-channel transistor P5, a sixth p-channel transistor P6, a seventh n-channel transistor N7, and an eighth n-channel transistor N8 connected in series. The signal of the internal node NC is input to the gate of the fifth p-channel transistor P5, and the signal of the internal node X is connected to the gate of the sixth p-channel transistor P6 and the gate of the seventh n-channel transistor N7. The clock signal CK is input to the gate of the eighth n-channel transistor N8.

  In this clocked inverter circuit CINV, the gate potential of the fifth p-channel transistor P5 is controlled not by the clock signal CK but by the internal node NC, so that it is floating during the operation period without disturbing the signal change of the internal node X. It prevents that.

  The specific circuit configuration described above is an example, and the circuit configuration is not necessarily limited to the above circuit as long as the same operation is performed.

  Next, the operation principle of the flip-flop circuit of this embodiment will be described. FIG. 3 is a timing chart for explaining the operation principle of the flip-flop circuit according to this embodiment. First, when the data signal D and the clock signal CK are set to the “L” level, the rising delay clock signal CKd is also set to the “L” level via the rising delay circuit DC, and the internal node NC is set to the “H” level. At this time, since the propagation delay of the fall is suppressed as much as possible by the rise delay circuit DC, the loss of the precharge time of the internal node NC can be suppressed.

  Next, in response to the “H” level of the internal node NC, the second n-channel transistor N2 is turned on, and the internal node A is also set to the “H” level.

  Next, when the clock signal CK becomes “H” level, the internal node A changes to “L” level, and the internal node X also becomes “L” level. At this time, the internal node NC is pulled down by the sixth n-channel transistor N6 controlled by the rising delay clock signal CKd, and is fixed at the “H” level (not floating). Thereby, the change of the internal node X is performed at high speed.

  Next, after the elapse of time t3 by the rising delay circuit DC, the rising delay clock signal CKd changes to “H” level, and the sixth n-channel transistor N6 is turned off. The delay time t3 is set to a time required for the internal node X to change and the inverter INV3 to respond.

  At the same time, the fifth p-channel transistor P5 is turned on, so that the state of the internal node X is maintained.

  As described above, in the flip-flop circuit of this embodiment, the rising delay clock signal CKd is input to both the second p-channel transistor and the sixth n-channel transistor, so that a node that floats during the operation period The precharge time of the internal node NC can be reduced by inputting a signal that does not exist and is delayed only at the rising edge, thereby enabling stable operation without impairing the characteristics of the TSPC-DFF such as high speed and narrow dead zone.

<Phase comparator>
FIG. 4 is a circuit diagram illustrating a configuration example (No. 1) of a phase comparator using the flip-flop circuit of the present embodiment. This phase comparator uses the high-speed, narrow dead-zone flip-flop circuit (TSPC type DFF) as shown in FIG. 1, and further advances or delays the current phase relationship and counter by 1 bit. By adding a means for simultaneously monitoring the phase relationship at, the lock point can be reliably found.

That is, this phase comparator has a configuration including a delayed phase detector K1 and a lead phase detector K2, and the phase detectors K1 and K2 are connected to the external clock CLK _EXE and the internal clock CLK _INT. Are connected in reverse.

  Among these, the delayed phase detection unit K1 includes a current phase relationship comparison unit K11, a post-undown phase relationship comparison unit K12, and AND1. The lead phase detection unit K2 includes a current phase relationship comparison unit K21, a post-count-up phase relationship comparison unit K22, and AND2.

  The current phase relationship comparison unit K11 includes a TSPCDFF1 as a TSPC type DFF that is the flip-flop circuit according to the present embodiment described above, and includes buffers BUF1, BUF2, and delay units 1, Delayunits as shown in FIG. It is composed of delay unit 2.

In the current phase relationship comparison unit K11, the internal clock CLK _INT is input from the delay 1 to the data signal D of the TSPCDFF1 via the buffer BUF1, and the external clock CLK _EXE is input from the delay 2 to the clock signal of the TSPCDFF1 via the buffer BUF2. The data output Q of TSPCDFF1 is connected to one of AND1.

  The phase relationship comparison unit K12 after one countdown also includes a TSPCDFF2 as a TSPC type DFF which is a flip-flop circuit according to the present embodiment. From the buffers BUF3 and BUF4, and delay units 3 and delay units 4 as shown in FIG. It is configured.

After one countdown, the phase relationship comparison unit 12 has basically the same circuit configuration as the current phase relationship comparison unit K11, and the internal clock CLK _INT is input from the delay unit 3 to the data signal D of the TSPCDFF 2 via the buffer BUF 3, and the external clock CLK _EXE Is input from delay unit 4 to the clock signal of TSPCDFF 2 via buffer BUF 4, and data output Q of TSPCDFF 2 is connected to one of AND 1, but DelayUnit 3 of the line connected to data signal D of TSPCDFF 2 is set to delay on. It is different in the state.

  The current phase relationship comparison unit K21 includes a TSPCDFF1 as a TSPC type DFF that is the flip-flop circuit according to the present embodiment described above, and includes buffers BUF5 and BUF6, and delay units 5 as delay units as shown in FIG. The delay unit 6 is configured.

In the current phase relationship comparison unit K2, the external clock CLK _EXE is input from the delay 5 to the data signal D of the TSPCDFF1 via the buffer BUF5, and the internal clock CLK _INT is input from the delay 6 to the clock signal of the TSPCDFF1 via the buffer BUF6. The data output Q of TSPCDFF1 is connected to one of AND2.

  The phase relationship comparison unit K22 after one count up also includes a TSPCDFF2 as a TSPC type DFF that is a flip-flop circuit according to this embodiment, and includes buffers BUF7 and BUF8, and delay units 7 and delay units 8 as shown in FIG. It is composed of

After one count-up, the phase relationship comparison unit K22 has basically the same circuit configuration as the current phase relationship comparison unit K21, and the external clock CLK _EXE is input from the delay unit 7 to the data signal D of the TSPCDFF 2 via the buffer BUF 7, and the internal raw clock CLK _INT is input from delay unit 8 to the clock signal of TSPCDFF 2 via buffer BUF 8, and data output Q of TSPCDFF 2 is connected to one side of AND 2, but delay unit 7 of the line connected to the data input side of TSPCDFF 2 is delayed. It is different in the on state.

Here, the delay on state indicates that the signal n bit shown in FIG. 8 is at the “H” level and the capacitor is connected to the delay line. That is, in the case of the delayed phase detection unit K1, the phase relationship comparison unit K12 after one countdown with respect to the current phase relationship comparison unit K11 causes the phase of the internal clock CLK _{INT to} be delayed by the minimum unit delay adjustable by the delay line. In the case of the lead phase detection unit K2, the minimum phase delay in which the external clock CLK _EXE can be adjusted by the delay line in the phase relationship comparison unit K22 after one count up with respect to the current phase relationship comparison unit K12. That is, the phase comparison is performed with a delay of a minute.

  Therefore, the current phase relationship and the phase relationship in the state where the counter is delayed by 1 bit are simultaneously monitored. In the case where the phase is reversed while the counter is delayed by 1 bit, that is, the phase relationship is compared after 1 countdown. When the output of the part K12 becomes "L" level, the countdown signal DN is set to "L" level by AND1 and the counter operation can be stopped, and the output of the phase relation comparison part K22 is "L" after one count up. When the level is reached, the count up signal UP can be set to "L" level by AND2 to stop the counter operation.

  As a result, in the case of a lag phase, it is possible to reliably lock with a phase shift within the minimum unit delay time adjustable by the delay line.

On the other hand, in the case of the lead phase detection unit K2, the state in which the external clock CLK _EXT is delayed by the minimum unit of delay that can be adjusted by the delay line in the phase relationship comparison unit K22 after one count up with respect to the current phase relationship comparison unit K21. This means that the phase is compared.

  Therefore, the current phase relationship and the phase relationship when the counter is advanced by 1 bit are simultaneously monitored, and the phase is reversed when the counter is advanced by 1 bit from the current state, that is, the phase relationship after 1 count up. When the output of the comparison unit K22 becomes “L” level, the count up signal UP is set to “L” level by AND2 and the counter operation can be stopped.

  As a result, even in the case of the lead phase, it is possible to securely lock the phase with a phase shift within the minimum delay time that can be adjusted by the delay line.

  FIG. 5 is a circuit diagram illustrating a configuration example (No. 2) of the phase comparator using the flip-flop circuit of the present embodiment. This phase comparator basically has a configuration including a plurality of phase comparators composed of a DFF, a buffer, and a delay unit, as in the phase comparator shown in FIG. K110 includes a phase relationship comparison unit K120 after one countdown, and a phase relationship comparison unit K220 after one countup. That is, the current phase relationship comparison unit K11 of the delayed phase detection unit K1 and the current phase relationship comparison unit K21 of the advance phase detection unit K2 are commonly used in the phase comparator shown in FIG. It is the composition made.

  4 differs from the phase comparator shown in FIG. 4 in that the phase relation comparison unit K120 after one count up sets the Delay Unit and delay unit 14 on the clock input line to the delay on state, and the reverse phase of TSPCDFF3 of the current phase relation comparison unit K110. The count-up signal UP is generated by AND4 using the output Qb and the output Q of the phase relationship comparison unit K220 after one count-up.

  Specifically, the current phase relationship comparison unit K110 includes a TSPCDFF3 as a TSPC type DFF that is the flip-flop circuit according to the present embodiment described above, and includes buffers BUF9 and BUF10, and a Delay as shown in FIG. The unit is composed of delay unit 9 and delay unit 10.

In the current phase relationship comparison unit K110, the internal clock CLK _INT is input from the delay 9 to the data signal D of the TSPCDFF3 via the buffer BUF9, and the external clock CLK _EXE is input from the delay 10 to the clock signal of the TSPCDFF3 via the buffer BUF10. The data output Q of TSPCDFF3 is connected to one of AND3, and the reverse phase output Qb of TSPCDFF3 is connected to one of AND4.

  The phase relationship comparison unit K120 after one countdown also includes a TSPCDFF4 as a TSPC type DFF which is a flip-flop circuit according to the present embodiment. From the buffers BUF11 and BUF12, and delay units 11 and delay units 12 as shown in FIG. It is configured.

After one countdown, the phase relationship comparison unit 12 has basically the same circuit configuration as the current phase relationship comparison unit K110, and the internal clock CLK _INT is input from the delay unit 11 to the data signal D of the TSPCDFF 4 via the buffer BUF 11, and the external clock CLK _EXE Is input from the delay unit 12 to the clock signal of the TSPCDFF4 via the buffer BUF12, and the data output Q of the TSPCDFF4 is connected to one of the AND3, but the DelayUnit 11 of the line connected to the data signal D of the TSPCDFF4 is set to delay on. It is different in the state.

  The phase relationship comparison unit K22 after one count up also includes a TSPCDFF2 as a TSPC type DFF that is a flip-flop circuit according to this embodiment, and includes buffers BUF7 and BUF8, and delay units 7 and delay units 8 as shown in FIG. It is composed of

The phase relationship comparison unit K22 after one count up also has basically the same circuit configuration as the current phase relationship comparison unit K110, and the internal force clock CLK _INT is input from the delay unit 13 to the data signal D of the TSPCDFF 5 via the buffer BUF 13, and the external clock CLK _EXE is input from delay unit 14 to the clock signal of TSPCDFF 5 via buffer BUF 14, and data output Q of TSPCDFF 4 is connected to one of AND 4, but delay unit 14 of the line connected to the clock input side of TSPCDFF 5 is delayed on The point is that of the state.

Here, the delay on state indicates that the signal n bit shown in FIG. 8 is at the “H” level and the capacitor is connected to the delay line. That is, after one countdown with respect to the current phase relationship comparison unit K110, the phase relationship comparison unit K120 performs phase comparison in a state where the internal clock CLK _INT is delayed by the minimum unit delay adjustable by the delay line. The phase relationship comparison unit K220 after one count up with respect to the current phase relationship comparison unit K110 performs phase comparison in a state where the external clock CLK _EXE is delayed by the minimum unit delay adjustable by the delay line.

  Therefore, the current phase relationship and the phase relationship in the state where the counter is delayed by 1 bit are simultaneously monitored. In the case where the phase is reversed while the counter is delayed by 1 bit, that is, the phase relationship is compared after 1 countdown. When the output of the part K120 becomes “L” level, the countdown signal DN is set to “L” level by AND3, the counter operation can be stopped, and the output of the phase relation comparison part K220 is “L” after one count up. When the level is reached, the count operation signal UP can be set to "L" level by AND4 to stop the counter operation.

  By adopting a configuration like the phase comparator shown in FIG. 5, it is possible to reduce the circuit scale to 2/3 while maintaining the same effect as the phase comparator shown in FIG.

<Display device>
FIG. 6 is a block diagram showing an example in which the phase comparator using the flip-flop circuit according to this embodiment is applied to a display device. The display device 100 is centered on a display area 101 in which a plurality of pixels are arranged in a matrix, for example, and a vertical driver 111, a horizontal driver 112, a common electrode 113, a reference driver 114, an interface circuit 115, and a data processing circuit 116 around the display area 101. A timing generation circuit 117 and a serial interface circuit 118 are configured.

  The display device 100 is supplied with a master clock (Master CLK), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and digital data (image data) from an external digital signal processing circuit 200. Based on this, each peripheral circuit is driven to display an image on the display area 110.

  The phase comparator using the flip-flop circuit according to the present embodiment is incorporated in, for example, the interface circuit 115, and includes a master clock (Master CLK) sent from the external digital signal processing circuit 200 and an internally generated clock. The phase shift is corrected. That is, the master clock (Master CLK) has a phase shift with the internal clock due to level shift or drive in the display device 100, and this phase shift is compared with the phase using the flip-flop circuit of the present embodiment. The result is compared by a device, and the comparison result is used to correct by DLL. The corrected clock is input to the data processing circuit 116, and data sampling is performed with high accuracy.

  In the above description, the flip-flop circuit of this embodiment is applied to a phase comparator. However, the present invention is not limited to this and can be applied to other circuits.

<Implementation effect>
According to this embodiment described above, the following effects can be achieved.

  (1) In the flip-flop circuit, a pull-down sixth n-channel transistor N6 is added to the internal node NC, and the gate potential and the gate potential of the second p-channel transistor P2 forming the first latch circuit L1 are set. By controlling the rising edge of the clock signal CK by the rising delay clock signal CKd delayed by the rising delay circuit DC, the internal node NC is prevented from being in a floating level during the operation period, and high speed operation and a narrow dead zone are realized. It becomes possible.

  (2) In the flip-flop circuit, the internal node X includes an inverter INV3, a fifth p-channel transistor P5, a sixth p-channel transistor P6, a seventh n-channel transistor N7, and an eighth n-channel transistor N8. A latch circuit by the clocked inverter circuit CINV is added, and the gate potential of the fifth p-channel transistor P5 is controlled not by the clock signal CK but by the internal node NC, so that the signal change of the internal node X is not hindered. It is possible to prevent floating during the operation period and to realize stable operation without impairing high speed.

  (3) A high-speed, narrow dead zone TSPC type DFF is used as the phase comparator, and the current phase relationship and the phase relationship in the state where the delay time phase of the minimum unit adjustable by the delay line is advanced or delayed are used. By adding means for monitoring at the same time, it is possible to reliably find the lock point.

  (4) A phase comparator that detects a phase relationship between two clock signals of a reference clock and a comparison clock, and separately includes a lag phase detector and a lead phase detector, each of which is a TSPC type It is composed of two phase comparators composed of a DFF, a buffer, and a Delay Unit. If one of the phase comparators is a delayed phase detector, the Delay Unit on the comparison clock signal side is set in a delay state, and an advanced phase detector In this case, the above-described functions can be realized by setting the delay unit on the reference clock side to the delay state and taking the logic with the output of the phase comparator that does not set the delay unit to the delay state.

  (5) A phase comparator that detects the phase relationship between the two clock signals of the reference clock and the comparison clock, and is composed of three phase comparators composed of a TSPC type DFF, a buffer, and a delay unit. The first phase comparator does not set the Delay Unit to the delay state, the second phase comparator sets the Delay Unit on the reference clock side to the delay state, and the third phase comparator has the Delay on the comparison clock signal side. Set the unit to the delay state and take the logic of the positive phase output of the first phase comparator and the logic of the third phase comparator, and the negative phase output of the first phase comparator and the second phase comparator By taking the logic, it is possible to realize the above-described functions while reducing the circuit scale.

It is a circuit diagram explaining the flip-flop circuit which concerns on this embodiment. It is a circuit diagram showing an example of a rising delay circuit. 3 is a timing chart for explaining the operation principle of the flip-flop circuit according to the present embodiment. It is a circuit diagram explaining the structural example (the 1) of the phase comparator using the flip-flop circuit of this embodiment. It is a circuit diagram explaining the structural example (the 2) of the phase comparator using the flip-flop circuit of this embodiment. It is a block diagram explaining the example of application to a display apparatus. It is a block diagram which shows the structure of DLL by a digital system as an example of a clock generator. It is a circuit diagram which shows the example of Delay Unit which comprises a delay line. It is a timing chart of a digital system DLL. It is a figure explaining the conventional phase comparator. It is a figure explaining the input-output waveform of the conventional phase comparator. It is a circuit diagram which shows an example of dynamic type DFF. It is a timing chart at the time of taking in "L" level of D of the data signal of DFF.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Phase comparator, 2 ... Up / down counter, 3 ... Delay line, 4 ... Clock driver, 100 ... Display apparatus, 200 ... Digital signal processing circuit, L1 ... 1st latch circuit, L2 ... 2nd latch circuit , L3 ... third latch circuit, PD ... pull-down circuit, CINV ... clocked inverter circuit

Claims (7)

A data signal and a rising delay clock signal delayed only by the rising edge of the clock signal are input, and the signal of the first node is raised by the falling edge of the rising delay clock signal while the data signal is falling, A first latch circuit that causes the signal of the first node to fall in response to a rise of a rising delay clock signal;
A second latch for inputting the signal of the first node and the clock signal, and for causing the signal of the second node to fall at the timing when the clock signal falls while the signal of the first node is rising Circuit,
A third latch circuit for inputting the signal of the second node and the clock signal and generating an output signal for holding the data signal in a state in which the clock signal is rising;
A pull-down circuit for pulling down the signal of the first node by the rising delay clock signal ,
A clocked inverter circuit is connected to the second node;
The clocked inverter circuit receives the clock signal and the signal of the first node, and prevents the floating of the second node by the signal of the first node when the clock signal rises.
Flip-flop circuit. The pull-down circuit receives the rising delay clock signal, and prevents the first node from floating by the rising delay clock signal when the clock signal rises.
Flip-flop circuit according to 請 Motomeko 1. The first latch circuit has a configuration in which a first p-channel transistor, a second p-channel transistor, and a first n-channel transistor are connected in series, and the first p-channel transistor and the first p-channel transistor The data signal is input to the gate of the n-channel transistor, and the rising delay clock signal is input to the gate of the second p-channel transistor.
Flip-flop circuit according to 請 Motomeko 1. The second latch circuit includes a third p-channel transistor, a second n-channel transistor, and a third n-channel transistor connected in series, the gate of the third p-channel transistor, and the The clock signal is input to the gate of the third n-channel transistor, and the signal of the first node is input to the gate of the second n-channel transistor.
Flip-flop circuit according to 請 Motomeko 1. The third latch circuit includes a configuration in which a fourth p-channel transistor, a fourth n-channel transistor, and a fifth n-channel transistor are connected in series, the gate of the fourth p-channel transistor, and the The signal of the second node is input to the gate of the fifth n-channel transistor, and the clock signal is input to the gate of the fourth n-channel transistor.
Flip-flop circuit according to 請 Motomeko 1. The pull-down circuit includes a sixth n-channel transistor, the rising delay clock signal is input to the gate of the sixth n-channel transistor, and the first node is connected to the source of the sixth n-channel transistor. Is connected
Flip-flop circuit according to 請 Motomeko 1. The clocked inverter circuit has a configuration in which a fifth p-channel transistor, a sixth p-channel transistor, a seventh n-channel transistor, and an eighth n-channel transistor are connected in series. The signal of the first node is input to the gate of the channel transistor, and the signal of the second node is input to the gate of the sixth p-channel transistor and the gate of the seventh n-channel transistor via an inverter. The clock signal is input to the gate of the eighth n-channel transistor.
Flip-flop circuit according to 請 Motomeko 2.

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