JP4535701B2 - 結合超伝導電荷量子ビット素子、それを用いた制御否定ゲート - Google Patents
結合超伝導電荷量子ビット素子、それを用いた制御否定ゲート Download PDFInfo
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- 239000002096 quantum dot Substances 0.000 title claims description 47
- 230000004888 barrier function Effects 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 17
- 239000002887 superconductor Substances 0.000 claims description 15
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 230000010365 information processing Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000005428 wave function Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 2
- 230000005667 quantum oscillations Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000005281 excited state Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000013642 negative control Substances 0.000 description 1
- 230000005610 quantum mechanics Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
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Description
200 標的量子ビット回路
101,201 超伝導箱電極
102,202 対向電極
103,203 ゲート電極
104,204 トンネルバリア
105,205 ゲート容量
106,206 読み出し電極
107,207 トンネルバリア
300 箱電極結合容量
Claims (8)
- 第1の超伝導電荷量子ビット素子と、第2の超伝導電荷量子ビット素子と、前記第1及び前記第2の超伝導電荷量子ビット素子を結合する電気容量素子とを有することを特徴とする超伝導電荷量子マルチビット素子。
- 前記第1の超伝導電荷量子ビット素子及び前記第2の超伝導電荷量子ビット素子の各々は、超伝導体で構成された量子箱電極と、該量子箱電極とトンネルバリアを挟んで結合された対向電極と、前記量子箱電極とゲート静電容量を介して結合したゲート電極とを有し、
前記第1の超伝導電荷量子ビット素子の量子箱電極と前記第2の超伝導電荷量子ビット素子の量子箱電極とが、前記電気容量素子を介して結合されていることを特徴とする請求項1記載の超伝導電荷量子マルチビット素子。 - 第1の超伝導ビット素子と第2の超伝導ビット素子とが結合された結合超伝導電荷量子ビットを用いた制御否定ゲートであって、
前記第1の超伝導ビット素子及び前記第2の超伝導ビット素子の各々は、超伝導体で構成された量子箱電極と、該量子箱電極とトンネルバリアを挟んで結合された対向電極と、前記量子箱電極と第1の静電容量を介して結合したゲート電極とを有し、
前記第1の超伝導ビット素子の量子箱電極と前記第2の超伝導ビット素子の量子箱電極とは、第2の静電容量を介して結合され、
前記第2の超伝導ビット素子のゲート電極に、所定のパルスを供給するパルス供給手段をさらに備えたことを特徴とする結合超伝導電荷量子ビットを用いた制御否定ゲート。 - 前記所定のパルスは、そのピーク値が前記第2の超伝導ビット素子の前記第1の静電容量により定まる電圧であり、ピーク値の継続時間が、超伝導箱電極と対向電極とのジョセフソン結合エネルギーにより定められる時間幅であるより定められる請求項3記載の制御否定ゲート。
- 前記所定のパルスは、台形パルスである請求項3に記載の制御否定ゲート。
- 前記パルス供給手段は、前記所定のパルスとしてマイクロ波パルスを、前記第2の超伝導ビット素子のゲート電極に供給する請求項3に記載の制御否定ゲート。
- 第1の超伝導ビット素子と第2の超伝導ビット素子とが結合された結合超伝導電荷量子ビットのエンタングルメント生成方法であって、前記第1の超伝導ビット素子及び前記第2の超伝導ビット素子の各々は、超伝導体で構成された量子箱電極と、該量子箱電極とトンネルバリアを挟んで結合された対向電極と、前記量子箱電極と第1の静電容量を介して結合したゲート電極とを有し、前記第1の超伝導ビット素子の量子箱電極と前記第2の超伝導ビット素子の量子箱電極とは、第2の静電容量を介して結合され、前記第1及び前記第2の超伝導ビット素子のゲート電極に、各々の前記第1の静電容量により定まる電圧を、所定時間印加することを特徴とする結合超伝導電荷量子ビットのエンタングルメント生成方法。
- 前記第1の静電容量により定まる電圧は、電荷素量を前記第1の静電容量で除算した値である請求項7に記載のエンタングルメント生成方法。
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JP2003286640A JP4535701B2 (ja) | 2003-08-05 | 2003-08-05 | 結合超伝導電荷量子ビット素子、それを用いた制御否定ゲート |
US10/910,770 US7145170B2 (en) | 2003-08-05 | 2004-08-04 | Coupled superconducting charge quantum bit device and controlled-not gate using the same |
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JP2003286640A JP4535701B2 (ja) | 2003-08-05 | 2003-08-05 | 結合超伝導電荷量子ビット素子、それを用いた制御否定ゲート |
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Cited By (1)
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US9633314B2 (en) | 2014-11-25 | 2017-04-25 | Samsung Electronics Co., Ltd. | Multi-qubit coupling structure |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP4438286B2 (ja) * | 2002-12-20 | 2010-03-24 | 日本電気株式会社 | 量子演算素子及びその使用方法 |
US20050250651A1 (en) * | 2004-03-29 | 2005-11-10 | Amin Mohammad H S | Adiabatic quantum computation with superconducting qubits |
US7109593B2 (en) * | 2004-07-30 | 2006-09-19 | Microsoft Corporation | Systems and methods for performing quantum computations |
JP4836064B2 (ja) * | 2004-08-16 | 2011-12-14 | 独立行政法人理化学研究所 | 量子状態読出回路 |
US7533068B2 (en) | 2004-12-23 | 2009-05-12 | D-Wave Systems, Inc. | Analog processor comprising quantum devices |
JP4824941B2 (ja) * | 2005-04-26 | 2011-11-30 | 日本電信電話株式会社 | 電子スピン対の量子エンタングルメント状態の生成方法及び検出方法 |
US8234103B2 (en) | 2007-04-05 | 2012-07-31 | D-Wave Systems Inc. | Physical realizations of a universal adiabatic quantum computer |
US8219871B2 (en) * | 2008-03-18 | 2012-07-10 | Nec Laboratories America, Inc. | Efficient decoupling schemes for quantum systems using soft pulses |
US8089286B2 (en) * | 2008-04-15 | 2012-01-03 | Nec Laboratories America, Inc. | System and method for quantum computer calibration and performance estimation |
US8315969B2 (en) * | 2008-10-10 | 2012-11-20 | Nec Laboratories America, Inc. | Estimating a quantum state of a quantum mechanical system |
US8485427B2 (en) | 2010-10-14 | 2013-07-16 | Nec Laboratories America, Inc. | System and method for synthetic commodity and synthetic legal tender creation |
EP2562694A1 (en) * | 2011-08-22 | 2013-02-27 | Hitachi, Ltd. | Quantum information processing |
US10037493B2 (en) | 2013-10-22 | 2018-07-31 | D-Wave Systems Inc. | Universal adiabatic quantum computing with superconducting qubits |
US10002107B2 (en) | 2014-03-12 | 2018-06-19 | D-Wave Systems Inc. | Systems and methods for removing unwanted interactions in quantum devices |
WO2019126396A1 (en) | 2017-12-20 | 2019-06-27 | D-Wave Systems Inc. | Systems and methods for coupling qubits in a quantum processor |
Citations (4)
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JPH10107340A (ja) * | 1996-09-27 | 1998-04-24 | Nec Corp | 微小トンネル接合部の製造方法及び微小トンネル接合素子の製造方法 |
JP2000277723A (ja) * | 1999-03-25 | 2000-10-06 | Nec Corp | 量子演算素子とその製造方法 |
JP2003067181A (ja) * | 2001-08-24 | 2003-03-07 | Nippon Telegr & Teleph Corp <Ntt> | 量子コンピュータおよびこの制御方法 |
JP2004200579A (ja) * | 2002-12-20 | 2004-07-15 | Nec Corp | 量子演算素子及びその使用方法 |
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CA2537602A1 (en) * | 2003-09-05 | 2005-03-17 | D-Wave Systems, Inc. | Superconducting phase-charge qubits |
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JPH10107340A (ja) * | 1996-09-27 | 1998-04-24 | Nec Corp | 微小トンネル接合部の製造方法及び微小トンネル接合素子の製造方法 |
JP2000277723A (ja) * | 1999-03-25 | 2000-10-06 | Nec Corp | 量子演算素子とその製造方法 |
JP2003067181A (ja) * | 2001-08-24 | 2003-03-07 | Nippon Telegr & Teleph Corp <Ntt> | 量子コンピュータおよびこの制御方法 |
JP2004200579A (ja) * | 2002-12-20 | 2004-07-15 | Nec Corp | 量子演算素子及びその使用方法 |
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US9633314B2 (en) | 2014-11-25 | 2017-04-25 | Samsung Electronics Co., Ltd. | Multi-qubit coupling structure |
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