JP4533019B2 - Graphic object processing apparatus and graphic object processing method - Google Patents

Description

  The present invention relates to an apparatus for rendering object graphic elements into a raster pixel image, and in particular, such object graphics that do not use frame or line storage of pixel data as part of the rendering process. The present invention relates to a graphic object processing apparatus and a graphic object processing method (rendering apparatus) that perform efficient rendering on pixel image data of elements.

  Most object-based graphics systems use a frame store or page buffer to hold a pixel-based image of the page or screen. Typically, the outline of a graphic object is calculated, filled and written to the frame store. In the case of two-dimensional graphics, the object in front of other objects is simply written to the frame store after the background object is written, thereby replacing the background on a pixel-by-pixel basis. This is commonly known in the art as the “Painter's algorithm”. Objects are considered in order of priority, from the deepest object to the foremost object, usually with each object rasterized in scan line order, with pixels in a sequential sequence along each scan line. Written to the frame store.

  There are basically two problems with this technique. The first problem is that fast random access to all pixels in the frame store is required. This is because each newly considered object can affect any pixel in the frame store. For this reason, the frame store is usually held in a semiconductor random access memory (RAM). For high resolution color printers, the amount of RAM required is very large, typically over 100 Mbytes, which is costly and difficult to operate at high speed. The second problem is that many pixels are painted (rendered) and overpainted (re-rendered) by objects later in time. Painting pixels with the previous object in time is time consuming. One way to overcome the large frame store problem is the use of "banding". When using banding, only a portion of the frame store is in memory at a time. All of the objects to be drawn are saved in the “display list store”. The entire image is rendered in the same manner as above, but pixel painting (rendering) operations that attempt to paint (render) outside the existing portion of the frame store are “clipped” out. After all of the objects have been drawn, the portion of the frame store is sent to the printer (or other location), another portion of the frame store is selected, and this process is repeated. This technique comes with a penalty. For example, the object being drawn must be reviewed and re-examined many times (once per band). As the number of bands increases, the inspection of objects that need to be rendered is repeated and the number of times increases. Banding techniques do not solve the problem of overcoating costs.

  In some other graphics systems, the images are examined in scan line order. Again, all of the drawn objects are saved in the display list store. On each scan line, the objects that intersect that scan line are considered for each object in order of priority, and the span of pixels between the intersections of the object's sides is set in the line store. Although this technique also overcomes the problem of large frame stores, there is still an overcoat problem.

  Other than these, there are techniques that solve both the large frame store problem and the overcoat problem. In one such technique, each scan line is created in turn. Again, all of the drawn objects are saved in the display list store. In each scan line, the side of the object that intersects the scan line is held in ascending order of the coordinates of the intersection with the scan line. These intersection points or edge intersections are considered in turn and used to toggle the array of active flags. There is one active flag for each object priority of interest on that scan line. Between each of the edge pairs considered, the color data for each pixel between the first edge and the next edge is at the highest priority, using the priority encoder for the active flag And using the color associated with that priority for the pixels of the span between the two sides. In preparation for the next scan line, the coordinates of the intersection of each side are updated according to the nature of each side. Adjacent edges that are missorted as a result of this update are swapped. New sides are also merged into the list of sides.

  This technique has the great advantage that there is no frame store or line store, no overcoat, and object priority is processed in constant order times rather than N times the order (where N is the number of priorities). Have. However, this technique is extremely limited in its use because it cannot perform the many functions required by existing graphic description languages.

  JP 2000-149035 (P2000-149035A) “Graphic Object Processing Method and Apparatus for High-Speed Raster Format Rendering” is a technique for substantially overcoming or at least improving one or more deficiencies associated with this technique. Canon Inc.) has been proposed.

In this technique, each scan line is created in turn. First, all objects to be drawn are sorted and stored in the display list store in the order of scan lines where drawing of each object is started. For each scan line, the sides of the object that intersect the scan line are maintained in ascending order of intersection coordinates, and for each adjacent pair of these side intersections, the information associated with the corresponding object is examined, and the side intersection Determine a set of active objects for a span of pixel positions between corresponding pairs of pixels, and for each of the spans of pixel positions, use the corresponding set of active objects to determine the value of each position in the span. decide.
Japanese Unexamined Patent Publication No. 2000-149035

  However, in implementing the above technique, edge processing, active object determination, determination of pixel values within a span, and determination of a single pixel value from the pixel values of multiple active objects are realized by dedicated hardware. It is realized by connecting the hardware to form a pipeline, or the entire processing is realized on the host by software. In this case, in hardware implementation, when a certain image is rendered by the hardware of a given pixel sequential rendering device, processing is concentrated on an arbitrary module or function depending on the characteristics of the image, and pipeline installation occurs. However, the processing speed may be limited.

  The present invention has been made to solve the above-described problems, and by changing the arbitration algorithm at the time of bus access by each module constituting the pipeline according to the load relationship between the modules. A graphic object processing apparatus (more specifically, a high-speed pixel sequential rendering apparatus) and a graphic object processing method capable of avoiding or reducing a stall or reducing the influence of the stall are provided.

In order to solve the above-described problem, a graphic object processing apparatus according to the present invention is a graphic object processing apparatus that performs a process designated in advance with respect to an arbitrary attribute of a graphic object to form a raster pixel image. A plurality of processing means for performing a plurality of processes relating to an arbitrary attribute; and a bus access arbitration means for arbitrating bus access from each of the plurality of processing means, wherein the bus access arbitration means includes the plurality of processing means. Bus interface means for transferring the bus access to the system bus based on the arbitration result, state detection means for detecting the load state of each of the plurality of processing means, and a bus arbitration algorithm based on the detection result by the state detection means And execute the bus interface Have a control means for controlling the Esu means, said bus access arbitration means further includes a request counting means for counting the number of requests for each of the bus access from the plurality of processing means, the value of the request count means Decoding means for generating a select signal by decoding according to a method specified in advance, wherein the control means selects and executes the bus arbitration algorithm based on the select signal generated by the decode means And

A graphic object processing method according to the present invention is a graphic object processing method for performing a process designated in advance with respect to an arbitrary attribute of a graphic object so as to form a raster pixel image. A bus access arbitration step for arbitrating bus access from each of a plurality of processing means for performing processing, wherein the bus access arbitration step determines bus access from the plurality of processing means based on the arbitration result. A transfer step of transferring to the system bus via the state, a state detection step of detecting the load state of each of the plurality of processing means, a bus arbitration algorithm based on a detection result of the state detection step, and the bus interface means Control to control Possess a degree, the bus access arbitration step further, a request count step of counting by the respective bus access request count request counter from said plurality of processing means, the count value obtained by said counting step And a decoding step of generating a select signal by decoding by a predesignated method, wherein the control step selects and executes the bus arbitration algorithm based on the select signal generated by the decoding step. And

  Further features of the present invention will become apparent from the best mode for carrying out the present invention and the accompanying drawings.

  According to the graphic object device and method of the present invention, the arbitration algorithm at the time of bus access by each module constituting the pipeline is changed according to the load relationship between the modules, thereby avoiding or reducing the stall, Or the influence of a stall can be reduced.

  The apparatus of the present invention and its operation will be described in detail below.

<First Embodiment>
FIG. 1 schematically illustrates a computer system 10 configured for rendering and presentation of computer graphic object images. The system includes a host processor 11 associated with a system random access memory (RAM) 12, which includes a non-volatile hard disk drive or similar device and a volatile semiconductor. RAM is included. The system 10 also includes a system read only memory (ROM) 13, which is usually based on a semiconductor ROM and can often be supplemented by a compact disk device (CD-ROM). System 10 may also incorporate means 14 for displaying images, such as a video display unit (VDU) or printer operating in a raster fashion.

  The components described above with respect to system 10 are interconnected via bus system 15 and are well known in the art, such as IBM PC / AT type personal computers and configurations developed therefrom, Sun Sparcstations and the like. It can operate in the normal operating mode of the computer system.

  As also shown in FIG. 1, the pixel sequential rendering device 16 is derived from a graphic object-based description connected to the bus 15 and supplied with instructions and data from the system 10 via the bus 15. Configured for sequential rendering of pixel-based images. The pixel sequential rendering device 16 can use the system RAM 12 for rendering the object description, but may also implement and use a dedicated local memory.

  FIG. 2 is a diagram showing a basic function data flow. The functional flow diagram of FIG. 2 begins with an object graphic description 21. This object graphic description 21 is generated by the host processor 11, stored in the system RAM 12, or provided by the system ROM 13, and is used to describe the parameters of the graphic object from which the pixel-based image is derived. Can be interpreted by the pixel sequential rendering device 16. For example, the object graphic description 21 includes an orthogonal side format in which a two-dimensional object is defined by a side of a straight line (simple vector) crossing from one point on the display to another point or a plurality of sides including orthogonal lines. Objects with edges can be incorporated in several formats including: Apart from this, formats in which objects are defined by continuous curves are also suitable, including several parameters that allow a quadratic curve to be rendered in a single output space without having to perform multiplication. Can contain a quadratic polynomial line that can describe a single curve. Other data formats such as cubic splines and the like can be used. An object can contain a mixture of many different edge types. Usually common to all formats is the identifier of the start and end of each line (whether straight or curved), which are usually identified by a scan line number, and hence the curve A specific output space that can be rendered is defined.

  Having identified the data necessary to describe the graphic object to be rendered, the graphic system 10 performs a display list generation step 22.

  The display list generator 22 is preferably implemented as a software module that runs on the host processor 11 having the ROM 13 and RAM 12 attached. The display list generator 22 converts an object graphic description expressed in one or more of a well-known graphic description language, graphic library call or other application specific format into a display list.

  The display list is normally written in the display list store 23. The display list store 23 is generally formed in the RAM 12, but may instead be formed in a memory that the pixel sequential rendering device 16 has locally. The display list store 23 can include a plurality of components, one of which is an instruction stream and the other is edge information, which can include raster image pixel data.

  The instruction stream includes code that can be interpreted as instructions that are read by the pixel sequential rendering device 16 to render the particular graphic object desired in the particular image.

  The display list store 23 is read by the pixel sequential rendering device 16. The pixel sequential rendering device 16 converts the display list into a stream of raster pixels, which can be transferred to another device such as a printer, display or memory store, for example.

  FIG. 3 is a configuration diagram of a pixel sequential rendering apparatus that processes a display list obtained from the object graphic description 21 to generate pixels.

  In the display list, the drawing objects included in the original object / graphic description are sorted and recorded in ascending order of the sub-scanning line direction (y-coordinate). In addition, the side information of each object is stored as a side table. The relationship (calculation method) between the correlated level information and pixels at the same coordinates on other levels is included as a level table, and information for determining the color inside the object is included as a fill table. In addition, as data for determining the color of an object, data and processing for generating a color are specified, and reading a bitmap or decompressing a compressed image, and capturing an arbitrary pixel from the result. It may be specified.

  In FIG. 3, reference numeral 16 denotes a pixel sequential rendering apparatus, which is composed of modules 31 to 38 described later (among these, 31 to 36 are referred to as pipeline modules). An instruction execution unit 31 accesses the system bus, reads the display list, interprets the instruction stream, and issues an internal command to a later-stage pipeline module including 32-35 described later. Reference numeral 32 denotes a side (edge) processing unit, which reads side information included in the display list according to an internal command issued by the instruction execution unit 31, extracts side information of a drawing object in units of scanning lines, and stores the side information. After sorting in ascending order of the scanning line direction (x coordinate), the edge information is transferred as a message to a level priority determination unit 33 located in a later stage of the pipeline, which will be described later.

  The level priority determination unit 33 reads the level table included in the display list and the side information generated by the side processing unit 32 in accordance with the instruction issued by the instruction execution unit 31, and sets each level for each scanning line. Determine the priority and the activated pixel range (influencing drawing), sort the information of the activated pixel range of each scanning line in order of priority, and pixel information together with the relationship information with other level pixels As the range information, the pixel range information is transferred to 34 fill data determination units located in the later stage of the pipeline.

  Reference numeral 34 denotes a fill data determination unit that reads the fill table included in the display list and the pixel range information generated by the level priority determination unit 33 according to an internal command issued by the instruction execution unit 31, and for each level. The color of the activated pixel is determined, and the color information of the activated pixel is transferred together with the pixel range information transferred from 33 to the color synthesis unit 35 located in the later stage of the pipeline, which will be described later.

  Reference numeral 35 denotes a color synthesizing unit, which displays the pixel range information of each level generated by the level priority determination unit 33 according to the internal command issued by the instruction execution unit 31 and the color information of the pixels determined by the fill data determination unit 34. An operation for determining a color for each pixel is executed to generate a final color of the pixel.

  Reference numeral 36 denotes a pixel output unit that sends the final pixel generated by the color composition unit 35 to a connected external device. Reference numeral 37 denotes a compatibility guarantee unit. In the display list, an internal command that requires a function that is not implemented in the side processing unit 32, the level priority determination unit 33, the fill data determination unit 34, and the color synthesis unit 35 is executed. When issued by the unit 31, the internal command is processed by software intervention.

  Reference numeral 38 denotes a bus access arbitration unit, which performs mediation and ordering for access to the system bus by the side processing unit 32, the level priority determination unit 33, the fill data determination unit 34, the color composition unit 35, and the compatibility guarantee unit 37. Relay access to the bus.

  FIG. 4 is a diagram showing memory access by the pixel sequential rendering apparatus. In FIG. 4, reference numeral 231 denotes an instruction stream in the display list, reference numeral 232 denotes edge information in the display list, and reference numeral 233 denotes fill information in the display list. Reference numeral 40 denotes a temporary data store, which is arranged in the local memory or the system RAM 12 or distributed between the local memory and the system RAM 12. 41 is an edge information store that is temporary data, 42 is a level table that is temporary data, 43 is a fill information table that is temporary data, and 44 is a color that is temporary data. It is a composite stack.

  The instruction stream 231 includes instructions that can be interpreted by the instruction execution unit 31 for appropriately processing the edge information 232 and the fill information 233 in the pixel sequential rendering apparatus to obtain a correct drawing result.

  In the edge information 232, edge information of a graphic object is recorded in association with a segment obtained by dividing the graphic object. In addition, for each segment, the start point coordinate, the y coordinate of the end point, the increment of x with respect to the unit increment of y, the level to which the segment belongs, and the segment following the end point coordinate constituting the object. And an attribute indicating whether the segment is a start point or an end point in the scanning line of the object, level information associated with each graphic object, and transmittance and other level pixels for each level information. And an attribute indicating the relationship (operation) and a pointer to the fill information.

  The fill information 233 includes data for obtaining a storage type address, color information, and raster type, such as a single color fill, gradation, and raster image paste.

  The side information store 41 is accessed by the side processing unit 32 in order to manage side information on the scanning line to be processed. The level table 42 is accessed so that the priority determination unit 33 manages the status and attributes of each level. The fill information table 43 is accessed so that the fill data determination unit 34 holds a color of a level having an arbitrary status in the level table 42.

  The color synthesis stack 44 is accessed to hold primary data when colors of different levels in a pixel are synthesized.

  Here, the display list 23, the edge (edge) information store 41, the level table 42, and the fill table 43 are arranged in the system RAM 12, and the color composition stack 44 is a local that the pixel sequential rendering device 16 has independently of the system RAM 12. Assume that it is located in memory.

  In the following, an outline of the operation of the pixel sequential rendering apparatus of FIG. 3 will be described by taking as an example the case of processing an object graphic description corresponding to an image as shown in FIG.

  FIG. 5 shows a drawing screen in which a triangular object 51 is first drawn (level 1) and an elliptical object 52 is drawn on top of it (level 2). Level 0 represents, for example, a default level farthest from the viewpoint corresponding to paper when an image is printed, and has a default background color such as white.

  Prior to processing by the pixel sequential rendering device of FIG. 3, the object graphic description is converted into a display list by software. The display list includes at least the following information.

  (1) Draw from y = 30 to y = 140.

  (2) From y = 30 to y = 140, there are straight sides indicating the start of the area of the object 51. In the case of a straight line, it is expressed as one segment without being divided. Also includes information about tilt.

  (3) From y = 30 to y = 140, there are straight sides indicating the end of the area of the object 51. In the case of a straight line, it is expressed as one segment without being divided. Also includes information about tilt.

  (4) From y = 70 to y = 115, there is an elliptical arc side indicating the start of the region of the object 52. To be precise, the elliptical arc is divided into short straight segments and is included with information on the starting position and slope of each segment. The information of each segment constituting one arc has a list structure, and it is possible to track continuous segments.

  (5) From y = 70 to y = 115, there is an elliptical arc side indicating the end of the region of the object 52. To be precise, the elliptical arc is divided into short straight segments and is included with information on the starting position and slope of each segment. The information of each segment constituting one arc has a list structure, and it is possible to track continuous segments.

  (6) The level (z coordinate) information of the object 51 and the relationship (calculation) with the pixel of the same coordinate at another level, whether the color information of the object at the lower level (the far side with respect to the viewpoint) is necessary (ie, transmission Or opaque)) and pointer information to the fill information.

  (7) The level (z coordinate) information of the object 51 and the relationship (calculation) with the pixel of the same coordinate at another level, whether the color information of the object at the lower level (the far side with respect to the viewpoint) is necessary (ie, transparency Or opaque)) and pointer information to the fill information.

  (8) Fill information of the object 51.

  (9) Fill information of the object 51.

(10) Edge information store address (11) Level table address (12) Fill table address When the pixel sequential rendering device 16 receives an activation instruction, the instruction execution unit 31 reads the instruction stream of the display list from a predetermined address. The processing start and drawing area are notified to each module downstream of the pipeline by an internal command, and the edge processing unit 32 is notified of the edge table address (10) by the internal command. Further, the level priority determination unit 33 is notified of the level table address (11) by an internal command, and the fill data determination unit 34 is notified of the fill table address (12) by an internal command. At this point, each module in the pipeline, that is, the edge processing unit 32, the level priority determination unit 33, the fill data determination unit 34, and the color synthesis unit 35, receives a predetermined internal command from a module located upstream of the pipeline. It will be in a standby state.

  Next, the instruction execution unit 31 takes in the new sides (2) and (3) from y = 30 to the side processing unit 32, the level priority determination unit 33, the fill data determination unit 34, and the color synthesis unit 35 and starts drawing. Issue a drawing start command to specify

  The side processing unit 32, the level priority determination unit 33, the fill data determination unit 34, and the color synthesis unit 35 generate default (background color) pixels from y = 0 to y = 30 if necessary. The intermediate processing unit 32 and the level priority determination unit 33 start processing from y = 30. The fill data determination unit 34 generates a background color for all pixels in the scanning line direction with respect to the default, that is, the background level, as a process for the region where y = 0 to y = 30. It passes through the color synthesis unit 35 (without inter-pixel calculation processing) and is output as the final pixel via the pixel output unit 36.

  The edge processing unit 32 skips to y = 30, and detects that two edges belonging to the object 51 are generated from y = 30. Then, the system RAM 12 is accessed to read the segment information, the edge information is extracted, the two edges are registered in the edge table assigned on the system RAM 12, and tracking is started. Since these two sides belong to the same object, they are already sorted in the x order, and are directly notified to the level priority determination unit 33 by an internal command. When edge processing shifts from an arbitrary scanning line to the next scanning line, edges are sorted, and reading and writing from the edge information store 41 allocated on the system RAM 12 occur.

  The level priority determination unit 33 detects the object to which these two pieces of side information belong, activates level 1 between the two sides, and sets the level 1 between the two sides in the level table 42 allocated on the system RAM 12. Record that the state of is active.

  Further, a pointer to the level 1 paint information is read from the display list, and an internal command is issued to notify the paint data determination unit 34 of the x coordinates of the two sides and the pointer to the level 1 paint information.

  The fill data determination unit 34 searches the fill table 43 allocated on the system RAM 12 according to the specified fill information, determines the color of the pixel between the two sides according to the fill table 43, and sets each pixel to the color synthesis unit 35. Notify In addition, for a region that is not between these two sides, a default color is generated and notified to the color composition unit 35 as in the case of y = 0 to y = 30.

  Since the color synthesizing unit 35 does not require arithmetic processing of pixels between a plurality of levels, the pixel received from the fill data determining unit 34 is output as it is as the final pixel.

  The side processing unit 32 starts tracking two sides belonging to the elliptical object from y = 70. The addition of a new edge from y = 70 is also instructed by an instruction in the instruction stream 231, and the instruction execution unit interprets the instruction to generate an internal command and transfer it to the edge processing unit 32. Here, since the two sides added later are located at coordinates where x is larger than the side of the triangle object 51, it is not necessary to sort the sides (however, the sorting process is performed to track the x-coordinates of the sides). Is done, it just doesn't change order).

  Since the two objects 51 and 52 do not overlap, the level priority determination unit 33, the fill data determination unit 34, and the color synthesis unit 35 operate in substantially the same manner from y = 30 to y = 69.

  The side information needs to be sorted in the scanning line after the side of the triangle object 51 and the side of the ellipse object 52 intersect. Also, since the objects have overlap, a plurality of levels are activated for the same pixel, and an operation for determining the pixel is performed. This situation will be described by taking a process for a scanning line of y = 85 as an example.

  The edge processing unit 32 monitors the intersection of the edges in the process of tracking the edges, and once the intersection is made, the tracing is continued according to the order after the intersection. Therefore, at y = 85, the side of the triangle object 51 and the side of the ellipse object 52 already intersect, and the x coordinate of the side is updated in the order of x0, x1, x2, and x3, and is notified to the level priority determination unit 33. .

  If the transmittance of the ellipse object 52 is not 0, the level priority determination unit 33 activates only level 1 from x0 to x1, activates level 1 and level 2 from x1 to x2, and activates levels from x2 to x3. Only 2 is activated. If the transmittance of the ellipse object 52 is 0, only level 1 is activated from x0 to x1, and only level 2 is activated from x1 to x3. Hereinafter, the description will be continued for the case where the transmittance of the ellipse object 52 is not zero. The level in the active state and the edge information at both ends are notified to the fill data determination unit 34.

  The fill data determination unit 34 generates a default color of a default level from x = 0 to x = x0. From x0 to x1, the color of the level 1 pixel is generated according to the level 1 attribute. From x1 to x2, the color of the pixel of level 1 is generated according to the attribute of level 1, and the color of the pixel of level 2 is generated according to the attribute of level 2. From x2 to x3, the color of the level 2 pixel is generated according to the level 2 attribute. For the pixels from x3 to the right end of the drawing size, a default color of a default level is generated and transferred to the color composition unit 35 in pixel order.

  The color synthesizing unit 35 outputs the pixel color received from the paint data determining unit 34 as it is between x = 0 and x1. For x1 to x2, the level 1 color is superimposed on the default color by the operation specified in level 1 and stacked in the color composition stack 44, and then the data accumulated in the color composition stack 44 is Then, the final pixel color is output by superimposing the level 2 color by applying the operation specified for the level 2. For the pixels from x2 to the right end of the drawing size, the pixel color received from the fill data determining unit 34 is output as it is. However, in the above processing, there is a case where nothing is done for the default color.

  The above processing is executed in a pipeline manner. That is, each module of the instruction execution unit 31, the edge processing unit 32, the level priority determination unit 33, the fill data determination unit 34, and the color composition unit 35 sends an internal command to the module that executes the next processing when its own processing is completed. Is issued to request processing, and when the next processing becomes possible, the internal command from the module that executes the previous processing is accepted. If processing is being executed internally, or if the buffer is full and new processing cannot be accepted, a busy state is notified through a path to the module that executes the previous processing, and notification that processing is not accepted. The module notified of the busy state cannot transfer the internal command to the module that executes the subsequent processing, and a stall occurs.

  As described above, the instruction execution unit 31 reads the display list instruction stream 231, the side processing unit 32 reads the display list side information 232, the side information store 41 reads and writes, and the priority determination unit 33 reads the level table 42. The system RAM 12 is accessed via the bus access arbitration unit 38 when reading / writing the display list fill information 233 and reading / writing the fill data table 43 by the read / write / fill data determination unit 34.

  Latency when accessing the system RAM 12 by the instruction execution unit 31, the edge processing unit 32, the priority determination unit 33, and the fill data determination unit 34 affects the processing time of the entire pixel sequential rendering device 16. In addition, the loads on the instruction execution unit 31, the edge processing unit 32, the priority determination unit 33, and the fill data determination unit 34 are not always constant, and the load may be concentrated on an arbitrary module depending on the image to be drawn. For example, when the number of objects is large but many objects are overwritten on an opaque object and there are few active levels, the edge processing unit 32 has a high load, but the load of other modules is not so high. If there is almost no overlap or many objects are not completely opaque even if they overlap, many levels are activated and the overall load becomes high.

  Furthermore, since the instruction execution unit 31, the edge processing unit 32, the priority determination unit 33, the fill data determination unit 34, the color synthesis unit 35, and the pixel output unit 36 are connected in a pipeline shape, between any modules When the stall occurs, there is a possibility that the processing speed of the pixel sequential rendering device 16 as a whole is reduced. The avoidance or reduction of the processing speed decrease can be achieved by changing the arbitration algorithm of the bus access arbitration unit 38 according to the load of the instruction execution unit 31, the side processing unit 32, the priority determination unit 33, and the fill data determination unit 34. It may be achievable by reducing the latency of access to the system RAM 12 and reducing pipeline stalls.

  In the first embodiment, the load relationship between each pipeline module is estimated based on the frequency of bus access by the instruction execution unit 31, the edge processing unit 32, the priority determination unit 33, and the fill data determination unit 34. FIG. 6 shows the configuration of the arbitration unit in the bus access arbitration unit 38. Although only the edge processing unit 32 is shown in FIG. 6, other pipeline modules and the compatibility guarantee unit 37 are also connected in the same manner.

  In FIG. 6, reference numeral 3861 denotes a bus interface unit, and 3862 denotes a counter that counts bus access requests from each pipeline module. Reference numeral 3863 denotes an encoder that converts the number of bus accesses from each pipeline module into a select signal having an arbitrary value. Reference numeral 3865 denotes a plurality of arbitration units each having a different arbitration algorithm. Reference numeral 3865 denotes a selector, which provides the bus interface 3861 with the arbitration result of any of the plurality of arbitration units 3864 based on the select signal provided by the encoder 3863. Reference numeral 3866 denotes a reset generator that issues a reset to the counter 3862 in an arbitrary period so as to count bus requests every arbitrary period.

  61 is a command transfer bus from the instruction execution unit 31 to the side processing unit 32, and 62 is a command transfer bus from the side processing unit 32 to the priority determination unit 33. 63 is a busy signal notifying that the command cannot be received from the side processing unit 32 to the instruction execution unit 31, and 64 is a busy signal notifying that the command cannot be received from the priority determination unit 33 to the side processing unit 32. 65 is a bus request signal that the side processing unit 32 asserts to the bus access arbitration unit 38 during bus access.

  With the above configuration, the arbitration algorithm is changed by regarding the occurrence frequency of bus access from each pipeline module in an arbitrary period as information related to the load level in each pipeline module.

<Second Embodiment>
In the second embodiment, the load relationship between the pipeline modules is estimated based on the frequency of busy signal assertion by the edge processing unit 32, the priority determination unit 33, and the fill data determination unit 34. FIG. 7 shows the configuration of the arbitration unit in the bus access arbitration unit 38. Although only the edge processing unit 32 is shown in FIG. 7 for simplicity of explanation, other pipeline modules other than the instruction execution unit 31 are similarly connected.

  In FIG. 7, 3871 is a bus interface unit, and 3872 is a counter that monitors the busy signal 63 of each pipeline module and counts the number of assertions. Reference numeral 3873 denotes an encoder that converts a select signal having an arbitrary value based on the value of the number of busy signal assertions from each pipeline module. Reference numeral 3874 denotes a plurality of arbitration units each having a different arbitration algorithm.

  Reference numeral 3875 denotes a selector that provides the arbitration result of one of the plurality of arbitration units 3874 to the bus interface 3871 based on a select signal given by the encoder 3873, and 3876 counts the number of times of busy signal assertion for each arbitrary period. The reset generator issues a reset to the counter 3872 at an arbitrary period.

  With the above configuration, the arbitration algorithm is changed by regarding the assertion frequency of the busy signal from each pipeline module in an arbitrary period as information related to the load height in each pipeline module.

<Third Embodiment>
In the third embodiment, the load relationship between each pipeline module is estimated based on the object information on the scanning line processed at an arbitrary time in the edge processing unit 32, the priority determination unit 33, and the fill data determination unit 34. . FIG. 7 shows the configuration of the arbitration unit in the bus access arbitration unit 38. Although only the edge processing unit 32 is shown in FIG. 8, other pipeline modules other than the instruction execution unit 31 are also connected in the same manner.

  In FIG. 8, reference numeral 3881 denotes a bus interface unit, and 3883 denotes an encoder that converts an object information value from each pipeline module into a select signal having an arbitrary value. Reference numeral 3884 denotes a plurality of arbitration units each having a different arbitration algorithm, and reference numeral 3885 denotes a selector that provides the arbitration result of one of the plurality of arbitration units 3884 to the bus interface 3881 based on a select signal provided by the encoder 3883. Reference numeral 81 denotes a signal for notifying object information such as the number of sides processed by the side processing unit 32 at that time.

  Although only the edge processing unit 32 is shown in FIG. 8, for example, the instruction execution unit 31 outputs the type of the instruction read at that time to the encoder 3883, and the priority determination unit 33 processes at that time. The number of levels existing on the scanning line is output to the encoder 3883, and the pixel data determination unit 34 outputs information about the number of activated levels and the type of the fill algorithm to the encoder 3883.

  With the above configuration, the arbitration algorithm is changed by regarding the information on the object being processed at an arbitrary time in each pipeline module in an arbitrary period as information related to the load level in each pipeline module.

<Other embodiments>
Method for changing arbitration algorithm by encoding information of bus request frequency and busy occurrence frequency by any combination of first embodiment, second embodiment, and third embodiment, bus request occurrence frequency and object Encoding information to change the arbitration algorithm, Busy frequency and object information to encode the mediation algorithm, and Bus request frequency, busy frequency and object information to encode the mediation algorithm Can be implemented.

<Effect of embodiment>
As described above, according to the first to third embodiments, the stall algorithm is changed by changing the arbitration algorithm at the time of bus access by each module constituting the pipeline according to the load relationship between the modules. A high-speed pixel sequential rendering device can be provided by avoiding or reducing or reducing the influence of stall.

1 is a configuration diagram of a rendering system according to the present invention. It is the figure which showed the flow of the function in a rendering system. 1 is a configuration diagram of a pixel sequential rendering apparatus according to the present invention. FIG. It is a figure for demonstrating the outline of the memory access at the time of rendering. It is a figure which shows the example of a drawing object. It is a figure which shows the bus access arbitration algorithm change method by 1st Embodiment. It is a figure which shows the bus access arbitration algorithm change method by 2nd Embodiment. It is a figure which shows the bus access arbitration algorithm change method by 3rd Embodiment.

Claims (12)

A graphic object processing device that performs a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A plurality of processing means for performing a plurality of processes relating to arbitrary attributes of the graphic object;
Bus access arbitration means for arbitrating bus access from each of the plurality of processing means,
The bus access arbitration means includes:
Bus interface means for transferring bus access from the plurality of processing means to the system bus based on the arbitration result; and
State detecting means for detecting a load state of each of the plurality of processing means;
Performs bus arbitration algorithm based on the detection result by the state detecting means, have a control means for controlling said bus interface means,
The bus access arbitration means further includes a request count means for counting the number of bus access requests from each of the plurality of processing means, and a value of the request count means is decoded by a method designated in advance to obtain a select signal. Decoding means for generating,
The control means selects and executes the bus arbitration algorithm based on a select signal generated by the decoding means ;
A graphic object processing apparatus.   The control means has a plurality of different bus arbitration algorithms, respectively, a plurality of arbitration means for executing the bus arbitration algorithm to obtain an arbitration result, and the arbitration means acquired by the plurality of arbitration means based on a select signal 2. The graphic object processing apparatus according to claim 1, wherein the graphic object processing apparatus comprises: selection means for inputting any of the results to the bus interface means. The bus access arbitration means further comprises a reset issuing means for issuing a reset in a predetermined period to the request counting means in order to count the number of bus accesses for each predetermined period. The graphic object processing device according to claim 1 . A graphic object processing device that performs a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A plurality of processing means for performing a plurality of processes relating to arbitrary attributes of the graphic object;
Bus access arbitration means for arbitrating bus access from each of the plurality of processing means,
The bus access arbitration means includes:
Bus interface means for transferring bus access from the plurality of processing means to the system bus based on the arbitration result; and
State detecting means for detecting a load state of each of the plurality of processing means;
Control means for executing a bus arbitration algorithm based on the detection result by the state detection means and controlling the bus interface means,
Each of the plurality of processing means has a busy signal output means for outputting a busy signal indicating that an input cannot be newly accepted,
The bus access arbitration means further includes an assert count means for counting the number of times the busy signal output from each busy signal output means of the plurality of processing means is asserted, and a count value counted by the assert count means. Decoding means for decoding by a method designated in advance and outputting a select signal;
Wherein the control means, wherein the to-tolyl La Fick object processing apparatus that the selected and performs bus arbitration algorithm based on a select signal generated by said decoding means. 5. The graphic object processing apparatus according to claim 4 , wherein the bus access arbitration unit further includes a reset issuance unit that issues a reset in a predetermined period to the assert count unit. A graphic object processing device that performs a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A plurality of processing means for performing a plurality of processes relating to arbitrary attributes of the graphic object;
Bus access arbitration means for arbitrating bus access from each of the plurality of processing means,
The bus access arbitration means includes:
Bus interface means for transferring bus access from the plurality of processing means to the system bus based on the arbitration result; and
State detecting means for detecting a load state of each of the plurality of processing means;
Control means for executing a bus arbitration algorithm based on the detection result by the state detection means and controlling the bus interface means,
Each of the plurality of processing means outputs information on attributes of the graphic object being processed,
The bus access arbitration unit includes a decoding unit that decodes information about the attribute of the graphic object from the plurality of processing units by a method designated in advance and outputs a select signal.
The control means, the select signal the feature and be tolyl La Fick object processing apparatus to select and execute the bus arbitration algorithm based on generated by said decoding means. A graphic object processing method for performing a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A bus access arbitration step of arbitrating bus access from each of a plurality of processing means for performing a plurality of processes related to an arbitrary attribute of the graphic object,
The bus access arbitration step
A transfer step of transferring the bus access from the plurality of processing means to the system bus via the bus interface means based on the arbitration result;
A state detection step of detecting a load state of each of the plurality of processing means;
Performs bus arbitration algorithm based on the detection result by the state detecting step, possess a controlling process of controlling the bus interface unit,
The bus access arbitration step further includes a request count step for counting the number of bus access requests from the plurality of processing means by a request counter, and a count value obtained by the count step by a method designated in advance. A decoding step for decoding and generating a select signal,
The control step selects and executes the bus arbitration algorithm based on a select signal generated by the decoding step .
A graphic object processing method characterized by the above. The control step has different bus request arbitration algorithms, respectively, and executes a bus arbitration algorithm to acquire an arbitration result, and the arbitration results acquired in the plurality of arbitration steps based on a select signal. The graphic object processing method according to claim 7 , further comprising: a selecting step for inputting any of the above to the bus interface means. The bus access arbitration step further includes a reset issuing step of issuing a reset in a predetermined period to the request counter in order to count the number of bus accesses for each predetermined period. The graphic object processing method according to claim 8 , wherein: A graphic object processing method for performing a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A bus access arbitration step of arbitrating bus access from each of a plurality of processing means for performing a plurality of processes related to an arbitrary attribute of the graphic object,
The bus access arbitration step
A transfer step of transferring the bus access from the plurality of processing means to the system bus via the bus interface means based on the arbitration result;
A state detection step of detecting a load state of each of the plurality of processing means;
A bus arbitration algorithm is executed based on the detection result of the state detection step, and the bus interface means is controlled.
Furthermore, a busy signal receiving step of receiving a busy signal indicating that a new input cannot be received from each of the plurality of processing means,
The bus access arbitration step further includes an assert count step of counting the number of times the busy signal output from each of the plurality of processing means is asserted by an assert counter, and a count value counted by the assert counter is designated in advance. A decoding process for decoding by the method and outputting a select signal,
Wherein the control step, wherein the to-tolyl La Fick object processing method that selects and executes the bus arbitration algorithm based on the select signal generated by the decoding process. 11. The graphic object processing method according to claim 10 , wherein the bus access arbitration step further includes a reset issuing step of issuing a reset after a predetermined period with respect to the assert counter. A graphic object processing method for performing a pre-specified process on an arbitrary attribute of a graphic object to form a raster pixel image,
A bus access arbitration step of arbitrating bus access from each of a plurality of processing means for performing a plurality of processes related to an arbitrary attribute of the graphic object,
The bus access arbitration step
A transfer step of transferring the bus access from the plurality of processing means to the system bus via the bus interface means based on the arbitration result;
A state detection step of detecting a load state of each of the plurality of processing means;
A bus arbitration algorithm is executed based on the detection result of the state detection step, and the bus interface means is controlled.
Further, an object information receiving step of receiving information on the attribute of the graphic object being processed from each of the plurality of processing means,
The bus access arbitration step further includes a decoding step of decoding information about the attribute of the graphic object from the plurality of processing means by a method designated in advance and outputting a select signal,
Wherein the control step, wherein the to-tolyl La Fick object processing method that selects and executes the bus arbitration algorithm based on the select signal generated by the decoding process.

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