JP4527079B2 - Equalizer - Google Patents

Description

  The present invention relates to an equalizer, and more particularly to an equalizer that suppresses the influence of multipath.

  A conventional equalizer operates in response to a received signal including a digital data signal, and includes a plurality of taps each responsive to tap coefficients and temporal displacement, and outputs a multipath corrected digital output signal. Includes sparse digital filter. The controller that controls the filter operates in response to the received signal, detects a multipath signal based on the autocorrelation of the received signal, and sets the tap coefficient and the temporal displacement to one of a plurality of taps. By giving, the detected multipath signal is canceled (for example, Patent Document 1).

JP-A-8-237179 (page 3, paragraph 0007, Fig. 2)

  However, when detecting a multipath signal based on autocorrelation as in a conventional equalizer, it is difficult to follow the time change of the multipath. This is because the time for calculating the autocorrelation becomes longer than the time for multipath change. Therefore, it has been difficult for conventional equalizers to sufficiently suppress the effects of multipath such as intersymbol interference.

  The present invention has been made to solve the above-described problems, and can detect a multipath in a shorter time than a conventional equalizer and suppress the influence of the multipath. The purpose is to obtain a generator.

The equalizer according to the present invention includes a first filter that equalizes input data and outputs first equalized data, and a filter coefficient corresponding to an amplitude value and a delay time of delay data included in the input data. An equalizer including a second filter to be updated, and performing Fourier transform on the first equalized data output from the first filter to output frequency domain data A plurality of amplitude values of positive-side or negative-side data from frequency zero in the frequency domain in the result of Fourier transformation by the Fourier transforming means by the transforming means , respectively, and multiplying the multiplication results in the time axis direction and integrating means for performing an integration by integrating the inverse Fourier transform means for performing inverse Fourier transform on the result of the integration in the integrating means, the inverse Fourier transform unit Depending on the result of the Fourier transform, a first calculating means for calculating the amplitude value and the delay time of the delay data included in the input data, the filter of the second filter in accordance with the amplitude value and the delay time A second calculating means for calculating a coefficient; an adder for adding the first equalized data output from the first filter and the second equalized data output from the second filter; A slicer that demaps the output of the adder in accordance with a predetermined modulation method, and the second filter equalizes the output of the slicer and outputs the second equalized data. The

  According to the equalizer according to the present invention, multipath can be detected in a shorter time than a conventional equalizer, and the influence of the multipath can be suppressed.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an equalizer in the first embodiment. In FIG. 1, input data is equalized by an FF (Feed Forward) filter. Data equalized by the FF filter (hereinafter also referred to as first equalized data) is output to the adder 2.

  The input data is data obtained by demodulating a broadcast data transmitted from a broadcast station or the like by a demodulator (not shown) provided in the preceding stage of the equalizer after the broadcast data is received by an antenna (not shown). (Demodulated data). The number of taps of the FF filter is arbitrarily set according to the specification of the equalizer.

  The adder 2 adds the first equalized data input from the FF filter and the data output from the filter block 13 of the sparse filter block 11 described later (hereinafter also referred to as second equalized data). And output to the slicer 4. The slicer 4 performs demapping corresponding to a predetermined modulation method on the data output from the adder 2 and outputs the demap to the second memory 5. Further, the data output from the slicer 4 is output as an output of the equalizer to a device (decoder or the like) arranged at the subsequent stage of the equalizer. Hereinafter, the data output from the slicer 4 is also referred to as output data. The predetermined modulation method is a modulation method used when the broadcast signal is generated in the broadcast station. For example, QPSK, BPSK, multi-level QAM, multi-level VSB, etc. are used as the modulation scheme.

The second memory 5 stores the output data input from the slicer 4. Further, the stored data is output to the filter block 13 in accordance with a signal (hereinafter also referred to as a memory control signal) input from the memory control means 9 described later. The number of data stored in the second memory 5 is ²ⁿ (symbols). N is determined according to the specifications of the equalizer. Specifically, it is set according to the influence of multipath removed by the equalizer (for example, the range of intersymbol interference (delay time range)). For example, if n = 10, data for 1024 symbols is stored in the second memory 5.

  The filter block 13 equalizes the data input from the second memory 5 and outputs the second equalized data to the adder 2. FIG. 2 is a block diagram showing the configuration of the filter block 13. In FIG. 2, the output data output from the second memory 5 is input to the first switch 14. The first switch 14 receives a control signal input from the memory control means 9 (hereinafter, the control signal input from the memory control means 9 to the first switch 14 or the second switch 15 is also referred to as a switch control signal). In response, the small filter 10 for inputting the output data is selected. Then, the output data is input to the small filter 10 selected by the first switch.

  More specifically, the switch control signal is input to the first switch 14 in accordance with the system clock of the equalizer. When a switch control signal is input, the first switch 14 sequentially switches the small filter 10 that receives the output data.

  In the small filter 10, the filter coefficient of the small filter is updated by a filter control signal input from the filter control means 12 (details will be described later). Then, the small filter 10 equalizes the output data using the filter coefficient.

  Similar to the first switch 14, the second switch 15 switches the small filter to be connected according to the switch control signal, and outputs the output data equalized by the small filter to the adder 2.

  FIG. 3 is a block diagram illustrating a configuration of the small filter 10. In FIG. 3, the output data output from the first switch 14 is input to a DDF (Delay Flip-Flop) block 18. Each DDF 101 in the DDF block 18 delays the output data according to the system clock, and outputs the delayed output data to the DDF 101 and the multiplier 102 in the subsequent stage of each DDF 101. Each multiplier 102 in the multiplication block 19 multiplies the filter coefficient set in the multiplier 102 by the output data input from the DDF, and outputs the result to the adder 103.

  The filter coefficient is updated according to the filter control signal output from the filter control means 12. The filter coefficient may be updated by using a LMS (Least Mean Square) algorithm, a sine LMS algorithm, a CMA (Constant Modulus Algorithm), a DD (Decision Direct) algorithm, or the like. The initial value of the filter coefficient may be set in the multiplier 102 in advance, or stored in the filter control unit 12 to be described later, and from the filter control unit 12 when the equalizer is turned on. You may make it input into the multiplier 102. FIG.

  Each adder 103 in the addition block 20 adds the data input from the adder 103 and outputs the result to the subsequent adder 103. The output of the last stage adder 103 (the leftmost adder 103 in FIG. 3) is output to the second switch 15.

In FIG. 1, the first equalized data output from the FF filter is also output to the first memory 3. The first memory 3 stores the first equalized data input from the FF filter 1. Note that the number of data stored in the first memory 3 is ²ⁿ as in the second memory 5. N is determined according to the specifications of the equalizer. Specifically, it is set according to the range of intersymbol interference to be removed by the equalizer. Further, n in the second memory 5 and n in the first memory 3 may be the same value or different values depending on the specifications of the equalizer.

  An FFT (Fast Fourier Transform) means 6 reads data stored in the first memory 3 every predetermined number of symbols. Then, the read data is subjected to FFT and output to the integration means 7.

  The integrating means 7 performs integration on the result of the FFT. FIG. 4 is an explanatory diagram for explaining calculation (integration) in the integration means 7. As shown in FIG. 4, when the input data input to the equalizer is affected by multipath (that is, when the input data includes delay data (delayed wave)), the FFT result A drop in amplitude occurs at a frequency interval that is the reciprocal of the delay time T. Note that the broken line portion 41 in FIG. 4 is the result of the FFT when the input data is not affected by multipath at all (that is, under ideal conditions).

The integrating means 7 is the maximum amplitude value from the frequency 0 (zero) to either the positive side or the negative side among the maximum amplitude values (A _{1 to} A _n ) during the drop in the FFT result as shown in FIG. Is multiplied by a predetermined coefficient (hereinafter also referred to as an integration coefficient), and integration is performed by integrating the multiplication results. That is, the above-described processing is performed on half of the FFT result. Then, the result of integration is output to the IFFT means 8.

  Usually, the result of FFT is a symmetric waveform on the positive side and the negative side with respect to the frequency 0 (ie, the amplitude axis). Therefore, in order to reduce the calculation load, the above-described processing is performed on half of the FFT result (frequency region on one side of the FFT result) using the symmetry. The integration coefficient is arbitrarily set according to the specifications of the equalizer. For example, an appropriate value is set through simulation or experiment.

  The IFFT unit 8 performs an IFFT (Inverse Fast Fourier Transform) on the integration result input from the integration unit 7 and outputs the IFFT result to the memory control unit 9. When IFFT is performed on the integration result, a desired wave (data that is not delay data) included in the input data and a peak (amplitude value) corresponding to the delay data appear on the time axis. That is, by performing the IFFT, it is possible to detect the position (delay time) and amplitude value of the delay data on the time axis.

  Based on the IFFT result input from the IFFT unit 8, the memory control unit 9 determines the amplitude value and delay time of the desired wave data, and the amplitude value and delay time of the delay data (hereinafter, the amplitude value and the delay time). Is also referred to as multipath information). Then, it is determined whether the multipath information has changed as a result of the calculation. That is, it is determined whether or not the multipath information obtained as a result of the calculation matches the multipath information calculated immediately before.

  When the multipath information changes, the multipath information is output to the filter control means 12. The filter control means 12 calculates the filter coefficient of the multiplier 102 according to the algorithm described above in accordance with the multipath information input from the memory control means 9, and outputs a signal corresponding to the filter coefficient to the filter control signal. To the multiplication block 19. The calculated filter coefficient is stored in a storage means (not shown). By storing the calculated filter coefficient in the storage unit, when the multipath information having the same content as the multipath information input in the past is input from the memory control unit, it corresponds to the multipath information. It is possible to output the filter coefficient stored in the storage means without calculating the filter coefficient again.

  The memory control means 9 generates a switch control signal based on the system clock and outputs it to the first switch means 14 and the second switch means 15. When detecting the new multipath, the amplitude values included in the multipath information may be rearranged in order of increasing or decreasing value.

  As described above, according to the equalizer in the first embodiment, multipath detection is performed using FFT without using autocorrelation, so that it is faster than conventional equalizers. Multipath detection can be performed. Therefore, it is possible to satisfactorily follow multipath fluctuations that change rapidly over time. Therefore, the influence of multipath (intersymbol interference, etc.) can be suppressed.

  Further, in the equalizer according to the first embodiment, the calculation load can be reduced and the calculation speed can be constrained by performing processing such as integration only on one side of the frequency domain in the FFT result. Therefore, it is possible to satisfactorily follow multipath fluctuations with a large temporal change, and to effectively suppress the influence of multipath.

It is a block diagram which shows the structure of the equalizer in Embodiment 1 of this invention. 3 is a block diagram showing a configuration of a filter block 13. FIG. 2 is a block diagram showing a configuration of a small filter 10. FIG. It is explanatory drawing for demonstrating the calculation in the integration means.

Explanation of symbols

  1 FF filter, 2 adder, 3 first memory, 4 slicer, 5 second memory, 6 FFT means, 7 integration means, 8 IFFT means, 9 memory control means, 11 sparse filter block, 12 filter control means, 13 Filter section lock.

Claims (4)

A first filter that equalizes input data and outputs first equalized data; and a second filter whose filter coefficient is updated according to the amplitude value and delay time of delay data included in the input data. An equalizer comprising:
Fourier transform means for performing Fourier transform on the first equalized data output from the first filter and outputting frequency domain data ;
By multiplying a plurality of amplitude values of positive or negative side data from frequency zero in the frequency domain in the result of Fourier transform by the Fourier transform means by respective predetermined coefficients, and integrating the multiplication results in the time axis direction Integration means for performing integration;
Inverse Fourier transform means for performing inverse Fourier transform on the result of integration in the integration means;
First computing means for computing an amplitude value and a delay time of the delay data included in the input data according to the result of the inverse Fourier transform in the inverse Fourier transform means;
Second calculating means for calculating the filter coefficients of the second filter in accordance with the amplitude value and the delay time,
An adder for adding the first equalized data output from the first filter and the second equalized data output from the second filter;
A slicer that performs demapping corresponding to a predetermined modulation method on the output of the adder;
Equipped with a,
The second filter equalizes the output of the slicer and outputs the second equalized data.
Equalizer you wherein a. The equalizer according to claim 1, wherein the input data is demodulated data obtained by receiving and demodulating transmitted broadcast data by an antenna . A first filter that equalizes input data and outputs first equalized data; and a second filter whose filter coefficient is updated according to the amplitude value and delay time of delay data included in the input data Using an equalization method,
For the first of the output from the filter first equalized data, the Fourier transform output data lines Do I frequency domain,
Wherein each from zero frequency of the frequency region in the result of the Fourier transform to a plurality of amplitude values of the data of the positive side or the negative side is multiplied by a predetermined coefficient, it performs integral by integrating the multiplication result in the time axis direction,
Inverse Fourier transform is performed on the result of the integration,
According to the result of the inverse Fourier transform, the amplitude value and the delay time of the delay data included in the input data are calculated,
Calculating a filter coefficient of the second filter according to the amplitude value and the delay time ;
Adding the first equalized data output from the first filter and the second equalized data output from the second filter;
Look including the <br/> to perform demapping corresponding to a predetermined modulation scheme for the addition result
The second filter equalizes data obtained by performing the demapping and outputs the second equalized data.
An equalization method characterized by that . 4. The equalization method according to claim 3, wherein the input data is demodulated data obtained by receiving and demodulating transmitted broadcast data by an antenna .

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