JP4522730B2 - Subordinate apparatus and provisioning support method - Google Patents

Description

  The present invention relates to a subordinate device that is connected to a host device via a connector and is detachable, and a provisioning support method that realizes starting of the subordinate device in cooperation with the host device.

In a transmission device that is mounted on a frame or shelf and realizes a predetermined function by linking the upper unit and the lower unit under a hierarchical system configuration, each lower unit is in the process of maintenance and operation. In order to realize mounting and replacement, for example, many connectors suitable for hot-plug insertion / removal are applied.
In addition, in recent years, such lower-level devices are loaded at the time of startup, such as FPGA (Field Prgramble Gate Array) and DSP (Digital Signal Processor), for the purpose of standardizing the hardware configuration and realizing high added value. Many devices are defined whose functions and behaviors are defined according to the software.

FIG. 7 is a diagram illustrating a configuration example of a conventional transmission apparatus.
In the figure, connectors 41-1, 41-2, 41-3 are mounted on a backboard 40 provided in a predetermined frame or shelf, and these connectors 41-1, 41-2, 41-3 are connected via these connectors 41-1, 41-2, 41-3. Thus, a network element manager unit (hereinafter referred to as “NEM”) 50 that is a higher-level device, a power supply unit 60, and a unit 70 that is a lower-level device are connected.

In addition to the processor (CPU) 51, the NEM 50 has “one terminal connected to the DC power supply line 52 formed inside the NEM 50 and the other terminal connected to a specific input port of the processor 51. A resistor 53 "is provided.
The unit 70 includes the following elements.
The output of the power supply unit 60 described above has a connector 41-1, a printed circuit formed on the backboard 40, and an input terminal connected via the connector 41-3. The output terminal is connected to each part of the unit 70. Connected DC / DC converter 71
"Connected to the other terminal of the resistor 53 through the connector 41-1, the printed circuit formed on the backboard 40 and the connector 41-3, and through the connector 41-3 and the backboard 40. “CONFIG START” terminal grounded on the unit 60 and “a specific output port of the processor 51 described above via the connector 41-1, the printed circuit formed on the backboard 40, and the connector 41-3. FPGA 72 having “DATA IN” terminal connected to each other
A ROM 73 having a control terminal connected to the “CONFIG START” terminal of the FPGA 72, and an output connected to the PROG terminal of the FPGA 72.
In the transmission apparatus having such a configuration, for example, in a state where the NEM 50 is connected to the backboard 40 via the connector 41-1 and the power supply unit 60 is connected to the backboard 40 via the connector 41-2. When the unit 70 is connected to the backboard 40 via the connector 41-3, each unit operates as follows.

  In the unit 70, the FPGA 72 sets a logical value of a “DONE signal” described later to “0”. Further, the ROM 73 is grounded on the unit 70 through the connector 41-3 and the back board 40 together with the “CONFIG START” terminal of the FPGA 72 as described above (FIG. 7 (1), FIG. 8 (a). ) (1)), and a program indicating the configuration of “a circuit that is stored in advance in the ROM 73 and should be formed in the FPGA 72 (hereinafter referred to as“ internal circuit ”)” collectively, the PROG terminal of the FPGA 72 (Fig. 8 (a) (2)).

  The FPGA 72 starts taking in such a program when the “CONFIG START” terminal is grounded as described above, and holds the program in a register provided therein, thereby configuring the internal circuit described above. Is determined (FIGS. 8 (a) (3)). Further, the FPGA 72 updates the logical value of the “DONE signal” described above to “1”, thereby notifying each unit of the unit 70 (FIGS. 8A and 4).

On the other hand, in the NEM 50, the potential v of the other terminal of the resistor 53 is such that when the unit 70 is mounted on the backboard 40 via the connector 41-3, the “CONFIG START” terminal of the FPGA 72 inside the unit 70. Are grounded together with the control terminal of the ROM 73 (FIGS. 8A and 5).
When the above-mentioned potential v becomes lower than the potential V of the power supply line 52 in accordance with such grounding, the processor 51 sends the message to the unit 70 via the connector 41-1, the backboard 40, and the connector 41-3 according to “NEM50. The unit 70 is shown under a centrally managed system configuration, and information to be referred to by the FPGA 72 (hereinafter referred to as “provisioning information”) in the course of operation of the unit 70 is given (FIG. 8A). 6)) In the following, a signal given to the processor 51 with the above potential v as an instant is referred to as a “mounting notification signal”.

The FPGA 72 takes in the provisioning information given through the “DATA IN” terminal and refers to it appropriately (FIGS. 8A and 7).
Hereinafter, the process performed when the unit 70 is started under the cooperation of the NEM 50 and the unit 70 in this manner is referred to as “provisioning”.
In addition, as a prior art related to the present invention, as disclosed in Patent Document 1 below, “a package mounted in an individual slot although the type of package mounted in each slot is not limited” Communication apparatus and communication in which setting data suitable for the type of the package is set in a package mounted in a desired slot and a communication path is established without setting data suitable for the type of the system being set from an external system There is a network management system.
JP 2000-10904 A

By the way, in the above-described conventional example, when the unit 70 is physically mounted on the backboard 40 and the potential v described above falls below the potential V, the processor 51 immediately starts sending provisioning information.
That is, the registers provided in the FPGA 72 cannot always hold all of the programs described before the provisioning information is given (FIGS. 8B and 8A).

Therefore, the FPGA 72 does not start normally, and since a regular function in cooperation with the processor 51 is not realized, the FPGA 51 may be identified as abnormal by the processor 51.
Such a problem can be solved by, for example, standardizing the time when provisioning information is started to be sent out by the processor 51 as the time elapsed from “the time when the potential v described above has decreased from the potential V”. .

  However, such time varies depending on the number and combination of units mounted under the NEM 50, and a failure has occurred in “another unit that has already been mounted” prior to the time point. In this case, the processor 51 must preferentially perform the failure processing of the corresponding unit, so that the value must be set to a value large enough to ensure that this failure processing is performed.

  In recent years, a removable package such as the unit 70 described above is equipped with many FPGAs, DSPs, and other general-purpose processors for the purpose of enhancing functions and realizing desired performance at a low cost. Since the loading of large size programs had to be completed prior to the above, the above time had to be extended further.

Moreover, the point at which provisioning information is started to be sent out by the processor 51 is likely to vary widely depending on the load of the processor 51 (NEM 50) and the number and combination of units installed under the processor 51 (NEM 50).
An object of the present invention is to provide a subordinate unit and a provisioning support method in which provisioning is started promptly without any unnecessary suspension regardless of the system configuration.

In one aspect of the present invention, the lower-level device is connected to a higher-level device that supplies information related to the system configuration via a connector, and is loaded according to the physical implementation of the lower-level device under the higher-level device. It is a lower-level device whose function is determined based on the hardware, and implementation information that means that information can be imported when software loading is completed and physical implementation continues. A provisioning support means for sending to the host device is provided.
In the first technique related to the present invention, a function is determined based on software loaded in accordance with physical implementation, and connected to a host device that supplies information related to the system configuration via a connector. In the lower apparatus, the provisioning support means sends mounting information indicating that the information can be taken in to the upper apparatus when the software loading is completed and the physical mounting is continued.

In other words, the information related to the above-described system configuration is supplied to the lower-level device according to the present technology by the higher-level device after the loading of the software is completed regardless of the size of the software described above.
Therefore, not only the functions of the lower-level devices implemented under the higher-level devices, but also the start-up delay due to the unnecessarily lapse of time during the provisioning process is avoided regardless of the number and combination of such lower-level devices. Can be flexibly adapted to various unit combinations.

In the second technique related to the present invention , the provisioning support means sends the mounting information via an element or a circuit that guarantees the activeness of the mounting information when power is not supplied in the subordinate apparatus related to the first technique. .
That is, the mounting information of the lower level device related to the present technology is stored in the higher level device even if the “power source that supplies power to the lower level device and is supplied separately from the power source that supplies power to the lower level device” fails. It is given continuously, and supervisory control is continuously performed by this host device.

Therefore, flexible adaptation to various system configurations is possible.
In the third technology related to the present invention, in the subordinate device related to the first technology , the provisioning support means sends the mounting information via an element or circuit that guarantees the inactivity of the mounting information when power is not supplied. The mounting information sent out and sent to the host device is held by the power supplied to the host device.

That is, when a lower-level device related to the present technology is physically mounted, the power supply for supplying main power to the lower-level device is transiently active for the higher-level device until the power source shifts to a steady state. It is avoided that the mounting information is transmitted. However, the active mounting information once sent to the host device is retained as long as the power supply operates normally.
Therefore, in the low-order apparatus according to the present technology , maintenance and operation are smoothly performed without causing unnecessary disturbance in the system configuration.

In the fourth technology related to the present invention, in the subordinate apparatus according to any one of the first technology to the third technology , the mounting information is grounded or supplied with power to the wiring for transmission of the mounting information. This is binary information indicating the activity in one of the first state and the second state in which the wiring is not grounded or fed.
That is, the mounting information of the lower device related to the present technology is reliably transmitted to the upper device via a single wiring.

Therefore, compared with the case where such mounting information is transmitted to the host device via a plurality of bit strings or a plurality of wirings laid in parallel, it is not obstructed by restrictions on mounting or wiring. Flexible adaptation to various system configurations becomes possible.
In the fifth technique related to the present invention, loading of software indicating a lower device connected to the upper device via a connector is started in accordance with physical implementation and indicates the function of the lower device. In addition, when the physical mounting is continued, the mounting information indicating that the information related to the system configuration can be fetched is transmitted to the host device.

That is, the information related to the above-described system configuration is supplied to the lower device by the upper device after the loading of the software is completed regardless of the size of the software described above.
Therefore, not only the functions of the lower-level devices implemented under the higher-level devices, but also the start-up delay due to the unnecessarily lapse of time during the provisioning process is avoided regardless of the number and combination of such lower-level devices. Can be flexibly adapted to various unit combinations.

In a sixth technique related to the present invention, in the provisioning support method according to the fifth technique , the mounting information is transmitted via an element or a circuit that guarantees the activeness of the mounting information when power is not supplied.
That is, the mounting information of the lower-level device is continuously given to the higher-level device even when “a power source that supplies power to the higher-level device and supplies power to the lower-level device” fails. Monitoring control is continuously performed by the host device.

Therefore, flexible adaptation to various system configurations is possible.
In a seventh technique related to the present invention, in the provisioning support method according to the fifth technique , the mounting information is transmitted via an element or a circuit that guarantees the inactivity of the mounting information when power is not supplied. The mounting information sent to the host device is held with the power supplied to the host device.

That is, when a lower-level device is physically mounted, transiently active mounting information is sent to the higher-level device until the power source that supplies main power to the lower-level device shifts to a steady state. Is avoided. However, the active mounting information once sent to the host device is held stably as long as the power supply operates normally.
Therefore, in the lower-level device, maintenance and operation can be smoothly performed without causing unnecessary disturbance in the system configuration.

According to an eighth technique related to the present invention, in the provisioning support method according to any of the fifth technique to the seventh technique , the mounting information is a ground wire or power supply for transmission of the mounting information. This is binary information indicating the activity in one of the first state to be performed and the second state in which the wiring is not grounded or fed.
That is, the mounting information of the lower apparatus is reliably transmitted to the upper apparatus via a single wiring.

  Therefore, compared with the case where such mounting information is transmitted to the host device via a plurality of bit strings or a plurality of wirings laid in parallel, it is not obstructed by restrictions on mounting or wiring. , Flexible adaptation to various system configurations becomes possible.

In the first and fifth technologies related to the present invention, not only in the function of the lower device implemented under the upper device, but also in the provisioning process regardless of the number and combination of such lower devices. Thus, a delay in starting due to the passage of time is avoided, and flexible adaptation to various unit combinations becomes possible.
The second and sixth techniques related to the present invention enable flexible adaptation to various system configurations.

In the third and seventh techniques related to the present invention, maintenance and operation of the lower-level apparatus can be smoothly realized without causing unnecessary disturbance in the system configuration.
In the fourth and eighth technologies related to the present invention , the mounting information and the wiring are compared with the case where the mounting information is transmitted to the host device through a plurality of bit strings or a plurality of wirings laid in parallel. It is possible to flexibly adapt to various system configurations without being hindered by restrictions on lines.

Therefore, in devices and systems to which these technologies are applied, the efficiency of maintenance and operation work that involves attaching and detaching lower-level devices is maintained at a high level, regardless of the system configuration, and overall reliability is improved. Thus, the cost can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First embodiment]
FIG. 1 is a diagram showing a first embodiment of the present invention.
The feature of this embodiment is the configuration of a unit 70A provided in place of the unit 70 shown in FIG.

The configuration of the unit 70A is different from the configuration of the unit 70 shown in FIG. 7 in the following points.
The other terminal of the resistor 53 provided in the NEM 50 is connected to a corresponding terminal (hereinafter referred to as “RMV terminal”) of the connector 41-3 via the connector 41-1 and the backboard 40. The RMV terminal is not connected to the “CONFIG START” terminal of the FPGA 72 on the unit 70A.
The primary side anode terminal and the secondary side source terminal are connected to the DONE terminal of the FPGA 72 and the RMV terminal, respectively, and the primary side cathode terminal is grounded, and the secondary side drain terminal is connected A photo moss relay 11 connected to a “CONFIG START” terminal of the FPGA 72 is provided.

FIG. 2 is a time chart of the first embodiment of the present invention.
The operation of the first embodiment of the present invention will be described below with reference to FIG. 1 and FIG.
In a state where the NEM 50 is connected to the backboard 40 via the connector 41-1 and the power supply unit 60 is connected to the backboard 40 via the connector 41-2, the backboard 40 is connected to the backboard 40 via the connector 41-3. When the unit 70A is connected, each unit operates as follows.

In the unit 70A, the FPGA 72 sets the logical value of the aforementioned “DONE signal” to “0” (here, it is assumed that the potential of the DONE terminal is set to 0 volts).
Therefore, the secondary side of the photo MOS relay 11 is set to an off state, and the potential v of the other terminal of the resistor 53 provided in the NEM 50 is maintained at a value equal to the potential V described above.
However, the ROM 73 is grounded on the unit 70 via the connector 41-3 and the backboard 40 together with the “CONFIG START” terminal of the FPGA 72 (FIG. 1 (1), FIG. 2 (1)). Therefore, as in the conventional example, a program stored in advance in the ROM 73 and indicating the configuration of the internal circuit to be formed inside the FPGA 72 is read in a lump and applied to the PROG terminal of the FPGA 72 (FIG. 2 ( 2)).

The FPGA 72 starts taking in such a program when the “CONFIG START” terminal is grounded as described above, and holds the program in a register provided therein, thereby configuring the internal circuit described above. Is confirmed (FIG. 2 (3)).
Further, the FPGA 72 fetches all such programs and holds them in a register provided therein (FIG. 2 (a)), and sets the logical value of the aforementioned “DONE signal” to “1”. (Here, it is assumed that the potential of the DONE terminal is set to a predetermined value higher than 0 volts) (FIG. 2 (4)).

Since the secondary side of the photo-moss relay 11 is injected into the primary side of the photo-moss relay 11 in accordance with the positive voltage applied by the DONE terminal, the photo-mos relay 11 transitions from the off state to the on-state (see FIG. 2 (b)).
In the NEM 50, the other terminal of the resistor 53 is the connector 41-1, the backboard 40, and the connector 41 as the other terminals as long as the unit 70A is mounted on the backboard 40 via the connector 41-3. -3, grounded on the unit 70A via the path (FIG. 1 (2)) including the secondary side of the photo MOS relay 11, the connector 41-1, the backboard 40, and the connector 41-3.

Therefore, the potential v of the other terminal of the resistor 53 drops to a value less than the potential V of the power supply line 52 (FIG. 2 (c)).
The processor 51 indicates to the unit 70A via the connector 41-1, the backboard 40, and the connector 41-3 that “the unit 70A is shown under a system configuration managed centrally by the NEM 50, and the operation of the unit 70A is performed. In the process, provisioning information referred to by the FPGA 72 is given (FIG. 2 (6)).

The FPGA 72 fetches and refers to provisioning information given via the “DATA IN” terminal (FIG. 8 (7)).
That is, provisioning information is given to the FPGA 72 by the processor 51 after all the programs are given to the FPGA 72.
Therefore, the provision of provisioning information by the processor 51 (NEM 50) is immediately started as soon as the loading of the program is completed regardless of the size of the program collectively given to the FPGA 72 by the ROM 73.

As described above, according to the present embodiment, regardless of the number or combination of units mounted under the NEM 50, delays in starting due to unnecessary passage of time during the provisioning process can be avoided, and various Flexible adaptation to the desired combination of units is possible.
[Second Embodiment]
FIG. 3 is a diagram showing a second embodiment of the present invention.

The difference in configuration between the present embodiment and the first embodiment described above lies in the configuration of a unit 70B provided instead of the unit 70A.
The configuration of the unit 70B is different from the configuration of the unit 70A in the following points.
A “resistor 21 that pulls up the anode terminal on the primary side of the photo-moss relay 11” and an “open collector inverter 22 whose input is connected to the DONE terminal of the FPGA 72 and whose output is connected to the anode terminal”; Is provided.
A photo moss relay 11B is provided instead of the photo mos relay 11.

FIG. 4 is a time chart of the second embodiment of the present invention.
The operation of the second embodiment of the present invention will be described below with reference to FIGS.
The characteristics of this embodiment are the characteristics of the photo moss relay 11B and the following operation in which the FPGA 72 drives the photo moss relay 11B via the resistor 21 and the inverter 22.
The photo-moss relay 11B maintains the secondary side in an on state when no current is injected into the primary side, and conversely maintains the secondary side in an off state when the current is injected. Type "photo moss relay.

However, the anode of such a photoMOS relay 11B is driven by the FPGA 72 via the inverter 22.
Therefore, in both the provisioning process and after the provisioning is completed, the photocoupler 11B performs the same behavior as the photocoupler 11 shown in FIG. 1 by the combination of the resistor 21 and the converter 22 (FIG. 4 ( 1) to (4), (6), (7), (a) to (c)).

In addition, when the DC / DC inverter 71 that supplies power to each part of the unit 70B fails after the provisioning is completed and the supply of the power is stopped, the open collector of the output stage of the inverter 22 is stopped. The transistor is turned off.
Further, in the photocoupler 11B, current is not injected into the primary-side anode terminal not only by the final stage of the inverter 22, but also by the resistor 21.

That is, even if the DC / DC converter 71 fails after the provisioning is completed, since the secondary side of the photoMOS relay 11B is turned on, the state of the unit 70B identified by the processor 51 monitoring the potential v in the NEM 50 Is regarded as an “implemented state” (FIG. 4 (P)).
Thus, according to the present embodiment, such a unit 70B is subject to monitoring control performed by the processor 51 (NEM 50) without being hindered by the failure of the DC / DC converter 71 (FIG. 2 (P)). .

Therefore, it is possible to flexibly adapt to various system configurations as compared with the first embodiment described above.
[Third embodiment]
FIG. 5 is a diagram showing a third embodiment of the present invention.
The feature of the configuration of the present embodiment is the configuration of a unit 70C provided instead of the unit 70A.

The configuration of the unit 70C is different from the configuration of the unit 70A in the following points.
The DONE terminal of the FPGA 72 is connected to the anode terminal on the primary side of the photomoss relay 31 (which is a “normally off type photomoss relay like the photomoss relay 11) instead of the photomoss relay 11. The primary cathode terminal is grounded.
The source terminal on the secondary side of the photo MOS relay 31 is connected to the anode output of the power supply unit 60 (here, it is assumed that it is connected via the connector 41-2, the backboard 40, and the connector 41-3). .) Connected to the ground line 32GND, the drain terminal on the secondary side is connected to one terminal of the resistor 34 and the base of the transistor 35 on the NPN side through the resistor 33.
The anode terminal on the primary side of the photo MOS relay 11 is connected to the collector of the PNP transistor 36, and the emitter of the transistor 36 is connected to the ground line 32GND described above.
The cathode terminal on the primary side of the photo MOS relay 11 is connected to the base of the NPN transistor 38 and one terminal of the resistor 39 via the resistor 37.
The base of the transistor 36 is connected to the ground line 32GND via the resistor 40, and is connected to the collector of the NPN transistor 35 via the resistor 41, and is connected to the collector of the NPN transistor 35 via the resistor 42. 38 collectors are connected.
The other terminals of the resistors 34 and 39 and the emitters of the transistors 35 and 38 are connected to the cathode output of the power supply unit 60 (here, via the connector 41-2, the back board 40, and the connector 41-3). Connected to the power line 32N.

FIG. 6 is a time chart of the third embodiment of the present invention.
The operation of the third embodiment of the present invention will be described below with reference to FIGS.
In a state where the NEM 50 is connected to the backboard 40 via the connector 41-1 and the power supply unit 60 is connected to the backboard 40 via the connector 41-2, the backboard 40 is connected to the backboard 40 via the connector 41-3. When the unit 70C is connected, each unit operates as follows.

In the unit 70C, the FPGA 72 sets the logical value of the “DONE signal” described above to “0”.
Therefore, the secondary side of the photoMOS relay 31 is set to an off state, and the transistor 35 is set to an off state because no current is injected into the base. Further, transistor 36 is turned off because the base is terminated by resistor 40, and transistor 38 is blocked by transistor 36 from forming a single path for current to be injected into the base. Turns off.

That is, the potential v of the other terminal of the resistor 53 provided in the NEM 50 is maintained at a value equal to the above-described potential V because the secondary side of the photoMOS relay 11 is turned off.
However, the ROM 73 is grounded on the unit 70C via the connector 41-3 and the backboard 40 together with the “CONFIG START” terminal of the FPGA 72 (FIG. 6 (1)), so the ROM 73 is a conventional example. In the same manner as described above, a program indicating the configuration of an internal circuit stored in advance in the ROM 73 and to be formed in the FPGA 72 is collectively applied to the PROG terminal of the FPGA 72 (FIG. 6 (2)).

The FPGA 72 starts taking in such a program when the “CONFIG START” terminal is grounded as described above, and holds the program in a register provided therein, thereby configuring the internal circuit described above. Is determined (FIG. 6 (3)).
Further, the FPGA 72 fetches all such programs and holds them in a register provided therein (FIG. 6A), and sets the logical value of the aforementioned “DONE signal” to “1”. (Here, it is assumed that the potential of the DONE terminal is set to a predetermined value higher than 0 volts) (FIG. 6 (4)).

The secondary side of the photo-moss relay 31 transitions from the off state to the on state because current is injected into the primary side according to the positive potential applied by the DONE terminal (FIG. 6 (b)).
The transistor 35 is turned on because the base current is injected through the secondary side of the photo MOS relay 31 and the resistor 33 (FIG. 6A).
Since the base current flows through the path from the ground line 32GND through the emitter of the transistor 36 and the resistor 41 to the emitter of the transistor 35, the transistor 36 is turned on (FIG. 6B). Further, the secondary side of the photo MOS relay 11 is turned on because current is injected into the primary side through the transistor 36 which is turned on in this way. The transistor 38 is turned on because a part of this current is injected into the base.

Therefore, a path through which the base current of the transistor 36 flows is ensured by the resistor 42 and the transistor 38 even when the transistor 35 returns to the off state.
In the NEM 50, the other terminal of the resistor 53 is the other terminal as in the first embodiment as long as the unit 70C is mounted on the backboard 40 via the connector 41-3. Is grounded on the unit 70A through a path comprising the connector 41-1, the backboard 40, the connector 41-3, the secondary side of the photo MOS relay 11, the connector 41-3, the backboard 40 and the connector 41-3. The

Therefore, the potential v of the other terminal of the resistor 53 is maintained at a value less than the potential V of the power supply line 52 (FIG. 6C).
The processor 51 indicates to the unit 70C via the connector 41-1, the backboard 40, and the connector 41-3 that “the unit 70C is shown under a system configuration managed centrally by the NEM 50, and the operation of the unit 70C is performed. In the process, provisioning information referred to by the FPGA 72 is given (FIG. 6 (6)).

The FPGA 72 fetches the provisioning information via the “DATA IN” terminal and refers to it appropriately (FIG. 6 (7)).
That is, provisioning information is given to the FPGA 72 by the processor 51 after all the programs are given to the FPGA 72.
Thus, according to the present embodiment, the photo MOS relay 11 provided in the unit 70C for setting the potential v monitored by the processor 51 in the NEM 50 to be equal to or lower than the potential V is not “normally on type” but “normal”. The circuit formed between the stages of the photo MOS relay 31 and the photo MOS relay 11 is continued by the power supply unit 60 even when the DC / DC converter 71 fails. The photo moss relay 11 is maintained in the ON state by the supplied electric power (FIG. 6 (P)).

Further, when the unit 70C is physically mounted on the backboard 40 via the connector 41-3, the photo MOS relay 11 is a “normally off type” photo MOS relay, so that the DC / DC converter 71 is It is avoided that the potential v is transiently lower than the potential V (FIG. 4 (Q)) until the transition to the steady state (FIG. 6 (Q)).
In each of the above-described embodiments, the units 70A to 70C include the FPGA 72 as an element whose function and behavior are determined according to the loaded program.

However, such an element is not limited to a programmable gate array, and may be, for example, a digital signal processor (DSP) or other general-purpose processor, and any of these programmable gate arrays, digital signal processors, and general-purpose processors may be used. It may be a combination.
In each of the above-described embodiments, the units 70A to 70C are provided with the ROM 73 in which a program loaded to the FPGA 72 is stored in advance.

However, such a ROM 73 or a storage device (element) that can replace the ROM 73 may be arranged in any package other than the NEM 50, the backboard 40, and the power supply unit 60.
Further, in each of the above-described embodiments, the present invention is applied to the transmission apparatus as in the conventional example shown in FIG.

However, the present invention is not limited to such a transmission apparatus, and can be applied to various apparatuses regardless of the presence or absence of the backboard 40 as long as it is configured as a set of units and packages mounted on a frame or shelf. Applicable.
Further, in each of the above-described embodiments, the potential v is a photo moss connected via a single wiring from the units 70A to 70C to the NEM 50 via the connector 41-3, the backboard 40, and the connector 41-1. It is handed over by the secondary side of the relay, and is increased or decreased according to binary information that takes one of a “power-free / non-grounded state” and a “grounded state”.

However, such binary information indicated by the potential v may be delivered from the units 70A to 70C to the NEM 50 based on a desired transmission method.
Furthermore, in each embodiment mentioned above, unit 70A-70C is comprised as a unit which can be attached or detached via the connector 41-3 which enables hot-swap.
However, in these units 70A to 70C, for example, when the physical attachment to the connector 41-3 is completed, the connection sequence of the power supply line and the signal line is appropriate through a switch that operates automatically or manually. It may be configured as a unit set to

Further, the present invention is not limited to the above-described embodiment, and various embodiments can be made within the scope of the present invention, and any improvement may be applied to all or part of the constituent devices. .
Hereinafter, the invention disclosed in each of the above-described embodiments is arranged hierarchically and multifacetedly and listed as an additional item.
(Supplementary note 1) In a lower-level device whose function is determined based on software loaded according to physical implementation and connected to a higher-level device that supplies information related to the system configuration via a connector,
Provided with provisioning support means for sending mounting information to the host device, which means that the information can be captured when loading of the software is completed and the physical mounting is continued Subordinate device characterized by that.
(Supplementary Note 2) In the subordinate device described in Supplementary Note 1,
The provisioning support means includes
A subordinate apparatus, wherein the mounting information is transmitted via an element or a circuit that guarantees the activeness of the mounting information when power is not supplied.
(Supplementary Note 3) In the subordinate device described in Supplementary Note 1,
Provisioning support means
When the power is not supplied, the mounting information is transmitted via an element or a circuit that guarantees the inactivity of the mounting information, and the mounting information transmitted to the host device is held with the power supplied to the host device. A subordinate apparatus characterized by comprising means.
(Supplementary note 4) In the subordinate apparatus according to any one of supplementary notes 1 to 3,
The mounting information is
Binary information indicating the activity in one of a first state in which the wiring provided for transmission of the mounting information is grounded or supplied with power and a second state in which the wiring is not grounded or supplied with power A subordinate device characterized by that.
(Supplementary Note 5) With respect to a lower level device connected to a higher level device via a connector, loading of software indicating a function of the lower level device that is started according to physical mounting is completed, and the physical mounting is completed. The provisioning support method is characterized in that, when the process continues, the implementation information indicating that the information related to the system configuration can be taken in is sent to the host device.
(Appendix 6) In the provisioning support method described in Appendix 5,
The provisioning support method, wherein the mounting information is transmitted via an element or a circuit that guarantees the activeness of the mounting information when power is not supplied.
(Supplementary note 7) In the provisioning support method described in supplementary note 5,
Sending the mounting information via an element or circuit that guarantees the inactivity of the mounting information when power is not supplied, and holding the mounting information sent to the host device with the power supplied to the host device. A provisioning support method characterized by the above.
(Supplementary note 8) In the provisioning support method according to any one of supplementary notes 5 to 7,
The mounting information is
Binary information indicating the activity in either one of a first state in which the wiring provided for transmission of the mounting information is grounded or supplied with power and a second state in which the wiring is not grounded or supplied with power A provisioning support method characterized by

It is a figure which shows 1st embodiment of this invention. It is a time chart of 1st embodiment of this invention. It is a figure which shows 2nd embodiment of this invention. It is a time chart of 2nd embodiment of this invention. It is a figure which shows 3rd embodiment of this invention. It is a time chart of 3rd embodiment of this invention. It is a figure which shows the structural example of the conventional transmission apparatus. It is a time chart of a prior art example.

Explanation of symbols

11, 11B, 31 Photo MOS relay 21, 33, 34, 37, 39, 40, 41, 42, 53 Resistor 22 Inverter 32N, 52 Power line 32 GND Ground line 35, 36, 38 Transistor 40 Backboard 41 Connector 50 Network Element manager 51 Processor (CPU)
60 Power supply unit 70, 70A, 70B, 70C Unit 71 DC / DC converter 72 FPGA
73 ROM

Claims (5)

It is connected via a connector to a host device supplies information relating to the system configuration, and subordinate functions based on software that is loaded in accordance with the physical implementation of the lower device Ru is determined to subordinate the host system In the device
Provided with provisioning support means for sending mounting information to the host device, which means that the information can be captured when loading of the software is completed and the physical mounting is continued Subordinate device characterized by that. The subordinate device according to claim 1,
The provisioning support means includes
The subordinate apparatus , wherein when the supply of power by an internal power supply is stopped in the subordinate apparatus, the implementation information is transmitted via an element or a circuit that guarantees the activeness of the implementation information. The subordinate device according to claim 1,
Provisioning support means
When the supply of power from the internal power supply is stopped in the lower-level device, the mounting information is sent via an element or circuit that guarantees the inactivity of the mounting information, and the mounting information sent to the higher-level device is externally transmitted. A subordinate device comprising means for holding with power supplied from a power source to the subordinate device. In the subordinate device according to any one of claims 1 to 3,
The mounting information is
Binary information indicating the activity in one of a first state in which the wiring provided for transmission of the mounting information is grounded or supplied with power and a second state in which the wiring is not grounded or supplied with power A subordinate device characterized by that. For the lower level device connected to the higher level device via a connector, the loading of the software indicating the function of the lower level device is started and started according to the physical implementation of the lower level device under the higher level device. And, when the physical mounting is continued, the provisioning support method is characterized in that mounting information which means that it is possible to take in information related to the system configuration is sent to the host device.

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