JP4521409B2 - Vertical semiconductor device structure and method for forming the same - Google Patents

Vertical semiconductor device structure and method for forming the same Download PDF

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JP4521409B2
JP4521409B2 JP2006550157A JP2006550157A JP4521409B2 JP 4521409 B2 JP4521409 B2 JP 4521409B2 JP 2006550157 A JP2006550157 A JP 2006550157A JP 2006550157 A JP2006550157 A JP 2006550157A JP 4521409 B2 JP4521409 B2 JP 4521409B2
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nanotube
gate electrode
substrate
semiconductor
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JP2007520073A (en
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ネスビット、ラリー、アラン
ハキー、マーク、チャールズ
フルカワ、トシハル
ホームズ、スティーブン、ジョン
ホラーク、デービッド、バツラフ
ミッチェル、ピーター
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インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
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Priority to US10/767,039 priority Critical patent/US7211844B2/en
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Priority to PCT/EP2005/050128 priority patent/WO2005076382A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/283Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part comprising components of the field-effect type
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
    • H01L51/0045Carbon containing materials, e.g. carbon nanotubes, fullerenes
    • H01L51/0048Carbon nanotubes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
    • H01L51/0504Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or swiched, e.g. three-terminal devices
    • H01L51/0508Field-effect devices, e.g. TFTs
    • H01L51/0512Field-effect devices, e.g. TFTs insulated gate field effect transistors
    • H01L51/057Field-effect devices, e.g. TFTs insulated gate field effect transistors having a vertical structure, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/701Integrated with dissimilar structures on a common substrate
    • Y10S977/707Integrated with dissimilar structures on a common substrate having different types of nanoscale structures or devices on a common substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/701Integrated with dissimilar structures on a common substrate
    • Y10S977/72On an electrically conducting, semi-conducting, or semi-insulating substrate
    • Y10S977/721On a silicon substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/724Devices having flexible or movable element

Description

  The present invention relates to the manufacture of semiconductor devices, and more specifically to a vertical field effect transistor incorporating a semiconductor nanotube as a channel region and a method of manufacturing such a vertical field effect transistor.

  A conventional field effect transistor (FET) is a well-known ordinary device that is typically incorporated as a basic component into the complex circuitry of an integrated circuit (IC) chip. A single IC chip may include thousands to millions of FETs interconnected by conduction paths, along with other passive components such as resistors and capacitors. The FET operates by changing the resistivity of the channel in the channel region that separates the source and drain. Carriers flow from the source to the drain through the channel in proportion to the change in electrical resistance. In the n-channel FET, electrons are involved in conduction in the channel, and in the p-channel FET, holes are involved in conduction in the channel. By applying a voltage to the capacitively coupled gate electrode located above the channel region between the source and drain, the output current of the FET changes. A thin gate dielectric electrically insulates the gate electrode from the channel region. A slight change in the gate voltage can cause a large change in the current flowing from the source to the drain.

  FETs can be classified into horizontal and vertical architectures. In the horizontal FET, carriers flow from the source to the drain in a direction parallel to the horizontal plane of the substrate on which they are formed. In the vertical FET, carriers flow from the source to the drain in the direction perpendicular to the horizontal plane of the substrate on which they are formed. Since the channel length of the vertical FET does not depend on the minimum shape that can be resolved by the lithographic apparatus and method, the vertical FET can be made to have a shorter channel length than the horizontal FET. Therefore, the vertical FET switches faster and has a higher power handling capability than the horizontal FET.

  Carbon nanotubes are nanoscale high aspect ratio cylinders made of hexagonal rings of carbon atoms that have been proposed for use in the formation of hybrid devices such as FETs. Carbon nanotubes conduct efficiently in a conductive form and work as a semiconductor in a semiconductor form. A horizontal FET uses a single semiconductor carbon nanotube as the channel region and forms ohmic contacts at both ends of the carbon nanotube extending between the gold source electrode and the gold drain electrode located on the surface of the substrate. manufactured. A gate electrode is defined in the substrate below the carbon nanotubes, approximately between the source and drain electrodes. The exposed surface of the substrate is oxidized to define a gate dielectric between the buried gate electrode and the carbon nanotube. Such horizontal FETs should switch reliably while consuming much lower power than the silicon-based device structure being compared, due to the small size of the carbon nanotubes. These horizontal FET device structures have been successfully formed under laboratory conditions by manipulating single carbon nanotubes using an atomic force microscope, but are not compatible with mass production techniques.

  Therefore, what is needed is a vertical FET structure that incorporates one or more semiconductor carbon nanotubes as a channel region that is compatible with IC chip mass production technology.

  According to the present invention, there is provided a vertical semiconductor device structure including a substrate that substantially defines a horizontal plane, a gate electrode that protrudes perpendicularly from the substrate and includes a vertical sidewall, and a spacer positioned on a side surface of the vertical sidewall. Is done. Positioned between the gate electrode and the spacer is a semiconductor nanotube that extends between the opposing first and second ends and has a substantially vertical orientation. Disposed on the vertical sidewall between the carbon nanotube and the gate electrode is a gate dielectric. The first end of the semiconductor nanotube is electrically coupled to the source, and the opposite second end of the semiconductor nanotube is electrically coupled to the drain.

  In another aspect of the invention, a method for manufacturing a semiconductor device structure includes forming a catalyst pad on a substrate and forming a gate electrode adjacent to the catalyst pad. A first spacer is formed on the vertical sidewall of the gate electrode at a position covering the catalyst pad, and a second spacer is formed on the first spacer. A passage or space surrounded by the second spacer and the gate electrode by removing the first spacer and having an opening at one end and a catalyst pad located at the opposite end or Define the space. A gate dielectric is formed on the vertical sidewalls of the gate electrode. The method further includes synthesizing semiconductor nanotubes on the catalyst pad that extend substantially vertically from the catalyst pad to a free end near the opening of the passage.

  In a preferred embodiment of the present invention, nanotube growth is limited to a specific vertical growth direction within a high aspect ratio space or passage defined by a spacer adjacent to the gate electrode. As a result, the conventional difficulties associated with isotropic growth of nanotubes are eliminated. The spacer provides an efficient and effective introduction of one or more reactants necessary to grow the carbon nanotubes in the passageway in the vicinity of the interface region between the catalyst material and each of the growing nanotubes. Clearances can be provided. The length of the channel region between the source and drain is determined by the vertical dimension or thickness of the gate electrode, without being limited by the conventional lithography process used in semiconductor device manufacturing. As a result, the length of the channel region can be smaller than that created by standard lithography and etching processes.

  The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the foregoing general description of the invention and the detailed description of embodiments described below. Useful for explaining the principles of the present invention.

  Preferred embodiments of the present invention are directed to vertical field effect transistors (FETs) that utilize carbon nanotubes as the semiconductor material for the channel region that provides a selective conduction path between the source and drain. In accordance with the principles of the present invention, carbon nanotubes grow in closed vertical spaces or passages so that isotropic growth is avoided. As a result, the carbon nanotubes are oriented in a substantially vertical orientation and are placed at a desired location adjacent to the gate electrode to which a voltage is applied to control the current flowing from the source to the drain. The length of the channel region between the source and drain is determined by the thickness of the gate electrode, which is substantially equal to the length of the nanotube, and does not depend on the lithography process. The growth rate of the nanotubes is improved by providing an additional flow path for gaseous or evaporative reactants that leads to the catalyst material that promotes nanotube growth at the bottom of the channel. As a result, the only flow path leading to the catalyst material does not exist in a direction perpendicular from the entrance to the bottom of the high aspect ratio passage.

With reference to FIGS. 1 and 2, a region of the substrate 10 is covered by a flat insulating layer 12 characterized by a high electrical resistivity relative to the underlying substrate 10. Substrate 10 may be any suitable semiconductor substrate, including but not limited to silicon (Si) and gallium arsenide (GaAs), on which an insulating layer such as insulating layer 12 may be formed. Can be a material. The insulating layer 12 can be made of, for example, silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).

  Suitable to aid carbon nanotube growth by depositing a blanket layer of catalytic material on insulating layer 12 and patterning the blanket layer using standard lithographic and subtractive etching processes A catalyst pad 14 of the catalyst material is formed on the insulating layer 12. The blanket layer of catalyst material patterned to form the catalyst pad 14 is formed by chemical vapor deposition (CVD), sputtering by thermal decomposition of metal precursors such as metal halides and metal carbonyls. And can be deposited by any conventional deposition technique including, but not limited to, physical vapor deposition (PVD). The catalyst material of the catalyst pad 14 can generate nuclei for carbon nanotube growth and assist in growth when exposed to suitable reactants under reaction conditions suitable to promote nanotube growth. It can be any material. For example, suitable catalyst materials include, but are not limited to, compounds such as iron, platinum, nickel, cobalt, and silicides of each of these metals.

  The insulating layer 12 can be omitted, and alternatively, the substrate 10 can be a shallow trench that electrically isolates the region of the substrate 10 shown in FIGS. Isolation (STI) structures or silicon local oxidation (LOCOS) structures can be included, and these can also be incorporated into additional device structures or other device structures described herein. In this alternative embodiment, the catalyst pad 14 is formed or deposited by conventional processes in a pad-shaped trench in the region of the substrate 10 separated by an STI or LOCOS structure. A number of catalyst pads 14 can be formed on the insulating layer 12 while maintaining mass production techniques.

Referring to FIGS. 3 and 4, a thin insulating layer 16 is conformally deposited over the insulating layer 12 and the catalyst pad 14. The insulating layer 16 can be deposited by thermal decomposition CVD or low pressure chemical vapor deposition (LPCVD) of silicon-containing precursors, or alternatively can be grown as an oxide by thermal oxidation, SiO 2 or Si. 3 N 4 or other dielectric material. A pillar 18 of conductive material is formed on the insulating layer 16 covering the catalyst pad 14. A hard mask 20 of insulating material is applied to the exposed upper surface of the pillar 18.

The pillars 18 and the hard mask 20 covering the pillars 18 are formed by standard lithography and etching processes, such as heavily doped polycrystalline silicon (polysilicon), which is first deposited by LPCVD. was a blanket layer of conductive material is deposited on the insulating layer 16, then the SiO 2, or more particularly, tetraethylorthosilicate-based (the TEOS-based) conductive layer of insulating material such as SiO 2 Deposit on the blanket layer of the functional material. The insulating material is patterned to expose an unmasked region of the blanket layer of conductive material and a mask region aligned with the catalyst pad 14, as described below, and then the conductive material in the unmasked region. For example, a reactive ion etching (RIE) process selective to the insulating material of the hard mask 20 is etched.

  Terms such as “vertical”, “horizontal”, etc. herein are referred to by way of example to define a reference system and are not intended to be limiting. The term “horizontal” as used herein is defined as a plane parallel to the normal plane or surface of the substrate 10, regardless of orientation. The term “vertical” refers to a direction perpendicular to the horizontal direction just defined. “On”, “above”, “below”, “side” (as in the case of “sidewall”), “higher” The terms "", "lower", "over", "beeneath", and "under" are defined relative to the horizontal plane. It should be understood that various other reference systems may be used without departing from the scope of the present invention.

Referring to FIGS. 5 and 6, a temporary spacer material spacer 22 conformally deposits a thin film of spacer material, eg, an RIE process selective to the material forming the insulating layer 12 and the hard mask 20. Is formed around the vertical side wall 21 of the pillar 18 by anisotropic etching using. The spacer material constituting the spacer 22 can be, for example, SiO 2 or Si 3 N 4 . The spacers 22 are sacrificial because they are completely removed during subsequent processing. In an exemplary embodiment of the invention, the insulating layer 12 and the hard mask 20 are SiO 2 so that the RIE that removes the spacers 22 is selective to the material forming the insulating layer 12 and the hard mask 20. The spacer 22 is made of Si 3 N 4 . The spacer 22 projects horizontally from the side wall 21 toward the outside.

  Referring to FIGS. 7 and 8, the catalyst pad 14 is reduced in size by removing the end region extending from directly below the pillar 18. To this end, an etching process that is different from the etching process that defines the spacer 22 or an etching process that can be a continuous etching process with the etching conditions changed to be suitable for etching the insulating layer 16, The region of the insulating layer 16 that is not masked by the pillar 18 and the spacer 22 is removed. Then, here again, an etching process different from the etching process for removing the region of the insulating layer 16, or a continuous etching process in which the etching conditions are changed to be suitable for etching the catalyst material 14, and Etching that can be performed removes areas of the catalyst pad 14 that are not masked by the pillars 10 and spacers 22 and reduces the exposed surface area of the catalyst pad 14. The catalyst pad 14 is covered with a layer 25 of an insulating material that is the remaining part of the insulating layer 16.

Referring to FIGS. 9 and 10, the spacers 22 are formed on the sidewalls 21 of the pillars 18 by any wet or dry etching process that is selective to the constituent materials of the substrate 10, the hard mask 20, and the catalyst pad 14. Removed from. A blanket layer 26 of a suitable spacer material, such as SiO 2 or germanium (Ge), is conformally deposited on the substrate 10 by a CVD or LPCVD process. A part of the blanket layer 26 covering the side wall 21 of the pillar 18 is formed as a spacer 30 having substantially the same thickness as the spacer 22 as described later.

  Referring to FIGS. 11 and 12, using a standard lithography and subtractive etching process aimed at dividing or dividing the pillar 18 into a number of gate electrodes 28, a blanket layer 26, a hard mask 20, The pillar 18 and the vertically aligned portion of the catalyst pad 14 are removed. To do so, a resist layer (not shown) is applied to the blanket layer 26 and exposed to give a latent image pattern, which is then applied in parallel to cover the blanket layer 26 at a location that will become the gate electrode 28 in the future. Development is performed to convert to a final image pattern having strip-shaped mask areas. After the etching process is completed, a region of the insulating layer 12 appears between the gate electrodes 28. Preferably, the shape of the gate electrode 28 is at or near the minimum dimension of lithography. The spacer 30 is defined as part of the patterned blanket layer 26 that extends vertically upward on the sidewall 31 of each gate electrode 28 above the position of the catalyst pad 14. The spacers 30 are sacrificial because they are completely removed during subsequent processing.

Referring to FIGS. 13 and 14, a spacer 32 of a suitable permanent spacer material such as Si 3 N 4 is formed around the sidewall 31 of each gate electrode 28. A portion of the spacer 32 overlies and covers each of the spacers 30. In contrast to the spacer 30, the material forming the spacer 32 is permanent in the sense that the spacer 32 is incorporated into the finished device structure. A blanket layer of permanent spacer material is conformally deposited on the substrate 10 and, for example, the insulating layer 12 so that the spacers 32 on each gate electrode 28 represent only the remaining portion of the blanket layer of permanent spacer material after the etching process. The spacer 32 is formed by anisotropically etching the blanket layer by an RIE process selective to the material forming the hard mask 20. The permanent spacer material constituting the spacer 32 can be, for example, Si 3 N 4 or SiO 2 when the material constituting the spacer 30 is Ge. The spacer 32 is separated from the side wall 31 of each gate electrode 28 by the spacer 30 on the two opposite side surfaces on the side edge of the catalyst pad 14, and on the other two opposite side surfaces of each gate electrode 28. Is attached.

Referring to FIGS. 15 and 16, the spacers 30 on each gate electrode 28 are removed by an isotropic etch process selective to the material forming the hard mask 20 and spacers 32. For example, when the spacer 30 is made of Ge and the spacer 32 is made of either Si 3 N 4 or SiO 2 , hydrogen peroxide (H 2) selective to the hard mask 20 and the spacer 32 is used. An aqueous etchant solution containing O 2 ) would be suitable for removing the spacer 30. The spacer 32 and the gate electrode 28 are separated by a space or passage 34 created by an isotropic etching process where the spacer 30 previously occupied. Each of the passages 34 has a substantially rectangular cross-sectional shape when viewed in the vertical direction. The isotropic etch process also removes the remaining portion of the patterned blanket layer 26 and re-exposes the insulating layer 12.

  A portion of the layer 25 exposed by the formation of the passage 34 is removed from the side edge of the catalyst pad 14 to expose or expose the corresponding nanotube synthesis region 36. A gap 38 previously filled with a portion of one of the spacers 30 is located below each spacer 32 adjacent to the corresponding nanotube synthesis region 36 and between the spacer 32 and the insulating layer 12 in the vertical direction. Exist. Each passage 34 extends vertically from one of the catalyst pads 14 to an opening 33 located next to the hard mask 20. The nanotube synthesis region 36 is vertically positioned below one of the corresponding openings 33.

Referring to FIGS. 17 and 18, each layer 40 of insulating material such as SiO 2 is then coextensive with the passages 34 to electrically isolate each gate electrode 28 from the corresponding passages 34. It is formed on the exposed portion of the side wall 31 of the gate electrode 28. The process of forming the layer 40 is such that the exposed material of the nanotube synthesis region 36 is not coated or otherwise modified in a manner that may not help carbon nanotube growth. Selected. For example, the oxygen partial pressure in the wet oxidation process that forms layer 40 can be adjusted so that SiO 2 grows on the exposed portions of sidewalls 31 and no oxide is formed on nanotube synthesis region 36. The horizontal dimension of each passage 34 that is reduced by the presence of the layer 40 is suitable to allow vertical growth of carbon nanotubes, as described below, otherwise the spacer 30 It is substantially determined by the dimensions.

  Referring to FIGS. 19 and 20, a bundle or group of carbon nanotubes 42 is formed in the passage 34 adjacent to the portion of the side wall 31 of each gate electrode 28 covered by the layer 40. The carbon nanotubes 42 are hollow cylindrical tubes composed of rings with carbon atoms arranged in a hexagonal shape, typically from about 0.5 nm to about 20 nm in diameter and from about 5 nm to about 50 nm. It is parameterized by the sidewall thickness of the range. The carbon nanotubes 42 have a height or length distribution, each measured between the tip or top 43 and one end or bottom 47 on one side of the nanotube synthesis region 36 opposite the tip 43. It seems to have. The length distribution of the carbon nanotubes 42 can be characterized by an average length and standard deviation. At least one of the carbon nanotubes 42 in each passage 34 protrudes vertically above a horizontal plane defined by the hard mask 20 covering each gate electrode 28.

  The carbon nanotubes 42 extend substantially vertically upward from the nanotube synthesis region 36 and occupy most of the voids within the passage 34 of each gate electrode 28. Each of the carbon nanotubes 42 is oriented perpendicularly or at least substantially perpendicular to the horizontal top surface of the corresponding nanotube synthesis region 36 because the growth direction of the carbon nanotubes 42 is limited by the presence of the spacers 32. The Within the passage 34, a slight tilt or tilt of the nanotube orientation is allowed, but isotropic growth is prevented by the spacer 32. For example, the carbon nanotubes 42 cannot grow parallel to the horizontal plane of the substrate 10.

The carbon nanotubes 42 are carbon monoxide (CO), ethylene (C 2 H 4 ), under growth conditions suitable to promote the growth of carbon nanotubes on the catalyst material that forms the nanotube synthesis region 36. Methane (CH 4 ), acetylene (C 2 H 2 ), a mixture of acetylene and ammonia (NH 3 ), a mixture of acetylene and nitrogen (N 2 ), a mixture of acetylene and hydrogen (H 2 ), xylene (C 6 H 4 (CH 3 ) 2 ), and any suitable gaseous carbon-based reactant or evaporated carbon, including but not limited to a mixture of xylene and ferrocene (Fe (C 5 H 5 ) 2 ) It grows by chemical vapor deposition (CVD) or plasma assisted CVD using a system reactant. The substrate 10 can be heated to promote CVD growth. The reactants initially flow laterally through each of the gaps 38 and down through each of the passages 34 to the catalyst material in the nanotube synthesis region 36. The reactant reacts chemically in the catalyst material of the nanotube synthesis region 36 to generate the nuclei of the carbon nanotubes 42. Subsequent vertical growth of the carbon nanotubes 42 occurs from the bottom on the surface of the nanotube synthesis region 36 or at the freeing tip 43 of the carbon nanotube 42 opposite the bottom 47. Arise. The presence of the gap 38 provides the ability for the reactants to reach the nanotube synthesis region 36 because the flow of fluid will be greatly limited when the reactants need to flow only downwardly through the passage 34. Improve. The gap 38 can be omitted if growth occurs from the free end 43 or if there is no fluid flow restriction.

  The growth conditions of the CVD or plasma assisted CVD process are selected to preferentially grow the carbon nanotubes 42 having a semiconductor molecular structure. Alternatively, from a collection of as-grown nanotubes 42 containing both metal and semiconductor molecular structures, for example by providing a high current sufficient to destroy nanotubes 42 having a metal molecular structure. The carbon nanotube 42 having a semiconductor molecular structure can be preferentially selected. In certain embodiments of the invention, a single semiconducting carbon nanotube 42 may be present in one or more passages 34. Nanotubes 42 can be composed of materials other than carbon that are characterized by band gaps and semiconductor properties.

  Referring to FIGS. 21 and 22, a layer 44 of a relatively high electrical resistance insulating material such as boron phosphosilicate glass (BPSG) is conformally formed on the substrate 10 by a deposition process such as LPCVD. Layer 44 is polished flat by a chemical mechanical polishing (CMP) process or any other suitable planarization technique. Polishing can remove layer 44 to a depth sufficient to shorten some very long nanotubes in the distribution of carbon nanotubes 42. A portion of the layer 44 can fill all the empty space between the individual carbon nanotubes 42. Part of the layer 44 also fills each gap 38.

  Referring to FIGS. 23 and 24, standard lithography and contact holes 46 extending through layer 44, hard mask 20, gate electrode 28, and layer 25 stop at the depth of catalyst pad 14. Defined by the etching process. An insulating material is deposited in the contact hole 46 and anisotropic etching is performed to form an insulating spacer 48 that electrically isolates the gate electrode 28 from the catalyst pad 14. Each gate electrode 28 is divided into two separate gate electrodes 28a, 28b by corresponding contact holes 46. Contact holes 50 are defined in layer 44 and hard mask 20 by standard lithography and etching processes that stop at the depth of gate electrodes 28a, b. Contact holes 52 are defined in layer 44 to a depth that exposes at least one tip 43 of carbon nanotubes 42 present in each passageway 34 by standard lithography and etching processes.

  Referring to FIGS. 25 and 26, contact openings 46, 50, and 52 are optionally covered with one or more barrier / adhesion enhancement layers (not shown) to form a plug, as appropriate. Contact 54, 56, by blanket depositing a new metal to fill the contact openings and then removing excess coverburden of conductive material by any suitable planarization technique, such as a CMP process. And 58 are formed in contact holes 46, 50 and 52, respectively. At least one of the carbon nanotubes 42 present in the passage 34 located next to each gate electrode 28a, b has a tip 43 which is in electrical contact, preferably in ohmic contact with a corresponding one of the contacts 58. Have. The tip 43 of the contacted carbon nanotube 42 protrudes perpendicularly to the interior of the corresponding contact 58 or contacts the corresponding contact 58 at the interface. The carbon nanotubes 42 in each passage 34 are electrically coupled, preferably ohmically joined to the catalyst pad 14. Contacts 54, 56, and 58 are electrically isolated from one another and are aluminum (Al), copper (Cu), gold (Au), molybdenum (Mo), tantalum (Ta), titanium (Ti), and tungsten (W )), But is not limited to any suitable conductive material. A standard back-end (BEOL) process is used to fabricate an interconnect structure (not shown) that joins adjacent completed device structures 60.

  Device structure 60 includes one of gate electrodes 28a, b, a gate dielectric defined by layer 40, a source defined by catalyst pad 14 and contact 54, a drain defined by corresponding contact 58, and catalyst pad 14. And a semiconductor channel region defined along at least one length of carbon nanotube 42 extending vertically into a suitable passage 34 between contacts 58. The channel region defined by the carbon nanotubes 42 is oriented substantially perpendicular to the horizontal plane of the substrate 10. When a voltage is applied to the appropriate one of the gate electrodes 28a, b and a channel is created in the associated carbon nanotube 42, carriers are selectively passed from the catalyst pad 14 through the carbon nanotube 42 to the contact 58. Flowing into. Each device structure 60 is electrically coupled with other device structures 60 and additional circuit elements (not shown) supported by the substrate 10 for device operation.

  Although the invention has been shown by way of description of various embodiments, and these embodiments have been described in great detail, it is not intended to limit the appended claims to such details or in any way Not intended by the applicant. Additional advantages and modifications will be readily apparent to those skilled in the art. Accordingly, the invention in its broader aspects is not limited to the specific details, representative apparatus and methods, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope of applicants' general inventive concept.

It is a top view of a part of a substrate. FIG. 2 is a cross-sectional view taken generally along line 2-2 of FIG. It is a top view similar to FIG. 1 in the next manufacturing stage. 4 is a cross-sectional view taken generally along line 4-4 of FIG. FIG. 4 is a top view similar to FIG. 3 in the next manufacturing stage. FIG. 6 is a cross-sectional view taken generally along line 6-6 of FIG. It is a top view similar to FIG. 5 in the next manufacturing stage. FIG. 8 is a cross-sectional view taken generally along line 8-8 of FIG. It is a top view similar to FIG. 7 in the next manufacturing stage. FIG. 10 is a cross-sectional view taken generally along line 10-10 of FIG. 9; FIG. 10 is a top view similar to FIG. 9 in the next manufacturing stage. FIG. 12 is a cross-sectional view taken generally along line 12-12 of FIG. FIG. 12 is a top view similar to FIG. 11 in the next manufacturing stage. FIG. 14 is a cross-sectional view taken generally along line 14-14 of FIG. 13. FIG. 14 is a top view similar to FIG. 13 in the next manufacturing stage. FIG. 16 is a cross-sectional view taken generally along line 16-16 of FIG. FIG. 16 is a top view similar to FIG. 15 in the next manufacturing stage. FIG. 18 is a cross-sectional view taken generally along line 18-18 of FIG. FIG. 18 is a top view similar to FIG. 17 in the next manufacturing stage. FIG. 20 is a cross-sectional view taken generally along line 20-20 of FIG. FIG. 20 is a top view similar to FIG. 19 in the next manufacturing stage. FIG. 22 is a cross-sectional view taken generally along line 22-22 of FIG. FIG. 22 is a top view similar to FIG. 21 in the next manufacturing stage. FIG. 24 is a cross-sectional view taken generally along line 24-24 of FIG. FIG. 24 is a top view similar to FIG. 23 in the next manufacturing stage. FIG. 26 is a cross-sectional view taken generally along line 26-26 of FIG.

Claims (5)

  1. A substrate that substantially defines a horizontal plane, a source or drain located on the substrate, a gate electrode that protrudes vertically through the source or drain and an insulating layer and includes a vertical sidewall, and a spacer that is located on a side surface of the vertical sidewall A semiconductor nanotube positioned between said gate electrode and said spacer and extending between opposing first and second ends and having a substantially vertical orientation, said nanotube and said nanotube A gate dielectric disposed on the vertical sidewall between the gate electrode, a source electrically coupled to the first end of the nanotube, and an electrical connection to the second end of the nanotube And a portion of the spacer is separated from the substrate by a gap, the gap being formed by an insulating material after the semiconductor nanotube is formed. A buried vertical semiconductor device structure.
  2. A method of forming a vertical semiconductor device structure, comprising: forming a catalyst pad on a substrate; forming a gate electrode on the catalyst pad through an insulating layer; and connecting the catalyst pad and the substrate . covers, removal and forming a first spacer on a vertical sidewall of the gate electrode, and forming a second spacer around the gate electrode and the first spacer, the first spacer doing, a passage surrounded by said second spacer and the gate electrode, the passage having the catalyst pad having an opening at one end, positioned at opposite ends, said first a step of determining a gap separating the second spacer and the substrate in the vertical direction, forming a gate dielectric on the vertical sidewall, on the catalyst pad, the catalyst Pas Synthesizing semiconductor nanotubes extending substantially perpendicularly from a channel to a free end close to the opening of the passage, wherein the second spacer is separated from the substrate by a gap that becomes a flow path to the catalyst pad. The step of synthesizing the semiconductor nanotubes separated in the vertical direction guides a reactant through the flow path defined by the gap to cause a chemical reaction to synthesize the semiconductor nanotubes in the catalyst pad. A method comprising steps.
  3.   The method of claim 2, wherein the reactant is a carbon-based reactant and the semiconductor nanotube is a carbon nanotube.
  4.   The method of claim 2, further comprising filling the gap with an insulating material after synthesizing the semiconductor nanotube.
  5. Step, the under conditions effective to grow the semiconducting nanotubes, the catalyst pad further including the step of exposing the reactants, the method described in Motomeko 2 synthesizing the semiconducting nanotubes.
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US7329567B2 (en) 2008-02-12
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