JP4516323B2 - Plasma display device - Google Patents

Description

The present invention relates to a plasma display device , and more particularly to a plasma display device in which alignment markers are formed at positions facing each other on a pair of substrates constituting a PDP.

  In general, a plasma display device mainly composed of a PDP is compared with a display device such as a CRT (Cathode Ray Tube) or LCD (Liquid Crystal Device) that has been widely used. Since it has many advantages such as small flickering, large display contrast ratio, thin and large screen, and high response speed, it has recently become a display for information processing equipment such as computers. It is used as a device.

  This plasma display device has an AC type in which an electrode is covered with a dielectric layer and is operated indirectly in an AC discharge state, and an electrode is exposed to a discharge space and is operated in a DC discharge state depending on an operation method. The former is roughly classified into the DC type, and the former is widely used because it can easily realize a large screen as described above with a relatively simple structure. A PDP constituting the main part of such an AC type plasma display device is a discharge gas space in which a front substrate and a rear substrate made of a transparent material such as glass are opposed to each other to generate plasma between both substrates. The basic structure is formed.

  Further, among AC type plasma display devices, a horizontal direction (row) is formed on the inner surface of a front substrate, which is one of a pair of substrates as described above, which form a PDP discharge cell (hereinafter also simply referred to as a cell). A pair of row electrodes (display electrodes) composed of scan electrodes and sustain electrodes (common electrodes) are arranged in parallel with each other along the direction), and intersect the row electrodes on the inner surface of the rear substrate, which is the other substrate ( A three-electrode surface discharge type configuration in which column electrodes made up of data electrodes (address electrodes) are arranged along the vertical direction (column direction) so as to be orthogonal to each other is a high-energy ion generated during surface discharge on the front substrate. This is the most widely used because it can extend the service life.

  The above-mentioned three-electrode surface discharge AC type plasma display device (hereinafter also referred to as plasma display device) selects a cell to be displayed (emitted) between a data electrode on the back substrate and a scan electrode on the front substrate. The discharge is performed, and then the sustain discharge (display discharge) is performed by the surface discharge of the selected cell between the scan electrode and the sustain electrode of the front substrate. In such a PDP, for example, a color plasma display device is provided in which red, green and blue phosphor layers are arranged on the inner surface of a back substrate to enable multicolor emission.

  In order to assemble the PDP as described above, alignment markers are formed in advance at positions where the front substrate and the rear substrate face each other, and the alignment markers are aligned with each other so that both substrates are overlapped and bonded. Is done. For example, Patent Document 1 discloses a method of manufacturing a PDP by forming an alignment marker as described above. 9, the first alignment marker 131 is formed on the front substrate 101 simultaneously with the formation of the transparent electrodes 102a and 103a on the front substrate 101, and the partition walls are formed on the rear substrate 108. The second alignment marker 132 is formed at the same time as the formation of the 111 and the partition wall 114, and then relative alignment is performed using the first alignment marker 131 and the second alignment marker 132, so that the two substrates 101 and 108 are overlapped. Bonded together. Reference numeral 102 denotes a scanning electrode, 103 denotes a sustain electrode, 102b and 103b denote bus electrodes (trace electrodes), 105 denotes a light shielding layer (black stripe layer), 107 denotes a protective layer, and 110 denotes a data electrode.

Alternatively, for the front substrate 101, as shown in FIG. 10A, a circular first alignment marker 131A is formed simultaneously with the formation of the light shielding layer 105, while for the rear substrate 108, FIG. As shown in b), the ring-shaped second alignment marker 132A is also formed simultaneously with the formation of the partition walls 111 and 114. In this case, as shown in FIG. 11, relative alignment is performed using the first alignment marker 131 </ b> A and the second alignment marker 132 </ b> A, and the two substrates 101 and 108 are overlapped and bonded. The relative alignment of the first and second alignment markers as described above is performed by recognizing an image within one field of view by a camera.
JP 2003-288842 A

By the way, in the conventional plasma display device, alignment markers formed respectively on the front substrate and the rear substrate for assembling the PDP are formed by only one component layer among a plurality of component layers sequentially formed on each substrate. Therefore, there is a problem that the alignment accuracy of the alignment is lowered when the two substrates are overlapped and bonded.
That is, conventionally, for example, as described in Patent Document 1 described above, the first alignment marker 131 of the front substrate 101 is formed of one constituent layer composed of the transparent electrodes 102a and 103a. The second alignment marker 132 of 108 is formed of one constituent layer including a partition wall 111 and a partition wall 114 (both partition walls are formed simultaneously).

  When the alignment markers 131 and 132 of the substrates 101 and 108 are formed of one component layer in this way, the display electrodes 104 of the front substrate 101 and the partitions 111 and 114 of the rear substrate 108 are assembled when the PDP is assembled. As for the assembly accuracy, since the displacement of the formation position of the display electrode 104 with respect to the transparent electrodes 102a and 103a is added to the alignment displacement, the alignment accuracy of alignment is lowered when the substrates 101 and 108 are bonded together. become.

The present invention has been made in view of the above-described circumstances, and prevents the alignment accuracy from degrading when the substrates are overlapped and bonded using alignment markers formed on the front substrate and the back substrate, respectively. It is an object of the present invention to provide a plasma display device that can be used.

In order to solve the above-mentioned problem, the invention according to claim 1 is arranged so that a pair of front substrate and rear substrate face each other so that a discharge space is formed between both substrates, and discharge is generated in the discharge space. A plasma display device in which display electrodes are arranged on the front substrate while data electrodes are arranged on the rear substrate in a direction intersecting the display electrodes, wherein the front substrate and the rear substrate face each other. And the alignment markers on the front substrate or the back substrate are formed in different orientations in different marker patterns formed in different layers or in different layers, respectively. It is characterized by being completed by partial overlapping of marker patterns having the same shape .

According to the configuration of the plasma display device of the present invention, at least one of the alignment markers formed on the front substrate and the back substrate facing each other is formed of a plurality of different layers. When the two substrates are overlapped and bonded using the formed alignment marker, it is possible to prevent the alignment accuracy from being lowered.

  A pair of front substrate and rear substrate are arranged to face each other so that a discharge space is formed between both substrates, and display electrodes are arranged on the front substrate so that discharge is generated in the discharge space, while display electrodes are arranged on the rear substrate. In the configuration in which the data electrodes are arranged in the intersecting direction, the alignment marker is formed at a position where the front substrate and the rear substrate face each other, and the alignment marker on the front substrate or the rear substrate is composed of a plurality of different layers. .

1 is a perspective view showing a schematic configuration of a PDP constituting a main part of a plasma display device according to Embodiment 1 of the present invention, FIG. 2 is a cross-sectional view showing the PDP, and FIG. 3 is a manufacturing method of the PDP. FIG. 4 is a plan view showing the first alignment marker formed on the front substrate, FIG. 4 is a plan view showing the alignment marker formed on the rear substrate in the manufacturing method of the PDP, and FIG. 5 is a process showing the manufacturing method of the PDP in order of steps. 6 is a plan view showing alignment markers formed on the front substrate and the back substrate in the manufacturing method of the PDP. FIG. 7 is a plan view showing the first and second alignment markers on the front substrate and the back surface in the manufacturing method of the PDP. It is a top view which shows the state which accumulated the alignment marker of the board | substrate.
As shown in FIGS. 1 and 2, the PDP 10 constituting the main part of the plasma display device of this example is disposed so that the front substrate 1 and the rear substrate 2 face each other. It has a basic configuration in which the discharge gas space 3 is formed.

Here, the front substrate 1 is disposed in parallel with each other along the row direction (horizontal direction) H on the first insulating substrate 4 made of a transparent material such as soda lime glass and the inner surface of the first insulating substrate 4. Transparent electrodes 5A and 6A made of ITO (Indium Tin Oxide), tin oxide (SnO ₂ ), etc., which are formed so as to face each other via a discharge gap and constitute a pair of row electrodes (display electrodes), and these transparent electrodes A bus electrode (trace) made of a metal material such as Al (aluminum), Ag (silver), or Cr (chromium) / Cu (copper) / Cr multilayer thin film formed in part of 5A and 6A to reduce the resistance. Electrode) 5B, transparent electrode made of low melting point lead glass (PbO) or the like covering the row electrode made up of scan electrode 5 and sustain electrode 6, and scan electrode 5 and sustain electrode (common electrode) 6 made up of 6B. Electrical layer 7, red color filter layer 8R, green color filter layer 8G and blue color filter layer 8B (not shown in FIG. 1 for convenience of space) formed on transparent dielectric layer 7, and each color filter A light-shielding layer (black stripe layer) 9 made of low melting point glass or the like added with a black pigment formed so as to be orthogonal to the scanning electrode 5 and the sustaining electrode 6 in the gaps between the layers 8R, 8G, and 8B, and each color filter layer 8R , 8G and 8B, and the protective layer 11 made of MgO (magnesium oxide) or the like for protecting the light shielding layer 9 from discharge.

  On the other hand, the back substrate 2 is formed along the column direction (vertical direction) V perpendicular to the row direction H on the second insulating substrate 12 made of a transparent material such as soda lime glass and the inner surface of the second insulating substrate 12. A data electrode (address electrode) 13 made of Al, Ag or the like, a white dielectric layer 14 made of lead-containing frit glass or the like covering the data electrode 13, and He (helium), Ne (neon), Xe (xenon) The discharge gas is made of lead-containing frit glass or the like formed along the column direction V so as to secure the discharge gas space 3 and to separate the individual discharge cells. A red phosphor layer 16R, a green phosphor layer 16G, and a blue phosphor that are formed at a position covering the partition wall 15 and the bottom and wall surfaces of the partition wall 15 and convert ultraviolet rays generated by the discharge of the discharge gas into visible light. And a phosphor layer 16 which is painted on the body layer 16B. The scan electrode 5, the sustain electrode 6 and the data electrode 13 constitute the above-mentioned three electrodes. In the PDP of the color plasma display device, one pixel of the screen is formed by three discharge cells including the phosphor layers 16R, 16G and 16B. Such one pixel corresponds to three pixels of the PDP of the monochrome plasma display device. A plurality of pixels are arranged in a matrix along the row direction H and the column direction V, whereby the PDP 10 is configured.

Here, in the PDP 10 constituting the main part of the plasma display device of this example, the bus electrodes 5B and 6B are provided at, for example, four corners on the first insulating substrate 4 of the front substrate 1 as shown in FIG. A linear first marker pattern 17A formed simultaneously with the formation of the same material and extending in the horizontal direction H, and a direction L perpendicular to H formed of the same material and formed simultaneously with the formation of the light shielding layer 9. A cross-shaped alignment marker 17 is formed so as to partially overlap the second linear marker pattern 17 </ b> B. In other words, the alignment marker is formed by partially overlapping the first marker pattern 17A and the second marker pattern 17B having the same shape formed on the front substrate 1 in different directions in different layers. 17 is formed.

On the other hand, as shown in FIG. 4, the four corners corresponding to the formation positions of the alignment markers 17 on the second insulating substrate 12 of the back substrate 2 are formed simultaneously with the formation of the partition walls 15 and are made of the same material. In addition, a cross-shaped alignment marker 18 having a cross-shaped marker pattern having an area larger than that of the alignment marker 17 is formed. That is, an alignment marker 18 composed of a single layer is formed on the back substrate 2.
Then, the front substrate 1 having the alignment markers 17 and the rear substrate 2 having the alignment markers 18 are overlapped and bonded as described later to manufacture the PDP 10.

Next, with reference to FIG. 5, the manufacturing method of the PDP 10 will be described in the order of steps.
First, in step a, a front glass substrate as a first insulating substrate 4 is prepared. Next, in step b, ITO or the like is formed on the inner surface of the substrate 4 by sputtering or the like and then patterned into a desired shape by photolithography. Then, each transparent electrode 5A, 6A is formed, and in step c, Al or the like is formed on each transparent electrode 5A, 6A by sputtering or the like and then patterned into a desired shape by photolithography. The electrodes 5B and 6B are formed to complete the scan electrode 5 and the sustain electrode 6. At the same time when the bus electrodes 5B and 6B are formed, at the four corners (only one corner is shown in the description) on the substrate 4, as shown in FIG. 6A, the bus electrodes 5B and 6B are made of the same material. A linear first marker pattern 17A extending in the horizontal direction H is formed.

  Next, in step d, a transparent dielectric layer 7 such as PbO is formed by a screen printing method or the like so as to cover the scanning electrode 5 and the sustain electrode 6, and then in the case of a PDP of a color plasma display device, each color filter layer 8R. , 8G, 8B. Next, in step e, a light shielding layer (black stripe layer) 9 is formed. Simultaneously with the formation of the light shielding layer 9, as shown in FIG. 6B, the linear second marker pattern 17B directed in the direction L perpendicular to H made of the same material as the light shielding layer 9 is used as the first marker pattern. A cross-shaped alignment marker 17 is formed so as to partially overlap 17A. Next, in step f, a protective layer 11 made of an MgO film is formed by vapor deposition or the like to complete the front substrate 1.

  On the other hand, in step g, a rear glass substrate is prepared as the second insulating substrate 12, and in step h, Al or the like is formed on the inner surface of the substrate 12 by sputtering or the like, and then patterned into a desired shape by photolithography. Then, the data electrode 13 is formed, and then the white dielectric layer 14 is formed by screen printing or the like so as to cover the data electrode 13 in step i. Next, in step j, partition walls 15 are formed on the white dielectric layer 14 by screen printing or the like. At the same time when the partition wall 15 is formed, at the four corners on the substrate 12, as shown in FIG. 6C, a cross shape made of the same material as the partition wall 15 and a cross-shaped marker pattern having an area larger than the alignment marker 17. The alignment marker 18 is formed.

  Next, in step k, the phosphor layer 16 is formed so as to cover the white dielectric layer 14 and the barrier ribs 15. Next, in step l, a seal frit is formed by screen printing or the like (not shown in FIGS. 1 and 2). To complete the back substrate 2.

  Next, in step m, the alignment marker 17 and the alignment marker 18 are used to position the alignment marker 17 within the alignment marker 18 while recognizing an image in one field of view using a camera as shown in FIG. The front substrate 1 and the back substrate 2 are overlapped and bonded together with a gap of about 100 μm facing each other. Next, in step n, the peripheral portions of both substrates 1 and 2 are sealed with a seal frit (sealing material). Next, in step o, the space between the substrates 1 and 2 is evacuated and the discharge gas is sealed. The second insulating substrate 12 constituting the back substrate 2 is formed with air holes at appropriate locations, and the outer surface of the substrate 12 is omitted in FIG. 1 and FIG. A vent tube is attached under sealed condition in alignment with the pores. The end of the vent pipe opposite to the end attached to the back substrate 2 is opened in the initial state, and the vent pipe is connected to the exhaust / gas filling device through this end. .

  First, after the discharge gas space is evacuated by the exhaust / gas filling device, the discharge gas space is filled with the discharge gas. After filling the discharge gas, the vent tube is chipped on by overheating, and the open end is closed. In this way, the discharge gas space is filled with the discharge gas, and the PDP 10 is completed.

As described above, in order to perform alignment using the alignment markers 17 and 18 in order to overlap and bond the front substrate 1 and the rear substrate 2, the following three elements are used for the PDP 10. Alignment is performed so that the shift amount at the center is minimized.
(1) Difference in pitch in the horizontal direction H between the alignment marker 17 on the front substrate 1 and the alignment marker 18 on the rear substrate 2 (2) A direction orthogonal to H of the alignment marker 17 on the front substrate 1 and the alignment marker 18 on the rear substrate 2 The center of gravity position obtained from the intersection of the L pitch difference (3) (1), (2) and the diagonal lines of the four markers at the four corners of each substrate 1 and 2

As described above, according to the PDP 10 constituting the main part of the plasma display device of this example, the alignment marker 17 formed on the front substrate 1 is formed simultaneously with the formation of the bus electrodes 5B and 6B and is made of the same material as that. A linear first marker pattern 17A directed in the horizontal direction H and a linear second marker pattern 17B formed simultaneously with the formation of the light shielding layer 9 and directed in the direction L perpendicular to H made of the same material as the first marker pattern 17A. Since it is configured to partially overlap, the alignment marker 17 can be formed by the two constituent layers of the bus electrodes 5B and 6B and the light shielding layer 9, so that the orthogonal components of the two constituent layers can be aligned simultaneously.
Therefore, it is possible to prevent the alignment accuracy from deteriorating when the substrates are overlapped and bonded using the alignment markers respectively formed on the front substrate and the rear substrate.

FIG. 8 is a block diagram showing the configuration of the plasma display device manufactured by the plasma display device manufacturing method according to Embodiment 2 of the present invention. The plasma display device manufacturing method of this example is characterized in that it is configured using the PDP manufactured according to the first embodiment.
As shown in FIG. 8, the plasma display device 60 of this example is designed to have a module structure, and specifically includes an analog interface (hereinafter referred to as IF) 20 and a PDP module 30. .

  As shown in FIG. 8, the analog IF 20 includes a Y / C separation circuit 21 including a chroma decoder, an A / D conversion circuit 22, a synchronization signal control circuit 23 including a PLL circuit, an image format conversion circuit 24, The circuit includes an inverse γ (gamma) conversion circuit 25, a system control circuit 26, and a PLE control circuit 27.

  Schematically, the analog IF 20 converts the received analog video signal into a digital video signal, and then supplies the digital video signal to the PDP module 30. For example, an analog video signal transmitted from a TV tuner is decomposed into RGB luminance signals in the Y / C separation circuit 21 and then converted into digital signals in the A / D conversion circuit 22. Thereafter, when the pixel configuration of the PDP module 30 is different from the pixel configuration of the video signal, the image format conversion circuit 24 performs necessary image format conversion. The display luminance characteristic with respect to the input signal of the PDP is linearly proportional, but a normal video signal is corrected (γ conversion) in advance in accordance with the characteristic of the CRT. For this reason, after the A / D conversion of the video signal is performed in the A / D conversion circuit 22, the inverse γ conversion circuit 25 performs the inverse γ conversion on the video signal, and the digital video signal restored to the linear characteristic is obtained. Generate. This digital video signal is output to the PDP module 30 as an RGB video signal.

  Since the analog video signal does not include the sampling clock and data clock signal for A / D conversion, the PLL circuit built in the synchronization signal control circuit 23 is supplied with the horizontal synchronization signal simultaneously with the analog video signal. Is used as a reference to generate a sampling clock and a data clock signal and output them to the PDP module 30. The PLE control circuit 27 of the analog IF 20 performs brightness control. Specifically, the display luminance is increased when the average luminance level is equal to or lower than a predetermined value, and the display luminance is decreased when the average luminance level exceeds a predetermined value.

  The system control circuit 26 outputs various control signals to the PDP module 30. The PDP module 30 further includes a digital signal processing / control circuit 31, a panel unit 32, and an in-module power supply circuit 33 incorporating a DC / DC converter. The digital signal processing / control circuit 31 includes an input IF signal processing circuit 34, a frame memory 35, a memory control circuit 36, and a driver control circuit 37.

  For example, the average luminance level of the video signal input to the input IF signal processing circuit 34 is calculated by an input signal average luminance level calculation circuit (not shown) in the input IF signal processing circuit 34 and output as, for example, 5-bit data. Is done. Further, the PLE control circuit 27 sets PLE control data according to the average luminance level and inputs it to a luminance level control circuit (not shown) in the input IF signal processing circuit 34.

  The digital signal processing / control circuit 31 processes these various signals in the input IF signal processing circuit 34 and then transmits the control circuit to the panel unit 32. At the same time, the memory control circuit 36 and the driver control circuit 37 transmit the memory control circuit and driver control signal to the panel unit 32.

  The panel unit 32 includes a PDP 70 manufactured according to the first embodiment, a scan driver 38 that drives the scan electrodes, a data driver 39 that drives the data electrodes, and a high-voltage pulse circuit 40 that supplies a pulse voltage to the PDP 70 and the scan driver 38. And a power recovery circuit 41 that recovers surplus power from the high-voltage pulse circuit 40.

The PDP 70 is configured to have pixels arranged, for example, 1365 × 768. In the PDP 70, the scanning driver 38 controls the scanning electrodes, and the data driver 39 controls the data electrodes, so that lighting or non-lighting of predetermined pixels among these pixels is controlled and desired display is performed. .
The logic power supply supplies logic power to the digital signal processing / control circuit 31 and the panel unit 32. Further, the in-module power supply circuit 33 is supplied with DC power from the display power supply, converts the voltage of the DC power into a predetermined voltage, and then supplies the voltage to the panel unit 32.

Hereinafter, a method for manufacturing the plasma display device 60 of this example will be schematically described.
First, the PDP 70 manufactured according to the first embodiment, the scan driver 38, the data driver 39, the high voltage pulse circuit 40, and the power recovery circuit 41 are arranged on one substrate to form the panel unit 32. Further, a digital signal processing / digital circuit 31 is formed separately from the panel section 32.

The panel unit 32, the digital signal processing / control circuit 31, and the in-module power supply circuit 33 thus formed are assembled as one module to form the PDP module 30. Further, the analog IF 20 is formed separately from the PDP module 30.
In this manner, after the PDP module 30 and the analog IF 20 are separately formed, both are electrically connected to complete the plasma display device 60 shown in FIG.

  As described above, by modularizing the plasma display device 60, it becomes possible to manufacture the plasma display device 60 independently of other components constituting the plasma display device. When a failure occurs, the repair can be simplified and shortened by replacing the PDP module 30 with each other.

  As described above, according to the method for manufacturing the plasma display device of this example, the plasma display device 60 is modularized so that the PDP module 30 can be replaced in the event of a failure. The time can be shortened.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in Example 1, the alignment markers formed on the front substrate are a plurality of layers of a linear first marker pattern extending in the horizontal direction and a linear second marker pattern extending in the direction orthogonal to the horizontal direction. However, the alignment marker formed on the back substrate can also be composed of a plurality of layers. For example, the alignment marker of the back substrate is formed at the same time when the data electrode is formed and is formed of the same material as the data electrode, and the second marker is formed at the same time of the formation of the partition and is formed of the same material as the partition. It can consist of multiple layers with patterns. Moreover, although the number of each alignment marker formed in a front substrate and a back substrate was demonstrated in the example of four, it is not restricted to this, At least each alignment marker should just be formed two or more.

It is a perspective view which shows schematic structure of PDP which comprises the principal part of the plasma display apparatus which is Example 1 of this invention. It is sectional drawing which shows the PDP. FIG. 5 is a plan view showing a first alignment marker formed on the front substrate in the method for manufacturing the PDP. FIG. 6 is a plan view showing alignment markers formed on the back substrate in the same PDP manufacturing method. It is process drawing which shows the manufacturing method of the same PDP in process order. In the manufacturing method of the PDP, it is a plan view showing each alignment marker formed on the front substrate and the back substrate. FIG. 6 is a plan view showing a state in which the first and second alignment markers on the front substrate and the alignment markers on the rear substrate are overlapped in the PDP manufacturing method. It is a block diagram which shows the structure of the plasma display apparatus manufactured by the manufacturing method of the plasma display apparatus which is Example 2 of this invention. It is sectional drawing which shows PDP which comprises the principal part of the conventional plasma display apparatus. FIG. 5 is a plan view showing a back substrate and alignment markers formed on the back substrate in the method for manufacturing the PDP. FIG. 5 is a plan view showing a state in which the alignment marker on the front substrate and the alignment marker on the rear substrate are overlapped in the method for manufacturing the PDP.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front substrate 2 Back substrate 3 Discharge gas space 4 1st insulating substrate 5 Scan electrode 5A, 6A Transparent electrode 5B, 6B Bus electrode (trace electrode)
6 Sustain electrode (common electrode)
7 Transparent dielectric layer 8R, 8G, 8B Color filter layer 9 Light-shielding layer (black stripe layer)
10, 70 PDP (Plasma Display Panel)
11 Protective layer 12 Second insulating substrate 13 Data electrode (address electrode)
14 White dielectric layer 15 Bulkhead 16, 16R, 16G, 16B Phosphor layer 17 Front substrate alignment marker 17A, 17B Marker pattern 18 Rear substrate alignment marker 20 Analog interface (IF)
30 Plasma Display Panel (PDP) Module 31 Digital Signal Processing / Control Circuit 32 Panel Unit 60 Plasma Display Device

Claims (1)

A pair of front substrate and rear substrate are arranged to face each other so that a discharge space is formed between both substrates, and display electrodes are arranged on the front substrate so that discharge occurs in the discharge space, while A plasma display device comprising data electrodes arranged in a direction intersecting with the display electrodes,
An alignment marker is formed at a position where the front substrate and the back substrate face each other, and the alignment marker of the front substrate or the back substrate is a different marker pattern formed on each of different layers or different from each other. A plasma display device, which is completed by partially overlapping marker patterns having the same shape formed in different directions on each of a plurality of layers .

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