JP4514208B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

  The present invention particularly relates to a solid-state imaging apparatus used as an imaging device such as a digital still camera and a video camera, and a driving method thereof.

  In recent years, image quality of digital still cameras has been rapidly increasing, and solid-state imaging devices (particularly CCD (electrically coupled device) image sensors) having a number of pixels of 1 million pixels or more are widely used. . In these CCD image sensors, the driving method (still mode) that obtains a still image by reading the signal charges of all pixels independently and the driving method (monitoring mode) that displays a moving image on a liquid crystal monitor or the like are switched. It is common to use.

  In order to achieve the function of the monitoring mode, it is necessary to improve the frame rate. However, due to the limitations of the drive frequency characteristics of the CCD image sensor or in order to reduce power consumption, the drive frequency cannot be increased and the frame rate in the monitoring mode can be secured as the number of pixels of the CCD image sensor increases. It becomes difficult. In order to improve the frame rate in a CCD image sensor, only the signal charges from some pixels in the vertical or horizontal direction are read out, and the number of lines is thinned out, or signals separated in the vertical or horizontal direction are stored in the vertical register. The method of adding by is common.

  In the conventional pixel thinning method, in order to realize thinning with a high degree of freedom in the horizontal direction, it is necessary to provide a drain for discharging unnecessary charges and a control gate for controlling discharge, and the chip size is small. It has become difficult as the size of the pixel cells has been reduced due to the increase in the number of pixels and the increase in the number of pixels.

  On the other hand, in order to realize a method of adding signals of the same color adjacent in the horizontal direction, it is necessary to control signal reading from the vertical register to the horizontal register for each column and to provide a difference in reading time.

  According to a conventional proposal for a method of adding pixel signals, for example, Japanese Patent Application Laid-Open No. 11-54741 (Patent Document 1) requires a three-layer gate structure. For example, Japanese Patent Application Laid-Open No. 2000-115643 (Patent Document 2) discloses a two-layer gate structure. In this Patent Document 2, a complicated gate electrode structure is required, and the number of gate electrodes constituting a vertical register is different for each column.

  FIG. 14 is a schematic plan view of a solid-state imaging device that adds pixel signals using a conventional two-layer gate structure described in Patent Document 2. In FIG. The solid-state imaging device shown in FIG. 14 is an example of a four-phase drive vertical register, and follows the vertical register 4 in the EE ′ column in order to provide a time difference in signal readout from the vertical register 4 to the horizontal register 5. Gate electrodes g 1 ′ to g 4 ′ are added to the transfer time difference generation region 7. Then, by applying in-phase drive pulses φV5 to φV8 to the gate electrodes g1 to g4, the signal charge transfer period from the vertical register 4 to the horizontal register 5 in the EE ′ column is changed to the gate electrodes g1 ′ to g4 ′. This is different from the FF 'column due to the presence of. Thus, charges are transferred to the horizontal register 5 with a time difference.

  1 is a pixel region, 2 is a photodiode (R (red), G (green), B (blue)), 3 is a transfer gate, 6a and 6b are vertical gate electrodes, 8 Is a horizontal register area, 9a and 9b are horizontal gate electrodes, 10 is a charge detector, and 11 is an output amplifier.

  In order to form the gate structure as described above with a two-layer gate, in FIG. 14, the gate electrodes g1, g3 and the gate electrodes g1 ′, g3 ′ are formed in the first layer or the second layer, and the gate electrodes g2, g4 and gate electrodes g2 ′ and g4 ′ are formed in a layer opposite to the above-described layer. Each of the gate electrodes g1 ′, g2 ′, g3 ′, and g4 ′ includes the gate electrode g1 ′ as the gate electrode g1, the gate electrode g2 ′ as the gate electrode g2, the gate electrode g3 ′ as the gate electrode g3, and the gate. In order to drive the electrode g4 ′ in phase with the gate electrode g4, it is necessary to cross wirings connecting the gate electrodes.

On the other hand, with the reduction of pixel cells due to the increase in the number of pixels of the CCD solid-state imaging device, it is necessary to increase the light collection rate in the light receiving portion, and reduction in the height direction of the pixel cells is desired. There are several proposals for reducing the pixel cell in the height direction, and one of them is a proposal for flattening the gate electrode by a chemical mechanical polishing method. However, this method cannot adopt a structure in which gate wirings are crossed or stacked, and there is a problem in that the gate wiring in the transfer time difference generation region 7 of the two-layer gate described above cannot be realized when the gate electrode is planarized.
Japanese Patent Laid-Open No. 11-54741 JP 2000-115643 A

  Therefore, an object of the present invention is to provide a solid-state imaging device having a two-layer gate structure capable of adding signals by controlling signal readout from a vertical register to a horizontal register for each column, and capable of flattening a gate electrode, and It is to provide a driving method thereof.

In order to solve the above problems, a solid-state imaging device of the present invention is
A plurality of light receiving parts formed on a semiconductor substrate or well and arranged two-dimensionally;
A plurality of first registers formed on the semiconductor substrate or the well and having a first gate electrode for transferring the signal charge read from the light receiving unit in one direction;
It is formed on the semiconductor substrate or on the well, and is arranged to extend in the other direction intersecting the one direction at the one-direction end of the first register, and transferred from the first register. A second register having a second gate electrode for transferring the signal charge in the other direction;
The second register is formed on the semiconductor substrate or the well, and is disposed between the one-direction end of the first register and the second register, receives the signal charge from the first register, and receives the second signal. A transfer time difference generating unit for transferring a signal charge from the first register to the second register with respect to each first register,
The transfer time difference generator is
For all the first registers, the same number of transfer electrodes for transferring signal charges received from the first register to the second register;
A channel barrier that shields movement of signal charges received from the first register to the second register with respect to the particular first register;
Together constituted by the transfer electrodes, and Nde including a third gate electrode for opening and closing of the channel barrier in accordance with an electrical signal applied thereto,
The first gate electrode of the first register and the transfer electrode of the transfer time difference generator are arranged adjacent to each other without overlapping each other, forming the same plane,
The channel barrier is a region having a potential energy different from that of the first resistor .

According to the above configuration, when a driving signal having a voltage that does not open the channel barrier is applied to the third gate electrode in the transfer time difference generation unit at a predetermined timing, the channel barrier related to the specific first register Movement of signal charges from the first register to the second register is blocked. Thus, only the signal charges from the first registers other than the specific first register are transferred to the second register.

In parallel with the transfer of the signal charge transferred to the second register to the position of the specific first register in the second register, the drive signal is applied to all transfer electrodes in the transfer time difference generation unit. Is applied at a predetermined timing, a driving signal having a voltage for opening the channel barrier is applied to the third gate electrode. Then, the channel barrier relating to the specific first register is released, the signal charge from the specific first register is transferred to the second register, and the signal from the first register other than the specific first register Mixed with charge. In this way, signal charges of pixels in the same row that are separated from each other are mixed in the second register.

  At this time, since the transfer time difference generating section is configured by the same number of transfer electrodes with respect to all the first registers, a two-layer gate structure can be easily configured.

Further , the channel barrier is a region having a potential energy different from that of the first resistor. Therefore , the channel barrier is opened and closed by applying a transfer pulse having a voltage different from that of the first register.

In the solid-state imaging device according to one embodiment,
The channel barrier is composed of a diffusion layer having a polarity different from that of the diffusion layer constituting the first register.

  According to this embodiment, the channel barrier is opened and closed by applying a transfer pulse having a voltage different from that of the first register.

In the solid-state imaging device according to one embodiment,
A transfer gate for transferring the signal charge accumulated in the light receiving section to the first register;
The channel barrier has the same potential energy as the transfer gate.

  According to this embodiment, the channel barrier is opened and closed by applying a transfer pulse having the same voltage as the signal charge read voltage from the light receiving unit to the first register.

In the solid-state imaging device according to one embodiment,
The third gate electrode is driven at a voltage level of 3 or higher.

According to this embodiment, the third gate electrode functions as a normal transfer electrode when it is driven at two voltage levels of the intermediate level and the lowest level (or the highest level). The channel barrier is not opened. On the other hand, in the case of driving with two voltage levels of the highest level (or lowest level) and the lowest level (or highest level), the channel barrier is opened.

In the solid-state imaging device according to one embodiment,
The one direction is a column direction, the other direction is a row direction,
A mixing mode in which signal charges from remote light receiving units in the same row are mixed in the second register, and the mixed signal charges are transferred in the row direction;
It is possible to switch to the normal mode in which the signal charges from the remote light receiving units in the same row are transferred in the row direction without being mixed in the second register.

  According to the above configuration, the mixed mode in which the signal charges of the pixels separated from each other in the same row are mixed in the second register and the normal mode in which the signal charges are not mixed are switched according to the electric signal applied to the gate electrode. A possible solid-state imaging device can be easily configured with a two-layer gate structure.

Further, the driving method of the solid-state imaging device of the present invention is as follows:
A driving method of the solid-state imaging device of the present invention,
A drive signal having a voltage that does not open the channel barrier is applied to the third gate electrode in the transfer time difference generation unit at a predetermined timing, and the second register of the signal charge is generated by the channel barrier related to the specific first register. Transferring only signal charges from a first register other than the specific first register to the second register;
Applying a drive signal to the second register at a predetermined timing to transfer the signal charge transferred to the second register to the position of the specific first register in the second register;
A drive signal is applied to all the transfer electrodes in the transfer time difference generator at a predetermined timing, and a drive signal having a voltage that opens the channel barrier is applied to the third gate electrode. The signal charge from the first register is transferred in the one direction, the channel barrier relating to the specific first register is opened, and the signal charge from the specific first register is transferred to the second register. And mixing with signal charges already transferred from a first register other than the specific first register.

  According to the above configuration, the signal charges of the pixels separated from each other in the same row are mixed in the second register. At this time, since the transfer time difference generating section is configured by the same number of transfer electrodes with respect to all the first registers, a two-layer gate structure can be easily configured.

As is clear from the above, according to the present invention, when a drive signal having a voltage that does not open the channel barrier is applied to the third gate electrode of the transfer time difference generator at a predetermined timing, the channel barrier related to the specific first register Movement of signal charge from the first register to the second register is blocked. Thus, only the signal charges from the first registers other than the specific first register are transferred to the second register. In parallel with the transfer of the signal charge to the second register to the position of the specific first register in the second register, a drive signal is applied to all transfer electrodes in the transfer time difference generation unit. When the voltage is applied at the timing, a driving signal having a voltage that opens the channel barrier is applied to the third gate electrode, so that the channel barrier related to the specific first register is opened, and the specific first Since the signal charge from the register is transferred to the second register and mixed with the signal charge from the first register other than the specific first register, the signal charges of the pixels separated from each other in the same row are transferred to the second register. Can be mixed in registers.

Therefore, according to the present invention, the reading time to the second register can be controlled in units of the first register, and reading can be performed at different timings in units of the first register. Further, the drive signal applied to the third gate electrode is always set to a voltage that opens the channel barrier so that signal charges of pixels in the same row that are separated from each other are not mixed in the second register. It is also possible to easily switch between the mode in which the signal charges of the distant pixels are mixed and the mode in which the mixing is not performed.

  In this case, the transfer time difference generating unit is configured by the same number of transfer electrodes with respect to all the first registers. Therefore, a two-layer gate structure can be easily configured.

Further, the transfer time difference generating unit is configured by the same number of transfer electrodes with respect to all the first registers, and the first gate electrode and the transfer electrode are adjacent to each other without forming an identical plane. because it is arranged Te, the gate wiring does not have to take a crossed or laminated structure. Therefore, for example, the first gate electrode and the transfer electrode can be flattened by a chemical mechanical polishing method or the like, and the pixel cell can be reduced in the height direction. The rate can be increased. As a result, even when the planarized electrode structure is used, the same effect as in the case of the first embodiment can be obtained.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a schematic configuration diagram of a color CCD image sensor as a solid-state imaging device according to the present embodiment. Here, a case where two adjacent pixels in the same row are set as one set and the same color signal charges in two adjacent sets of pixels are mixed will be described. FIG. 1 shows a pixel region 1 of 4 rows and 4 columns. For the sake of simplicity, the signal charge transfer state in the AA ′ section and the BB ′ section in FIG. 1 will be described.

  The color CCD image sensor according to the present embodiment is an interline transfer type CCD image sensor having a four-phase drive vertical register with a two-layer gate structure, and includes RGB three-color photodiodes 22 arranged in a matrix and each photodiode. The pixel region 21 including the transfer gate 23 connected to the pixel 22, the vertical register 24 arranged in the column direction between the photodiodes 22 and connected to the transfer gate 23, and arranged in the row direction at one end of the vertical register 24. A horizontal register area 26 including a horizontal register 25 for receiving signal charges from the vertical register 24 is provided.

  The vertical register 24 includes a vertical gate electrode 27 to which drive pulses ΦV1 to ΦV4 are applied. Among them, the vertical gate electrode 27b to which the drive pulses ΦV2 and ΦV4 are applied constitutes a first layer gate, and the vertical gate electrode 27a to which the drive pulses ΦV1 and ΦV3 are applied constitutes a second layer gate.

  The driving pulses ΦV1 to ΦV7 are applied at a general four-phase driving timing, and the signal charges are held in the storage portion for two vertical gate electrodes 27 and the barrier portion for two vertical gate electrodes 27. Is done.

  In addition, a color filter (not shown) is disposed on the photodiode 22 to form an RGB Bayer array. A transfer time difference generation region 28 including vertical gate electrodes 27c to 27f to which drive pulses ΦV5 to ΦV7 are applied is provided at the boundary between the vertical register 24 and the horizontal register 25. Among them, the vertical gate electrode 27c to which the drive pulse ΦV5 is applied constitutes the second layer gate, and the vertical gate electrode 27d of the vertical gate electrodes 27d and 27e to which the drive pulse ΦV6 is applied constitutes the first layer gate. The vertical gate electrode 27e constitutes a second layer gate, and the vertical gate electrode 27f to which the drive pulse ΦV7 is applied constitutes a first layer gate.

  2A shows the AA ′ cross section of FIG. 1, and FIG. 2B shows the BB ′ cross section. As shown in FIG. 2A, the surface of the diffusion layer contacting the vertical gate electrode 27c to which the drive pulse ΦV5 is applied and the vertical gate electrode 27f to which the drive pulse ΦV7 is applied has a potential different from that of the vertical register region. Channel barriers 29a and 29b set by energy (hereinafter simply referred to as potential) are formed and function as channel barriers for generating a delay in signal charge transfer. The channel barrier 29 is formed of a diffusion layer having a polarity different from that of the diffusion layer constituting the vertical register 24. That is, when the vertical register 24 is formed of an n-type semiconductor diffusion layer, the channel barrier 29 is formed of a p-type semiconductor diffusion layer, whereas when the vertical register 24 is formed of a p-type semiconductor diffusion layer. The channel barrier 29 is formed of an n-type semiconductor diffusion layer. FIG. 2A shows a case where the vertical register 24 is configured by an n-type semiconductor diffusion layer 33 formed on the p-type well 34, and the channel barrier 29 is formed by a p-type semiconductor diffusion layer. Yes.

  That is, in the present embodiment, the transfer electrodes are constituted by the vertical gate electrodes 27c to 27f.

  The potential of the channel barrier 29 may be the same as that of the diffusion layer under the transfer gate 23. In that case, the transfer time difference generation region 28 can be driven at the same voltage level as the signal charge read voltage from the photodiode 22 to the vertical register 24.

  As can be seen from FIG. 2B, the channel barrier 29 is not formed immediately below the vertical gate electrodes 27c and 27f in the BB ′ section, and the AA ′ section and the BB ′ section. In either case, a gate insulating film 35 is formed in a region where the vertical gate electrode 27 constituting the first layer gate and the vertical gate electrode 27 constituting the second layer gate overlap.

  In FIG. 1, after signal charges are read from the vertical register 24 to the horizontal register 25, two-phase horizontal transfer clocks ΦH1 and ΦH2 are applied to the horizontal gate electrodes 30a and 30b constituting the horizontal register 25. The horizontal gate electrodes 30a and 30b are driven. Thus, the signal charges are sequentially transferred to the charge detector 31 and then output from the output amplifier 32.

  The color CCD image sensor having the above configuration is operated as follows to mix the same color signal charges of the two adjacent pixels in the same row. First, the flow of signal charges when mixing the same color signal charges of the two adjacent pixels in the same row will be described in detail with reference to FIGS.

  FIG. 3A shows a signal charge accumulation state in the initial state. The signal charges stored in the initial state are given an odd number in the A column and an even number in the B column together with the color symbols R, G, and B in order from the horizontal register 25 side. In the initial state, when the drive pulses ΦV5, ΦV6, and ΦV7 are applied to the vertical gate electrodes 27c, 27d, 27e, and 27f, as shown in FIG. 3B, only the B column in which the channel barrier 29 is not formed is provided. , The signal charges R2 and G2 are transferred from the vertical register 24 to the horizontal register 25. At that time, since the channel barrier 29 is formed in the A column, the signal charges R1 and G1 are not transferred and are held at the same positions as in the initial state.

  Next, when horizontal transfer clocks ΦH1 and ΦH2 are applied to the horizontal gate electrodes 30a and 30b, as shown in FIG. 4C, the signal charges R2 and G2 in the horizontal register 25 correspond to two columns in the horizontal direction. Only forwarded. Next, pulses that lower the potential of the channel barrier 29 are applied to the vertical gate electrodes 27c, 27d, 27e, and 27f as drive pulses ΦV5, ΦV6, and ΦV7. Then, as shown in FIG. 4D, the signal charges R1 and G1 are transferred from the vertical register 24 to the horizontal register 25 only in the column A. At this time, the signal charges R2 and G2 have already been transferred to the transfer destination of the signal charges R1 and G1 in the horizontal register 25. Therefore, the mixing of the signal charges R1 and the signal charges R2 and the mixing of the signal charges G1 and the signal charges G2 are performed simultaneously with the transfer of the signal charges R1 and G1.

  Next, when drive pulses [Phi] V1- [Phi] V7 are applied to the vertical gate electrodes 27a-27f, as shown in FIG. 5 (e), only one stage of all signal charges in the vertical register 24 is on the horizontal register 25 side. Forwarded to Next, when the horizontal transfer clocks ΦH1 and ΦH2 are applied to the horizontal gate electrodes 30a and 30b, the signal charges (R1 + R2) and (G1 + G2) mixed in the horizontal register 25 as shown in FIG. The data is transferred to the charge detector 31 and the output is completed.

  FIG. 6 shows the timing of the drive pulses ΦV1 to ΦV7 when the same color signal charges of the two adjacent pixels in the same row are mixed as described above. 7 and 8 show signal charge transfer states and potentials of the n-type semiconductor diffusion layer 33 including the channel barrier 29 corresponding to the time points T1 to T13 in FIG.

  The transfer cycle per stage in the vertical register 24 is from time T1 to time T13. First, the operation in the periods T1 to T4 will be described in detail.

  As shown in FIGS. 7 and 8, in the row B represented by the BB ′ cross section, the packet (transfer time difference generation region 28) that is closest to the horizontal register 25 and includes the vertical gate electrodes 27c to 27f is shown. The signal charge 37 is accumulated. At time T2, a high level (hereinafter referred to as “H”) drive pulse ΦV7 is applied to the vertical gate electrode 27f, so that the potential of the n-type semiconductor diffusion layer 33 immediately below the vertical gate electrode 27f becomes the vertical gate electrode 27d, It becomes the same as the potential of the n-type semiconductor diffusion layer 33 just under 27e. Further, at time T3, the levels of the drive pulse ΦV6 and the drive pulse ΦV7 applied to the vertical gate electrodes 27d and 27e start to decrease from the above “H” and become “H” and low level (hereinafter referred to as “L”). The potential of the n-type semiconductor diffusion layer 33 immediately below the vertical gate electrodes 27d to 27f rises to a position slightly lower than the potential immediately below the vertical gate electrode 27c. As the potential rises directly below the vertical gate electrodes 27d to 27f, the signal charge 37 stored in the packet is transferred to the horizontal register 25.

  At that time, in the column A represented by the AA ′ cross section, since the potential barrier 29b exists immediately below the vertical gate electrode 27f, the potential is n-type semiconductor diffusion layer immediately below the vertical gate electrodes 27d and 27e. Thus, the signal charge 36 stored in the packet is not transferred to the horizontal register 25. Therefore, the signal charge 36 stops in the packet.

  Thereafter, at the time point T4, the levels of the drive pulses ΦV6 and ΦV7 return to the “L”, and the transfer of the signal charge 37 in the B column to the horizontal register 25 is completed.

  Next, the operation in the period T5 to T8 will be described in detail.

  First, at the time T5, when the level of the drive pulse ΦV6 becomes “H”, the signal charge 36 accumulated in the n-type semiconductor diffusion layer 33 immediately below the vertical gate electrodes 27d and 27e in the A column is It is stored in the packet that has returned to the same potential as the time T1. Next, by making the level of the drive pulse ΦV7 one level higher than “H” (hereinafter referred to as “HH”), the potential immediately below the vertical gate electrode 27f at time T6 is higher than that at time T2. Further down, the potential is the same as the potential immediately below the vertical gate electrodes 27d and 27e. Further, at time T7, the level of the drive pulse ΦV6 returns from “H” to “L”, and the potential immediately below the vertical gate electrodes 27d and 27e becomes higher than the potential directly below the vertical gate electrode 27f. As the potential rises just below the vertical gate electrodes 27d and 27e, the signal charge 36 stored in the packet is transferred to the horizontal register 25.

  In the meantime, the signal charges 37 in the B column existing in the horizontal register 25 at the time T4 are set to the level of the horizontal transfer clocks ΦH1 and ΦH2 between the time T5 and the time T6. The data is transferred in the horizontal register 25 toward the output amplifier 32 side. Thus, the signal charges 37 are transferred in the horizontal register 25 by two columns of the vertical register 24, and the state shown in FIG. At time T7, when the level of the drive pulse ΦV6 returns from “H” to “L” and the signal charges 36 of the A column are transferred to the horizontal register 25, the signals of the A column in the horizontal register 25 are transferred. The charges 36 and the signal charges 37 in the B column are mixed.

  Thereafter, at the time T8, the level of the drive pulse ΦV7 returns to the “L” level, and the transfer of the signal charges 36 in the A column to the horizontal register 25 and the mixing with the signal charges 37 in the B column are completed. .

  In the period T5 to T8, in FIG. 1, the driving pulse ΦV1 applied to the odd-numbered vertical gate electrodes 27a, the driving pulse ΦV2 applied to the even-numbered vertical gate electrodes 27b, and the even-numbered vertical gates in FIG. The levels of the drive pulse ΦV3 applied to the electrode 27a and the drive pulse ΦV4 applied to the odd-numbered vertical gate electrodes 27b are respectively controlled by the four-phase drive timing. As a result, at the time point T1, the potentials immediately below the odd-numbered vertical gate electrodes 27a and even-numbered vertical gate electrodes 27b in which signal charges are accumulated sequentially move toward the horizontal register 25 with the same potential. The signal charges subsequent to the signal charges 36 and 37 transferred to the horizontal register 25 sequentially move in the vertical register 24.

  Next, the operation in the periods T9 to T13 will be described in detail.

  First, at the time T9, the level of the drive pulse ΦV1 is set to “H” while the level of the drive pulse ΦV5 is set to “HH”, so that the signal charges move in the vertical register 24 in both the A column and the B column. To do. Further, the next signal charge is transferred and stored in the n-type semiconductor diffusion layer 33 immediately below the vertical gate electrode 27a in the first row in FIG. Next, at time T10, the level of the drive pulse ΦV3 becomes “L”, and at time T11, the levels of the drive pulses ΦV2 and ΦV6 become “H”. The signal charge moves. Next, at time T12, the level of the drive pulse ΦV4 becomes “L”, and at time T13, the level of the drive pulse ΦV5 becomes “L”. Thus, one cycle of signal charge transfer is completed.

  At the time T13, the signal charge in the vertical register 24 is moved to the horizontal register 25 side by one row at the same potential of the n-type semiconductor diffusion layer 33 as in the initial state T1.

  Next, an operation when the same color signal charges of the two adjacent pixels in the same row are not mixed will be described. FIG. 9 shows the timing of the drive pulses ΦV1 to ΦV7 when the same color signal charges of the two adjacent pixels in the same row are not mixed as described above. 10 and 11 show signal charge transfer states and potentials of the n-type semiconductor diffusion layer 33 corresponding to the respective times T1 to T11 in FIG.

  The transfer cycle per stage in the vertical register 24 is from time T1 to time T11. When signal reading is performed collectively without mixing signal charges, the levels of the drive pulses ΦV1, ΦV2, ΦV3, ΦV4, and ΦV6 are set to “H” and “L” at the drive timing shown in FIG. The color CCD image sensor can be driven at the four-phase drive timing by changing the levels of the drive pulses ΦV5 and ΦV7 to “HH” and “L”. As a result, the A column and the B column sequentially move toward the horizontal register 25 in the same potential state. Then, the transfer of signal charges from the transfer time difference generation region 28 to the horizontal register 25 in the A column and the B column starts at time T2 and is completed at the same time at time T4.

  As described above, in this embodiment, the transfer time difference generation region 28 composed of the vertical gate electrodes 27 c to 27 f is provided at the boundary between the plurality of vertical registers 24 and the horizontal register 25. Then, the vertical gate electrode 27c is formed in the second layer so as to partially overlap the vertical gate electrode 27b formed in the first layer in the pixel region 21 and closest to the horizontal register 25 via the gate insulating film 35. is doing. The vertical gate electrode 27d is formed in the first layer so as to partially overlap the vertical gate electrode 27c. The vertical gate electrode 27e is formed in the second layer so as to partially overlap the vertical gate electrode 27d. The vertical gate electrode 27f is formed in the first layer so as to partially overlap the vertical gate electrode 27e.

  Further, among the plurality of vertical registers 24, the adjacent two columns of vertical registers 24, 24 are taken as one set, and the transfer time difference following the vertical registers 24 (the vertical register 24 of the A column in FIG. 1) arranged in every other group. In the generation region 28, a diffusion having a polarity different from that of the diffusion layer 33 constituting the vertical register 24 is formed on the contact surface between the vertical gate electrode 27 c and the vertical gate electrode 27 f in the extending portion of the diffusion layer 33 constituting the vertical register 24. Layered channel barriers 29a and 29b are formed.

  When the signal charge 37 is transferred to the horizontal register 25 only from the transfer time difference generation region 28 following the B-column vertical register 24 in which the channel barrier 29 is not formed, the drive pulse ΦV7 applied to the vertical gate electrode 27f. , The potential immediately below the vertical gate electrode 27f in the B column transfer time difference generation region 28 is lowered to a potential at which the stored charge 37 can be transferred to the horizontal register 25, while the transfer time difference generation region 28 in the A column The potential immediately below the vertical gate electrode 27f in FIG. 3 maintains a potential at which the accumulated charge 36 cannot be transferred to the horizontal register 25.

  Further, after the signal charge 37 transferred from the transfer time difference generation region 28 in the B column to the horizontal register 25 moves to the boundary position with the transfer time difference generation region 28 in the A column, the A column in which the channel barrier 29 is formed. When the signal charge 36 is transferred to the horizontal register 25 from the transfer time difference generation area 28 and mixed with the signal charge 37, the level of the drive pulse ΦV7 is set to “HH” and the transfer time difference generation area 28 in the A column is changed. The potential immediately below the vertical gate electrode 27 f is lowered to a potential at which the accumulated charge 36 can be transferred to the horizontal register 25.

  Therefore, according to the present embodiment, a color CCD image sensor capable of adding signals by controlling signal reading from the vertical register 24 to the horizontal register 25 for each column can be realized with a two-layer gate structure. It is.

  Further, by changing the levels of the drive pulses ΦV5 and ΦV7 to “HH” and “L” and controlling the levels of the drive pulses ΦV1 to ΦV7 at the four-phase drive timing, the two adjacent sets in the same row are controlled. It is possible to read out the same color signal charges of the pixels without mixing.

  Therefore, according to the color CCD image sensor (solid-state imaging device) and the driving method thereof in the present embodiment, the same color signals of the two adjacent pixels in the same row can be changed only by changing the level and application timing of the drive pulse ΦV7. The case of mixing charges and the case of reading signals all together without mixing signal charges can be used separately.

  In the present embodiment, the case where the present invention is applied to an interline transfer type CCD image sensor having a four-phase drive vertical register has been described as an example. However, the present invention is also applicable to CCD image sensors other than the 4-phase drive vertical register and CCD image sensors other than the interline transfer type. As for the driving method of the CCD image sensor, various driving methods are possible as long as the configuration of the CCD image sensor in the present embodiment.

Second Embodiment FIG. 12 is a schematic configuration diagram of a color CCD image sensor as an individual image sensor according to the present embodiment. This color CCD image sensor is an interline transfer type color CCD image sensor having a four-phase drive vertical register with a flattened electrode structure.

  In FIG. 12, 41 is a pixel area, 42 is a photodiode, 43 is a transfer gate, and 46 is a horizontal register area.

  FIG. 13A shows a CC ′ section of FIG. 12, and FIG. 13B shows a DD ′ section. As can be seen from FIG. 13, in the present embodiment, the vertical gate electrodes 47a and 47b are adjacent to each other through the gate insulating film 55 without overlapping each other, and are arranged in the same plane. Similarly, the vertical gate electrodes 47c to 47f are arranged in the same plane without overlapping each other.

  In the C column represented by the CC ′ cross section, the surface of the diffusion layer contacting the vertical gate electrode 47c to which the drive pulse ΦV5 is applied and the vertical gate electrode 47f to which the drive pulse ΦV7 is applied are different. Channel barriers 49a and 49b made of a polar diffusion layer are formed. That is, when the vertical register 44 is formed of an n-type semiconductor diffusion layer, the channel barrier 49 is formed of a p-type semiconductor diffusion layer, while the vertical register 44 is formed of a p-type semiconductor diffusion layer. The channel barrier 49 is formed of an n-type semiconductor diffusion layer. FIG. 13A shows a case where the vertical register 44 is configured by an n-type semiconductor diffusion layer 53 formed on the p-type well 54, and the channel barrier 49 is formed by a p-type semiconductor diffusion layer. Yes. As can be seen from FIG. 13B, the channel barrier 49 is not formed immediately below the vertical gate electrodes 47c and 47f in the DD ′ cross section.

  In FIG. 12, after the signal charges are read from the vertical register 44 to the horizontal register 45, two-phase horizontal transfer clocks ΦH1 and ΦH2 are applied to the horizontal gate electrodes 50a and 50b constituting the horizontal register 45. The horizontal gate electrodes 50a and 50b are driven. Thus, the signal charges are sequentially transferred to the charge detector 51 and then output from the output amplifier 52.

  Also in the case of the color CCD image sensor of the present embodiment, as shown in FIGS. 3 to 5 by applying the drive pulses ΦV1 to ΦV7 at the timing shown in FIG. 6 as in the case of the first embodiment. By such a flow of signal charges, two adjacent pixels in the same row can be considered as one set, and the same color signal charges in the two adjacent sets of pixels can be mixed. Further, by applying the drive pulses ΦV1 to ΦV7 at the timing shown in FIG. 9, it is possible to prevent the same color signal charges of the two adjacent pixels in the same row from being mixed.

  As described above, in the present embodiment, the transfer time difference generation region 48 composed of the vertical gate electrodes 47c to 47f is provided at the boundary between the plurality of vertical registers 44 and the horizontal register 45. Further, in the transfer time difference generation region 48 following the vertical register 44 (the vertical register 44 of the C column in FIG. 12) arranged every other set of two adjacent vertical registers 44, 44, the vertical gate electrode Channel barriers 49a and 49b are formed immediately below 47c and 47f.

  The vertical gate electrodes 47a to 47f are arranged so as to form the same plane without overlapping each other.

  As described above, any two transfer time difference generation regions are obtained with respect to two adjacent vertical registers 44 (the vertical register 44 of the C column and the D column in FIG. 12), with two adjacent vertical registers 44 and 44 as one set. 48 also has the same vertical gate electrode structure, and each vertical gate electrode 47a to 47f is effectively formed in one layer. Therefore, it is not necessary to adopt a structure in which the gate wiring intersects or is stacked in the transfer time difference generation region 48.

  Therefore, in this embodiment, the gate electrode can be planarized by, for example, a chemical mechanical polishing method or the like. As a result, the pixel cell can be reduced in the height direction, and the light collection rate can be increased when the pixel cell is reduced. And even if it is a case where a planarization electrode structure is used, the effect similar to the case of the said 1st Embodiment can be acquired.

  In each of the above embodiments, a color CCD image sensor in which the vertical register 24 is configured by the n-type semiconductor diffusion layer 33 on the p-type well 34 is described as an example. It may be a color CCD image sensor formed in the above.

  Further, in each of the above embodiments, the vertical registers 24 and 44 provided with the channel barriers 29 and 49 are arranged as a pair, and the vertical registers 24 and 44 arranged in every other pair are taken as one set. 24; 44, 44. However, the position of the vertical register in which the channel barriers 29 and 49 are provided is not limited to this. Furthermore, the number of pixels of the same color to be added is not limited to two pixels.

It is a schematic block diagram of the color CCD image sensor which is a solid-state imaging device of this invention. It is a figure which shows the AA 'cross section and BB' cross section in FIG. It is a figure which shows the flow of the signal charge in the case of mixing the same color signal charge of four adjacent pixels of the same row. It is a figure which shows the flow of the signal charge following FIG. It is a figure which shows the flow of the signal charge following FIG. It is a timing chart of a drive pulse in the case of mixing the same color signal charges of four adjacent pixels in the same row. It is a figure which shows the transfer state of the signal charge corresponding to each time in FIG. 6, and the potential of an n-type semiconductor diffusion layer. FIG. 8 is a diagram illustrating a signal charge transfer state and the potential of the n-type semiconductor diffusion layer following FIG. 7. It is a timing chart of a drive pulse when the same color signal charges of four adjacent pixels in the same row are not mixed. It is a figure which shows the transfer state of the signal charge corresponding to each time in FIG. 9, and the potential of an n-type semiconductor diffusion layer. It is a figure which shows the transfer state of the signal charge following FIG. 10, and the potential of an n-type semiconductor diffusion layer. It is a schematic block diagram of the color CCD image sensor different from FIG. It is a figure which shows the CC 'cross section and DD' cross section in FIG. It is a schematic plan view in the solid-state imaging device which adds a pixel signal with the conventional 2 layer gate structure.

21, 41 ... Pixel region,
22, 42 ... photodiode,
23, 43 ... Transfer gate,
24, 44 ... vertical register,
25, 45 ... Horizontal register,
26, 46 ... horizontal register area,
27a, 27b, 47a, 47b ... vertical gate electrodes in the pixel region,
27c to 27f, 47c to 47f, vertical gate electrodes in the transfer time difference generation region,
28, 48 ... transfer time difference generation area,
29a, 29b, 49a, 49b ... channel barrier,
30a, 30b, 50a, 50b ... horizontal gate electrode,
31, 51... Charge detection unit,
32, 52 ... Output amplifier,
33, 53 ... n-type semiconductor diffusion layer,
34, 54 ... p-type well,
35, 55 ... gate insulating film,
36, 37: Signal charge.

Claims (6)

A plurality of light receiving parts formed on a semiconductor substrate or well and arranged two-dimensionally;
A plurality of first registers formed on the semiconductor substrate or the well and having a first gate electrode for transferring the signal charge read from the light receiving unit in one direction;
It is formed on the semiconductor substrate or on the well, and is arranged to extend in the other direction intersecting the one direction at the one-direction end of the first register, and transferred from the first register. A second register having a second gate electrode for transferring the signal charge in the other direction;
The second register is formed on the semiconductor substrate or the well, and is disposed between the one-direction end of the first register and the second register, receives the signal charge from the first register, and receives the second signal. A transfer time difference generating unit for transferring a signal charge from the first register to the second register with respect to each first register,
The transfer time difference generator is
For all the first registers, the same number of transfer electrodes for transferring signal charges received from the first register to the second register;
A channel barrier that shields movement of signal charges received from the first register to the second register with respect to the particular first register;
Together constituted by the transfer electrodes, and Nde including a third gate electrode for opening and closing of the channel barrier in accordance with an electrical signal applied thereto,
The first gate electrode of the first register and the transfer electrode of the transfer time difference generator are arranged adjacent to each other without overlapping each other, forming the same plane,
The solid-state imaging device , wherein the channel barrier is a region having a potential energy different from that of the first register . The solid-state imaging device according to claim 1,
The channel barrier, a solid-state imaging device according to claim that you have been configured by the diffusion layers of different polarity to the polarity of the diffusion layer constituting the first register. The solid-state imaging device according to claim 1 ,
A transfer gate for transferring the signal charge accumulated in the light receiving section to the first register;
The solid-state imaging device , wherein the channel barrier has the same potential energy as the transfer gate . The solid-state imaging device according to claim 1 ,
The third gate electrode, a solid-state imaging device according to claim Rukoto driven by three or more voltage levels. The solid-state imaging device according to claim 1,
The one direction is a column direction, the other direction is a row direction,
A mixing mode in which signal charges from remote light receiving units in the same row are mixed in the second register, and the mixed signal charges are transferred in the row direction;
A normal mode in which signal charges from remote light receiving units in the same row are transferred in the row direction without being mixed in the second register;
The solid-state imaging device characterized that you have enabled switched. A driving method of the solid-state imaging device according to claim 1,
A drive signal having a voltage that does not open the channel barrier is applied to the third gate electrode in the transfer time difference generation unit at a predetermined timing, and the second register of the signal charge is generated by the channel barrier related to the specific first register. shields the movement to the step of transferring only the signal charges from the first register other than the specific first register to said second register,
Applying a drive signal to the second register at a predetermined timing to transfer the signal charge transferred to the second register to the position of the specific first register in the second register;
A drive signal is applied to all the transfer electrodes in the transfer time difference generator at a predetermined timing, and a drive signal having a voltage that opens the channel barrier is applied to the third gate electrode. The signal charge from the first register is transferred in the one direction, the channel barrier relating to the specific first register is opened, and the signal charge from the specific first register is transferred to the second register. Mixing with signal charges already transferred from a first register other than the particular first register;
A method for driving a solid-state imaging device.

Images