JP4513970B2 - Multi-channel digital-analog converter - Google Patents

Description

  The present invention relates to an improvement of a multi-channel digital-analog converter used for adjusting circuit parameters.

  FIG. 6 shows an 8-channel digital-analog converter. In FIG. 6, reference numeral 100 denotes an 8-channel digital / analog converter, which includes eight digital / analog conversion units 110-180. The digital / analog conversion unit 110 includes a latch 111, a DAC 112, and a buffer 113. The digital value stored in the latch 111 is converted into an analog signal by the DAC 112 and output to the outside as Vout1 via the buffer 113.

  Since the digital-analog converters 120 to 180 have the same configuration, description thereof is omitted. Reference numeral 190 denotes a control unit to which addresses A0 to A2 and a write signal WR are input. The control unit 190 writes the digital value on the data bus into the latches in the digital / analog conversion units 110 to 180 according to the values of the addresses A0 to A2. Such an 8-channel digital-analog converter 100 can be easily connected to a microcomputer, and is often used for adjusting parameters of electronic circuits.

  As can be seen from FIG. 6, the same reference signal Vref is input to the DACs in the digital-analog converters 110 to 180. Therefore, the full scales of these digital-analog converters 110 to 180 are the same. That is, the same analog value is output for the same digital value. Therefore, when the voltage required for parameter adjustment is small, there are many areas that are not used, and the use efficiency is reduced.

  FIG. 7 shows an example of an offset voltage adjustment circuit using this multi-channel digital-analog converter. In addition, the same code | symbol is attached | subjected to the same element as FIG. 6, and description is abbreviate | omitted. In FIG. 7, reference numerals 211 to 281 denote adders, to which the outputs of the digital / analog converters 110 to 180 and the offset voltages Voff1 to Voff8 are input, respectively. The adders 211 to 281 output the added value of the input digital-analog converter and the offset voltage. Outputs of the adders 211 to 281 are output via buffers 212 to 282, respectively.

  In such a configuration, the offset voltage can be removed by setting the input digital signal of the digital-to-analog converters 110 to 180 so as to output a voltage signal that cancels the values of the offset voltages Voff1 to Voff8.

Data sheet for Maxim Integrated Products, Inc. CMOS, Octal, 8-Bit DAC “MX7228”. 1989, [Search on March 22, 2005], Internet <URL: http://pdfserv.maxim-ic.com/en/ds/MX7228.pdf>

  However, since such a multi-channel digital-analog converter has a fixed full scale, there has been a problem of poor utilization efficiency. Consider a case where there are eight parameters of the circuit to be adjusted and the offset is eliminated in the circuit of FIG. It is assumed that the offset voltages Voff1 to Voff8 are all normally normally distributed, the average value is 0, and the standard deviation is σ.

In order to reduce the failure rate that the adjustment range of the digital-analog converters 110 to 180 is narrow and the offset voltage cannot be corrected to 0.1% or less, the probability that all offset adjustments are successful must be 99.9% or more. I must. Assuming success rate of the digital-analog converter 110 to 180 equal shall the success rate of the digital-analog converter ^0.999 1/8 = 0.999875, i.e. more than 99.9875%.

  For that purpose, all the output ranges of the digital-analog converters 110 to 180 must be ensured to be ± 3.836σ or more. The sum of the output ranges of all eight digital-to-analog converters is ± 30.688σ which is eight times this. As described above, an output range of 30 times or more as compared with the standard deviation of the offset voltage has to be secured, and there is a problem that the circuit scale increases.

  Therefore, the problem to be solved by the present invention is to provide a multi-channel digital-to-analog converter that has high circuit utilization efficiency and can consequently reduce the circuit scale.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A plurality of reference sources having the same output voltage; and
A buffer having two input terminals of different polarities;
A plurality of input digital values are input, and for each of the input digital values, the number of the reference sources corresponding to the input digital value is selected, and an analog voltage corresponding to the input digital value by combining the selected reference sources A switch matrix that selects and outputs this analog voltage to the two input terminals of the buffer based on the polarity of the input digital value;
Is provided. The circuit scale can be reduced.

The invention according to claim 2 is the invention according to claim 1,
An average value adjustment digital input value is input, and an average value adjustment unit that converts the average value adjustment digital input value into an analog signal;
An adder for adding the output of the average value adjustment unit and the output of the buffer;
Is provided. Even if it is used for adjustment of a circuit whose error voltage average value of the circuit to be corrected is not 0, the circuit scale does not increase.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
A plurality of second reference sources having different output voltages, and the second reference source is selected according to the value of the inputted digital signal, and the inputted digital signal is combined with the selected second reference source. A second multi-channel digital-to-analog converter having a plurality of digital-to-analog converters composed of a switch matrix for obtaining an analog signal corresponding to the signal;
An adder for adding the output of the second multi-channel digital-analog converter and the output of the buffer;
Each of the plurality of input digital values is divided into two at predetermined bit positions, one of the divided digital values is input to the switch matrix, and the other is input to the second multi-channel digital-analog converter. It is what I did. The circuit scale can be optimized.

The invention according to claim 4 is the invention according to claim 3,
Of the two divided values, the upper side is input to the switch matrix and the lower side is input to the second multi-channel digital-analog converter. The circuit scale can be further reduced.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, and fourth aspects of the present invention, a plurality of reference sources having the same output voltage are provided, and this reference source is selected by the absolute value of the input digital value. Since the required number of reference sources is used, the number of reference sources to be prepared can be reduced, and as a result, the circuit scale can be reduced. Since the reference source is an analog circuit, the element size must be increased, which is particularly effective.

  Further, an average value adjustment unit is provided, and the output of each average value adjustment unit is added to the output of each channel of the multi-channel digital-analog converter, so that it can be used for adjustment of a circuit whose error voltage average value is not zero. There is also an effect that an increase in circuit scale can be suppressed. In addition, the circuit scale can be optimized by using the weighted digital-analog converter together.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multi-channel digital-analog converter according to the present invention. This embodiment is an example of an 8-channel digital-analog converter.

  In FIG. 1, reference numeral 300 denotes a multi-channel digital-analog converter, which includes a decoder 310, a switch matrix 320, a segment reference array 330, and a buffer array 340.

  The decoder 310 receives digital input values of 8 channels from CH1 to CH8 and decodes these digital input values. Each digital input value is 8 bits and takes a value of -128 to 127.

  The segment reference array 330 includes a plurality of reference sources 331 to 33n. Each of the reference sources 331 to 33n outputs a positive analog voltage corresponding to one step (1LSB) of the multichannel digital-analog converter.

  The output of the decoder 310 is input to the switch matrix 320, the number corresponding to the digital input value of each channel is selected from the reference sources 331 to 33n, and the selected reference sources are connected in series.

  The buffer array 340 includes 341 to 348 buffers. The buffers 341 to 348 have two positive and negative input terminals, and the output of the reference source selected by the switch matrix 320 is input to these input terminals. The outputs of the buffers 341 to 348 become analog outputs of the channels 1 to 8, respectively.

  Next, the operation of this embodiment will be described. Assume that the digital input value of channel 1 is a positive or zero value m (m = 0 to 127). This digital input value is decoded by the decoder 310 and input to the switch matrix 320. The switch matrix 320 selects m unused reference sources from the segment reference array 330, connects these selected reference sources in series, and outputs them to the non-inverting input terminal of the buffer 341. When the output voltage of the reference sources 331 to 33n is ΔV, the output of the buffer 341 becomes m × ΔV and can be converted into an analog signal.

  When the input digital value is negative (m = −1 to −128), the switch matrix 320 selects | m | (|| represents an absolute value) reference sources that are not used from the reference array 340; These reference sources are connected in series and output to the inverting input terminal of the buffer 341. Since the polarity of this signal is inverted by the buffer 341, an analog signal corresponding to m is obtained. Since the operations of channel 2 to channel 8 are the same, description thereof is omitted. In this embodiment, the decoder 310 and the switch matrix 320 are separated from each other. However, the decoder 310 may be included in the switch matrix 320.

  FIG. 2 shows an offset adjustment circuit using the multi-channel digital-analog converter 300. The same elements as those in FIGS. 1 and 7 are denoted by the same reference numerals and description thereof is omitted. In FIG. 2, reference numeral 200 denotes a target circuit that adjusts an offset voltage, and includes adders 211 to 281 and buffers 212 to 282 to which outputs of the adders 211 to 281 are input, respectively. Each adder receives the offset voltages Voff1 to Voff8 and the analog output of each channel of the multi-channel digital-analog converter 300, respectively. Adders 211 to 281 add the input signals and output the added signals to buffers 212 to 282, respectively.

The number of reference sources built in the segment reference array 330 is 2 ^{N-1 at the} maximum when the number of bits of the digital input value is N (128 when N = 8), but is actually much smaller than this value. it can. This will be described.

As described above, in this embodiment, a number corresponding to the digital input value of each channel is selected from the reference sources 331 to 33n and used. Step number of individual digital-analog converter is a maximum 2 ⁸ for an 8-bit converter, except that the total number of steps of all the digital-analog converter is limited by the number of reference sources 331～33N, individual The full scale of the digital-analog converter can be set freely. Therefore, the number of required reference sources must be considered as the sum of offsets to be adjusted. When this sum is small, the number of required reference sources is small, and when the sum is large, the number is large.

Although the offset voltages Voff1 to Voff8 take various values depending on the situation, they have a normal distribution, and the average value is 0 and the standard deviation is σ. From the laws of statistics, the average value of the sum of offsets m _sum = 0 and the standard deviation σ _sum = √8 × σ.

In order to reduce the failure rate in which offset adjustment cannot be performed due to the narrow adjustment range of the multi-channel digital-analog converter 300 to 0.1% or less, the sum of the output ranges of all channels is ± 2.576σ _sum (= ± 7.286σ) or more.

  As described above, in the conventional example shown in FIG. 6, the total output range needs to be ± 30.688 σ in order to suppress the defect rate to 0.1% or less, so the number of reference sources is 7.286 / 30.576. × 100 = 24% can be reduced.

  Since the reference source is an analog circuit, the element size is increased to ensure the DC accuracy of the digital-analog converter. Since this portion is ¼ or less of the conventional size, the circuit scale can be greatly reduced. Note that the decoder 310 and the switch matrix 320 are more complicated than the conventional one, but since this portion can be composed of analog switches and digital circuits, the circuit scale is not so large.

  In the embodiment of FIG. 1, it is assumed that the average value of the offset voltage is 0. However, in practice, a value other than 0 may be taken and cannot be predicted. For example, the average offset value may not be zero in circuits other than the fully differential configuration. Even if the offset design center is set to 0 by adjusting circuit constants, the average value does not become 0 if there is lot variation. If the average value of the offset voltage does not become zero, the number of required reference sources increases and the circuit scale increases.

FIG. 3 is a configuration diagram of an embodiment that assumes a case where the average value of the offset voltage varies from lot to lot. The same elements as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 3, reference numeral 400 denotes an average value adjusting unit, which includes a decoder 410, a switch matrix 420, a segment reference array 430, and a buffer 440. The segment reference array 430 includes 2 ⁴ = 16 reference sources.

  The decoder 410 receives a 5-bit average value adjusted digital input value. The decoder 410 decodes this input value and outputs it to the switch matrix 420. The switch matrix 420 selects the number of reference sources corresponding to the absolute value of the average digital input value from the reference sources built in the segment reference array 430, and connects the selected reference sources in series to the buffer 440. Output. At this time, when the average value adjustment digital input value is positive or 0, it is output to the non-inverting input terminal of the buffer 440, and when it is negative, it is output to the inverting input terminal. That is, the average value adjustment unit 400 is a single-channel digital-analog converter, and the basic configuration is the same as that of the multi-channel digital-analog converter 300.

  An adder array 500 includes adders 510 to 580. Each of these adders receives the output of each channel of the multi-channel digital-analog converter 300 and the output of the average value adjustment unit 400, and adds these input values for output. By doing so, the value set by the average value adjustment digital input value is added to the analog output of each channel, so that fluctuation of the average value due to lot fluctuation can be corrected.

Adjustment is performed according to the following procedure.
Set the digital input value and average value adjustment digital input value of all channels to 0.
Channel 1 offset adjustment is performed, the adjusted digital input value is stored in a register, and this digital input value is returned to zero.
The same operation as (2) is performed for channels 2 to 8.
The average value of the digital input values of channels 1 to 8 stored in the register is calculated and set to the average value adjustment digital input value.
A value obtained by subtracting the average adjustment digital input value from the digital input value stored in the register is set as the digital input value of each channel.

  FIG. 4 shows another embodiment. In this embodiment, the offset of a circuit in which a plurality of circuits are vertically connected is adjusted. In addition, the same code | symbol is attached | subjected to the same element as FIG. 3, and description is abbreviate | omitted. In FIG. 4, reference numeral 600 denotes a circuit for adjustment, and circuits 621 to 628 are vertically connected. Adders 611 to 618 are inserted between these circuits 621 to 628, and the outputs of the adders 510 to 580 are added to perform offset adjustment.

The adjustment procedure in this case is as follows.
All digital input values and average value adjustment digital input values are set to zero.
The CH1 digital input value is set, and the offset adjustment of the circuit 621 is performed. The adjusted digital input value is stored in the register, and the set value is left as it is.
The CH2 digital input value is set, and the offset adjustment of the circuit 622 is performed. The adjusted digital input value is stored in a register, the CH1 digital input value is set to 0, and offset adjustment is performed again. The CH2 digital input value after adjustment is not saved, but the set value is left as it is.
The same procedure is used for channels 3-8.
The average value of the digital input values stored in the register is obtained and set to the average value adjustment digital input value.
A value obtained by subtracting the average value from the set CH1 to CH8 digital input values is set as the digital input value of each channel.

  In this way, even when any of the circuits 621 to 628 is adjusted, it is possible to make the previous circuit adjusted. Further, since it is only necessary to set values for the channel to be adjusted and the preceding channel, the reference source is not used excessively.

FIG. 5 shows another embodiment. In this embodiment, a segment type digital analog converter and a weighted digital analog converter are used in combination. The segment type digital / analog converter uses a reference source having the same output voltage, and the weighted type digital / analog converter ²ⁿ times the voltage of one step (n = 0, 1, 2,...). These reference sources are used in combination. The weighted digital-to-analog converter is less efficient in using the reference source, but the number can be reduced.

  In FIG. 5, reference numeral 700 denotes an 8-channel segment type multi-channel digital-analog converter, which includes a decoder 710, a switch matrix 720, a segment reference array 730, and a buffer array 740. Of the digital input values of channels 1 to 8, The upper 4 bits are input. Since this digital-analog converter 700 has the same configuration as the multi-channel digital-analog converter 300 except for the number of bits, the description thereof is omitted.

  Reference numeral 800 denotes an 8-channel weighted digital / analog converter, which includes a decoder 810 and weighted digital / analog converters 820 to 890. The weighted digital-analog converter 820 includes a buffer 821, a switch matrix 822, and a weighted reference array 823. Although not shown, the weighted digital-analog converters 830 to 890 have the same configuration.

  An adder array 900 includes eight adders 910 to 980. The adder 910 receives the output of channel 1 of the digital-analog converter 700 and the digital-analog converter 800, adds these outputs, and outputs the result. This output becomes the analog output of channel 1.

  Similarly, the outputs of the channels 2 to 8 of the segment type digital-analog converter 700 and the weighted digital-analog converter are input to the adders 920 to 980, and these outputs are added and output. The outputs of the adders 920 to 980 become analog outputs of channels 2 to 8, respectively. Since the digital-to-analog converter 700 has a 4-bit configuration, the number of reference sources in the segment reference array 730 can be reduced. In this embodiment, a weighted digital-to-analog converter 800 must be newly added. However, since the weighted digital-to-analog converter has a small circuit scale and is used for the lower 4 bits, accuracy requirements can be reduced. The circuit scale can be reduced.

It is a block diagram which shows one Example of this invention. It is a block diagram of the offset adjustment circuit using one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram of the offset adjustment circuit using one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram of the conventional multi-channel digital analog converter. It is an example of the offset adjustment using the conventional multichannel digital analog converter.

Explanation of symbols

300, 700 8-channel digital analog converter 310, 410, 710, 810 Decoder 320, 420, 720, 822 Switch matrix 330, 430, 730 Segment reference array 331-33n Reference source 340 Buffer array 341-348, 440 Buffer 400 Average Value controller 500, 900 Adder array 510-580, 910-980 Adder 823 Weighted reference array 820-890 Weighted digital-analog converter

Claims (4)

A plurality of reference sources having the same output voltage; and
A buffer having two input terminals of different polarities;
A plurality of input digital values are input, and for each of the input digital values, the number of the reference sources corresponding to the input digital value is selected, and an analog voltage corresponding to the input digital value by combining the selected reference sources A switch matrix that selects and outputs this analog voltage to the two input terminals of the buffer based on the polarity of the input digital value;
A multi-channel digital-to-analog converter comprising: An average value adjustment digital input value is input, and an average value adjustment unit that converts the average value adjustment digital input value into an analog signal;
An adder for adding the output of the average value adjustment unit and the output of the buffer;
The multi-channel digital-to-analog converter according to claim 1, comprising: A plurality of second reference sources having different output voltages, and the second reference source is selected according to the value of an input digital signal, and the input digital signal is combined with the selected second reference source. A second multi-channel digital-to-analog converter having a plurality of digital-to-analog converters composed of a switch matrix for obtaining an analog signal corresponding to the signal, an output of the second multi-channel digital-to-analog converter, and an output of the buffer And an adder for adding
Each of the plurality of input digital values is divided into two at a predetermined bit position, one of the divided digital values is input to the switch matrix, and the other is input to the second multi-channel digital-analog converter. The multi-channel digital-analog converter according to claim 1 or 2, wherein the multi-channel digital-analog converter is configured as described above. 4. The multi-channel digital according to claim 3, wherein, of the two divided values, an upper side is input to the switch matrix and a lower side is input to the second multi-channel digital-analog converter. Analog converter.

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