JP4508488B2 - Manufacturing method of ceramic circuit board - Google Patents
Manufacturing method of ceramic circuit board Download PDFInfo
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- JP4508488B2 JP4508488B2 JP2001260271A JP2001260271A JP4508488B2 JP 4508488 B2 JP4508488 B2 JP 4508488B2 JP 2001260271 A JP2001260271 A JP 2001260271A JP 2001260271 A JP2001260271 A JP 2001260271A JP 4508488 B2 JP4508488 B2 JP 4508488B2
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C10/00—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition
- C03C10/0054—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition containing PbO, SnO2, B2O3
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C10/00—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition
- C03C10/0036—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition containing SiO2, Al2O3 and a divalent metal oxide as main constituents
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C10/00—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition
- C03C10/0036—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition containing SiO2, Al2O3 and a divalent metal oxide as main constituents
- C03C10/0045—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition containing SiO2, Al2O3 and a divalent metal oxide as main constituents containing SiO2, Al2O3 and MgO as main constituents
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Description
【０００１】
【発明の属する技術分野】
本発明は、セラミック回路基板の製法に関し、特に、異なる焼成収縮開始温度を有する複数の絶縁層を同時焼成して寸法精度を改善するセラミック回路基板の製法に関する。
【０００２】
【従来技術】
従来、強度の弱い絶縁層を強度の強い絶縁層で補強するためや回路基板の中に容量値の高いキャパシタを内蔵するために、絶縁層と、この絶縁層とは異なる材料からなる異種材料絶縁層を積層したセラミック回路基板が知られている（例えば、特開昭５９ー１９４４９３号公報参照）。このような回路基板では、磁器のクラックやデラミネーションを防止するために、絶縁層と異種材料絶縁層とは、焼成収縮率および熱膨張係数を一致させるように材料を決定していた。
【０００３】
しかしながら、このようなセラミック回路基板においては、クラックやデラミネーションを防止できるものの、焼成収縮率が大きいため、セラミック回路基板内に形成された導体層の主面（ｘ−ｙ）方向における寸法精度が低下するという問題があった。特に、近年においては、セラミック回路基板の小型薄型化のため、ますます導体層の主面（ｘ−ｙ）方向における寸法精度が要求されている。
【０００４】
そこで、近年においては、セラミック回路基板の積層成形体をＡｌ2Ｏ3基板等で挟持して焼成する加圧焼成法（特開昭６２−２６０７７７号公報）、セラミック回路基板の積層成形体の表面に、この積層成形体の焼成温度では焼結しないグリーンシートを積層し、焼成後にそれを削り取る拘束焼成法（特開平４−２４３９７８号公報）によって焼成時の収縮を抑制し、寸法精度を高めることが提案されている。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記した加圧焼成法では、Ａｌ2Ｏ3基板等により加圧する必要があり、そのための設備やＡｌ2Ｏ3基板等が必要であった。また、拘束焼成法では、未焼結グリーンシートを除去する工程が必要であり、しかも、除去したグリーンシートは廃棄しなければならず、原料が無駄であった。
【０００６】
従って、本発明は、異なる焼成収縮開始温度を有する複数の絶縁層を同時焼成しても基板の主面（ｘ−ｙ）方向における収縮率を容易にかつ安価に小さくして、回路基板の寸法精度を改善できる回路基板の製法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
本発明のセラミック回路基板の製法は、ＳｉＯ２：１８質量％、ＭｇＯ：４５質量％、Ｂ２Ｏ３：１８質量％と、ＣａＯ：０．４質量％、Ａｌ２Ｏ３ ：０．６質量％、ＢａＯ：１５質量％、ＳｎＯ２ ：１．９質量％、Ｐ２Ｏ３ ：１．０質量％、ＺｒＯ２ ：０．１質量％とを含有する結晶化ガラス粉末を含み低温側から焼成収縮を開始する絶縁層Ａ成形体を形成するとともに、ＳｉＯ２：４４質量％、ＭｇＯ：１８質量％と、ＣａＯ：３３質量％、Ａｌ２Ｏ３ ：４．５質量％、ＺｎＯ：０．１質量％、Ｎａ２Ｏ：０．１質量％、Ｐ２Ｏ３ ：０．１質量％、ＺｒＯ２ ：０．１質量％およびＬｉ２Ｏ：０．１質量％とを含有する結晶化ガラス粉末を含み前記絶縁層Ａ成形体よりも高温側から焼成収縮を開始する絶縁層Ｂ成形体を形成する工程と、前記絶縁層Ａ成形体および前記絶縁層Ｂ成形体の表面および／または内部に所定の導体層パターンを形成する工程と、該導体層パターンが形成された前記絶縁層Ａ成形体および前記絶縁層Ｂ成形体を複数積層して積層成形体を形成する工程と、該積層成形体を、前記絶縁層Ｂ成形体の焼成収縮率が０．１％のとき、前記絶縁層Ａ成形体の焼成収縮が、該絶縁層Ａ成形体が有する最終収縮率の１００％に達するように焼成して、前記積層成形体の主面方向の焼成収縮率を０％にする工程とを具備する製法である。
【００１４】
このような構成によれば、上記の組成のように絶縁層成形体中に複数種の結晶化ガラス粉末を含有させることにより、焼成収縮開始温度、焼成収縮する温度範囲および最終焼成収縮率等の焼成収縮挙動の異なる２種以上の絶縁層成形体を容易に形成でき、絶縁層成形体として低温側で焼成収縮する絶縁層Ａ成形体と高温側とで焼成収縮する絶縁層Ｂ成形体とを積層して用いることにより、両絶縁層の主面（ｘ−ｙ）方向の焼成収縮を抑制できる。
また、このことにより、絶縁層Ａ、Ｂの焼成収縮挙動が異なる場合であっても、層間の接着性が高まりクラックやデラミネーションを防止できる。
そして、同時焼成する際に、Ａｌ ２ Ｏ ３ 基板等により加圧する加圧焼成法に比較して、そのための設備やＡｌ ２ Ｏ ３ 基板等の必要がなく、また、拘束焼成法に比較して、焼成後にこの未焼結グリーンシートを除去する必要が無く、そのための原料を無駄にすることもないことから製造コストを低減できる。
【００１５】
また、積層成形体の主面方向の焼成収縮率を０％とすることにより、低温側絶縁層成形体および高温側絶縁層成形体の相互の拘束力を効果的に発揮させることができ焼成されたセラミック回路基板の反りを抑え、寸法精度を向上できる。
また、このように焼成中の両絶縁層成形体間の焼成収縮率差が大きいほど拘束力が大きくなり、回路基板の最終的な焼成収縮率を容易により小さくでき、寸法精度を高めることができる。
【００１６】
上記セラミック回路基板の製法では、絶縁層Ａ成形体と絶縁層Ｂ成形体との間の焼成収縮開始温度差が１０℃以上であることが望ましい。この製法は、焼成収縮する側の絶縁層を焼成収縮しない方の絶縁層が拘束することにより焼成収縮率を低減することができるものであることから、互いの絶縁層が共に焼成収縮する温度領域が狭いほど収縮の拘束の効果を大きくでき、特に、焼成収縮開始温度差が１０℃以上であれば両絶縁層成形体の焼成収縮挙動を相互に容易に制御できる。
【００１７】
上記セラミック回路基板の製法では、絶縁層Ｂ成形体の焼成収縮率が０．１％のとき、絶縁層Ａ成形体は、該絶縁層Ａ成形体が有する最終収縮率の９０％以上に達していることが望ましい。このように焼成中の両絶縁層成形体間の焼成収縮率差が大きいほど拘束力が大きくなり、回路基板の最終的な焼成収縮率を容易により小さくでき、寸法精度を高めることができる。
【００１８】
【発明の実施の形態】
図１は、セラミック回路基板の一例の概略断面図を示すもので、図１において、セラミック回路基板１０は、絶縁層１ａ〜１ｇが積層された基板１と、この基板１の表裏面および／または内部に形成された導体層３、導体層３間を接続するためのビアホール導体４を有する。
【００１９】
基板１は、収縮開始温度が異なる絶縁層１ａ〜１ｇによって形成され、この図１のセラミック回路基板１０では、絶縁層１ａ〜１ｇのうち、絶縁層Ａ１ａ、１ｇが、他の絶縁層Ｂ１ｂ〜１ｆと焼成収縮開始温度が異なるセラミック材料から形成されている。例えば、絶縁層Ａ１ａ、１ｇの焼成収縮開始温度は絶縁層Ｂ１ｂ〜１ｆよりも低いものである。
【００２０】
この２種の絶縁層１ａ〜１ｇを形成するセラミックスの焼成収縮挙動の概要について、図２の焼成収縮曲線に基づき説明する。図２は焼成収縮挙動の異なるセラミックスの加熱時の収縮曲線であり、横軸は温度、縦軸は収縮率を示す。この収縮曲線によれば、焼成収縮開始温度が異なる２つのセラミックスＡ、Ｂは、それぞれ焼成収縮開始温度ＳA、ＳB（ＳA＜ＳB）、焼成収縮終了温度ＥA、ＥB（ＥA＜ＥB）を有する。図１のセラミック回路基板１０に当てはめると、絶縁層Ａ１ａ、１ｇはセラミックスＡ、絶縁層Ｂ１ｂ〜１ｆはセラミックスＢと当てはめられる。
【００２２】
また、絶縁層Ａ１ａ、１ｇと絶縁層Ｂ１ｂ〜１ｆとの間の熱膨張係数差は２×１０-6／℃以下であることが、両絶縁層Ａ、Ｂ１ａ〜１ｇの熱膨張係数差が小さいほど焼成中および焼成後の反りが抑制されるという理由から望ましく、特に熱膨張係数の差は１×１０-6／℃以下が望ましい。
【００２３】
ここで、セラミック回路基板１０を構成する絶縁層１ａ〜１ｇのうち、絶縁層Ａ１ａ、１ｇに含まれる結晶化ガラスは、ＳｉＯ２：１８質量％、ＭｇＯ：４５質量％、Ｂ２Ｏ３：１８質量％と、ＣａＯ：０．４質量％、Ａｌ２Ｏ３ ：０．６質量％、ＢａＯ：１５質量％、ＳｎＯ２ ：１．９質量％、Ｐ２Ｏ３ ：１．０質量％、ＺｒＯ２ ：０．１質量％とを含有する範囲の組成とされている。
【００２４】
一方、絶縁層Ｂ１ｂ〜１ｆに含まれる結晶化ガラスは、ＳｉＯ２：４４質量％、ＭｇＯ：１８質量％と、ＣａＯ：３３質量％、Ａｌ２Ｏ３ ：４．５質量％、ＺｎＯ：０．１質量％、Ｎａ２Ｏ：０．１質量％、Ｐ２Ｏ３ ：０．１質量％、ＺｒＯ２ ：０．１質量％およびＬｉ２Ｏ：０．１質量％とを含有する範囲の組成とされている。
【００２５】
絶縁層Ａ１ａ、１ｇおよび絶縁層Ｂ１ｂ〜１ｆに含まれるガラス組成を上記のような組成としたのは、これらの絶縁層１ａ〜１ｇの収縮開始温度差を設けかつ焼成温度範囲を異なるものとしつつも最終的な焼成収縮率を同じ値とするためである。
【００２６】
ここで、絶縁層Ａ１ａ、１ｇおよび絶縁層Ｂ１ｂ〜１ｆに含まれるガラス組成の中で、ＭｇＯとＢ2Ｏ3の量を増すことにより、結晶化ガラスの軟化点が低下し、絶縁層Ａの焼成開始温度の低温下を図ることができ、一方、ＳｉＯ2の量を増すことにより、結晶化ガラスの軟化点を高め、これにより焼成開始温度の高温化を図ることができる。
【００２７】
そして、ＭｇＯとＢ２Ｏ３の量は、絶縁層Ｂ１ｂ〜１ｆ中よりも絶縁層Ａ１ａ、１ｇの方が多く、一方、ＳｉＯ２の量は、絶縁層Ａ１ａ、１ｇよりも絶縁層Ｂ１ｂ〜１ｆの方が多くなっている。
【００２８】
また、上記の結晶化ガラスとセラミックフィラーによる組み合わせによれば、絶縁層Ａ１ａ、１ｇおよび絶縁層Ｂ１ｂ〜１ｆ同士の拘束力が高まり、両絶縁層Ａ、Ｂ１ａ〜１ｇが積層された主面方向の焼成収縮率を５％以下とすることができ、また、絶縁層間の接着性が強くなり、反り、剥がれ、デラミネーションを防止できる。そして、基板の寸法精度を高めることができる。
【００２９】
一方、上記以外の組成のガラスの組み合わせでは、絶縁層Ａ１ａ、１ｇおよび絶縁層Ｂ１ｂ〜１ｆ同士の拘束力が弱く、両絶縁層Ａ、Ｂ１ａ〜１ｇが接地された主面方向の焼成収縮率を５％以下とすることが困難であり、絶縁層１ａ〜１ｇ間の接着性が弱くなり、反り、剥がれ、デラミネーションが発生しやすくなる。
【００３０】
また、絶縁層１ａ〜１ｇには、上記ガラス以外に、セラミックフィラーを含有してもよい。用いられるセラミックフィラーとしては、高強度化と理由からＡｌ２Ｏ３が好適に用いられ、上記以外のセラミック粉末を混合して焼成を行うと、ガラスと反応してガラスの熱特性が変化し、その結果焼成収縮挙動が変わり、焼成時の主面（ｘ−ｙ）方向の拘束力が弱くなるからである。
【００３１】
そして、絶縁層Ａ１ａ、１ｇに含まれるセラミックフィラー量は、２０質量％、一方、絶縁層Ｂ１ｂ〜１ｆに含まれるセラミックフィラー量は、３０質量％である。
【００３２】
このように絶縁層Ａ１ａ、１ｇに含まれる結晶化ガラス量を８０質量％、そして、セラミックフィラー量を２０質量％としたのは、絶縁層Ａ１ａ、１ｇの焼結性をさらに向上させるという観点からであり、絶縁層Ａおよび絶縁層Ｂ間において結晶化ガラスに加えて絶縁層に含まれるセラミックフィラー量に差を持たせることにより、両絶縁層の焼成収縮開始温度差をさらに顕著にすることができる。
【００３３】
本発明のセラミック回路基板の製法について具体的に説明する。
【００３４】
先ず、絶縁層Ａ成形体中に含まれる結晶化ガラス粉末の組成は、ＳｉＯ２：１８質量％、ＭｇＯ：４５質量％、Ｂ２Ｏ３：１８質量％と、ＣａＯ：０．４質量％、Ａｌ２Ｏ３ ：０．６質量％、ＢａＯ：１５質量％、ＳｎＯ２ ：１．９質量％、Ｐ２Ｏ３ ：１．０質量％、ＺｒＯ２ ：０．１質量％の範囲の組成とされている。
【００３５】
一方、絶縁層Ｂ成形体中に含まれる結晶化ガラス粉末の組成は、ＳｉＯ２：４４質量％、ＭｇＯ：１８質量％と、ＣａＯ：３３質量％、Ａｌ２Ｏ３ ：４．５質量％、ＺｎＯ：０．１質量％、Ｎａ２Ｏ：０．１質量％、Ｐ２Ｏ３ ：０．１質量％、ＺｒＯ２ ：０．１質量％およびＬｉ２Ｏ：０．１質量％の範囲の組成とされている。
【００３６】
そして、これらの結晶化ガラス粉末とセラミックフィラーとを混合して焼成収縮挙動の異なる２種のセラミック材料を調製し、これら２種のセラミック材料と有機バインダと有機溶剤および必要に応じて可塑剤とを混合しセラミックスラリを調製する。このセラミックスラリを用いてドクターブレード法などによりテープ成形を行い、所定寸法に切断し絶縁層Ａ成形体および絶縁層Ｂ成形体となるセラミックグリーンシートを作製する。
【００３７】
次に、このセラミックグリーンシートにパンチングなどによって貫通孔を形成し、その貫通孔内に導体ペーストを充填したり、表面導体層や内部導体層を導体ペーストを用いてスクリーン印刷法などによって被着形成する。
【００３８】
このようにして得られた各セラミックグリーンシートを所定の積層順序に応じて積層して積層成形体を形成した後、焼成する。
【００３９】
焼成にあたっては、昇温して、セラミックスＡ（絶縁層Ａ）の収縮開始温度ＳＡに達した後、除々に昇温するか、または収縮開始温度ＳＡ、あるいは収縮開始温度ＳＡ以上、セラミックスＢ（絶縁層Ｂ）の収縮開始温度ＳＢよりも低い温度で、一時的に炉内温度を保持してセラミックスＡ（絶縁層Ａ）が最終収縮率の１００％まで焼成が進行するまで保持する。この時、セラミックスＡ（絶縁層Ａ）は、その温度で焼成収縮しないセラミックスＢ（絶縁層Ｂ）によって主面（ｘ−ｙ）方向への収縮が抑制され、Ｚ方向に焼成収縮する。
【００４０】
その後、セラミックスＡ（絶縁層Ａ）が最終収縮率の１００％まで収縮した後、セラミックスＢ（絶縁層Ｂ）の収縮開始温度ＳＢに昇温して焼成する。この焼成によって、セラミックスＢ（絶縁層Ｂ）は、焼結が完了したセラミックスＡ（絶縁層Ａ）によって主面（ｘ−ｙ）方向への焼成収縮が抑制され、Ｚ方向に焼成収縮する。その結果、セラミックスＡ（絶縁層Ａ）およびセラミックスＢ（絶縁層Ｂ）ともに主面（ｘ−ｙ）方向への焼成収縮が抑制され、Ｚ方向に焼成収縮した寸法精度の高い基板を作製することができる。
【００４１】
ここで、絶縁層Ｂ成形体の焼成収縮率が０．１％のとき、絶縁層Ａ成形体は、この絶縁層Ａ成形体が有する最終収縮率の１００％まで収縮が進行していることとしたのは、全体の体積収縮率が１００％未満の場合には主面（ｘ−ｙ）方向の収縮が大きくなり、配線導体の寸法精度が悪くなるからである。ここで、焼成収縮が高温側の絶縁層が０．１％体積収縮するということは、Ｚ方向のみの収縮であってもよい。
【００４２】
また、絶縁層１ａ〜１ｇの収縮開始温度差は１０℃以上、特に２０℃以上であることが望ましい。これは、互いのセラミックスが共に焼成収縮する温度領域が減少するほど収縮の拘束の効果が大きくなるためである。なお、ここでは収縮開始温度とは、絶縁層１ａ〜１ｇが０．１％焼成収縮した時点の温度とし、焼成収縮終了温度とは、焼成収縮が最終焼成体積収縮率の９９％進行した時点の温度を意味する。
【００４３】
尚、本発明のセラミック回路基板１０の製法では、焼成収縮挙動もしくは焼成収縮開始温度、焼成収縮終了温度の異なる材料から形成される絶縁層１ａ〜１ｇが複数積層されており、それらの誘電率は等しくても良いが、目的によっては異なっていても良く、焼成挙動が異なる２種のセラミックスは、例えば、焼成収縮挙動の相違のみならず、目的に応じて比誘電率が異なる、強度が異なる、誘電損失が異なるなどの他の特性が異なっていても良い。
【００４４】
また、焼成収縮挙動が異なる２種のセラミックスＡ−Ｂの積層形態としては、図１では、ＡＢＢＢＢＢＡ、ＡＡＢＡＢＡＡ、ＡＡＢＢＡＡＡ、ＡＢＡＡＡＡＡでもよく、また、ＡとＢとを反対に入れ換えても良い。
【００４５】
【実施例】
表１および表２に示すような、焼成収縮開始温度が異なる絶縁層Ａ、絶縁層Ｂを形成するセラミックスＡとセラミックスＢを形成する材料それぞれに、有機バインダとしてエチルセルロースと、有機溶剤として２・２・４トリメチル３・３ペンタジオールモノイソブチレートを添加してなるスラリを調製し、これをドクターブレード法により薄層化し、基板用のセラミックグリーンシートを作製した。
【００４６】
次に、絶縁層ＢとなるセラミックスＢを含むセラミックグリーンシートの所定の位置にパンチング等により貫通孔を形成し、この貫通孔にＡｇを含む導電性ペーストを充填し、また、この導電性ペーストを用いて、スクリーン印刷により所定の導体層パターンを形成した。
【００４７】
一方、最上層、最下層の絶縁層ＡとなるセラミックスＡを含むセラミックグリーンシートに、表層導体となるＡｇからなる導電性ペーストを用いて所定形状の導体層パターンを印刷形成した。
【００４８】
導電性ペーストが充填され、所定形状の導体層パターンが形成された絶縁層ＢとなるセラミックスＢを含むセラミックグリーンシートを複数積層するとともに、最上層および最下層に、表層導体となる導体膜形成した絶縁層Ａとなるグリーンシートを積層し、積層成形体を作製した。
【００４９】
この後、大気中４００℃で脱バインダ処理し、さらに９１０℃で焼成し、図１に示すようなセラミック回路基板１０を作製した。尚、絶縁層１ａ〜１ｇの厚みは０．１５ｍｍであり、セラミック回路基板１０の大きさは、縦１０ｍｍ、横１０ｍｍ、厚み１．２ｍｍであった。
【００５０】
尚、積層成形体と焼成後のセラミック回路基板１０に対して、所定のポイント間の長さを測定することにより、主面（ｘ−ｙ）方向のセラミック回路基板１０の収縮率を測定した。尚、各試料について１０個の試料を作製し、それぞれの収縮率を測定し、１０個の試料の収縮率の最大収縮率と最小収縮率の差を収縮ばらつきとして評価した。また、基板を研磨して金属顕微鏡を用いて断面を研磨することにより、基板におけるクラック、デラミネーションの有無を評価した。
【００５１】
また、セラミックスＡとセラミックスＢを形成する材料に、ワックスを添加し、圧力１ｔ／ｃｍ2でプレスすることにより圧粉体を形成し、この圧粉体に対して空気中で熱機械分析（ＴＭＡ）による室温〜１０００℃の温度範囲により各セラミックスの焼成収縮開始温度ＳA、ＳB、焼成収縮終了温度ＥA、ＥB熱膨張係数を評価した。
【００５２】
【表１】
【表２】
【表３】
この表３から、表１、２に示した本発明の結晶化ガラス組成を含有する絶縁層Ａの収縮終了温度ＥAと絶縁層Ｂの収縮開始温度ＳBとの差を０℃とした試料Ａでは、（ｘ−ｙ）収縮率が０％となり無収縮基板を作製できた。また、絶縁層Ａおよび絶縁層Ｂの熱膨張差を１．６×１０ー6／℃以下とした試料では焼成におけるクラックやデラミネーションが無かった。
【００５６】
【発明の効果】
本発明によれば、絶縁層として絶縁層Ａと絶縁層Ｂとを積層して、これら複数の絶縁層を一体焼成することにより、基板のｘ−ｙ収縮率が０％のセラミック回路基板を得ることができる。また、前記絶縁層と異種材料絶縁層の間の熱膨張係数差を小さくすることにより、クラックやデラミネーションの生じない基板を得ることができる。
【図面の簡単な説明】
【図１】 セラミック回路基板の概略断面図を示す。
【図２】 焼成収縮挙動が異なるセラミックスＡとセラミックスＢの焼成収縮曲線を示す。
【符号の説明】
１・・・・・・・・・・・・・・・・・基板
１ａ、１ｇ・・・・・・・・・・・・・絶縁層Ａ
１ｂ、１ｃ、１ｄ、１ｅ、１ｆ・・・・絶縁層Ｂ
３・・・・・・・・・・・・・・・・・導体層
１０・・・・・・・・・・・・・・・・セラミック回路基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a process for preparing ceramic circuit board, in particular, it relates to a process for the preparation of ceramic circuit board for improving the co-firing dimensional accuracy a plurality of insulating layers with different firing shrinkage initiation temperature.
[0002]
[Prior art]
Conventionally, in order to reinforce a weak insulating layer with a strong insulating layer or to incorporate a capacitor with a high capacitance value in a circuit board, an insulating layer and a different material insulation made of a material different from this insulating layer are used. A ceramic circuit board in which layers are laminated is known (for example, see Japanese Patent Application Laid-Open No. 59-194493). In such a circuit board, in order to prevent cracking and delamination of porcelain, the materials of the insulating layer and the dissimilar material insulating layer are determined so that the firing shrinkage rate and the thermal expansion coefficient coincide with each other.
[0003]
However, in such a ceramic circuit board, although cracking and delamination can be prevented, since the firing shrinkage rate is large, the dimensional accuracy in the principal surface (xy) direction of the conductor layer formed in the ceramic circuit board is high. There was a problem of lowering. In particular, in recent years, dimensional accuracy in the principal surface (xy) direction of the conductor layer is increasingly required in order to reduce the size and thickness of the ceramic circuit board.
[0004]
Therefore, in recent years, a pressure firing method (Japanese Patent Laid-Open No. Sho 62-260777) in which a multilayer molded body of ceramic circuit boards is sandwiched between Al 2 O 3 substrates and fired, the surface of the multilayer molded body of ceramic circuit boards is disclosed. In addition, the shrinkage at the time of firing is suppressed and the dimensional accuracy is improved by a constrained firing method (Japanese Patent Laid-Open No. Hei 4-243978) that laminates green sheets that are not sintered at the firing temperature of the laminated molded body and scrapes them after firing. Has been proposed.
[0005]
[Problems to be solved by the invention]
However, in the above-mentioned pressure firing method, it is necessary to pressurize with an Al 2 O 3 substrate or the like, and equipment for that purpose, an Al 2 O 3 substrate or the like is required. Further, the restraint firing method requires a step of removing the unsintered green sheet, and the removed green sheet has to be discarded, and the raw material is wasted.
[0006]
Therefore, the present invention makes it possible to easily and inexpensively reduce the shrinkage rate in the principal surface (xy) direction of the substrate even if a plurality of insulating layers having different firing shrinkage start temperatures are simultaneously fired, thereby reducing the dimensions of the circuit board. and to provide a production method of a circuit board capable of improving the accuracy.
[0013]
[Means for Solving the Problems]
The manufacturing method of the ceramic circuit board of the present invention is SiO 2 : 18 % by mass, MgO: 45 % by mass, B 2 O 3 : 18 % by mass, CaO 2 : 0.4% by mass , Al 2 O 3 : 0.6 % by mass. %, BaO : 15% by mass, SnO 2 : 1.9% by mass, P 2 O 3 : 1.0% by mass , ZrO 2 : 0.1% by mass In addition to forming an insulation layer A molded body that starts shrinkage, SiO 2 : 44 mass%, MgO: 18 mass% , C aO : 33 mass% , Al 2 O 3 : 4.5 mass%, ZnO : 0. 1 mass%, Na 2 O: 0.1 wt%, P 2 O 3: 0.1 wt%, ZrO 2: 0.1% by weight and Li 2 O: crystallized glass containing 0.1 wt% Baking shrinkage is started from higher temperature side than the molded body of insulating layer A containing powder Forming an insulating layer B molded body, forming a predetermined conductor layer pattern on and / or inside the insulating layer A molded body and the insulating layer B molded body, and forming the conductor layer pattern. A step of laminating a plurality of the insulating layer A molded body and the insulating layer B molded body to form a laminated molded body; and the laminated molded body having a firing shrinkage ratio of the insulating layer B molded body of 0.1%. When firing shrinkage of the insulating layer A molded body reaches 100% of the final shrinkage rate of the insulating layer A molded body, the firing shrinkage rate in the main surface direction of the laminated molded body is 0% a method comprising the step of the.
[0014]
According to such a configuration, by including a plurality of types of crystallized glass powder in the insulating layer molded body as in the above composition, the firing shrinkage start temperature, the firing shrinkage temperature range, the final firing shrinkage rate, etc. Two or more types of insulating layer molded bodies having different firing shrinkage behavior can be easily formed. As the insulating layer molded body, an insulating layer A molded body that is fired and shrunk on the low temperature side and an insulating layer B molded body that is fired and shrunk on the high temperature side are formed. By stacking and using, it is possible to suppress firing shrinkage in the principal surface (xy) direction of both insulating layers.
Moreover, even if it is a case where the baking shrinkage | contraction behaviors of the insulating layers A and B differ by this, the adhesiveness between layers increases and a crack and delamination can be prevented.
And, compared with the press firing method in which pressurization is performed with an Al 2 O 3 substrate or the like when co-firing , there is no need for equipment or an Al 2 O 3 substrate for that purpose, and in comparison with the restraint firing method. It is not necessary to remove the unsintered green sheet after firing, and the raw material for that purpose is not wasted, so that the manufacturing cost can be reduced.
[0015]
Further, by setting the firing shrinkage rate in the main surface direction of the laminated molded body to 0%, the mutual restraining force of the low temperature side insulating layer molded body and the high temperature side insulating layer molded body can be effectively exhibited and fired. It is possible to suppress warpage of the ceramic circuit board and improve dimensional accuracy.
In addition, the greater the difference in firing shrinkage between the two insulating layer molded bodies during firing, the greater the binding force, the easier the final firing shrinkage of the circuit board can be reduced, and the dimensional accuracy can be increased. .
[0016]
In the manufacturing method of the ceramic circuit board, it is desirable that the difference in firing shrinkage start temperature between the insulating layer A molded body and the insulating layer B molded body is 10 ° C. or more. This manufacturing method is capable of reducing the firing shrinkage rate by constraining the insulating layer on the side to be fired and contracted by the insulating layer that is not fired and contracted. The narrower the effect of restraining the shrinkage, the more the firing shrinkage behavior of both insulating layer molded bodies can be easily controlled with each other if the firing shrinkage start temperature difference is 10 ° C. or more.
[0017]
In the method for producing a ceramic circuit board, when the firing shrinkage rate of the insulating layer B molded body is 0.1%, the insulating layer A molded body reaches 90% or more of the final shrinkage rate of the insulating layer A molded body. It is desirable. Thus, the greater the difference in firing shrinkage between the two insulating layer molded bodies during firing, the greater the restraining force, the smaller the final firing shrinkage of the circuit board, and the higher the dimensional accuracy.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Figure 1 shows a schematic cross-sectional view of an example of a ceramic circuit board, in FIG. 1, the
[0019]
The substrate 1 is formed by insulating layers 1a to 1g having different shrinkage start temperatures. In the
[0020]
An outline of the firing shrinkage behavior of the ceramics forming these two types of insulating layers 1a to 1g will be described based on the firing shrinkage curve of FIG. FIG. 2 is a shrinkage curve during heating of ceramics having different firing shrinkage behavior, where the horizontal axis represents temperature and the vertical axis represents the shrinkage rate. According to this shrinkage curve, the two ceramics A and B having different firing shrinkage temperatures have firing shrinkage start temperatures S A and S B (S A <S B ) and firing shrink end temperatures E A and E B (E A <E B ). When applied to the
[0022]
Further, the difference in thermal expansion coefficient between the insulating layers A1a and 1g and the insulating layers B1b to 1f is 2 × 10 −6 / ° C. or less, so that the difference in thermal expansion coefficient between the two insulating layers A and B1a to 1g is small. It is desirable for the reason that warpage during and after firing is suppressed, and the difference in thermal expansion coefficient is particularly preferably 1 × 10 −6 / ° C. or less.
[0023]
Here, in the insulating layer 1a~1g constituting the
[0024]
On the other hand, crystallized glass contained in the insulating layer B1b~1f is, SiO 2: 44 wt%, MgO: 18 mass%, C aO: 33 wt%, Al 2 O 3: 4.5 wt%, ZnO: 0 .1 wt%, Na 2 O: 0.1 wt%, P 2 O 3: 0.1 wt%, ZrO 2: 0.1% by weight and Li 2 O: range you containing 0.1 wt% The composition of the wall.
[0025]
The reason why the glass compositions contained in the insulating layers A1a and 1g and the insulating layers B1b to 1f are as described above is to provide a shrinkage start temperature difference between these insulating layers 1a to 1g and to make the firing temperature range different. This is because the final firing shrinkage rate is set to the same value.
[0026]
Here, among the glass compositions contained in the insulating layers A1a and 1g and the insulating layers B1b to 1f, increasing the amount of MgO and B 2 O 3 reduces the softening point of the crystallized glass, and the insulating layer A The firing start temperature can be lowered. On the other hand, by increasing the amount of SiO 2 , the softening point of the crystallized glass can be increased, and thereby the firing start temperature can be increased.
[0027]
Then, the amount of MgO and B 2 O 3 is an insulating layer B1b～1f insulating layer A1a than in Trip 1g many, while the amount of SiO 2, the insulating layer A1a, an insulating layer than 1g B1b～1f who is multi-Kuna'.
[0028]
Further, according to the combination of the crystallized glass and the ceramic filler, the binding force between the insulating layers A1a and 1g and the insulating layers B1b to 1f is increased, and the main surface direction in which both the insulating layers A and B1a to 1g are laminated is increased. The firing shrinkage rate can be 5% or less, and the adhesiveness between the insulating layers becomes strong, so that warping, peeling, and delamination can be prevented. And the dimensional accuracy of a board | substrate can be raised.
[0029]
On the other hand, in the combination of glasses having a composition other than the above, the binding force between the insulating layers A1a and 1g and the insulating layers B1b to 1f is weak, and the firing shrinkage rate in the main surface direction where both the insulating layers A and B1a to 1g are grounded. It is difficult to make it 5% or less, the adhesiveness between the insulating layers 1a to 1g becomes weak, and warping, peeling, and delamination tend to occur.
[0030]
In addition, the insulating layers 1a to 1g may contain a ceramic filler in addition to the glass . As the ceramic filler to be used, Al 2 O 3 is suitably used for reasons of high strength, and when ceramic powders other than the above are mixed and fired, the thermal properties of the glass change by reacting with the glass, As a result, the firing shrinkage behavior is changed, and the restraining force in the main surface (xy) direction during firing is weakened.
[0031]
The ceramic filler content in the insulating layer A1a, in 1g is 20 mass%, hand, ceramic filler content in the insulating layer B1b~1f is Ru Ah at 30 wt%.
[0032]
Thus insulating layer A1a, 80 wt% crystallized glass content in the 1g, then was ceramic filler amount is 20% by mass, the insulating layer A1a, from the viewpoint of further improving the sinterability of 1g By making a difference in the amount of ceramic filler contained in the insulating layer in addition to the crystallized glass between the insulating layer A and the insulating layer B, the difference in the firing shrinkage start temperature of both insulating layers can be made more remarkable. I can .
[0033]
The method for producing the ceramic circuit board of the present invention will be specifically described.
[0034]
First , the composition of the crystallized glass powder contained in the insulating layer A molded body is SiO 2 : 18 % by mass, MgO: 45 % by mass, B 2 O 3 : 18 % by mass, CaO 2 : 0.4% by mass , Al 2 O 3 : 0.6% by mass, BaO : 15% by mass, SnO 2 : 1.9% by mass, P 2 O 3 : 1.0% by mass , ZrO 2 : 0.1% by mass Has been.
[0035]
On the other hand, the composition of the crystallized glass powder contained in the insulating layer B compact is as follows: SiO 2 : 44 mass%, MgO: 18 mass% , C aO : 33 mass% , Al 2 O 3 : 4.5 mass%. , ZnO: 0.1 wt%, Na 2 O: 0.1 wt%, P 2 O 3: 0.1 wt%, ZrO 2: 0.1% by weight and Li 2 O: 0.1 wt% range It is said that the composition.
[0036]
These crystallized glass powders and ceramic fillers are mixed to prepare two kinds of ceramic materials having different firing shrinkage behaviors, and these two kinds of ceramic materials, an organic binder, an organic solvent, and a plasticizer as necessary. Are mixed to prepare a ceramic slurry. Using this ceramic slurry, tape molding is performed by a doctor blade method or the like, and the ceramic green sheets are cut into predetermined dimensions to form the insulating layer A molded body and the insulating layer B molded body.
[0037]
Next, a through hole is formed in this ceramic green sheet by punching and the like, and a conductive paste is filled in the through hole, or a surface conductor layer and an internal conductor layer are formed by screen printing using a conductive paste. To do.
[0038]
The ceramic green sheets thus obtained are laminated according to a predetermined lamination order to form a laminated molded body, and then fired.
[0039]
Firing In is heated, after reaching the shrinkage start temperature S A ceramic A (insulating layer A), or heated gradually, or shrinkage starting temperature S A, or shrinkage starting temperature S A above, ceramics At a temperature lower than the shrinkage start temperature S B of B (insulating layer B), the furnace temperature is temporarily held, and the ceramic A (insulating layer A) is held until firing proceeds to 100 % of the final shrinkage rate. To do. At this time, the ceramic A (insulating layer A) is restrained from shrinking in the principal surface (xy) direction by the ceramic B (insulating layer B) that does not fire and shrink at that temperature, and fires and shrinks in the Z direction.
[0040]
Thereafter, ceramics A (insulating layer A) is contracted to 100% of the final shrinkage, calcined by heating to shrink start temperature S B of the ceramic B (insulating layer B). This firing ceramics B (insulating layer B) is, firing shrinkage of the main surface (x-y) direction by ceramics A sintering is complete (insulating layer A) is suppressed, and firing shrinkage in the Z-direction. As a result, both ceramics A (insulating layer A) and ceramics B (insulating layer B) are suppressed from firing shrinkage in the principal surface (xy) direction, and a substrate with high dimensional accuracy is obtained which is fired and shrunk in the Z direction. Can do.
[0041]
Here, when the firing shrinkage rate of the insulating layer B formed body is 0.1%, the insulating layer A molded body that has progressed contracted to 10 0% of the final shrinkage insulating layer A molded body has This is because when the overall volume shrinkage rate is less than 100 %, the shrinkage in the main surface (xy) direction increases, and the dimensional accuracy of the wiring conductor deteriorates. Here, the fact that the insulating layer on the high temperature side shrinks by 0.1% by volume may be shrinkage only in the Z direction .
[0042]
Moreover, the shrinkage start temperature difference of the insulating layers 1a to 1g is preferably 10 ° C. or more, and particularly preferably 20 ° C. or more. This is because the effect of restraining shrinkage increases as the temperature range in which the ceramics are fired and shrunk together decreases. Here, the shrinkage start temperature is the temperature at which the insulating layers 1a to 1g are fired and shrunk by 0.1%, and the firing shrinkage end temperature is the time when the firing shrinkage has progressed 99% of the final fired volume shrinkage rate. It means temperature.
[0043]
In the manufacturing method of the
[0044]
Moreover, as a laminated form of two kinds of ceramics AB having different firing shrinkage behaviors, in FIG. 1, ABBBBBA, AABABAA, AABBAAA, ABAAAAA may be used, and A and B may be interchanged.
[0045]
【Example】
As shown in Table 1 and Table 2, the insulating layer A and the ceramic A forming the insulating layer B having different firing shrinkage start temperatures and the material forming the ceramic B are respectively composed of ethyl cellulose as the organic binder and 2.2 as the organic solvent. A slurry formed by adding 4 trimethyl 3-3 pentadiol monoisobutyrate was prepared, and this was thinned by a doctor blade method to prepare a ceramic green sheet for a substrate.
[0046]
Next, a through-hole is formed by punching or the like at a predetermined position of the ceramic green sheet containing the ceramic B serving as the insulating layer B, and the conductive paste containing Ag is filled in the through-hole. A predetermined conductor layer pattern was formed by screen printing.
[0047]
On the other hand, a conductor layer pattern having a predetermined shape was printed on a ceramic green sheet containing ceramics A to be the uppermost layer and the lowermost insulating layer A by using a conductive paste made of Ag to be a surface layer conductor.
[0048]
A plurality of ceramic green sheets containing ceramic B, which is an insulating layer B filled with a conductive paste and formed with a conductor layer pattern of a predetermined shape, were laminated, and conductor films serving as surface layer conductors were formed on the uppermost layer and the lowermost layer. The green sheet used as the insulating layer A was laminated | stacked and the laminated molded object was produced.
[0049]
Thereafter, the binder removal treatment was performed at 400 ° C. in the atmosphere, followed by firing at 910 ° C., thereby producing a
[0050]
In addition, the shrinkage | contraction rate of the
[0051]
In addition, a green compact is formed by adding wax to the materials forming the ceramics A and B and pressing at a pressure of 1 t / cm 2 , and thermal mechanical analysis (TMA) is performed on the green compacts in air. The firing shrinkage start temperatures S A and S B , firing shrink end temperatures E A and E B thermal expansion coefficients of each ceramic were evaluated in the temperature range from room temperature to 1000 ° C.).
[0052]
[Table 1]
[Table 2]
[Table 3]
From this Table 3, and 0 ℃ the difference between shrinkage starting temperature S B of the insulating layer B and contraction end temperature E A crystallized glass composition for you containing insulation layer A of the present invention shown in Tables 1 and 2 In sample A, the (xy) shrinkage rate was 0%, and a non-shrinkable substrate could be produced. Further, in the sample in which the difference in thermal expansion between the insulating layer A and the insulating layer B was 1.6 × 10 −6 / ° C. or less, there were no cracks or delamination during firing.
[0056]
【The invention's effect】
According to the present invention , the insulating layer A and the insulating layer B are stacked as the insulating layers, and the plurality of insulating layers are integrally fired to obtain a ceramic circuit board having a xy shrinkage of 0%. it is possible. Further, by reducing the difference in thermal expansion coefficient between the insulating layer and the dissimilar material insulating layer, a substrate free from cracks and delamination can be obtained.
[Brief description of the drawings]
1 shows a schematic cross-sectional view of a ceramic circuit board.
[Figure 2] Firing shrinkage behavior indicates sintering shrinkage curve of different ceramic A and ceramic B.
[Explanation of symbols]
1 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Substrate 1a, 1g ・ ・ ・ ・ ・ ・ ・ ・ Insulating layer A
1b, 1c, 1d, 1e, 1f,... Insulating layer B
3 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
Claims (2)
前記絶縁層Ａ成形体および前記絶縁層Ｂ成形体の表面および／または内部に所定の導体層パターンを形成する工程と、
該導体層パターンが形成された前記絶縁層Ａ成形体および前記絶縁層Ｂ成形体を複数積層して積層成形体を形成する工程と、
該積層成形体を、前記絶縁層Ｂ成形体の焼成収縮率が０．１％のとき、前記絶縁層Ａ成形体の焼成収縮が、該絶縁層Ａ成形体が有する最終収縮率の１００％に達するように
焼成して、前記積層成形体の主面方向の焼成収縮率を０％にする工程と
を具備することを特徴とするセラミック回路基板の製法。SiO 2 : 18 % by mass, MgO: 45 % by mass, B 2 O 3 : 18 % by mass, CaO : 0.4% by mass , Al 2 O 3 : 0.6% by mass, BaO : 15% by mass, SnO 2 Insulating layer A molded body containing crystallized glass powder containing 1.9% by mass, P 2 O 3 : 1.0% by mass , ZrO 2 : 0.1% by mass and starting firing shrinkage from the low temperature side and forming, SiO 2: 44 wt%, MgO: 18 wt% and, C aO: 33 wt%, Al 2 O 3: 4.5 wt%, ZnO: 0.1 wt%, Na 2 O: 0. 1 mass%, P 2 O 3: 0.1 wt%, ZrO 2: from the insulating layer comprises a crystallized glass powder containing 0.1 wt% a molded body: 0.1 wt% and Li 2 O Forming an insulating layer B molded body that starts firing shrinkage from the high temperature side,
Forming a predetermined conductor layer pattern on the surface and / or inside of the insulating layer A molded body and the insulating layer B molded body;
A step of forming a laminated molded body by laminating a plurality of the insulating layer A molded body and the insulating layer B molded body on which the conductor layer pattern is formed;
When the firing shrinkage of the insulating layer B compact is 0.1%, the firing shrinkage of the insulating layer A compact is 100% of the final shrinkage of the insulating layer A compact. A method of producing a ceramic circuit board, comprising: firing so as to reach a firing shrinkage ratio of 0% in the principal surface direction of the laminated molded body.
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| JP2001260271A JP4508488B2 (en) | 2001-08-29 | 2001-08-29 | Manufacturing method of ceramic circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4508625B2 (en) * | 2003-12-16 | 2010-07-21 | 京セラ株式会社 | Multilayer substrate and manufacturing method thereof |
| WO2005108327A1 (en) * | 2004-05-06 | 2005-11-17 | Asahi Glass Company, Limited | Method for producing multilayer dielectric body |
| JP4594021B2 (en) * | 2004-09-28 | 2010-12-08 | 京セラ株式会社 | Dielectric ceramic composition, method for producing the same, and wiring board |
| JP4606115B2 (en) * | 2004-10-20 | 2011-01-05 | 京セラ株式会社 | Multilayer substrate and manufacturing method thereof |
| WO2006068121A1 (en) * | 2004-12-20 | 2006-06-29 | Matsushita Electric Industrial Co., Ltd. | Strain sensor and method for manufacture thereof |
| US7687137B2 (en) | 2005-02-28 | 2010-03-30 | Kyocera Corporation | Insulating substrate and manufacturing method therefor, and multilayer wiring board and manufacturing method therefor |
| JP5070723B2 (en) * | 2005-11-04 | 2012-11-14 | 旭硝子株式会社 | Multilayer dielectric and layered dielectric manufacturing method |
| JP4994052B2 (en) * | 2006-03-28 | 2012-08-08 | 京セラ株式会社 | Board and circuit board using the same |
| JP2008085034A (en) * | 2006-09-27 | 2008-04-10 | Kyocera Corp | Wiring substrate |
| JP4869005B2 (en) * | 2006-09-27 | 2012-02-01 | 京セラ株式会社 | Multilayer substrate manufacturing method |
| JP2008109018A (en) * | 2006-10-27 | 2008-05-08 | Kyocera Corp | Wiring board |
| JP2008159940A (en) * | 2006-12-25 | 2008-07-10 | Kyocera Corp | Multi-layer wiring substrate and manufacturing method therefor |
| KR20100014344A (en) | 2007-04-25 | 2010-02-10 | 아사히 가라스 가부시키가이샤 | Method for production of laminated dielectric material |
| JP4784689B2 (en) * | 2008-03-07 | 2011-10-05 | 株式会社村田製作所 | Electronic component and manufacturing method thereof |
| JP6374417B2 (en) * | 2016-01-27 | 2018-08-15 | 日本特殊陶業株式会社 | Aluminum nitride substrate, semiconductor manufacturing component, CVD heater, and aluminum nitride substrate manufacturing method |
| DE102018131605A1 (en) * | 2018-12-10 | 2020-06-10 | Tdk Electronics Ag | Substrate and method of making the substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582963A (en) * | 1985-05-30 | 1993-04-02 | Narumi China Corp | Manufacture of ceramic substrate baked at low temperature |
| JPH07249869A (en) * | 1994-03-08 | 1995-09-26 | Sumitomo Metal Mining Co Ltd | Glass ceramic multilayer circuit board and its manufacture |
| JPH08236936A (en) * | 1995-02-27 | 1996-09-13 | Kyocera Corp | Laminated glass-ceramic circuit board |
| JP2001189555A (en) * | 1999-12-27 | 2001-07-10 | Kyocera Corp | Multilayer substrate |
-
2001
- 2001-08-29 JP JP2001260271A patent/JP4508488B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582963A (en) * | 1985-05-30 | 1993-04-02 | Narumi China Corp | Manufacture of ceramic substrate baked at low temperature |
| JPH07249869A (en) * | 1994-03-08 | 1995-09-26 | Sumitomo Metal Mining Co Ltd | Glass ceramic multilayer circuit board and its manufacture |
| JPH08236936A (en) * | 1995-02-27 | 1996-09-13 | Kyocera Corp | Laminated glass-ceramic circuit board |
| JP2001189555A (en) * | 1999-12-27 | 2001-07-10 | Kyocera Corp | Multilayer substrate |
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