JP4485080B2 - Signal error compensation device - Google Patents

Signal error compensation device Download PDF

Info

Publication number
JP4485080B2
JP4485080B2 JP2001029699A JP2001029699A JP4485080B2 JP 4485080 B2 JP4485080 B2 JP 4485080B2 JP 2001029699 A JP2001029699 A JP 2001029699A JP 2001029699 A JP2001029699 A JP 2001029699A JP 4485080 B2 JP4485080 B2 JP 4485080B2
Authority
JP
Japan
Prior art keywords
phase
signal
amplitude
quadrature
amplifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001029699A
Other languages
Japanese (ja)
Other versions
JP2002232497A (en
Inventor
邦彦 酒井原
頼広 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2001029699A priority Critical patent/JP4485080B2/en
Publication of JP2002232497A publication Critical patent/JP2002232497A/en
Application granted granted Critical
Publication of JP4485080B2 publication Critical patent/JP4485080B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は信号誤差補償装置に係り、特に、複数の位相軸または複数の振幅レベルの各信号に含まれているアナログ的な誤差を補償する信号誤差補償装置に関する。
【0002】
【従来の技術】
携帯電話等で用いられる変調方式には、搬送波の位相を離散的に変化させるPSK(Phase Shift Keying)や搬送波の同相成分と直交成分とを独立に変調するQAM(Quadrature Amplitude Modulation)等がある。例えば、QPSK(Quadrature PSK)は、1シンボル時刻毎に2ビットずつ情報を伝送する4値伝送方式であり、直並列変換を行った後レベル変換を行い、I信号(同相成分)およびQ信号(直交成分)を得る。図3(a)に、本変調方式の信号点配置図を示す。
【0003】
また、搬送波の振幅と位相とを利用して1シンボル時刻毎に4ビットずつ情報を伝送する16QAM(16値QAM)では、同相成分と直交成分をそれぞれ独立に等しい信号間距離で4値変調し、その2つの変調信号を加算することによって変調信号を得ている。図3(b)に、本変調方式の信号点配置図を示す。このような多値変調方式を実現する直交変調器は、直交ベースバンド信号(I,Q信号)を入力として搬送波の位相と振幅を変調することによって変調信号を得ている。例として、図4にQPSKの直交変調器の基本構成を示す。
【0004】
【発明が解決しようとする課題】
なお、通常の直交変調器であれば、出力信号としての変調信号にアナログ的な誤差が含まれている。これらの誤差は設計精度や半導体プロセスの精度等の関係上、直交変調器に限らず直交復調器やその他の回路においてある意味必然的なものであるが、今日では誤差の小さい高精度な直交変調器が求められている。例えば、4値や16値のQAMであれば信号点同士の間隔が広いためある程度の誤差であれば許容できるが、64値や256値のQAMでは信号点同士の間隔が非常に狭いため誤り率が高くなり、少しの振幅誤差(利得誤差)や位相誤差(直交誤差)でも誤判定につながってしまうといった恐れがある。
【0005】
また、直交変調器の誤差は機器毎で異なるため、誤差補償は各機器に対してそれぞれ行う必要があり、例えば、誤差補償の一方式としてデジタル演算がある。しかしながら、直交ベースバンド信号に対して誤差補償のためのデジタル演算を行うと、その分演算負荷が増すため消費電力が増し、クロック速度の高い演算処理手段が必要となり、さらに、演算処理を制御するための時間が必要となるため遅延が発生するという問題点があった。したがって、デジタル演算による誤差補償はできる限り行わない方が望ましい。
【0006】
以上の誤差に関する問題および対策は、直交変換器に限らず直交復調器や複数の位相軸または複数の振幅レベルの信号を扱う機器全般に共通の課題でもある。
【0007】
本発明は、上記従来の事情に鑑みてなされたものであって、複数の位相軸または複数の振幅レベルの各信号に含まれているアナログ的な誤差を補償することのできる信号誤差補償装置を提供することを目的としている。
【0008】
【課題を解決するための手段】
上記課題を解決するために、本発明の請求項1に係る信号誤差補償装置は、直交ベースバンド信号の同相成分および直交成分に含まれている誤差を補償する信号誤差補償装置であって、同相成分の信号を増幅する第1増幅手段と、直交成分の信号を増幅する第2増幅手段と、前記第1増幅手段で増幅された直交ベースバンド信号の同相成分と前記第2増幅手段で増幅された直交ベースバンド信号の直交成分とをマトリクス上で組み合わせることによって、出力信号の振幅または位相を調整する2つの振幅/位相調整手段と、抵抗値を変えることによって、前記振幅/位相調整手段で振幅または位相を調整するための行列の各要素を変更可能な調整抵抗と、を備え、前記2つの振幅/位相調整手段は、前記第1増幅手段の利得、前記第2増幅手段の利得および前記調整抵抗の各抵抗値に基づき決定された行列に応じて誤差が補償された信号の同相成分または直交成分をそれぞれ出力し、前記2つの振幅/位相調整手段から出力された信号の同相成分および直交成分は、それぞれ直交変調器に入力されるものである。
【0009】
また、請求項2に係る信号誤差補償装置は、請求項1に記載の信号誤差補償装置において、前記調整抵抗は、前記第1増幅手段、前記第2増幅手段および前記2つの振幅/位相調整手段とは別に外付けされている。
【0013】
請求項1に係る信号誤差補償装置では、第1増幅手段において直交ベースバンド信号の同相成分を増幅し、第2増幅手段において直交ベースバンド信号の直交成分を増幅し、2つの振幅/位相調整手段において、第1増幅手段で増幅された直交ベースバンド信号の同相成分と第2増幅手段で増幅された直交ベースバンド信号の直交成分とをマトリクス上で組み合わせることによって、出力信号の振幅または位相を調整しており、調整抵抗の抵抗値を変えることによって、振幅/位相調整手段で振幅または位相を調整するための行列の各要素を変更している。2つの振幅/位相調整手段は、第1増幅手段の利得、第1増幅手段の利得および調整抵抗の各抵抗値に基づき決定された行列に応じて誤差が補償された信号の同相成分または直交成分をそれぞれ出力し、前記2つの振幅/位相調整手段から出力された信号の同相成分および直交成分は、それぞれ直交変調器に入力されるため、精度の高い出力信号(I信号,Q信号)を得ることができる
【0014】
さらに、請求項2に係る信号誤差補償装置では、調整抵抗は第1増幅手段、第2増幅手段および2つの振幅/位相調整手段とは別に外付けされている。したがって、製造過程の最終段階でも抵抗値を調整することができ、個々の機器に対して最適な誤差補償をハード的に行うことができる。
【0015】
【発明の実施の形態】
以下、本発明の信号誤差補償装置の実施の形態について、図面を参照して詳細に説明する。
図1は、本発明の一実施形態に係る信号誤差補償装置を示すブロック構成図である。同図において、本実施形態の信号誤差補償装置は、特許請求の範囲の増幅手段または第1増幅手段に該当する第1増幅部11と、増幅手段または第2増幅手段に該当する第2増幅部13と、調整手段に該当する調整抵抗15a〜15fと、振幅/位相調整手段に該当する第1振幅/位相調整部17と、振幅/位相調整手段に該当する第2振幅/位相調整部19とを備えて構成されており、第1振幅/位相調整部17および第2振幅/位相調整部19は直交変調器に接続されている。なお、調整抵抗15a〜15fは抵抗値を変更可能な抵抗である。
【0016】
まず、第1増幅部11は、送信信号を直並列変換して得られた同相成分のI信号(Ii)を利得G1によって所定レベルまで増幅するものである。第1増幅部11の出力信号は、調整抵抗15aを経由して第1振幅/位相調整部17に入力され、調整抵抗15bを経由して第2振幅/位相調整部19に入力される。
【0017】
また、第2増幅部13は、送信信号を直並列変換して得られた直交成分のQ信号(Qi)を利得G2によって所定レベルまで増幅するものである。第2増幅部13の出力信号は、調整抵抗15cを経由して第1振幅/位相調整部17に入力され、調整抵抗15dを経由して第2振幅/位相調整部19に入力される。
【0018】
また、第1振幅/位相調整部17は、調整抵抗15aを経由して入力された第1増幅部11の出力信号および調整抵抗15cを経由して入力された第2増幅部13の出力信号を入力とし、調整抵抗15a,15c,15eの抵抗値Ra,Rc,Reに基づいて利得および位相を調整した後、同相成分としての出力信号(Io)を出力するものである。
【0019】
また、第2振幅/位相調整部19は、調整抵抗15bを経由して入力された第1増幅部11の出力信号および調整抵抗15dを経由して入力された第2増幅部13の出力信号を入力とし、調整抵抗15b,15d,15fの抵抗値Rb,Rd,Rfに基づいて利得および位相を調整した後、直交成分としての出力信号(Qo)を出力するものである。
【0020】
したがって、第1振幅/位相調整部17および第2振幅/位相調整部19から出力される信号Io,Qoは、以下に示す式(1)によって得られる。
【0021】
【数1】

Figure 0004485080
【0022】
したがって、図2(a)に示すように、送信信号を直並列変換して得られたI信号(Ii)の振幅AIとQ信号(Qi)の振幅AQとの関係がAI=cAQ(但し、cは定数)となっており、AI=AQとなるよう振幅誤差(利得誤差)を補償するとき、調整抵抗15a〜15fの抵抗値Ra〜Rfを調節して式(1)に示した行列Mを以下のように設定する。
【0023】
【数2】
Figure 0004485080
【0024】
また、図2(b)に示すように、第1振幅/位相調整部17の出力信号Ioと第2振幅/位相調整部19の出力信号Qoとの間に“90+θ”の位相のずれがあり、位相差が90度となるよう位相誤差(直交誤差)を補償するとき、調整抵抗15a〜15fの抵抗値Ra〜Rfを調節して行列Mを以下のように設定する。
【0025】
【数3】
Figure 0004485080
【0026】
本実施形態において、第1振幅/位相調整部17から出力された出力信号(Io)および第1振幅/位相調整部17から出力された出力信号(Qo)は、それぞれ直交変調器に入力される。また、直交復調器から出力されたI信号およびQ信号が本実施形態の信号誤差補償装置に入力されるといった形態でも良い。
【0027】
また、直交変調器や直交復調器に限定されず、複数の位相軸または複数の振幅レベルの信号を扱う回路等にも本発明に係る信号誤差補償装置を適用することができ、入力信号は2つに限らず、3つ以上でも良い。但し、このときの信号誤差補償装置は入力信号の種類と同数の増幅部および振幅/位相調整部を有し、各振幅/位相調整部には設けられた全増幅部からの出力信号が調整抵抗を経由して入力される。
【0028】
なお、本実施形態の信号誤差補償装置が有する第1増幅部11、第2増幅部13、第1振幅/位相調整部17および第2振幅/位相調整部19はトランジスタやOPアンプ等によって実現され、直交変調器や直交復調器等の回路に組み込まれていることが望ましい。また、調整抵抗15a〜15fは、製造過程の最終段階で抵抗値Ra〜Rfを調整可能なように外付けとされている。さらに、送信信号を直並列変換して得られたI信号(Ii)およびQ信号(Qi)が複数の信号誤差補償装置を経由した後に直交変調器や直交復調器、その他の回路に入力されるようにしても良い。
【0029】
以上説明したように、本実施形態の信号誤差補償装置では、I信号(Ii)およびQ信号(Qi)をそれぞれマトリックス上で組み合わすことによって直交ベースバンド信号の振幅誤差(利得誤差)や位相誤差(直交誤差)を補償することができるため、精度の高いI信号(Io)およびQ信号(Qo)を得ることができる。なお、上述したように、複数の位相軸または複数の振幅レベルの信号に対しても誤差補償することができるため、精度の高い出力信号を得ることができる。
【0030】
また、式(1)に示した行列Mの各要素を調整するための調整抵抗15a〜15fが外付けとされているため、製造過程の最終段階でも抵抗値を調整することができるため、個々の機器に対して最適な誤差補償をハード的に行うことができる。さらに、本実施形態の信号誤差補償装置があれば誤差補償のためのデジタル的な演算処理を行う必要がないため、演算手段に伴う消費電力や演算時間等の問題は生じない。
【0031】
【発明の効果】
以上説明したように、本発明の信号誤差補償装置によれば、増幅手段において、複数の位相軸または複数の振幅レベルの各入力信号をそれぞれ増幅し、振幅/位相調整手段において、増幅手段で増幅された各入力信号を行列上で組み合わせることによって出力信号の振幅または位相を調整しており、調整手段が、振幅/位相調整手段で振幅または位相を調整するための行列の各要素を変更することによって入力信号の誤差を補償している。振幅/位相調整手段は、複数の増幅手段の各利得および調整手段による設定に基づき決定された行列に応じて誤差が補償された信号をそれぞれ出力するため、精度の高い出力信号を得ることができる。
【0032】
また、調整手段は増幅手段および振幅/位相調整手段とは別に外付けされているため、製造過程の最終段階でも抵抗値を調整することができ、個々の機器に対して最適な誤差補償をハード的に行うことができる。
【図面の簡単な説明】
【図1】本発明の一実施形態に係る信号誤差補償装置を示すブロック構成図である。
【図2】直交ベースバンド信号の振幅誤差(a)および位相誤差(b)を示す説明図である。
【図3】QPSKの信号点配置図(a)および16QAMの信号点配置図(b)である。
【図4】QPSKの直交変調器の基本構成を示す構成図である。
【符号の説明】
11 第1増幅部
13 第2増幅部
15a〜15f 調整抵抗
17 第1振幅/位相調整部
19 第2振幅/位相調整部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal error compensator, and more particularly to a signal error compensator that compensates for an analog error included in each signal having a plurality of phase axes or a plurality of amplitude levels.
[0002]
[Prior art]
Modulation methods used in mobile phones and the like include PSK (Phase Shift Keying) that discretely changes the phase of the carrier wave, QAM (Quadrature Amplitude Modulation) that independently modulates the in-phase component and the quadrature component of the carrier wave, and the like. For example, QPSK (Quadrature PSK) is a quaternary transmission system that transmits information by two bits at each symbol time. After performing serial-parallel conversion, level conversion is performed, and an I signal (in-phase component) and a Q signal ( (Orthogonal component). FIG. 3A shows a signal point arrangement diagram of this modulation system.
[0003]
Also, in 16QAM (16-value QAM) that transmits information by 4 bits for each symbol time using the amplitude and phase of the carrier wave, the in-phase component and the quadrature component are each quaternarily modulated at equal signal distances. The modulation signal is obtained by adding the two modulation signals. FIG. 3B shows a signal point arrangement diagram of this modulation system. A quadrature modulator that realizes such a multi-level modulation method obtains a modulated signal by modulating the phase and amplitude of a carrier wave with an orthogonal baseband signal (I, Q signal) as an input. As an example, FIG. 4 shows a basic configuration of a QPSK quadrature modulator.
[0004]
[Problems to be solved by the invention]
In the case of a normal quadrature modulator, an analog error is included in the modulation signal as the output signal. These errors are inevitable in some ways not only in quadrature modulators but also in quadrature demodulators and other circuits due to design accuracy and semiconductor process accuracy. Today, high-precision quadrature modulation with small errors is required. A vessel is required. For example, a 4-level or 16-level QAM allows a certain amount of error because the interval between signal points is wide, but a 64-level or 256-level QAM allows an error rate because the interval between signal points is very narrow. And a slight amplitude error (gain error) or phase error (orthogonal error) may lead to erroneous determination.
[0005]
Further, since the error of the quadrature modulator varies from device to device, it is necessary to perform error compensation for each device. For example, there is a digital calculation as one method of error compensation. However, if digital computation for error compensation is performed on the orthogonal baseband signal, the computation load increases accordingly, so that power consumption increases, and a computation processing means with a high clock speed is required. Further, computation processing is controlled. Therefore, there is a problem that a delay occurs because time is required. Therefore, it is desirable not to perform error compensation by digital calculation as much as possible.
[0006]
The above-mentioned problems and countermeasures related to errors are not limited to the quadrature converter, but are also common problems for all devices that handle quadrature demodulators and signals having a plurality of phase axes or a plurality of amplitude levels.
[0007]
The present invention has been made in view of the above-described conventional circumstances, and is a signal error compensation device capable of compensating for an analog error included in each signal having a plurality of phase axes or a plurality of amplitude levels. It is intended to provide.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a signal error compensation device according to claim 1 of the present invention is a signal error compensation device that compensates for errors contained in an in-phase component and a quadrature component of a quadrature baseband signal. A first amplifying means for amplifying the component signal; a second amplifying means for amplifying the quadrature component signal; and the in-phase component of the quadrature baseband signal amplified by the first amplifying means and the second amplifying means. By combining the orthogonal components of the orthogonal baseband signal on the matrix , two amplitude / phase adjusting means for adjusting the amplitude or phase of the output signal, and changing the resistance value, the amplitude / phase adjusting means changes the amplitude by the amplitude / phase adjusting means. Or an adjustment resistor capable of changing each element of the matrix for adjusting the phase, and the two amplitude / phase adjusting means include the gain of the first amplifying means and the second amplifying means. The outputs respectively the in-phase component or quadrature component of a signal error is compensated in accordance with the gain and the determined based on the resistance value of the adjusting resistor matrix, the signal output from the two amplitude / phase adjusting means phase and quadrature components are it shall be input to the orthogonal modulator.
[0009]
A signal error compensation device according to claim 2 is the signal error compensation device according to claim 1, wherein the adjustment resistor includes the first amplification unit, the second amplification unit, and the two amplitude / phase adjustment units. It is externally attached separately.
[0013]
In the signal error compensating apparatus according to claim 1, the first amplification means amplifies the in-phase component of the quadrature baseband signal, the second amplification means amplifies the quadrature component of the quadrature baseband signal, and two amplitude / phase adjustment means The amplitude or phase of the output signal is adjusted by combining the in-phase component of the quadrature baseband signal amplified by the first amplifying means and the quadrature component of the quadrature baseband signal amplified by the second amplifying means on the matrix Then, by changing the resistance value of the adjusting resistor, each element of the matrix for adjusting the amplitude or the phase is changed by the amplitude / phase adjusting means. The two amplitude / phase adjusting means include an in-phase component or a quadrature component of a signal in which an error is compensated according to a matrix determined based on the gain of the first amplifying means, the gain of the first amplifying means, and the resistance values of the adjusting resistors. the outputs respectively, in-phase and quadrature components of the signal output from the two amplitude / phase adjusting means is obtained because the input to the orthogonal modulator, accurate output signal (I signal, Q signal) of it is possible.
[0014]
Further, in the signal error compensating apparatus according to claim 2 , the adjusting resistor is externally attached separately from the first amplifying means, the second amplifying means, and the two amplitude / phase adjusting means. Therefore, the resistance value can be adjusted even in the final stage of the manufacturing process, and optimal error compensation can be performed in hardware for each device.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a signal error compensating apparatus of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a signal error compensating apparatus according to an embodiment of the present invention. In the figure, the signal error compensation device of the present embodiment includes a first amplifying unit 11 corresponding to the amplifying unit or the first amplifying unit and a second amplifying unit corresponding to the amplifying unit or the second amplifying unit. 13, adjustment resistors 15a to 15f corresponding to the adjustment means, a first amplitude / phase adjustment section 17 corresponding to the amplitude / phase adjustment means, and a second amplitude / phase adjustment section 19 corresponding to the amplitude / phase adjustment means The first amplitude / phase adjustment unit 17 and the second amplitude / phase adjustment unit 19 are connected to a quadrature modulator. The adjustment resistors 15a to 15f are resistors whose resistance values can be changed.
[0016]
First, the first amplifying unit 11 amplifies an in-phase component I signal (Ii) obtained by serial-parallel conversion of a transmission signal to a predetermined level by a gain G 1 . The output signal of the first amplifying unit 11 is input to the first amplitude / phase adjusting unit 17 via the adjusting resistor 15a, and is input to the second amplitude / phase adjusting unit 19 via the adjusting resistor 15b.
[0017]
The second amplifying section 13 is for amplifying the Q signal of the quadrature component obtained transmission signal to serial-parallel convert the (Qi) to a predetermined level by the gain G 2. The output signal of the second amplification unit 13 is input to the first amplitude / phase adjustment unit 17 via the adjustment resistor 15c, and is input to the second amplitude / phase adjustment unit 19 via the adjustment resistor 15d.
[0018]
The first amplitude / phase adjustment unit 17 receives the output signal of the first amplification unit 11 input via the adjustment resistor 15a and the output signal of the second amplification unit 13 input via the adjustment resistor 15c. As an input, after adjusting the gain and phase based on the resistance values Ra, Rc, Re of the adjustment resistors 15a, 15c, 15e, an output signal (Io) as an in-phase component is output.
[0019]
In addition, the second amplitude / phase adjustment unit 19 receives the output signal of the first amplification unit 11 input via the adjustment resistor 15b and the output signal of the second amplification unit 13 input via the adjustment resistor 15d. As an input, after adjusting the gain and phase based on the resistance values Rb, Rd, Rf of the adjustment resistors 15b, 15d, 15f, an output signal (Qo) as a quadrature component is output.
[0020]
Therefore, the signals Io and Qo output from the first amplitude / phase adjusting unit 17 and the second amplitude / phase adjusting unit 19 are obtained by the following equation (1).
[0021]
[Expression 1]
Figure 0004485080
[0022]
Accordingly, as shown in FIG. 2 (a), the relationship between the amplitude A Q is A I = cA amplitude A I and Q signals of the I signal obtained transmission signal to serial-parallel conversion (Ii) (Qi) Q (where c is a constant), and when the amplitude error (gain error) is compensated so that A I = A Q , the resistance values Ra to Rf of the adjustment resistors 15a to 15f are adjusted to obtain the formula (1 ) Is set as follows.
[0023]
[Expression 2]
Figure 0004485080
[0024]
Further, as shown in FIG. 2B, there is a phase shift of “90 + θ” between the output signal Io of the first amplitude / phase adjustment unit 17 and the output signal Qo of the second amplitude / phase adjustment unit 19. When the phase error (orthogonal error) is compensated so that the phase difference becomes 90 degrees, the matrix M is set as follows by adjusting the resistance values Ra to Rf of the adjustment resistors 15a to 15f.
[0025]
[Equation 3]
Figure 0004485080
[0026]
In the present embodiment, the output signal (Io) output from the first amplitude / phase adjustment unit 17 and the output signal (Qo) output from the first amplitude / phase adjustment unit 17 are respectively input to the quadrature modulator. . Further, the I signal and the Q signal output from the quadrature demodulator may be input to the signal error compensator of this embodiment.
[0027]
Further, the signal error compensation apparatus according to the present invention can be applied to a circuit that handles signals having a plurality of phase axes or a plurality of amplitude levels without being limited to a quadrature modulator or a quadrature demodulator. It is not limited to three, but may be three or more. However, the signal error compensator at this time has the same number of amplification units and amplitude / phase adjustment units as the types of input signals, and output signals from all amplification units provided in each amplitude / phase adjustment unit are adjusted resistors. Is entered via.
[0028]
The first amplifying unit 11, the second amplifying unit 13, the first amplitude / phase adjusting unit 17 and the second amplitude / phase adjusting unit 19 included in the signal error compensating apparatus according to the present embodiment are realized by a transistor, an OP amplifier, or the like. It is desirable to be incorporated in a circuit such as a quadrature modulator or a quadrature demodulator. The adjustment resistors 15a to 15f are externally attached so that the resistance values Ra to Rf can be adjusted in the final stage of the manufacturing process. Further, the I signal (Ii) and the Q signal (Qi) obtained by serial-parallel conversion of the transmission signal are input to a quadrature modulator, a quadrature demodulator, and other circuits after passing through a plurality of signal error compensation devices. You may do it.
[0029]
As described above, in the signal error compensator of this embodiment, the amplitude error (gain error) or phase error of the orthogonal baseband signal is obtained by combining the I signal (Ii) and the Q signal (Qi) on the matrix. Since (orthogonal error) can be compensated, an I signal (Io) and a Q signal (Qo) with high accuracy can be obtained. Note that, as described above, errors can be compensated for signals having a plurality of phase axes or a plurality of amplitude levels, so that an output signal with high accuracy can be obtained.
[0030]
In addition, since the adjustment resistors 15a to 15f for adjusting each element of the matrix M shown in the equation (1) are externally attached, the resistance value can be adjusted even in the final stage of the manufacturing process. It is possible to perform an optimal error compensation for hardware of hardware. Furthermore, since there is no need to perform digital arithmetic processing for error compensation with the signal error compensator of this embodiment, problems such as power consumption and arithmetic time associated with the arithmetic means do not occur.
[0031]
【The invention's effect】
As described above, according to the signal error compensation device of the present invention, the amplification means amplifies each input signal having a plurality of phase axes or a plurality of amplitude levels, and the amplitude / phase adjustment means amplifies by the amplification means. The amplitude or phase of the output signal is adjusted by combining each input signal on the matrix, and the adjusting means changes each element of the matrix for adjusting the amplitude or phase by the amplitude / phase adjusting means Thus, the error of the input signal is compensated. The amplitude / phase adjusting means outputs a signal in which an error is compensated according to each gain determined by the gains of the plurality of amplifying means and a matrix determined based on the setting by the adjusting means, so that a highly accurate output signal can be obtained. .
[0032]
In addition, since the adjusting means is externally attached separately from the amplifying means and the amplitude / phase adjusting means, the resistance value can be adjusted even in the final stage of the manufacturing process. Can be done automatically.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a signal error compensating apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing an amplitude error (a) and a phase error (b) of an orthogonal baseband signal.
FIG. 3 is a signal point arrangement diagram (a) of QPSK and a signal point arrangement diagram (b) of 16QAM.
FIG. 4 is a configuration diagram showing a basic configuration of a QPSK quadrature modulator.
[Explanation of symbols]
11 1st amplification part 13 2nd amplification part 15a-15f Adjustment resistance 17 1st amplitude / phase adjustment part 19 2nd amplitude / phase adjustment part

Claims (2)

直交ベースバンド信号の同相成分および直交成分に含まれている誤差を補償する信号誤差補償装置であって、
同相成分の信号を増幅する第1増幅手段と、
直交成分の信号を増幅する第2増幅手段と、
前記第1増幅手段で増幅された直交ベースバンド信号の同相成分と前記第2増幅手段で増幅された直交ベースバンド信号の直交成分とをマトリクス上で組み合わせることによって、出力信号の振幅または位相を調整する2つの振幅/位相調整手段と、
抵抗値を変えることによって、前記振幅/位相調整手段で振幅または位相を調整するための行列の各要素を変更可能な調整抵抗と、を備え、
前記2つの振幅/位相調整手段は、前記第1増幅手段の利得、前記第2増幅手段の利得および前記調整抵抗の各抵抗値に基づき決定された行列に応じて誤差が補償された信号の同相成分または直交成分をそれぞれ出力し、
前記2つの振幅/位相調整手段から出力された信号の同相成分および直交成分は、それぞれ直交変調器に入力されることを特徴とする信号誤差補償装置。
A signal error compensator that compensates for errors contained in in-phase and quadrature components of a quadrature baseband signal,
First amplifying means for amplifying the signal of the in-phase component;
A second amplifying means for amplifying the signal of the orthogonal component;
The amplitude or phase of the output signal is adjusted by combining the in-phase component of the quadrature baseband signal amplified by the first amplifying unit and the quadrature component of the quadrature baseband signal amplified by the second amplifying unit on a matrix. Two amplitude / phase adjusting means for
An adjustment resistor capable of changing each element of a matrix for adjusting the amplitude or phase by the amplitude / phase adjustment means by changing a resistance value,
The two amplitude / phase adjusting means are configured to provide an in-phase signal whose error is compensated according to a matrix determined based on a gain of the first amplifying means, a gain of the second amplifying means, and resistance values of the adjusting resistors. Output each component or quadrature component ,
Phase and quadrature components of the signal output from the two amplitude / phase adjusting means is input to the orthogonal modulator signal error compensating apparatus according to claim Rukoto.
前記調整抵抗は、前記第1増幅手段、前記第2増幅手段および前記2つの振幅/位相調整手段とは別に外付けされていることを特徴とする請求項1記載の信号誤差補償装置。  2. The signal error compensator according to claim 1, wherein the adjustment resistor is externally attached separately from the first amplification unit, the second amplification unit, and the two amplitude / phase adjustment units.
JP2001029699A 2001-02-06 2001-02-06 Signal error compensation device Expired - Fee Related JP4485080B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001029699A JP4485080B2 (en) 2001-02-06 2001-02-06 Signal error compensation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001029699A JP4485080B2 (en) 2001-02-06 2001-02-06 Signal error compensation device

Publications (2)

Publication Number Publication Date
JP2002232497A JP2002232497A (en) 2002-08-16
JP4485080B2 true JP4485080B2 (en) 2010-06-16

Family

ID=18894011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001029699A Expired - Fee Related JP4485080B2 (en) 2001-02-06 2001-02-06 Signal error compensation device

Country Status (1)

Country Link
JP (1) JP4485080B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3984965B2 (en) 2004-02-25 2007-10-03 株式会社日立コミュニケーションテクノロジー COMMUNICATION TERMINAL DEVICE, COMMUNICATION CONNECTION DEVICE, AND COMMUNICATION METHOD USING THE SAME
JP5104561B2 (en) * 2008-06-05 2012-12-19 富士通株式会社 Quadrature signal output circuit

Also Published As

Publication number Publication date
JP2002232497A (en) 2002-08-16

Similar Documents

Publication Publication Date Title
TWI417560B (en) Testing apparatus and digital modulator, digital demodulator of digital modulation signal, and semiconductor devices applying the same
JP3169803B2 (en) Nonlinear compensation circuit of power amplifier
US7881401B2 (en) Transmitter arrangement and signal processing method
ES2282634T3 (en) COMPENSATION OF THE INCREASED UNBALANCE OF A SQUARE MODULATOR.
CN101167243B (en) Polar coordinate modulating circuit, integrated circuit and radio apparatus
TWI513251B (en) Transmitter with pre-distortion module and a method thereof
US20050215206A1 (en) Multimodulation transmitter
US20050226340A1 (en) Electromagnetic wave transmitter, receiver and transceiver systems, methods and articles of manufacturre
US20050018790A1 (en) Electromagnetic wave transmitter, receiver and transceiver systems, methods and articles of manufacture
AU764136B2 (en) Amplitude calculation circuit
JP3537988B2 (en) Wireless transmitter
US7221915B2 (en) Electromagnetic wave transmitter, receiver and transceiver systems, methods and articles of manufacture
JP2002135349A (en) Pre-distortion type distortion compensation circuit
US6870435B2 (en) Electromagnetic wave transmitter, receiver and transceiver systems, methods and articles of manufacture
JP4485080B2 (en) Signal error compensation device
US7346100B2 (en) Estimating gain and phase imbalance in upconverting transmitters
US7362820B2 (en) Apparatus and method for modulating and digitally predistorting a signal in a multiple modulation schemes
JP3144649B2 (en) Distortion compensated quadrature modulator
EP2547059B1 (en) Transmitter including calibration of an in-phase/Quadrature (I/Q) modulator and associated methods
US20060195284A1 (en) Signal processing device, use of the signal processing device and method for signal processing
JP3301287B2 (en) Linear compensation circuit
JPS63121326A (en) Transmitter
JPH11196140A (en) Power amplifier
JPH11261660A (en) Transmission device having aperture characteristic correction circuit
JP4803379B2 (en) Wireless transmission device with quadrature modulator

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060324

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070215

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20071114

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20071121

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20071128

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20071205

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20071212

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090529

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090623

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090821

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20091006

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091225

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100122

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100223

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100324

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130402

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130402

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140402

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees