JP4476053B2 - Program and storage medium - Google Patents

Description

The present invention is a program for realizing the test bench system, and to a storage medium that stores the program.

  As for a test bench system for a circuit to be designed, a technique disclosed in Patent Document 1 is known.

JP 2002-230073 A

  In a circuit for encoding and decoding an image using JPEG or the like, or in a manufacturing process of an image processing circuit, the operation is verified using an algorithm described in a C language base as an expected value.

  However, in recent years, with the high integration of LSIs, the number of algorithms mounted on one LSI has increased, and the number of data path branches has increased, so the number of functional verification steps has increased. Therefore, it is desirable to facilitate verification of an LSI mounted with such an algorithm and improve circuit productivity.

  On the other hand, in the technique disclosed in Patent Document 1, since it is assumed that the data output by the circuit to be verified is output to a file for visual recognition, it is impossible to deny the occurrence of a human error due to visual verification. Therefore, there is a problem that the verification accuracy is low and the productivity is insufficient.

  An object of the present invention is to prevent the occurrence of a human error and improve productivity particularly in verification of a circuit such as an LSI mounted with an algorithm.

  Another problem will be described. Each component of a test bench system whose circuit is to be verified, such as an ASIC (Application Specified IC), can be easily converted into a part and reused to facilitate the construction of a new test bench. Focusing on the bus function model connected to the circuit to be verified, this bus function model inputs data to the circuit to be verified and expects that data output from the circuit to be verified is prepared in advance. Has the function to compare with the value. Since the input data and the expected value data vary depending on the situation, the buffer for buffering these data is defined as an independent component.

  This buffer has an application interface (for example, READ or CHECK) for reading data and comparing it with the expected value of the output data. By using an address as an argument in the read interface, the data at the corresponding address is read. In the expected value comparison interface, the address is compared with the expected value by using the data output from the circuit to be verified as an argument.

  Here, when the circuit to be verified has multiple data channels and data is transferred via a single interface such as a PCI bus, the bus function model switches access to multiple buffers for each data channel. It will be necessary.

  Another object of the present invention is to make a plurality of buffers appear as if they are one buffer from the bus function model, and by switching the buffer that is actually accessed in response to the access from the bus function model, It is to improve reusability.

The present invention provides means for realizing a CPU interface model which is a bus function model corresponding to a CPU interface of a target circuit, and a first buffer for buffering data input to the circuit by the CPU interface model. Means for realizing the storage device, and means for realizing a data input interface model for inputting the data buffered by the first buffer to the circuit, the bus function model corresponding to the data input interface of the circuit Means for realizing a second buffer for buffering an expected value of data output from the circuit in a predetermined storage device, and a bus function model corresponding to the data output interface of the circuit, and outputting from the circuit Was A data output interface model for comparing data to an expected value for the data buffered in the second buffer, and switching access to the first and second buffers according to conditions A computer-readable program that causes a computer to execute buffer switching means .

According to the present invention, the data obtained from the circuit and the expected value of the data buffered in the second buffer are automatically compared by the data output interface model. Human error does not occur, so it is possible to improve verification accuracy and productivity , and the buffer switching means appears as a single buffer from the bus function model, so that the bus function model has multiple buffers, That is, since the buffered data can be accessed without being aware of the first buffer and the second buffer, the reusability of the bus function model as the test bench component is improved .

  The best mode for carrying out the present invention will be described.

  FIG. 1 is a functional block diagram of a test bench system 1 according to the present embodiment.

  The circuit 2 to be a test bench executed by the test bench system 1 includes a data input / data output interface and a CPU interface for accessing an internal register of the circuit 2. The test bench system 1 includes a bus function model corresponding to these interfaces. That is, a data input interface model 3 which is a bus function model corresponding to the data input interface, a data output interface model 4 which is a bus function model corresponding to the data output interface, and a CPU interface model 5 which is a bus function model corresponding to the CPU interface. It is.

  The data input interface model 3 has a function of executing, responding to, and monitoring a protocol with the circuit 2, reading data from the input data buffer 6 serving as a first buffer, and inputting the data to the circuit 2.

  The data output interface model 4 executes, responds to, and monitors a protocol with the circuit 2, captures data output from the circuit 2, and compares the content of the expected value data buffer with the expected value.

  The CPU interface model 5 executes, responds to, and monitors a protocol with the circuit 2 according to an instruction of a predetermined test scenario 8 and performs read / write access to an internal register in the circuit 2.

  Here, in the test scenario 8, in addition to executing the register access to the CPU interface model 5 as described above, the data input interface model 3 and the data output interface model 4 are connected to the circuit 2 by the bus master (the protocol is executed by itself). In the case of having a role of “Yes”, execution of the protocol is instructed to these interface models at a predetermined timing.

  The input data buffer 6 and the expected value data buffer 7 serving as the second buffer are each provided with an area for storing data, and means for supplying data from the external data file 9, input data to the external data file 9 Means for storing the buffered contents of the buffer 6 and the expected value data buffer 7 are provided. These means can be executed by an instruction from the test scenario 8.

  The input data buffer 6 and the expected value data buffer 7 have means for accessing the internal data, address type access means for accessing by specifying an address, and access from the head of each of the buffers 6 and 7 without specifying the address. FIFO (First In First Out) type access means. These means are used by the data input interface model 3 and the data output interface model 4.

  The sizes of the input data buffer 6 and the expected value data buffer 7 and the start address in the case of the address type access described above are set by the test scenario 8. The input data buffer 6 and the expected value data buffer 7 count data accesses, report data access overruns, multiple accesses of the same address (only in the case of address type access) as needed, and after the test is completed, unaccessed parts If there is, report this.

  Such a test bench system 1 is input to an HDL (hardware description language) simulator together with the circuit 2 and a simulation is executed. In the test bench system 1, input data to the circuit 2 and expected value data are supplied by the data file 9, and the expected value verification is automatically executed during the simulation.

  Next, the process executed by the test bench system 1 will be described by taking as an example the case where the test bench of the circuit 2 for color conversion from RGB to CMYK is performed.

  FIG. 2 is a functional block diagram of the test bench system 1 in this case. The data input interface model 3 operates as a master, reads data from an input data buffer 6 having three channels (corresponding to R, G, and B colors, respectively), and sends the data to a design target circuit (RGB-CMYK converter) 2. input.

  The data output interface model 4 responds to the output of the RGB-CMYK converter 2 as a slave, and outputs the output data by an expected value data buffer 7 having four channels (corresponding to C, M, Y, and K colors, respectively). Perform expected value verification.

  FIG. 3 is an example of a timing diagram viewed from the master (input data buffer) 6 side of the data interface of the RGB-CMYK converter 2. Frame indicates a page valid period, lstart indicates a line start pulse, and both are output from the master 6 side. When the data output is ready, the master 6 asserts txrdy and outputs data to data. If the rxrdy signal from the slave side is asserted while txrdy is asserted, transfer is established. The data interface is a FIFO type having no address.

  FIG. 4 is a communication sequence diagram showing a test bench execution sequence in this case. First, in the test scenario 8, after the size of each input data buffer 6 is set, reading of an input file is instructed (1). The size of the expected value data buffer 7 is similarly set, and an instruction to read an expected value file created in advance is given (2).

  Subsequently, in the test scenario 8, in order to set parameters (image size, conversion parameter, etc.) in the internal register of the RGB-CMYK converter which is the circuit 2, the CPU interface model 5 is written to the internal register of the circuit 2. Instruct (3). The CPU interface model 5 sets the internal register of the RGB-CMYK converter 2 according to a predetermined protocol (4).

  In the test scenario 8, a transfer start instruction is issued to the data input interface model 3 (5), and image data transfer starts.

  The data input interface model 3 reads the data of the minimum transaction unit from the input data buffer 6 (6) and inputs it to the RGB-CMYK converter 2 (7). Thereafter, this is repeated for a predetermined size.

  On the other hand, on the data output interface model 4 side, the RGB-CMYK converter 2 serves as the master 6 to capture the output data (8), and instructs the expected value data buffer 7 to compare the expected value (9). . This is repeated as long as the RGB-CMYK converter 2 outputs data.

  In addition, when there is no data to access while accessing each data buffer 6 or 7 (overrun), the data buffer 6 or 7 reports an error to the interface 3 or 4 and stops the simulation.

  After receiving the last data from the RGB-CMYK converter 2, the data output interface model 4 notifies the test scenario 8 of the end of the process (10). In the test scenario 8, upon receiving this end notification, the input data buffer 6 and the expected value data buffer 7 are checked for unaccess (11) and (12). If data that has not been accessed still remains, Notifies the error and stops the simulation.

  Next, another embodiment of the test bench system 1 will be described.

  FIG. 5 is a functional block diagram of the test bench system 1. In the following description, the same components as those in the test bench system 1 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  The test bench system 1 is different from the above-described example in that the test bench system 1 includes an expected value generation unit 10 that reads data from the input data buffer 6, generates an expected value by executing an algorithm, and outputs the expected value to the expected value data buffer 7. It is that you are. Therefore, in this example, data exchange between the expected value data buffer 7 and the data file 9 is not necessary. This algorithm uses a C language algorithm created in the previous process of circuit design of the circuit 2.

  In the test bench system 1, the expected value is automatically generated from the input data to the circuit 2, so that it is not necessary to prepare the expected value in an external data file as in the above example.

  As a specific example of the test bench system 1, a test bench of a circuit 2 having a PCI input interface and performing JPEG decoding will be described. FIG. 6 is a functional block diagram of the test bench system 1 in this case. In FIG. 6, the data input interface model 3 operates as a PCI slave, and the input data buffer 6 has one channel (JPEG input). The data output interface model 4 operates as a slave model similar to the above example. The expected value data buffer 7 has three channels corresponding to each color of RGB after JPEG decoding (however, only one channel is used in the case of gray scale).

  The expected value generation unit 10 is equipped with a JPEG decoding algorithm, reads data from the input data buffer 6, and writes the decoded R, G, B data (or gray scale data) into the expected value data buffer 7.

  The input data buffer 6 corresponds to PCI address type access.

  FIG. 7 is a communication sequence diagram of processing executed by the test bench system 1. In FIG. 7, the processing with the same reference numerals as in FIG. 4 is the same as in the case of FIG. The processing of FIG. 7 differs from the processing of FIG. 4 in that after the processing of (1), the expected value generation unit 10 is instructed to generate expected values (13), and the generated expected values are read to the input data buffer 6. (14) Write to the expected value data buffer 7 (15). Accordingly, the process (2) described above is not performed.

  Since the data input interface model 3 operates as a PCI slave, the test scenario 8 does not instruct the data input interface model 3 to start transfer. In this example, it is assumed that a transfer start control register is provided in the internal register of the circuit to be designed (JPEG decoder) 2 and transfer is started by the register.

  Further, in this example, since the address type access is performed for data input, the input data buffer 6 also checks for overlapping access addresses. When the address is duplicated, the simulation is stopped by reporting to the user interface at any time.

  Still another embodiment of the test bench system 1 will be described.

  FIG. 8 is a functional block diagram of the test bench system 1. In the following description, the same components as those in the test bench system 1 of FIG. 5 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  The test bench system 1 is different from the example of FIG. 5 described above in that a plurality of the expected value generation units 10 described above are prepared (two in this example (expected value generation units 10a and 10b)), and the image processing algorithm is continued. It is to generate an expected value by executing an operation, and to target a plurality of circuits 2, in this example, two circuits 2 (circuits 2a and 2b).

  The circuit 2 in the present embodiment includes a JPEG decoder (circuit 2a) described with reference to FIG. 5 before the RGB-CMYK converter (circuit 2b) in the embodiment described with reference to FIG. It is configured to connect. The test bench system 1 includes an expected value generation unit 10a that supports JPEG decoding and an expected value generation unit 10b that supports RGB-CMYK conversion.

  As shown in FIG. 9, the expected value generation unit 10 a has an input data buffer 6 as an input, and an expected value generation unit 10 b is connected to the subsequent stage. The expected value generation unit 10 b is connected to the expected value data buffer 7. The expected value generation unit 10a can create a temporary output buffer 10a1.

  FIG. 10 is a flowchart of processing executed by the connected expected value generation units 10a and 10b.

  First, the test scenario 8 instructs the expected value generation unit 10b at the last stage of the connected expected value generation units 10a and 10b to execute generation of expected values. Then, the process of FIG. 10 starts. First, the expected value generation unit 10a in the previous stage creates the temporary output buffer 10a1 (step S1). Next, the expected value generation unit 10a executes the algorithm (JPEG decoding in this example) (step S2). Here, data is read from the input data buffer 6, and the calculation result is output to the temporary output buffer 10a1.

  Then, the expected value generation unit 10b at the subsequent stage executes the algorithm (in this example, RGB-CMYK conversion) (step S3). Here, data is read from the temporary output buffer 10a1 of the expected value generation unit 10a at the previous stage and executed, and the calculation result is output to the expected value data buffer 7. Finally, the temporary output buffer 10a1 of the previous expected value generation unit 10a that is no longer necessary is deleted (step S4), and the series of processing ends. In this way, the expected value can be generated by connecting the expected value generators 10a and 10b between the input data buffer 6 and the expected value data buffer 7. The processing performed using the expected value is the same as that in the embodiment shown in FIGS.

  Finally, a hardware configuration example of the test bench system 1 according to each of the above-described embodiments will be described.

  FIG. 11 is a block diagram of electrical connection of the test bench system 1. As shown in FIG. 11, the test bench system 1 is realized by a computer such as a workstation. The computer performs various operations and centrally controls each unit of the image processing apparatus, and various ROMs and RAMs. The memory 212 is connected by a bus 213.

  The bus 213 is connected to a magnetic storage device 214 such as a hard disk, an input device 215 such as a keyboard and a mouse, and a display device 216 via a predetermined interface, and a predetermined communication for communicating with the network 201. An interface 219 is connected. As the storage medium 217, various media such as an optical disk such as a CD and a DVD, a magneto-optical disk, and a flexible disk can be used. As the storage medium reading device 218, specifically, an optical disk device, a magneto-optical disk device, a flexible disk device, or the like is used according to the type of the storage medium 217.

  The test bench system 1 becomes operable by reading the program 220 for executing the program of the present invention from the storage medium 217 for implementing the storage medium of the present invention and installing it in the magnetic storage device 214. These programs 20 may be downloaded and installed via a network 201 such as the Internet. Note that the program 220 may operate on a predetermined OS.

  The bus 213 is connected to the circuit 2 via a predetermined interface 221. The CPU interface model 3, the data input interface model 4, the data output interface model 5, and the expected value generation unit 10 (or the expected value generation units 10a and 10b) are constructed by processing executed by the CPU 211 based on the program 220. The input buffer 6 and the expected value buffer 7 are prepared in a storage device such as a RAM of the memory 212, and the various processes described above are executed.

  Another embodiment will be described.

  FIG. 12 is an explanatory diagram of a configuration of the test bench system 101 according to the present embodiment. The circuit 102 to be verified in the test bench system 101 of this embodiment is an ASIC, which is mounted on a color copying machine, a color printer, and the like, and is C (cyan), M (magenta), Y (yellow), K (black). ) To perform predetermined processing on the image data of each color. The circuit 102 includes a CMYK data processing unit 103 that executes the predetermined processing, and a PCI controller 104 that interfaces the CMYK data processing unit 103 and a PCI bus 105 described later. In an actual machine such as a color copying machine or a color printer, a memory controller is present beyond the PCI bus 105 connected to the circuit 102, and each plane of image data of each color of CMYK is accessed via this memory controller.

  On the test bench system 101, the bus function model 106 is connected to the PCI bus 105, and the bus function model 106 accesses the buffers 111 and 112 and responds to the access to the PCI bus 105 of the circuit 102.

  The bus function model 106 is a bus function model corresponding to the PCI bus, a data input interface model that is a bus function model corresponding to the data input interface, a data output interface model that is a bus function model corresponding to the data output interface, and a CPU. It has functions such as a CPU interface model which is a bus function model corresponding to the interface.

  The data input interface model has a function of executing, responding to, and monitoring a protocol with the circuit 102, reading data from the input data buffer 111, and inputting the data to the circuit 102.

  The data output interface model has a role of executing, responding to, and monitoring a protocol with the circuit 102, capturing data output from the circuit 102, and comparing the contents of the expected value data buffer 112 with the expected value.

  The CPU interface model executes, responds to, and monitors a protocol with the circuit 102 according to an instruction of a predetermined test scenario.

  The input data buffer 111 (first buffer) buffers input data read by the data input interface model.

  The expected value buffer 112 (second buffer) buffers the expected value used by the data output interface model for comparison with the data output from the circuit 102.

  As described above, the basic functions of the bus function model 106, the input data buffer 111, and the expected value buffer 112 are the same as those of the test bench system 1 of the above-described embodiment, and the input to the input data buffer 111 and the expected value buffer 112 is performed. The input of data and expected values is performed from a data file (not shown), the test bench is performed based on a test scenario (not shown), and the like, as in the test bench system 1 of the above-described embodiment.

  The input data buffer 111 and the expected value buffer 112 correspond to each of the CMYK four color image data, and in order to buffer the input data and the expected value corresponding to the CMYK four colors, respectively, four buffers 111a to 111d, 112a to 112d. As described above, in this system, both input data and output data correspond to CMYK four colors. Therefore, data access to the input data buffer 111 and the expected value buffer 112 is data access for each of four channels of input / output via the PCI bus. become.

  The buffer switching unit 107 (buffer switching means) has the same interface as the input data buffer 111 and the expected value buffer 112, and is connected to the input data buffer 111 and the expected value buffer 112. These input data buffer 111 and expected value buffer The access to 112 is switched according to conditions. Specifically, the buffer switching unit 107 distributes access to each of the buffers 111a to 111d and 112a to 112d according to the access address. That is, the condition for switching the buffers 111a to 111d and 112a to 112d is the access address.

  As described above, in the test bench system 101, the function of the buffer switching unit 107 described above makes the buffer switching unit 107 appear to the bus function model 106 as a single buffer, so that the bus function model 106 has a plurality of buffers, that is, Since the buffered data can be accessed without being aware of the input data buffer 111 and the expected value buffer 112, the reusability of the bus function model 106 as a test bench component is improved.

  In this case, in the test bench system 101, since the switching condition of each of the buffers 111a to 111d and 112a to 112d held by the buffer switching unit 107 is an address, an input data buffer for a data channel group in which the address range to be used does not overlap. 111. The reusability of the bus function model 106 as a test bench component is further improved by accessing the buffered data without being aware of the expected value buffer 112.

  Another embodiment will be described.

  FIG. 13 is an explanatory diagram of a configuration of the test bench system 101 according to the present embodiment. In FIG. 13, elements having the same reference numerals as those in FIG. 12 are the same as those in the embodiment described with reference to FIG. The circuit 102 to be verified in the present embodiment is an ASIC mounted on a color copying machine or the like, which compresses and encodes R (red), G (green), and B (blue) image data using the JPEG method. This is a circuit for outputting code data. The circuit 102 includes an RGB-JPEG conversion unit 121 in order to realize such a function. Circuit 102 is accessed via a single PCI bus 105, similar to the embodiment of FIG.

  In the test bench, input data buffer 111 and expected value buffer 112 have the expected values of each plane of RGB input image data and code data after JPEG compression, respectively. That is, the input data buffer 111 is composed of buffers 111a to 111c and buffers R, G, and B image data, respectively. The expected value buffer 112 is composed of a buffer 112a and is an expected value of code data after JPEG compression. Is buffered. That is, data access to the input data buffer 111 and the expected value buffer 112 is input 3 channels and output 1 channel via the PCI bus 105.

  Here, the address range of the code data output after JPEG compression cannot be an actual color copier, but a part of it is allowed to overlap with the input of RGB image data. In this way, by deliberately removing the address range restriction, it is possible to easily verify a wider address range.

  In the data access via the PCI bus 105 of the circuit 102, the code data output address after JPEG compression partially overlaps the input address of RGB image data, but access to the buffer depends on the difference between input and output. Are different (reading input data and comparing expected values), the buffers 111a to 111c and 112a to be used are correctly identified.

  As described above, since the switching condition of the input data buffer 111 and the expected value buffer 112 is the read / write access section of the data channel, even if the address overlaps between the channels, the input data is different if the read / write section is different. The buffer 111 and the expected value buffer 112 are distinguished and accessed. By allowing overlapping address ranges, flexible verification with fewer address restrictions can be performed.

  Another embodiment will be described.

  FIG. 14 is an explanatory diagram of a configuration of the test bench system 101 according to the present embodiment. In FIG. 14, elements having the same reference numerals as those in FIG. 12 are the same as those in the embodiment described with reference to FIG. The circuit 102 to be verified in the present embodiment is an ASIC mounted on a copying machine or the like, and uses image data of a document read by a scanner mounted on the copying machine as input data (scanner input), and is mounted on the copying machine. This is a circuit for transferring output data (plotter output) to be output to the plotter via a single PCI bus 105. Plotter output is performed by the plotter output unit 131, and scanner input is performed by the scanner input unit 132. This scanner input and plotter output operate independently. The plotter output becomes input data, and the scanner input becomes data to be compared with the expected value. The input data buffer 111 and the expected value data buffer 112 are composed of a plurality of buffers 111a, 111b,..., 112a, 112b,.

  In the test bench, first, one buffer image 111a, 111b,..., 112a, 112b,... Is provided for one document image of scanner input (expected value) and plotter output (input data). Then, by operating the circuit 102, scanner input and plotter output proceed.

In the test scenario, the progress of data transfer is grasped through the operation of the bus function model 106 or via the internal register of the circuit 102, and the buffer switching unit 107 is used to transfer the next original image of the scanner input or plotter output. On the other hand, new buffers (buffers 111a, 111b,..., 112a, 112b,...) Are added. The buffer switching unit 107 accesses the newly added buffer immediately after the current buffer access is completed.
Such dynamic buffer addition is used, for example, when transferring data repeatedly to obtain coverage of the timing relationship between the scanner input and the plotter output with random verification. This is because in such a case, the number of image data planes cannot be determined in advance. In this manner, input / output of image data via the PCI bus 105 is performed by independent scheduling.

  In this embodiment, since the switching conditions of the buffers 111a, 111b,..., 112a, 112b,... Are in the order of access, dynamic connection / disconnection of the buffers is possible unless the buffer is currently being accessed. Can verify complex data transfer operations.

  The hardware configuration of the test bench system 101 shown in FIGS. 12 to 14 is the same as that shown in FIG. The circuit 102 is connected to the CPU 211 via the PCI bus 105. Then, the bus function model 106 and the buffer switching unit 107 are constructed by the processing executed by the CPU 211 based on the program 220, and the input buffer 111 and the expected value buffer 112 are prepared in a storage device such as the RAM of the memory 212, as described above. Various processes are executed.

It is a functional block diagram of the test bench system which is one embodiment of the present invention. It is a functional block diagram explaining operation | movement of the test bench system of FIG. It is a timing chart explaining the operation of. It is a communication sequence diagram explaining the process which the test bench system of FIG. 1 performs. It is a functional block diagram of the test bench system which is another embodiment of this invention. It is a functional block diagram explaining operation | movement of the test bench system of FIG. It is a communication sequence diagram explaining the process which the test bench system of FIG. 5 performs. It is a functional block diagram of the test bench system which is another embodiment of this invention. It is a functional block diagram explaining operation | movement of the test bench system of FIG. It is a flowchart explaining operation | movement of the test bench system of FIG. It is a block diagram of the electrical connection of each said test bench system. It is a functional block diagram of the test bench system which is another embodiment of this invention. It is a functional block diagram of the test bench system which is another embodiment of this invention. It is a functional block diagram of the test bench system which is another embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test bench system 2 Circuit 3 Data input interface model 4 Data output interface model 5 CPU interface model 6 1st buffer 7 2nd buffer 217 Storage medium 220 Program 102 Circuit 107 Buffer switching means 111 1st buffer 112 2nd buffer

Claims (5)

Means for realizing a CPU interface model which is a bus function model corresponding to a CPU interface of a target circuit;
Means for realizing, in a predetermined storage device, a first buffer for buffering data input to the circuit by the CPU interface model;
A bus function model corresponding to the data input interface of the circuit, and means for realizing a data input interface model for inputting data buffered by the first buffer to the circuit;
Means for realizing, in a predetermined storage device, a second buffer for buffering an expected value of data output from the circuit;
A bus function model corresponding to the data output interface of the circuit, which realizes a data output interface model for comparing data output from the circuit with an expected value for the data buffered in the second buffer Means,
Buffer switching means for switching access to the first and second buffers according to conditions;
A computer-readable program that causes a computer to execute.   The program according to claim 1, wherein the buffer switching unit has an access address as the switching condition. 2. The program according to claim 1, wherein the buffer switching unit is a read / write access section to the first and second buffers.   2. The program according to claim 1, wherein access to the first and second buffers is sequential access, and the buffer switching unit can dynamically connect and disconnect the first and second buffers.   The storage medium which has memorize | stored the program as described in any one of Claims 1-4.

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