JP4475283B2 - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a manufacturing method of the nonvolatile semiconductor memory device.

  Conventionally, as a structure of a nonvolatile semiconductor memory device such as an EEPROM, as shown in Patent Document 1 and the like, a one-layer gate electrode structure (one layer) in which a control gate is formed of a diffusion layer and only a floating gate is formed of PolySi. PolySi structure).

  Such an EEPROM includes a sense transistor having a floating gate and a selection transistor. A sense transistor has a thin tunnel film between a region where a BN layer (buried N-type layer) operating as a control gate and a floating gate are capacitively coupled, and a BN layer different from the floating gate and the control gate. And a tunnel region that is formed.

  On the other hand, the selection transistor includes a source and a drain formed on the surface layer of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate via a gate insulating film and made of PolySi.

  An interlayer insulating film composed of an oxide film or a BPSG film is formed on the sense transistor and the select transistor.

Such writing and erasing of the EEPROM is performed in the tunnel region by injecting electrons into the floating gate and extracting electrons from the floating gate through the tunnel film. In reading, “1” and “0” are detected by turning on and off the sense transistor when the selection transistor is turned on.
Japanese Patent No. 2568940

In the above-described EEPROM having a single-layer polySi structure, the floating gate is not electrically neutral but charged to + or − after writing or erasing. At this time, OH ⁻ or H ⁺ ions in the interlayer insulating film move to the floating gate, and charges in the floating gate are neutralized with OH ⁻ or H ⁺ ions. As a result, since the effective charge in the floating gate is lowered, there is a problem that the threshold voltage Vt fluctuates and the so-called charge retention life is lowered.

On the other hand, as a method for suppressing the decrease in the charge retention life, it is conceivable to cover the floating gate with a film through which OH ⁻ or H ⁺ ions cannot pass. However, further suppression of the decrease in the charge retention life is required.

  At the time of reading, the voltage applied to the drain is only about 1 V in order to suppress the electrons in the floating gate from being discharged through the tunnel film to the BN layer below the tunnel film. Not applied. Therefore, a selection transistor having a high current driving capability is required so that a sufficient current flows even at such a low voltage. On the other hand, as a method for improving the current driving capability of the selection transistor, it is conceivable to form the gate insulating film with a high dielectric constant film.

Since the sense transistor and the select transistor require different performances, they are usually formed in separate steps. Therefore, as a method for suppressing the decrease in the charge retention life of the former, as a method for covering the floating gate with a film through which OH ⁻ or H ⁺ ions cannot pass and for improving the current driving capability of the selection transistor, a high dielectric When forming a gate insulating film composed of a film having a high refractive index, the formation process of the film through which these OH ⁻ or H ⁺ ions cannot pass and the film having a high dielectric constant are considered to be separate processes. It is done. However, in order to reduce manufacturing costs, it is desirable that the number of processes be small.

  By the way, the floating gate and the gate electrode made of PolySi are implanted with, for example, phosphorus as an impurity. In the sense transistor, when the phosphorus concentration of the floating gate is high, phosphorus precipitates at the grain boundary of PolySi. If the precipitation of phosphorus occurs on the surface of PolySi in contact with the tunnel film, the portion of the tunnel film where phosphorus is precipitated becomes thin. Since the tunnel current mainly flows through the minimally thinned portion, the minimally thinned portion is more likely to deteriorate than the other portions.

  Thus, the tunnel film is damaged by the deposited phosphorus. Therefore, in order to improve the number of times of rewriting until destruction, it is necessary to reduce the phosphorus concentration. On the other hand, the selection transistor needs to function so that a voltage higher than that of the floating gate is applied and the voltage applied to the drain is transmitted to the BN layer below the tunnel film.

  In the manufacturing method having the above-described structure, conventionally, as disclosed in Patent Document 1 and the like, the floating gate and the gate electrode of the selection transistor are formed at the same time. For this reason, when the phosphorus concentration in the floating gate is optimized to improve the number of rewrites, the phosphorus concentration in the gate electrode of the selection transistor becomes the same concentration. At this concentration, when a high voltage is applied, As a result, a charge bias occurs. As a result, the voltage applied to the gate oxide film is lowered, so that the circuit operation speed is lowered. For this reason, rewriting time and reading time become long.

The present invention is made in view of the above disadvantages, and purpose thereof is to provide a method of manufacturing a nonvolatile semiconductor memory device which can satisfy the improvement of the rate of increase and the circuit operation of the rewrite frequency simultaneously.

In order to achieve the above object, in the present invention, the step of forming the floating gate (4) and the step of forming the gate electrode (9) are performed separately, and at least the tunnel film is formed in the step of forming the floating gate (4). the impurity concentration of the region in contact with the (7) is a feature to form a floating gate (4) to be lower than the gate electrode (9).

  Here, in the case where the floating gate and the gate electrode of the selection transistor are formed at the same time, at an impurity concentration that can suppress the precipitation of impurities from the floating gate and at which the gate electrode is not depleted, A floating gate and a gate electrode had to be formed.

  On the other hand, according to the present invention, since the floating gate and the selection transistor are formed separately, the impurity concentration of the region in contact with the tunnel film in the floating gate is formed to be lower than that of the gate electrode. Can do.

  Accordingly, the impurity concentration of the floating gate is set to be high so that the current capability is increased, and in order to suppress damage to the tunnel film due to precipitation of impurities from the floating gate. Can be set low. Therefore, the nonvolatile semiconductor memory device can be manufactured so as to satisfy both the improvement of the number of rewrites and the improvement of the circuit operation speed.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
FIG. 1 shows an EEPROM according to a first embodiment to which the present invention is applied. The EEPROM includes a sense transistor and a selection transistor formed on a P ⁻ type Si substrate 1.

The sense transistor is formed on the surface layer of the P ⁻ -type Si substrate 1, and includes a control gate 2 constituted by a BN layer (buried N-type layer), an insulating film 3 formed on the control gate 2, and an insulating film 3 And a floating gate 4 made of PolySi. The floating gate 4 is electrically insulated from the outside. In the present embodiment, a single-layer PolySi structure in which only the floating gate 4 is made of PolySi is thus obtained.

  The BN layer 6 is formed by being separated by the control gate 2 and the LOCOS oxide film 5. An insulating film 3 is formed on the surface of the BN layer 6, and a part of the insulating film 3 is thinner than other regions. The thin film portion is a so-called tunnel film 7, which has a film thickness of, for example, about 7 to 11 nm and is composed of a silicon oxide film or a silicon oxynitride film (silicon oxynitride film). Hereinafter, these films are simply referred to as an oxide film and an oxynitride film, respectively.

The floating gate 4 is disposed on the tunnel film 7, and the concentration of the floating gate 4 at least in a portion in contact with the tunnel film 7 is 1.5 × 10 ²⁰ cm ⁻³ or less, for example.

On the surface of the floating gate 4, an insulating film 8 a that is in direct contact with the floating gate 4 and covers the floating gate 4 and has higher moisture resistance than the oxide film is formed. The highly moisture-resistant insulating film 8a is a film having a higher density than the oxide film and a low ion permeability such as H ⁺ and OH ⁻ . The thickness of the insulating film 8a is, for example, 15 to 80 nm.

On the other hand, in the selection transistor, a gate insulating film 8b having the same film quality as the insulating film 8a formed in the sense transistor is formed on the surface of the P ⁻ type Si substrate 1. The gate insulating film 8b has a dielectric constant higher than that of the oxide film. For example, a nitride film (silicon nitride film), an oxynitride film, or the like is used as an insulating film having higher moisture resistance than this oxide film and having a high dielectric constant. The thickness of the gate insulating film 8b is also the same as that of the insulating film 8a, and is, for example, 15 to 80 nm.

A gate electrode 9 is formed on the gate insulating film 8b. The gate electrode 9 is made of PolySi in which P (phosphorus) is implanted as a conductive impurity and the phosphorus concentration is high. The phosphorus concentration is, for example, 1.5 × 10 ²⁰ cm ⁻³ or more.

Further, an N ⁺ type source region 10 and an N ⁺ type drain region 11 are formed on both sides of the gate electrode 9 in the surface layer of the P ⁻ type Si substrate 1. The source region 10 is electrically connected to the BN layer 6 of the sense transistor.

  The EEPROM having such a structure is rewritten and read out in the same manner as in a general single-layer PolySi structure.

In this embodiment, the sense transistor directly contacts the floating gate 4 and covers the floating gate 4 with the insulating film 8a having higher moisture resistance than the oxide film. Since the insulating film 8 a has high moisture resistance, it has an effect of shielding H ⁺ and OH ⁻ ions existing outside the floating gate 4 from the floating gate 4. From this, it is possible to suppress the H ⁺ and OH ⁻ ions from reaching the floating gate 4 exceeding the neutral state after writing or erasing.

  In addition, when the gate insulating film 8b in the selection transistor has the same film thickness, the dielectric constant is higher than that of a normally used oxide film. In this embodiment, the gate insulating film 8b has a film thickness that is normally used. And the same film thickness. For this reason, the current drive capability of the selection transistor can be improved. Thereby, the circuit operation can be speeded up, so that the memory can be read at a high speed.

In this embodiment, the portion of the floating gate 4 of the sense transistor that is in contact with the tunnel film 7 and the gate electrode 9 of the selection transistor have different phosphorus concentrations. Since the portion of the floating gate 4 in contact with the tunnel film 7 has a low concentration of 1.5 × 10 ²⁰ cm ⁻³ or less, the precipitation of phosphorus from the grain boundary of PolySi can be suppressed. This has been confirmed by experiments by the present inventors.

  For this reason, damage to the tunnel film due to the deposited phosphorus can be suppressed. As a result, the number of rewrites up to destruction can be increased.

  On the other hand, the phosphorus concentration of the gate electrode 9 of the selection transistor is higher than the portion of the floating gate 4 in contact with the tunnel film 7. Thereby, when the voltage is applied to the gate electrode 9 as compared with the case where the phosphorus concentration of the gate electrode 9 and the floating gate 4 is the same and the concentration is optimized to improve the number of rewrites, the gate electrode 9 The depletion of 9 can suppress the voltage applied to the gate oxide film from being lowered.

  FIG. 2 shows a method for manufacturing the nonvolatile semiconductor memory device.

In the step shown in FIG. 2A, first, a LOCOS oxide film 5 as a field insulating film is formed on a P ⁻ type Si substrate 1. Thereafter, the BN layer as the control gate 2 and the BN layer 6 are formed by selectively implanting ions in the formation region of the sense transistor.

Next, an insulating film 3 such as an oxide film is formed on the control gate 2 and the BN layer 6. Subsequently, the tunnel film 7 is formed by etching a part of the insulating film 3. Then, a PolySi film in which phosphorus is implanted as a conductive impurity is formed on the surface of the P ⁻ type Si substrate 1 in the region where the sense transistor is to be formed, and the floating gate 4 is formed.

At this time, the total impurity concentration is set to 1.5 × 10 ²⁰ cm ⁻³ or less so that the phosphorus concentration of the floating gate 4 in contact with the tunnel film 7 is 1.5 × 10 ²⁰ cm ⁻³ or less. A floating gate 4 is formed. The lower limit of the impurity concentration is set to a concentration that does not cause depletion when a voltage is applied to the floating gate 4 via the control gate 2.

In the step shown in FIG. 2 (b), higher humidity resistance than oxide film, and an insulating film 8 which is a high dielectric constant than oxide film from the surface of the floating gate 4, P in the formation region of the select transistor ^- It is formed on the surface of the mold Si substrate 1. At this time, specifically, a nitride film or an oxynitride film is formed by a CVD method. Thereby, the insulating film 8a of the sense transistor and the gate insulating film 8b of the selection transistor are formed at the same time.

In the step shown in FIG. 2C, a PolySi film in which phosphorus is implanted as a conductive impurity is formed on the gate insulating film 8b in the region where the selection transistor is to be formed, and the gate electrode 9 is formed. At this time, the phosphorus concentration is set to 1.5 × 10 ²⁰ cm ⁻³ or more.

Subsequently, the source region 10 and the drain region 11 are formed on both sides of the gate electrode 9 in the surface layer portion of the P ⁻ -type Si substrate 1 in the region where the selection transistor is to be formed. Thereby, the EEPROM shown in FIG. 1 is formed.

  In the present embodiment, the sense transistor insulating film 8a and the select transistor gate insulating film 8b are simultaneously formed in the step shown in FIG. Thereby, the manufacturing process can be reduced as compared with the case where the insulating film 8a and the gate insulating film 8b are formed separately.

  Conventionally, the floating gate 4 of the sense transistor and the gate electrode 9 of the selection transistor are formed simultaneously. For this reason, the floating gate 4 needs to be formed at a phosphorus concentration at which phosphorus does not precipitate, and the gate electrode 9 needs to be formed at a phosphorus concentration at which the gate electrode 9 is not depleted when a voltage is applied. It was necessary to form so as to satisfy both.

  On the other hand, in this embodiment, the floating gate 4 of the sense transistor and the gate electrode 9 of the selection transistor are formed in separate steps in the steps shown in FIGS. . As a result, the floating gate 4 and the gate electrode 9 can be formed with an optimum phosphorus concentration.

  In the present embodiment, the entire phosphorus concentration of the floating gate 4 is lowered so that phosphorus does not precipitate from the grain boundary of PolySi. However, the portion of the floating gate 4 in contact with the tunnel film 7 is not formed. It is also possible to form the floating gate 4 by reducing only the concentration.

  As this method, for example, after depositing PolySi, phosphorus is ion-implanted while masking the region located above the tunnel film 7 when ion-implanting phosphorus. Thereby, only the concentration of the floating gate 4 located on the upper side of the tunnel film 7 can be set to a low concentration at which phosphorus does not precipitate.

As another method, STI (Shallow Trench Isolation) is formed instead of the LOCOS oxide film 5. Then, after forming the insulating film 3 and the tunnel film 7 on the P ⁻ type Si substrate 1, a floating gate is formed. At this time, the floating gate is formed at a concentration that does not cause precipitation of phosphorus as a whole. Thereafter, the floating gate is polished by utilizing the difference in surface height between the insulating film 3 and the tunnel film 7. In other words, the surface of the insulating film 3 is polished to leave the low concentration of PolySi on the tunnel film 7. Subsequently, PolySi having a higher concentration of phosphorus than PolySi on the tunnel film 7 is formed again. As a result, the floating gate 4 having a low concentration can be formed only in the portion in contact with the tunnel film 7.

In the sense transistor, the insulating film 8a is directly formed on the surface of the floating gate 4 in order to prevent ions such as H ⁺ and OH ⁻ from moving to the floating gate 4 that is not neutral and neutralized. The floating gate 4 is preferably formed in contact with each other, but if the charge in the floating gate 4 is not neutralized, the floating gate 4 and the insulating film 8a are not in direct contact with each other, and other layers are interposed between them. A formed structure may also be used.

(Second Embodiment)
FIG. 3 shows a cross-sectional view of the EEPROM according to the second embodiment.

The difference from the structure of the EEPROM in the first embodiment is that there is a difference between PolySi and the floating gate 4 in the sense transistor and the insulating film 8a, and between the P ⁻ type Si substrate 1 and the gate insulating film 8b in the select transistor. It has a nitride film 21 formed by reacting the Si substrate 1. The other structure is the same as that of the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted.

  In the EEPROM shown in FIGS. 2A to 2C, before the step of forming the insulating film 8 shown in FIG. 2B, the EEPROM is used in a nitrogen atmosphere such as ammonia gas. A heat treatment at 1200 ° C. is performed. In this manner, the nitride film 21 is formed by reacting PolySi in the sense transistor. At the same time, the nitride film 21 is formed by reacting the Si substrate 1 with a selection transistor.

  Thereafter, the insulating film 8 is formed on the nitride film 21, and the process shown in FIG. Thereby, the EEPROM shown in FIG. 3 is formed.

The manufacturing method of the present embodiment is a method for improving the interface characteristics between the floating gate 4 and the insulating film 8a and the interface characteristics between the gate insulating film 8b and the Si substrate 1. Thus, by forming the nitride film 21 by reacting, in the sense transistor, the adhesion between the floating gate 4 and the insulating film 8a can be improved. Further, in the select transistor, the interface state between the gate insulating film 8b and the P ⁻ type Si substrate 1 can be reduced.

Note that an oxynitride film can be formed in place of the nitride film 21 and has the same effect as when the nitride film 21 is formed. When forming the oxynitride film, for example, heat treatment is performed at a heat treatment temperature similar to the formation of the nitride film 21 in an oxynitride atmosphere such as NO, N ₂ O, or N ₂ + O _2. A nitride film is formed.

(Third embodiment)
FIG. 4 is a sectional view of the nonvolatile semiconductor memory device according to the third embodiment.

  The EEPROM of the present embodiment is different from the EEPROM structure of the first embodiment in that the sense transistor covers the floating gate 4 on the surface of the insulating film 8a and shields the potential of the floating gate 4. A conductive film 22 is formed.

The conductive film 22 is made of PolySi, and is electrically connected to the P ⁻ type Si substrate 1 through, for example, an Al wiring. That is, the potential of the conductive film 22 is fixed to the P ⁻ type Si substrate 1. Usually, the P ⁻ type Si substrate 1 is set to the ground potential. Since the floating gate 4 is covered with the conductive film 22 having the ground potential, even if the potential of the floating gate 4 fluctuates due to injection or extraction of electrons, the periphery of the floating gate 4 and the floating gate 4 can suppress a variation in potential difference between the four.

Therefore, even after writing or erasing, even if the floating gate 4 is not electrically neutral, H ⁺ , OH ⁻ ions and other movable ions existing outside the floating gate 4 move to the floating gate 4. Can be suppressed. From this, compared with 1st Embodiment, the tolerance with respect to H ^<+> , OH ^{< - >} ion or a movable ion can be raised, and a charge retention characteristic can be improved more.

  Note that the potential of the conductive film 22 is not limited to the ground potential, and may be a positive or negative potential. As a result, it is possible to prevent specific ions existing outside the floating gate 4 from attracting the conductive film 22 and moving to the floating gate 4.

The EEPROM having such a structure is formed on the insulating film 8a by the sense transistor simultaneously with the formation of the gate electrode 9 of the selection transistor in FIG. 2C in the manufacturing process of FIGS. A PolySi film is formed. Thereafter, this PolySi film and, for example, the P ⁻ type Si substrate 1 are electrically connected. In this way, the conductive film 22 for shielding the potential of the floating gate 4 is formed. Thereby, the EEPROM shown in FIG. 4 is formed.

(Other embodiments)
In each of the above-described embodiments, the insulating film 8a and the gate insulating film 8b are formed at the same time, and the floating gate 4 and the gate electrode 9 are separately formed, so that each has an appropriate impurity concentration. Although the case where both of these are performed has been described as an example, each of them can be performed independently.

  That is, only the method of forming the insulating film 8a and the gate insulating film 8b at the same time can be performed. In addition, by forming the floating gate 4 and the gate electrode 9 separately, it is possible to carry out only the method of setting each to an appropriate impurity concentration.

  Further, the present invention can be applied not only to an EEPROM but also to an EPROM that performs erasing by electrically writing ultraviolet rays.

It is a figure which shows the cross section of EEPROM in 1st Embodiment of this invention. It is a figure which shows the manufacturing process of EEPROM in 1st Embodiment of this invention. It is a figure which shows the cross section of EEPROM in 2nd Embodiment of this invention. It is a figure which shows the cross section of EEPROM in 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... P ^- type Si substrate, 2 ... Control gate, 3, 8 ... Insulating film, 4 ... Floating gate,
5 ... LOCOS oxide film, 6 ... BN layer, 7 ... tunnel film,
8b ... gate insulating film, 9 ... gate electrode, 10 ... source region,
11 ... drain region, 21 ... nitride film, 22 ... potential shielding film.

Claims (1)

A sense transistor having a one-layer gate electrode structure in which a control gate is constituted by an impurity diffusion layer in a semiconductor substrate, a floating gate is constituted by a conductive film on the semiconductor substrate, and a tunnel film is formed in contact with the floating gate; In a method for manufacturing a nonvolatile semiconductor memory device comprising a selection transistor,
Forming the floating gate (4) made of PolySi containing a conductive impurity on the formation region of the sense transistor in the semiconductor substrate (1) via the tunnel film (7);
After forming a gate insulating film (8b) on the formation region of the selection transistor in the semiconductor substrate (1), a gate made of PolySi containing a conductive impurity on the gate insulating film (8b). Forming an electrode (9),
By separately performing the step of forming the floating gate (4) and the step of forming the gate electrode (9), the step of forming the floating gate (4) is in contact with at least the tunnel film (7). A method for manufacturing a nonvolatile semiconductor memory device, wherein the floating gate (4) is formed so that the impurity concentration of the region is lower than that of the gate electrode (9).

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