JP4474305B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment, and more specifically, to a method for manufacturing a semiconductor equipment utilizing a strained Si as a channel.

In strained Si-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) which are currently mainstream, a Si crystal serving as a channel region is formed by heteroepitaxial on SiGe having a lattice constant larger than that of Si, or Ge crystal is included in the Si crystal. Ion is implanted to form SiGe inside the Si bulk. Then, depending on the large lattice constant of SiGe, most of them apply a tensile stress by laterally expanding the Si lattice adjacent to the SiGe region. As such a transistor or a semiconductor device, for example, there are technologies shown in the following patent documents and non-patent documents.
JP 2002-76334 A JP 2001-44425 A JP-A-9-82948 Japanese Patent Laid-Open No. 7-32222 JP-A-6-216376 Toshiba Review Vol.56, No.1, 2001 MV Fischetti and SE Laux, "Band structure, deformation potentials, and carrier mobility in straind Si, Ge, and SiGe alloys", Journal of applied Physics, vol. 80 (4), 15 August, 1996 R. People, "Physics and Applications of GexSi (1-x) / Si Strained-Layer HeteroStructures", IEEE JOURNAL OF QUANTUM ELECTRONICS, VOL.QE-22, NO. 9, SEPTEMBER, 1986

Also, as shown in the following patent documents and non-patent documents, a technique for realizing an SOI (Silicon On Insulator) structure by epitaxial growth on an insulating film has been developed for a long time.
JP-A-4-137723 Japanese Patent Laid-Open No. 3-125259 L. JASTRZEBSKI, "SOI BY CVD: EPITAXICAL LATERAL OVERGROWTH (ELO) PROCESS-REVIEW", Journal of Crystal Growth, vol. 63, (1983), pp. 493-526 Y. Suzuki and T. Nishinaga, "Epitaxial Lateral Overgrowth of Si by LPE with Sn Solution and Its Orientation Dependence", Japanese Journal of Applied Physics, Vol. 28, No. 3, March, 1989, pp. 440-445

  However, the above background art has the following disadvantages. First, in the strained Si-MOSFET in which lattice strain is introduced by SiGe, first, in order to control the tensile stress, it is extremely important to control the composition ratio and film thickness of the SiGe layer. There are problems such as difficulty in coordinating and building a stable process, and high costs. Second, since Si deposited on SiGe is heteroepitaxy, degradation of crystal quality is always a problem, and in order to avoid this, return to the first problem described above and redesign. There was a need.

  Thirdly, when SiGe is formed in a Si bulk crystal by Ge ion implantation, since the Ge ions pass through a Si region that later becomes a MOS channel, there is a problem that the crystal quality is impaired. It takes time and effort to add an annealing process to recover. Fourthly, the formation of the SiGe layer has a problem that it takes a long time and throughput is low regardless of which method is CVD or ion implantation.

  Fifth, the main source of Ge is the use of monogermane gas, but monogermane gas is said to be self-degradable and very rarely explodes suddenly. Therefore, it cannot be said that safety is sufficiently high. In the first place, Si (silicon), O (oxygen), P (phosphorus) as dopamine, As (arsenic), Sb (antimony), B (boron) is a new element called Ge (germanium). Introducing the process puts a heavy burden on process technology and should be avoided if possible.

  On the other hand, among the techniques for realizing the SOI structure by epitaxial growth on the insulating film, in the experiment described in Non-Patent Document 5, the SOI formed on the oxide film in the temperature range of 800 to 950 ° C. by liquid phase epitaxial growth. It has been confirmed that the film is subjected to tensile stress at room temperature. However, this experiment was performed using a Si substrate having a (111) plane as a main surface. When a MOSFET is formed with such a (111) plane as a main surface, the (111) plane becomes a MOS channel. I must. In a Si crystal, it is known that when a MOS channel is formed on the (111) plane, interface states are generated at a high density, and an increase in Vth (threshold voltage) and channel mobility (in the MOS channel region). In general, it is considered undesirable because it causes a decrease in the carrier mobility. Further, the effect of increasing the carrier mobility due to the distortion in the (111) plane has not been sufficiently investigated. On the other hand, the Si (100) plane has a low interface state density and is most suitable for forming a MOS channel. Currently, most mass-produced Si MOSFETs form a MOS channel on the (100) plane. It has a configuration. Further, the effect of increasing the carrier mobility due to strain has been sufficiently studied, and mass production and shipment of some strained Si-MOSFETs using the SiGe / Si system has been started. Therefore, it is convenient to form the MOS channel on the (100) plane.

The present invention has focused on the above points, and its object is without using the Ge elements, high process reliability and crystal quality, and easy to stress management, high-speed operation capable of semiconductor equipment It is to provide a manufacturing method.

In order to achieve the above object, a method of manufacturing a semiconductor substrate according to the present invention includes a step of forming an insulating layer having a thermal expansion coefficient different from that of the Si substrate on the surface of the Si substrate, opening the insulating layer, and opening the Si substrate. Forming a surface exposed portion connected in a substantially comb-like shape on the surface of the silicon substrate, forming an n + type or p + type low resistance region in a substantially comb-like surface exposed portion of the Si substrate, the Si substrate After the Si crystal is epitaxially grown at a high temperature in the upward direction from the exposed surface of the substrate, the high temperature epitaxial growth is also performed in the lateral direction, and the insulating layer is coated. The epitaxially grown Si layer is polished, and the Si layer coated with the insulating layer to form a SOI region where the thickness of the layer is 200nm or less, forming a Si layer on the exposed surface of the Si substrate, before provided on both sides of the SOI region to be a channel region The Si layer, by forming a source region and a drain region of the low-resistance region the same conductivity type, the channel region, thereby forming a plurality of MOSFET having the source region and the drain region, the source region and the drain region the electrically connected to the low-resistance region by annealing to activate the step of connecting the source region and between the drain region between the MOSFET adjacent to the gate width direction of the plurality of MOSFET, with including, the channel region the strain caused by the difference in thermal expansion coefficient between the insulating layer and the Si layer is characterized Tei Rukoto occur. One of the main forms is characterized in that the low resistance region is formed by ion implantation into a surface exposed portion of the Si substrate.

Another embodiment includes (1) a step of forming a step in the insulating layer formed on the surface of the Si substrate, and in the polishing step, the thickness of the Si layer in the SOI region is determined using the step. Or (2) the thickness of the Si layer in the SOI region is controlled by film thickness management by CMP polishing or time management.

Yet another embodiment is characterized in that the epitaxial growth is performed at 800 ° C. or higher.

Yet another embodiment, the main surface of the Si substrate is (100) plane or an equivalent plane, the stripe direction of the exposed surface for the epitaxial growth is <010> or equivalent person position It is characterized by being.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

  In a semiconductor device using strained Si as a channel, the present invention controls the thickness of an SOI region when using an epitaxial growth technique on an insulating layer (or insulating film), and the difference in thermal expansion coefficient between Si and the insulating layer, The tensile stress was introduced into the Si layer using the temperature difference between the film formation temperature and room temperature. For this reason, it is possible to obtain a semiconductor device that suppresses variations in electrical characteristics, has high process reliability and crystal quality, is easy to manage stress, and can operate at high speed.

  Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

  First, Embodiment 1 of the present invention will be described with reference to FIGS. 1-5 is a figure which shows an example of the manufacturing process of a present Example. In this embodiment, the present invention is applied to a MOSFET having a strained Si channel, and has a structure having a MOS structure in an SOI region. In this embodiment, a MOSFET is taken as an example of a semiconductor device. However, the present invention includes all MOS structures such as an IGBT (Insulated Gate Bipolar Transistor) and an insulated gate thyristor. It can be applied to the semiconductor device. Hereinafter, although the manufacturing method of a present Example is demonstrated in order, you may make it implement by replacing p type and n type in the following description.

  First, as shown in the cross-sectional view of FIG. 1A, an Si substrate 11 is prepared, and an insulating film (or insulating mask) is formed on the surface thereof by thermal oxidation or CVD (Chemical Vapor Deposition). ) 12 is formed. The main surface of the Si substrate 11 is preferably a (100) plane from the viewpoint of the lowest interface state density in a MOS channel to be formed later. The Si substrate 11 is a Si wafer manufactured by the CZ (Czochralski) method or FZ (floating zone) method, and the conductivity type may be any of n-type, p-type, and non-doped depending on the use of the device. What is necessary is just to select a density | concentration within the range suitably according to a use. In this embodiment, it is assumed that the p-type Si substrate 11 is selected. In general, it is convenient to use a thermal oxide film as the insulating film 12 because it is excellent in terms of reliability and mass productivity. However, an oxide film such as HTO or TEOS by CVD is used. Alternatively, a nitride film may be used.

  Next, using a mask (not shown), the insulating film 12 is opened by photolithography or the like, and as shown in the sectional view of FIG. 1B and the perspective view of FIG. To expose the surface. FIG. 1 (B) corresponds to a cross section of FIG. 1 (C) taken along line # A- # A and viewed in the direction of the arrow. The area of the window opening portion 12A is appropriately set according to the size and number of semiconductor elements formed in the SOI region. Subsequently, another insulating film (or insulating mask) 14 is newly formed on the surface of the Si substrate 11. As the insulating film 14, for example, a thermal oxide film is used. In this case, as shown in the cross-sectional view of FIG. 1D, a newly oxidized region is formed between the insulating film 12 and the Si substrate 11. Since it is an interface, the insulating film 14 has a structure of being recessed under the insulating film 12 formed previously.

  Alternatively, when an oxide film or a nitride film such as HTO or TEOS by CVD is used as the insulating film 14, the insulating film 14 is formed on the surface of the insulating film 12 previously formed as shown in FIG. It comes to cover. In this embodiment, as shown in FIG. 1D, the following steps will be described on the assumption that a thermal oxide film is used as the insulating film 14, but it is easy to change the stacking order of the insulating films 12 and 14. When the structure shown in FIG. 1E is selected, it can be replaced. Note that in FIG. 1D or 1E, the step d of the insulating film is desirably 200 nm or less. However, when the amount of wear due to CMP (Chemical Mechanical Polishing) in a process described later cannot be ignored, it may be set to about 300 nm or less. The level difference d using the insulating films 12 and 14 is used for controlling the thickness of the Si layer in a polishing process described later.

Next, a resist 16 is applied to the entire surface of the substrate, patterning is performed using a mask (not shown), and the insulating film 14 is etched using the resist 16 as a mask to form a window opening 18 shown in FIG. . Although the etching method of the insulating film 14 may be performed by hydrofluoric acid treatment, since dry etching has better controllability in recent years, it may be performed by dry etching. Subsequently, ion implantation is performed to form a wiring region while using the resist 16 as a mask. When the wiring is n-type conduction, As or P ions are implanted, and when the wiring is p-type conduction, B ions are implanted. It is desirable to increase the dose so as to be 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² to reduce the wiring resistance. In this embodiment, n-type conduction is used, As ions that are less diffused at a high temperature in the process described later are selected, and implanted with a dose amount of 1 × 10 ¹⁵ cm ⁻² .

  When ion implantation is performed as shown in FIG. 2A to form the n + type wiring region 20 shown in FIG. 2B, the resist 16 is removed. Here, the order of ion implantation and removal of the resist 16 is preferably performed in the order described above. As shown in FIG. 2B, if ion implantation is performed using the insulating film 14 as a mask after the resist 16 is removed, the ions stopped by the insulating film 14 cause the channel of the MOSFET in the process described later. This is because it may ooze out into the SOI region to be formed and impair the characteristics of the MOSFET. Therefore, if the resist 16 is removed after ion implantation, it is advantageous because it does not affect the processes described later.

  As shown in the cross-sectional view of FIG. 2B and the perspective view of FIG. 2C, an n + type wiring region 20 by ion implantation is formed in a portion corresponding to the window opening 18. 2 (B) corresponds to a cross section of FIG. 2 (C) taken along line # B- # B and viewed in the direction of the arrow. The ions implanted in the above process are exposed to a high temperature in the epitaxial film forming process to be described later and are always activated, so that it is not necessary to perform an activation process at this stage. Here, the window opening 18 where the n + -type wiring region 20 is exposed by As ion implantation is preferably comb-shaped or substantially comb-shaped as shown in FIG. This is to avoid the occurrence of dislocations (crystal defects) 62 due to collision of the epitaxially grown epitaxial film from both sides, as shown in FIG. It is. Examples of such dislocations being eliminated by comb-like window opening are, for example, Z. Yan, Y. Hamaoka, S. Naritsuka and T. Nishinaga, "Coalescence in microchannel epitaxy of InP", Journal of Crystal. Growth, vol. 212 (2000) pp. 1-10 and JP-A-2000-114278 (however, the experiments described in the above-mentioned academic papers are based on the liquid phase growth of InP (LPE: Liquid Phase Epitaxy). ).

  2B and 2C, the stripe direction of the window opening 18 (that is, the n + type wiring region 20) is preferably the <010> direction or an equivalent direction. With such a configuration, an ELO (Epitaxial Lateral Overgrowth) layer formed in an epitaxial film forming process described later has a main surface as a (100) plane and side surfaces as a (010) plane and a (0-10) plane. grow up. In terms of atomic arrangement, since the (100) plane, (010) plane, and (0-10) plane are equivalent planes, the deposition rate is the same, and the aspect ratio of the cross section of the ELO layer is approximately 1: 1 Originally, when it is intended to obtain an SOI structure, it is desirable that the ELO layer extends more laterally. However, as long as the main surface is the (100) plane and the film is formed by the CVD method, the most lateral orientation is the configuration of this example, and the maximum aspect ratio is 1: 1. It should be noted that conditions for further extending in the lateral direction can be found by changing the film formation temperature, gas type, and stripe orientation, and epitaxial film formation described later may be performed according to the conditions. On the other hand, when the main surface is the (111) surface, the (111) surface is an extremely slow film-forming surface, so it is easy to increase the aspect ratio horizontally. This will be described in another embodiment.

  After obtaining the states shown in FIGS. 2B and 2C, Si is epitaxially deposited on the window opening 18. The film forming conditions are, for example, 800 ° C. or higher shown in Non-Patent Document 5 described above. Actually, in consideration of mass productivity and process stability, the CVD method is most suitable, using hydrogen as a carrier gas, and using a silane-based gas such as SiH4, SiH3Cl, SiH2Cl2, SiHCl3, or SiCl4 as a film forming gas, A halogen-based etching gas such as HCl is added and supplied to the surfaces of the films 12 and 14 so that polysilicon does not nucleate and become large. Further, in the CVD method, a sufficient film forming speed cannot be obtained unless the film forming temperature is set to 900 ° C. or higher. Therefore, it is desirable to set the film forming temperature within a range of about 900 to 1100 ° C. Further, although the pressure in the CVD reactor can be implemented even at normal pressure, it is necessary to increase the amount of HCl added so that polysilicon does not nucleate and become large on the surfaces of the insulating films 12 and 14. . On the other hand, according to the CVD method under reduced pressure, the risk of polysilicon nucleating on the surfaces of the insulating films 12 and 14 is reduced and the amount of HCl added can be reduced, but the deposition rate is slow. There is a problem of becoming. Therefore, it is convenient to carry out at least the furnace pressure of 30 Torr or higher even when the pressure is reduced.

  First, as shown in FIGS. 3A and 3B, an epitaxial layer 22 is formed upward from the window opening 18 by the epitaxial film forming process described above. FIG. 3A is a cross-sectional view of FIG. 3B taken along line # C- # C and viewed in the direction of the arrow. The epitaxial layer 22 then grows in the lateral direction and grows along the surface of the insulating film 14. At this time, the V-shape 24 shown in FIG. 3B promotes faster growth than the normal lateral growth due to the indentation angle effect, and the dislocation 62 shown in FIG. 5C is generated. Can be prevented. The reason why the shape of the window opening 18 is a comb-like shape is to use the recess angle effect due to the introduction of the V-shape 24. Note that the concave angle effect is publicly known, and a detailed description is described in, for example, Japanese Patent Application Laid-Open No. 2004-158835. The conductivity type of the epitaxial layer 22 in this embodiment is preferably n-type or non-doped. When epitaxial film formation is continued as described above, the epitaxial layer 22 covers the entire surface of the insulating film 14 as shown in the sectional view of FIG. 3C and the perspective view of FIG. The surface is slightly raised from the surface of 12. FIG. 3C corresponds to a cross section of FIG. 3D cut along line # D- # D and viewed in the direction of the arrow.

  Next, as shown in the sectional view of FIG. 4A, the raised portion of the epitaxial layer 22 is polished and removed by CMP polishing using the insulating film 12 as a stopper to form an SOI region. Usually, in silicon polishing using an oxide film as a stopper, a polishing rate selection ratio of 1: 100 or more is obtained, and the oxide film acts as an extremely strong stopper. However, depending on the structure of the CMP apparatus, the oxide film may be slightly worn. In this case, it is preferable to make the insulating film 12 slightly thick in anticipation of wear. For example, in FIG. 4A, the thickness of the epitaxial layer 22 in the SOI region (that is, the thickness of the step d) is desirably 200 nm or less, but when the insulating film 12 is expected to be worn as described above. First, the step d is set to about 300 nm so that a step of 200 nm remains after wear. As described above, the thickness of the epitaxial layer (Si layer) 22 in the SOI region is set to about 200 nm (or 300 nm) or less because if the thickness is too large, the lattice distortion of Si is relaxed, and the strained Si-MOSFET is formed. This is because it cannot be obtained.

Further, in the state of FIG. 4A, the epitaxial layer 22 in the vicinity (upper side) of the insulating film 14 receives tensile residual stress 26. For example, when the insulating film 14 is an oxide film, the thermal expansion coefficient of the oxide film is 0.5 × 10 ⁻⁶ / K, whereas the thermal expansion coefficient of Si is 2.4 × 10 6. ^-6 / K. Therefore, when the film is formed at a high temperature of 900 ° C. or higher and then returns to room temperature, Si tends to shrink more and the oxide film does not shrink much. As a result, tensile residual stress 26 is generated in Si, and compressive residual stress is generated in the oxide film. Since the Si single crystal (epitaxial layer 22) epitaxially formed on the SiO ₂ oxide film (insulating film 14) has high adhesion to SiO ₂ , there is little possibility that the stress is relieved by peeling of the two. 4A, a structure in which an oxide film (insulating film 14) is clamped by a single-crystal Si ring composed of an epitaxially formed Si layer (epitaxial layer 22) and a Si substrate 11. It has become. Therefore, even if Si and SiO ₂ are peeled off, the residual stress 26 remains mechanically. When roughly estimating the magnitude of the lattice strain due to the residual stress 26, for example, if epitaxial film formation is performed by the CVD method at 1050 ° C. and the temperature is returned to room temperature, a temperature difference of about 1000 ° C. is generated. Since the difference in thermal expansion coefficient between the oxide film and Si is in the range of 1 × 10 ⁻⁶ / K, when 1000 K is applied to this, 1 × 10 ⁻³ units of lattice distortion remain. This number is almost equivalent to the amount of strain obtained in the SiGe / Si system.

  Subsequently, using a mask (not shown), B ions are implanted into a region where the channel of the n-channel MOSFET is formed to obtain a p-type channel region 28 shown in the cross-sectional view of FIG. The dose amount of B ions is adjusted to match the desired Vth. It is desirable that the surface of the epitaxial layer 22 be subjected to dilute hydrofluoric acid treatment or light RCA cleaning before or after the B ion implantation. This is because a gate insulating film is formed later on the surface of the epitaxial layer 22, but if a gate insulating film is formed on the surface immediately after a mechanical process called CMP, reliability may be lowered. is there.

  Next, as shown in the cross-sectional view of FIG. 4C, a gate insulating film 30 is formed on the surface region of the epitaxial layer 22, and then a polysilicon gate electrode 32 is formed by a technique such as CVD. The gate insulating film 30 is generally a thermal oxide film. When thermal oxidation is performed, Si in the surface region of the epitaxial layer 22 is consumed by oxidation, the thickness of the SOI region is further reduced, and a portion receiving a stronger tensile stress becomes a channel, which is convenient. However, deposition-type oxide films such as HTO have also been improved in reliability in recent years, and HTO may be used because it exhibits performance comparable to a thermal oxide film even when used as the gate insulating film 30. . In this embodiment, the gate insulating film 30 is formed by thermal oxidation.

  Subsequently, the polysilicon gate electrode 32 and the gate insulating film 30 other than the channel region are appropriately removed, and As or P ions are implanted in a self-aligned manner, as shown in the cross-sectional view of FIG. An n + type semiconductor region 34 to be a drain region is formed. During the annealing for activating the impurities in the source / drain regions, the n + type semiconductor region 34 is electrically connected to the n + type wiring region 20 by diffusion of As ions and P ions (FIG. 5). (See (A)). Next, according to a normal MOSFET forming method, as shown in FIG. 5A, the interlayer insulating film 36 and the extraction electrode 38 are formed, and the strained Si-MOSFET 10 is completed.

  For reference, a perspective view of FIG. 5B shows a state where the interlayer insulating film 36 and the extraction electrode 38 are removed from the strained Si-MOSFET 10 of FIG. 5A. Electrical wiring between neighboring FETs can be performed using the n + type wiring region 20 (or n + type semiconductor region 34). However, the connection between the FETs that are so far apart that the wiring resistance of the n + -type wiring region 20 cannot be ignored may be made by bringing the extraction electrode 38 into contact.

  According to the present embodiment, the magnitude of the tensile stress is determined by the difference in thermal expansion coefficient between the Si single crystal and the insulating film 14 and the temperature difference between the epitaxial film formation temperature at the time of forming the SOI region and room temperature. At this time, the coefficient of thermal expansion of the Si single crystal and the insulating film 14 is a physical property value and therefore does not vary. Specifically, it is considered realistic to use a thermal oxide film, HTO, nitride film or the like as the insulating film 14, but the thermal oxide film has a stable composition and has physical properties such as a thermal expansion coefficient. It is unlikely that the values will vary. In addition, since HTO and nitride films can be formed with a stable composition in recent years, it is considered that physical property values such as thermal expansion coefficient are also stable. On the other hand, since the film forming temperature can be accurately measured with a thermocouple or pyrometer, the variation between wafers or lots can be kept within 5 ° C. at the maximum. In the present invention, the tensile stress at room temperature applied to the SOI region is defined by the parameters described above, so that there are very few factors that cause variations and instabilities. Therefore, according to the present invention, it is possible to produce a strained Si-MOSFET 10 having more stable electrical characteristics than a strained Si-MOSFET using a conventional SiGe / Si system with high throughput and low cost.

Thus, according to the first embodiment, there are the following effects.
(1) Since the strained Si-MOSFET 10 is formed without using any Ge element, the process can be simplified and the operation can be stabilized and the cost can be reduced.
(2) Since the thickness of Si in the SOI region can be accurately defined by the step d between the insulating films 12 and 14, the amount of lattice distortion in the channel region is also stabilized, and variations in electrical characteristics can be suppressed.
(3) Since the magnitude of the tensile stress is determined by the difference in thermal expansion coefficient between the Si single crystal and the insulating film and the difference between the film formation temperature and room temperature (room temperature), there are few factors that cause variation and instability, The strained Si-MOSFET 10 having stable electrical characteristics can be manufactured with high throughput and low cost.

  Next, Embodiment 2 of the present invention will be described with reference to FIG. In addition, the same code | symbol shall be used for the component which is the same as that of Example 1 mentioned above, or respond | corresponds (it is the same also about a following example). In the first embodiment described above, when the n + type wiring region 20 is unnecessary and obstructive, the As ion implantation process in which the n + type wiring region 20 is formed in the above embodiment may be omitted. If stronger insulation is required to isolate the FETs, as shown in FIG. 6A, an oxide film 40 may be formed and insulated by implanting oxygen ions between the FETs. . Alternatively, insulation may be achieved by a method such as digging a trench and embedding an insulating material. When each FET is isolated and used as in the present embodiment, the FET is orthogonal to the stripe defined by the window opening 18 as shown in FIG. The source / gate / drain may be formed side by side in a direction parallel to the stripe.

  Next, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 6B is a main cross-sectional view showing a single vertical power MOSFET 50 according to the present embodiment. A p-type or p + -type semiconductor region is interposed on the upper surface side of the n − -type semiconductor region 52 with an insulating film 14 interposed therebetween. A state in which 54 is formed is shown. A source electrode 56 and a drain electrode 58 are also formed. In such a single vertical power MOSFET 50 as well, the channel portion is formed with a thickness of 200 nm or less as in the above-described embodiment, thereby increasing the mobility of the channel portion and contributing to low ion resistance. Is possible.

  Next, Embodiment 4 of the present invention will be described with reference to FIG. In Example 2 described above, when the electric potential of the Si substrate 11 underlying the insulating film 14 has a non-negligible influence on the electrical characteristics and the insulation is desired, the Si substrate 11 is ground back from the back surface and shaved. The thickness of the Si substrate 11 is driven to 60 μm or less to obtain a thin wafer. After thinning, the oxide film 60 shown in FIG. 6C may be formed by selectively oxidizing only the back surface. By doing so, the potential of the Si substrate 11 can be ignored. Note that the Si substrate may be insulated by ion implantation instead of selective oxidation.

In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) The resist and the elements used for ion implantation shown in the above-described embodiments are examples, and can be appropriately changed so as to achieve the same effect.
(2) The shapes and dimensions shown in the above embodiments are also examples, and may be appropriately changed so as to achieve the same effect. Further, the number of FETs built in the window opening portion 12A is arbitrary, and may be increased or decreased as appropriate.

  (3) The manufacturing procedure and manufacturing conditions shown in the above embodiment are examples, and may be appropriately changed so as to achieve the same effect. For example, in the above-described embodiment, the main surface of the Si substrate is the (100) plane or a plane equivalent thereto, and the surface exposed portion for performing the epitaxial growth is oriented to <010> or an equivalent orientation thereof. It was decided that it was a stripe shape. However, when the principal surface of the Si substrate 11 is a (111) plane or a plane equivalent thereto, and the stripe direction of the window opening 18 is set to <1-1-2> or an equivalent direction, the epitaxial layer 22 is It extends well in the horizontal direction and does not extend much in the vertical direction, and the epitaxial film formation time can be reduced when forming the SOI structure. Further, the fact that the epitaxial layer 22 does not extend so much in the vertical direction means that the amount of polishing can be reduced in the CMP polishing performed using the insulating film 12 or 14 as a stopper, so that the time required for the CMP process can be reduced and the CMP apparatus can be reduced. There is also an advantage that the wear parts of this type also last longer. In the first embodiment, the thickness of the Si layer in the SOI region is defined by the step d of the insulating film. However, this is also an example, and the thickness is reduced by the film thickness management or time management by CMP polishing. The epitaxial layer 22 of about 200 nm may be left.

  (4) In the above embodiment, the present invention is applied to a transistor. However, according to the present invention, an IGBT having a known MOS gate structure using lateral epitaxial growth or a MOS structure portion of an insulated gate type thyristor is formed according to the present invention. If it is formed with a thickness of 200 nm or less, the mobility of the channel portion is increased, and low ion resistance can be achieved.

  According to the present invention, the epitaxial growth technique on the insulating layer (insulating film) is used, and the thickness of the Si layer in the SOI region is controlled to suppress variation in electrical characteristics. In addition, since the tensile stress is introduced into the Si layer by utilizing the difference in thermal expansion coefficient between Si and the insulating layer and the temperature difference between the deposition temperature and room temperature (or room temperature), strained Si is used as the channel. It is suitable for the use of a semiconductor device.

It is a figure which shows an example of the manufacturing process of Example 1 of this invention. It is a figure which shows an example of the manufacturing process of the said Example 1. FIG. It is a figure which shows an example of the manufacturing process of the said Example 1. FIG. It is a figure which shows an example of the manufacturing process of the said Example 1. FIG. It is a figure which shows an example of the manufacturing process of the said Example 1. FIG. It is principal sectional drawing of the other Example of this invention.

Explanation of symbols

10: Strained Si-MOSFET
11: Si substrate
12, 14: Insulating film (or insulating mask)
12A, 18: Window opening 16: Resist 20: n + type wiring region 22: Epitaxial layer 24: V-shaped 26: Residual stress 28: p-type channel region 30: Gate insulating film 32: Polysilicon gate electrode 34: n + type Semiconductor region 36: Interlayer insulating film 38: Lead metal 40: Oxide film 50: Vertical power MOSFET
52: n− type semiconductor region 54: p type or p + type semiconductor region 56: source electrode 58: drain electrode 60: oxide film 62: dislocation (crystal defect)

Claims (6)

Forming an insulating layer having a thermal expansion coefficient different from that of the Si substrate on the surface of the Si substrate;
Opening the insulating layer and forming a surface exposed portion connected in a substantially comb shape on the surface of the Si substrate;
Forming an n + -type or p + -type low-resistance region on the substantially comb-shaped surface exposed portion of the Si substrate;
A step of subjecting the Si substrate to high temperature epitaxial growth from the exposed surface of the Si substrate in the upward direction and then high temperature epitaxial growth in the lateral direction to cover the insulating layer;
Polishing the epitaxially grown Si layer, forming an SOI region in which the thickness of the Si layer covering the insulating layer is 200 nm or less, and forming a Si layer on the surface exposed portion of the Si substrate ;
The Si layer provided on both sides of the SOI region to be a channel region, by forming the source and drain regions of the low-resistance region the same conductivity type, having the channel region, the source region and the drain region thereby forming a plurality of MOSFET, the connected low-resistance region electrically by annealing to activate the source and drain regions, the source region and between the drain of the MOSFET adjacent to the gate width direction of the plurality of MOSFET The process of connecting the areas together,
Including
The method of manufacturing a semiconductor device according to claim Tei Rukoto cause distortion due to thermal expansion coefficient difference between the insulating layer and the Si layer in the channel region.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the low resistance region is formed by ion implantation into a surface exposed portion of the Si substrate. Forming a step in the insulating layer formed on the surface of the Si substrate;
Including
3. The method of manufacturing a semiconductor device according to claim 1, wherein in the polishing step, the thickness of the Si layer in the SOI region is controlled using the step.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the Si layer in the SOI region is controlled by film thickness management by CMP polishing or time management.   The method for manufacturing a semiconductor device according to claim 1, wherein the epitaxial growth is performed at 800 ° C. or higher. Wherein Si is the main surface is (100) plane or an equivalent plane of the substrate, the stripe direction of the surface exposed portion for performing the epitaxial growth, and characterized by a <010> or equivalent person position A method for manufacturing a semiconductor device according to claim 1.

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