JP4473775B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device characterized by an insulating structure between wirings and a manufacturing method thereof.

  Improvement of LSI performance can be basically achieved by increasing the degree of integration of elements, that is, by miniaturizing elements. However, when the degree of integration of the elements becomes extremely high, the capacitance between the wirings increases, so that it is not easy to improve the performance (high-speed operation or the like) of the LSI.

  Therefore, in an ultra-large scale integrated circuit (ULLSI) such as a microprocessor, it is indispensable to reduce the parasitic resistance and parasitic capacitance of the internal wiring of the integrated circuit in order to achieve improvement in performance.

  Reduction of the parasitic resistance of the internal wiring can be achieved by configuring the internal wiring with a material having a low resistivity. At present, research is being conducted on the use of copper, which has a resistivity of 30% or more lower than that of an aluminum alloy, for the internal wiring instead of the aluminum alloy.

  The parasitic capacitance of the internal wiring has two components.

  The first is a capacitance generated between wirings existing at different levels, that is, a capacitance generated between upper and lower wirings. This capacitance can be reduced by increasing the thickness of the interlayer insulating film formed on the lower wiring.

  The second is a capacitance generated between wirings existing at the same level, that is, a capacitance generated between the left and right wirings. This capacity can be achieved by widening the wiring interval and reducing the wiring thickness.

  However, if the wiring interval is widened, the degree of integration of the elements will be reduced, and if the wiring thickness is reduced, the wiring resistance will increase, so that the performance of the LSI cannot be improved.

  Therefore, at present, in order to reduce the parasitic capacitance of the internal wiring, the use of a low dielectric constant ε for the insulating layer between the wirings has been studied.

  FIG. 233 shows a semiconductor device having a structure in which an insulating layer having a low dielectric constant ε is filled between wirings.

  An insulating layer 12 is formed on the semiconductor substrate 11. The wiring 13 is disposed on the insulating layer 12. A plasma TEOS layer 14 containing fluorine is formed between the wirings 13 and on the wirings 13.

  The plasma TEOS layer 14 containing fluorine has a dielectric constant ε of about 3.3, and the dielectric constant ε is reduced by about 15% compared to the plasma TEOS layer containing no fluorine.

  However, with the recent increase in the degree of integration of elements, the improvement in LSI performance cannot be achieved unless the dielectric constant ε between wirings is 3.3 or less.

  Thus, conventionally, in order to improve the performance of an LSI, it is essential to reduce the dielectric constant of the insulating layer between the wirings. However, since it is very difficult to reduce the dielectric constant of the insulating layer to 3.3 or less, the dielectric constant of the insulating layer is an obstacle to improving the performance of the LSI as the degree of integration of the device advances. .

  On the other hand, in recent years, attempts have been made to reduce the parasitic capacitance between wirings by making a space between wirings existing at the same level.

  Japanese Patent Application Laid-Open No. H10-228561 discloses a technique for making a space between wirings existing at the same level. The feature of this technique is that the ice film previously filled between the wirings is evaporated.

  However, this technique has the following drawbacks because it utilizes the phase transition of the material. First, volume expansion occurs when water between wirings is frozen, which adversely affects the wiring. This defect is caused by embedding the material using phase transition after forming the wiring, and is not limited to the ice film but occurs for all materials shown in the literature. Second, when the ice film is polished by CMP (Chemical Mechanical Polishing), all of the ice film may be melted by frictional heat. Third, it is necessary to perform all the steps before evaporation of the solid film at a low temperature (in the case of an ice film, less than 0 degrees Celsius), which makes handling of the wafer difficult.

Further, in this technique, water vapor is filled in the cavities between the wirings. Therefore, the water vapor causes short circuit and corrosion of the wiring, and adversely affects the reliability of the wiring. Furthermore, since this technology does not disclose a technology for making a space between wires existing at different levels, reduction of parasitic capacitance between wires is not necessarily sufficient.
JP 7-45701 A JP-A-2-218150

  In an example of the present invention, a technique is proposed that achieves an improvement in device integration and LSI performance at the same time by filling a gas that has a low dielectric constant between wires and does not adversely affect the wires.

A semiconductor device according to an example of the present invention includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of first wirings formed on the first insulating layer, and the plurality of the plurality of first wirings. A second insulating layer formed on the plurality of first wirings so that a space containing oxygen is formed between the first wirings; and the second insulating layer on the plurality of first wirings. A plurality of first contact holes formed respectively, a plurality of columnar conductive layers formed in and on the plurality of first contact holes, and between the plurality of conductive layers contain oxygen. A third insulating layer formed on the plurality of conductive layers so as to form a cavity, and a plurality of second contact holes respectively formed on the third insulating layer on the plurality of conductive layers; the plurality of second contact hole and the upper, respectively further to the third insulating layer A plurality of second wiring made, a fourth insulating layer between the plurality of the second wiring is formed on the second wiring of said plurality such that the cavity containing oxygen.

  A method for manufacturing a semiconductor device according to an example of the present invention includes a step of forming a first insulating layer on a semiconductor substrate, a step of forming a first solid layer on the first insulating layer, and the first Forming a plurality of first grooves in the solid layer, forming a plurality of first wirings by embedding a first conductor in the plurality of first grooves, and the first solid Forming a second insulating layer having a property of transmitting oxygen on the layer and the plurality of first wirings; and transmitting the oxygen through the second insulating layer to form the first solid layer Oxidizing the first solid layer by reacting and converting the first solid layer into a first gas layer; forming a second solid layer on the second insulating layer; Forming a plurality of first contact holes reaching the plurality of first wirings in the second solid layer and the second insulating layer. Forming a plurality of columnar conductive layers by embedding a second conductor in the plurality of first contact holes, on the second solid layer, and on the plurality of conductive layers Forming a third insulating layer having a property of allowing oxygen to permeate, forming a third solid layer on the third insulating layer, and forming a plurality of second layers on the third solid layer. Forming a plurality of grooves, forming a plurality of second contact holes reaching the plurality of conductive layers in the third insulating layer, and forming the plurality of second contact holes in the plurality of second grooves and the plurality of second layers. A step of embedding a third conductor in the two contact holes to form a plurality of second wirings, and allowing the oxygen to permeate over the third solid layer and the plurality of second wirings. Forming a fourth insulating layer having properties, and transmitting the oxygen through the third and fourth insulating layers. And reacting with the second and third solid layers to oxidize the second and third solid layers and converting the second and third solid layers into second and third gas layers. With.

  A method for manufacturing a semiconductor device according to an example of the present invention includes a step of forming a first insulating layer on a semiconductor substrate, a step of forming a first solid layer on the first insulating layer, and the first Forming a plurality of first grooves in the solid layer, forming a plurality of first wirings by embedding a first conductor in the plurality of first grooves, and the first solid Forming a second insulating layer having a property of transmitting oxygen on the layer and the plurality of first wirings; and transmitting the oxygen through the second insulating layer to form the first solid layer Oxidizing the first solid layer by reacting and converting the first solid layer into a first gas layer; forming a second solid layer on the second insulating layer; Forming a third insulating layer having a property of transmitting oxygen on the second solid layer; and on the third insulating layer. A step of forming a third solid layer; a step of forming a plurality of second grooves in the third solid layer; the third insulating layer; the second solid layer; and the second insulating layer. Forming a plurality of contact holes reaching the plurality of first wirings, and embedding a second conductor in the plurality of second grooves and the plurality of contact holes. Forming a second wiring and a plurality of columnar conductive layers simultaneously, and forming a fourth insulating layer having a property of transmitting oxygen on the third solid layer and the plurality of second wirings; And oxidizing the second and third solid layers by allowing the oxygen to pass through the third and fourth insulating layers and reacting with the second and third solid layers, and to oxidize the second and third solid layers. And converting the third solid layer into second and third gas layers.

  According to the example of the present invention, by filling a gas that has a low dielectric constant between the wirings and does not adversely affect the wirings, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

  FIG. 1 shows a semiconductor device according to the first embodiment of the present invention.

  An insulating layer (for example, silicon oxide layer) 12 is formed on the semiconductor substrate (for example, silicon wafer) 11. The wiring 13 is disposed on the insulating layer 12. The wiring 13 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

A plate-like insulating layer (for example, silicon oxide layer) 14 that does not fill between the wirings 13 is formed on the wirings 13 using the wirings 13 as columns. That is, a space (cavity) 15 is formed between the wirings 13. The cavity 15 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

The concentration of carbon dioxide CO ₂ gas in the cavity is at least higher than the concentration of carbon dioxide gas in the air (atmosphere). Further, the cavity 15 may be filled with air by making the cavity 15 contact with air at the time of manufacture, or by providing a hole in the package.

According to the semiconductor device having the above configuration, the space between the wirings 13 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings 13 is filled with an insulating layer such as a silicon oxide layer. Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 1 will be described.

  First, as shown in FIG. 2, the insulating layer 12 is formed on the semiconductor substrate 11. A carbon (carbon) layer 16 is formed on the insulating layer 12 by sputtering or the like. Here, the thickness of the carbon layer 16 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 17 is formed on the carbon layer 16 by sputtering or CVD. Here, when the mask material 17 is made of an oxide, the mask material 17 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 16 may disappear due to oxygen contained in the reaction gas.

  Next, a resist is applied on the mask material 17, and this resist is patterned by using PEP (Photo Etching Process). Further, the mask material 17 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, the carbon layer 16 is etched by anisotropic etching using the mask material 17 as a mask, and a groove is formed in the carbon layer 16.

  The carbon layer 16 may be etched using a resist as a mask.

The resist is peeled off with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . This is because the resist can be removed by oxygen plasma treatment, but if the oxygen plasma treatment is used, the carbon layer 16 also disappears.

  Next, as shown in FIG. 3, a conductive layer made of copper or the like is formed on the entire surface of the semiconductor substrate 11 by a CVD method or a sputtering method. The conductive layer is left only in the groove between the carbon layers 16 by chemical mechanical polishing (CMP), and the wiring 13 is formed.

  Note that the wiring 13 may be formed by using anisotropic etching or isotropic etching instead of CMP.

  Thereafter, the mask material 17 is peeled off.

Next, as shown in FIG. 4, an insulating layer (for example, silicon oxide layer) 14 is formed on the wiring 13 and the carbon layer 16 by sputtering. Here, when the insulating layer 14 is an oxide such as a silicon oxide layer, it is better not to use the CVD method. This is because the oxygen gas O ₂ is contained in the reaction gas, so that the carbon layer 16 may be removed when the insulating layer 14 is formed.

Next, as shown in FIGS. 5 and 6, the carbon layer 16 is ashed, and the carbon layer 16 is converted into a cavity 15 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layer 16 is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). This method has the advantage of preventing the burst of the insulating layer 14 due to the expansion of the volume of the carbon layer 16 because the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds slowly, but has the disadvantage that the processing time becomes long. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 14 may burst due to the expansion of the volume of the carbon layer 16. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 14 or decreasing the temperature of the oxygen plasma treatment.

  It should be noted that the cavity 15 may be filled with air by making the cavity 15 come into contact with air at the time of manufacture or by providing a hole in the package.

  According to the above method, a carbon layer is used as an insulating layer having a groove for forming a wiring, and after the wiring is formed in the groove, the carbon layer is ashed to be converted into a gas-filled cavity. ing. Therefore, the semiconductor device of FIG. 1 can be easily provided.

  FIG. 7 shows a semiconductor device according to the second embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 includes metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b that cover the bottom and side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  It should be noted that the cavities 31 and 38 may be filled with air by making the cavities 31 and 38 come into contact with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 7 will be described.

  First, as shown in FIG. 8, a field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  Next, as shown in FIG. 9, a carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  Next, as shown in FIG. 10, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer 39 to a thickness of about 0.05 μm by sputtering.

  Here, when the mask material 29 is made of an oxide, the mask material 29 is preferably formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

  Next, as shown in FIG. 11, a resist is applied on the mask material 29, and this resist is patterned by using PEP (Photo Etching Process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off. The pattern of the mask material 29 is the same as the pattern of the wiring.

  Next, as shown in FIG. 12, the carbon layer 39 is etched by anisotropic etching using the mask material 29 as a mask.

  In this embodiment, the carbon layer 39 is etched by PEP without directly etching the carbon layer 39, using the mask material 29 processed by PEP as a mask.

The reason for this is as follows. The resist used for PEP is removed by oxygen plasma treatment (asher) or a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . However, when the resist is removed by the oxygen plasma treatment, the patterned carbon layer 39 is removed at the same time. On the other hand, when the resist is removed with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ , the conductive layers (only in the case of a refractory metal) 26a and 26b are simultaneously removed.

  Therefore, when the conductive layers 26a and 26b are refractory metal, the carbon layer 39 is preferably etched using the mask material 29 processed by PEP as a mask.

  Next, as shown in FIG. 13, a barrier layer 27 made of, for example, a laminate of titanium and titanium nitride is formed on the inner surface of the wiring trench XX and on the mask material 29 by sputtering or CVD.

  Next, as shown in FIG. 14, a metal 28 made of copper, aluminum alloy, or the like is formed on the barrier layer 27 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 15, the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP) to form the wiring W1.

  Note that the wiring W1 may be formed by using anisotropic etching or isotropic etching instead of CMP.

  Next, as shown in FIG. 16, an insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering.

Here, when the insulating layer 30 is an oxide, it is better not to form the insulating layer 30 by a CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 17 and 18, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 29 and 30 can be prevented from bursting due to the expansion of the volume of the carbon layer 39, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 29 and 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 29 and 30 and decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 19, an insulating layer 32 (for example, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 20, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 21, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 22, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, the mask material 36 is patterned using PEP (photo etching process) and anisotropic etching. Further, the carbon layer is etched by anisotropic etching using the mask material 36 as a mask. For example, barrier layers 34a and 34b formed of a laminate of titanium and titanium nitride are formed by sputtering or CVD.

  Metal layers 35a and 35b made of copper, aluminum alloy, or the like are formed on the barrier layers 34a and 34b by sputtering or CVD. By chemical mechanical polishing (CMP), the barrier layers 34a and 34b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, and the wiring W2 is formed.

  Note that the wiring W2 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 37 is formed on the mask material 36 and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  It should be noted that the cavities 31 and 38 may be filled with air by making the cavities 31 and 38 come into contact with air at the time of manufacture or by providing holes in the package.

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 7 can be easily provided.

  FIG. 23 shows a semiconductor device according to the third embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 includes metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b that cover the bottom and side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  It should be noted that the cavities 31 and 38 may be filled with air by making the cavities 31 and 38 come into contact with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 23 will be described.

  First, as shown in FIG. 24, the process until the carbon layer 39 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the second embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer 39 with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material, and this resist is patterned using PEP (Photo Etching Process). Further, the mask material is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer 39 is etched by anisotropic etching using the mask material as a mask.

  The reason why the carbon layer 39 is etched by PEP without directly etching the carbon layer 39 using the mask material processed by PEP as a mask is the reason described in the manufacturing method in the second embodiment described above. Is the same.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer 39 is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer 39 is preferably etched using a resist as a mask.

  Thereafter, the mask material is removed, and a barrier layer 27 made of, for example, a laminate of titanium and titanium nitride is formed on the inner surface of the wiring trench XX and the carbon layer 39 by sputtering or CVD.

  Next, as shown in FIG. 25, a metal 28 made of copper, aluminum alloy, or the like is formed on the barrier layer 27 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 26, the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP), thereby forming the wiring W1.

  Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIG. 27, an insulating layer (for example, a silicon oxide layer) 30 is formed on the carbon layer 39 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 28 and 29, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the explosion of the insulating layer 30 due to the expansion of the volume of the carbon layer 39 can be prevented. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 30 or decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 30, an insulating layer 32 (eg, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 31, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 32, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 33, the wiring W2 is formed by the same process as that used to form the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, a resist is applied on the mask material, and this resist is patterned by using PEP (Photo Etching Process). Further, the mask material is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer is etched by anisotropic etching using the mask material as a mask.

  Further, the mask material is removed, and barrier layers 34a and 34b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD.

  Metal layers 35a and 35b made of copper, aluminum alloy, or the like are formed on the barrier layers 34a and 34b by sputtering or CVD. By chemical mechanical polishing (CMP), the barrier layers 34a and 34b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, and the wiring W2 is formed.

  Note that the wiring W2 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  It should be noted that the cavities 31 and 38 may be filled with air by making the cavities 31 and 38 come into contact with air at the time of manufacture or by providing holes in the package.

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 23 can be easily provided.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 34 shows a semiconductor device according to the fourth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed.

  However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Shelf-like insulating layers 36 and 37 are formed above the columnar conductive layers 33a and 33b. The insulating layers 36 and 37 are supported by the conductive layers 33a and 33b. A space (cavity) 40 is formed between the columnar conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the positions and cross-sectional areas of the conductive layers 33a and 33b, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when the cavity 40 is provided, and is also important as a base when further wiring is stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Note that the cavities 31 and 40 may be filled with air by contacting the cavities 31 and 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the wirings W1, and the conductive layers (contact plugs for the upper and lower wirings) 33a and 33b. Between these, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the wiring W1 and the conductive layers 33a and 33b are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 34 will be described.

  First, as shown in FIG. 35, the process until the wiring W1 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the second embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed with a thickness of about 0.05 μm on the carbon layer by sputtering.

  Further, a resist is applied on the mask material 29, and this resist is patterned by using PEP (Photo Etching Process). The mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer is etched by anisotropic etching using the mask material 29 as a mask.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layers 27a and 27b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers to form the wiring W1.

  Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

  The mask material 36 is patterned using PEP (Photo Etching Process) and anisotropic etching. Using this mask material 36 as a mask, the carbon layer 41 and the insulating layer 30 are etched by anisotropic etching. As a result, a via hole reaching the wiring W <b> 1 is formed in the carbon layer 41 and the insulating layer 30.

  Next, as shown in FIG. 36, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that other materials than the refractory metal may be embedded in the via holes of the insulating layer 30 and the carbon layer 41.

  Next, as shown in FIG. 37, an insulating layer (for example, silicon oxide layer) 37 is formed on the mask material 36 and the conductive layers 33a and 33b by sputtering. Here, the insulating layer 37 is preferably not formed by the CVD method in order to prevent the carbon layer 41 from disappearing.

  The thickness of the insulating layer 37 is in the range of 0.01 to 0.1 μm when the insulating layer 37 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 37. Good. However, the optimum thickness of the insulating layer 37 varies depending on the type and quality of the insulating layer 37.

Next, as shown in FIGS. 38 and 39, the carbon layer 41 is ashed, and the carbon layer 41 is converted into a cavity 40 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 41 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 41 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 36 and 37 can be prevented from bursting due to the expansion of the volume of the carbon layer 41, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 41 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 36 and 37 may be ruptured due to the volume expansion of the carbon layer 41. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 36 and 37 and decreasing the temperature of the oxygen plasma treatment.

  Note that the cavities 31 and 40 may be filled with air by contacting the cavities 31 and 40 with air at the time of manufacture or by providing holes in the package.

  According to the manufacturing method described above, a carbon layer is used for the insulating layer having a groove for forming the wiring W1, and after the wiring is formed in the groove, the carbon layer is ashed to form a cavity filled with gas. It has been converted.

  Further, a carbon layer is used as an insulating layer having via holes for forming conductive layers (upper and lower wiring contact plugs) 33a and 33b, and the carbon is formed after the conductive layers 33a and 33b are formed in the via holes. The layer is ashed and converted into a gas-filled cavity.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  FIG. 40 shows a semiconductor device according to the fifth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed.

  However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Shelf-like insulating layers 36 and 37 are formed above the columnar conductive layers 33a and 33b. The insulating layers 36 and 37 are supported by the conductive layers 33a and 33b. A space (cavity) 40 is formed between the columnar conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when the cavity 40 is provided, and is also important as a base when further wiring is stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Note that the cavities 31 and 40 may be filled with air by contacting the cavities 31 and 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the wirings W1, and the conductive layers (contact plugs for the upper and lower wirings) 33a and 33b. Between these, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the wiring W1 and the conductive layers 33a and 33b are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 40 will be described.

  First, as shown in FIG. 41, the process until the wiring W1 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the third embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are corroded by a chemical solution of H ₂ SO ₄ and H ₂ O _2. If the material is not used, the carbon layer is preferably etched using the resist as a mask.

  Thereafter, the mask material is removed, and barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metals 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layers 27a and 27b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers to form the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the carbon layer and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material 36, and this resist is patterned using PEP (Photo Etching Process). Further, the mask material 36 is patterned using the patterned resist as a mask.

  Thereafter, the resist is peeled off, and the carbon layer 41 and the insulating layer 30 are etched by anisotropic etching using the mask material 36 as a mask. As a result, a via hole reaching the wiring W <b> 1 is formed in the carbon layer 41 and the insulating layer 30. Thereafter, the mask material 36 is removed.

  Next, as shown in FIG. 42, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 43, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 41 and the conductive layers 33a and 33b by sputtering. Here, the insulating layer 37 is preferably not formed by the CVD method in order to prevent the carbon layer 41 from disappearing.

  The thickness of the insulating layer 37 is in the range of 0.01 to 0.1 μm when the insulating layer 37 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 37. Good. However, the optimum thickness of the insulating layer 37 varies depending on the type and quality of the insulating layer 37.

Next, as shown in FIGS. 44 and 45, the carbon layer 41 is ashed, and the carbon layer 41 is converted into a cavity 40 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 41 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 41 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 36 and 37 can be prevented from bursting due to the expansion of the volume of the carbon layer 41, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 41 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 36 and 37 may be ruptured due to the volume expansion of the carbon layer 41. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 36 and 37 and decreasing the temperature of the oxygen plasma treatment.

  Note that the cavities 31 and 40 may be filled with air by contacting the cavities 31 and 40 with air at the time of manufacture or by providing holes in the package.

  According to the manufacturing method described above, a carbon layer is used for the insulating layer having a groove for forming the wiring W1, and after the wiring is formed in the groove, the carbon layer is ashed to form a cavity filled with gas. It has been converted.

  Further, a carbon layer is used as an insulating layer having via holes for forming conductive layers (upper and lower wiring contact plugs) 33a and 33b, and the carbon is formed after the conductive layers 33a and 33b are formed in the via holes. The layer is ashed and converted into a gas-filled cavity.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 46 shows a semiconductor device according to the sixth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Insulating layers 42 and 43 are formed on the conductive layers 33a and 33b. The insulating layers 42 and 43 are supported by the conductive layers 33a and 33b. A cavity 40 is formed between the conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 42 determines the positions and cross-sectional areas of the conductive layers 33a and 33b, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 43 is important when the cavity 40 is provided between the conductive layers 33a and 33b, and is important as a base when the wiring W2 is stacked on the insulating layer 43. The insulating layer 43 is made of, for example, a silicon oxide film.

  The wiring W2 is disposed on the insulating layer 43 and connected to the conductive layers 33a and 33b. The wiring W2 includes metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b that cover the bottom and side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture, or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the conductive layers 33a and 33b, that is, between the wiring W1 and the wiring W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 46 will be described.

  First, as shown in FIG. 47, a process similar to the manufacturing method in the second embodiment is performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material 29, and the resist is patterned using a PEP (Photo Etching Process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer is etched by anisotropic etching using the mask material 29 as a mask.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metals 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layers 27a and 27b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers to form the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 42 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

  The mask material 42 is patterned using PEP (Photo Etching Process) and anisotropic etching. Using this mask material 42 as a mask, the carbon layer 41 and the insulating layer 30 are etched by anisotropic etching. As a result, a via hole reaching the wiring W <b> 1 is formed in the carbon layer 41 and the insulating layer 30.

  Next, as shown in FIG. 48, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that other materials than the refractory metal may be embedded in the via holes of the insulating layer 30 and the carbon layer 41.

Next, as shown in FIG. 49, an insulating layer (for example, a silicon oxide layer) 43 is formed on the mask material 42 and the conductive layers 33a and 33b by sputtering. Here, it is better not to form the insulating layer 43 by the CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Next, as shown in FIG. 50, the wiring W2 is formed by the same process as that used to form the wiring W1.

  That is, first, the carbon layer 44 is formed on the insulating layer 43 by sputtering. Here, the thickness of the carbon layer 44 is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer 44 with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material 36, and the resist is patterned using a PEP (Photo Etching Process). Further, the mask material 36 is patterned using the patterned resist as a mask.

  Thereafter, the resist is peeled off, and the carbon layer 44 is etched by anisotropic etching using the mask material 36 as a mask.

  For example, barrier layers 34 a and 34 b made of a laminate of titanium and titanium nitride are formed on the insulating layer 43 and the mask material 36 by sputtering or CVD.

  Metal layers 35a and 35b made of copper, aluminum alloy, or the like are formed on the barrier layers 34a and 34b by sputtering or CVD. By chemical mechanical polishing (CMP), the barrier layers 34a and 34b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, and the wiring W2 is formed.

  An insulating layer (for example, silicon oxide layer) 37 is formed on the mask material 36 and the wiring W2 by sputtering.

  When the insulating layer 37 is a silicon oxide layer, the thickness of the insulating layer 37 is in the range of 0.01 to 0.1 μm, which is convenient for ashing without rupture of the insulating layer 37. However, the optimum thickness of the insulating layer 37 varies depending on the type and quality of the insulating layer 37.

Next, as shown in FIGS. 51 and 52, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO ₂ . It converts into a cavity 40 filled with a mixed gas, and converts the carbon layer 44 into a cavity 38 filled with a mixed gas of mainly oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture, or by providing holes in the package.

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity.

  Further, a carbon layer is used as an insulating layer having via holes for forming conductive layers (upper and lower wiring contact plugs) 33a and 33b, and the carbon is formed after the conductive layers 33a and 33b are formed in the via holes. The layer is ashed and converted into a gas-filled cavity.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  FIG. 53 shows a semiconductor device according to the seventh embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

An insulating layer 43 is formed on the conductive layers 33a and 33b. The insulating layer 43 is supported by the conductive layers 33a and 33b. A cavity 40 is formed between the conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 43 is important when the cavity 40 is provided between the conductive layers 33a and 33b, and is important as a base when the wiring W2 is stacked on the insulating layer 43. The insulating layer 43 is made of, for example, a silicon oxide film.

  The wiring W2 is disposed on the insulating layer 43 and connected to the conductive layers 33a and 33b. The wiring W2 includes metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b that cover the bottom and side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture, or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the conductive layers 33a and 33b, that is, between the wiring W1 and the wiring W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 53 will be described.

  First, as shown in FIG. 54, a process similar to the manufacturing method in the third embodiment is performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material 29 is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material 29 as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, the mask material 29 is removed, and barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metals 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layers 27a and 27b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers to form the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the carbon layer and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 42 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material 42, and the resist is patterned using a PEP (Photo Etching Process). Further, the mask material 42 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer 41 and the insulating layer 30 are etched by anisotropic etching using the mask material 42 as a mask. As a result, a via hole reaching the wiring W <b> 1 is formed in the carbon layer 41 and the insulating layer 30.

  Next, as shown in FIG. 55, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole by using a selective growth method. Note that other materials than the refractory metal may be embedded in the via holes of the insulating layer 30 and the carbon layer 41.

Next, as shown in FIG. 56, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 and the conductive layers 33a and 33b by sputtering. Here, it is better not to form the insulating layer 43 by the CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Next, as shown in FIG. 57, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, the carbon layer 44 is formed on the insulating layer 43 by sputtering. Here, the thickness of the carbon layer 44 is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer 44 by sputtering to a thickness of about 0.05 μm.

  Thereafter, the mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material as a mask, the carbon layer 44 and the insulating layer 43 are etched by anisotropic etching.

  The mask material is removed, and barrier layers 34a and 34b made of, for example, a laminate of titanium and titanium nitride are formed on the inner surface of the wiring groove YY and the carbon layer 44 by sputtering or CVD.

  Metal layers 35a and 35b made of copper, aluminum alloy, or the like are formed on the barrier layers 34a and 34b by sputtering or CVD. By chemical mechanical polishing (CMP), the barrier layers 34a and 34b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, and the wiring W2 is formed.

  Note that the wiring W2 may be formed by anisotropic etching or isotropic etching instead of CMP.

  An insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 and the wiring W2 by sputtering.

  When the insulating layer 37 is a silicon oxide layer, the thickness of the insulating layer 37 is in the range of 0.01 to 0.1 μm, which is convenient for ashing without rupture of the insulating layer 37. However, the optimum thickness of the insulating layer 37 varies depending on the type and quality of the insulating layer 37.

Next, as shown in FIGS. 58 and 59, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO ₂ . It converts into a cavity 40 filled with a mixed gas, and converts the carbon layer 44 into a cavity 38 filled with a mixed gas of mainly oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture, or by providing holes in the package.

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity.

  Further, a carbon layer is used as an insulating layer having via holes for forming conductive layers (upper and lower wiring contact plugs) 33a and 33b, and the carbon is formed after the conductive layers 33a and 33b are formed in the via holes. The layer is ashed and converted into a gas-filled cavity.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 60 shows a semiconductor device according to the eighth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the conductive layers 33a and 33b, that is, between the wiring W1 and the wiring W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 60 will be described.

  First, as shown in FIG. 61, the process until the wiring W1 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the second embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  A resist is applied on the mask material 29, and the resist is patterned using a PEP (Photo Etching Process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer is etched by anisotropic etching using the mask material 29 as a mask.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layers 27a and 27b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metals 28a and 28b are left only in the grooves between the carbon layers to form the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods of patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 62, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 63, the insulating layer 30 exposed at the bottom of the trench is etched using anisotropic etching to form a via hole reaching the wiring W1.

  A barrier layer 34 composed of, for example, a laminate of titanium and titanium nitride is formed on the carbon layer 44, in a groove between the carbon layers 44, and in a via hole of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy or the like is formed on the barrier layer 34 by sputtering or CVD.

  Next, as shown in FIG. 64, the barrier layers 34a and 34b and the metal layer 35a are respectively formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41 by chemical mechanical polishing (CMP) or etching. , 35b.

  Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 65 and 66, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of steps can be greatly reduced as compared with the manufacturing methods in the second to seventh embodiments.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  FIG. 67 shows a semiconductor device according to the ninth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, cavities 40 and 43 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air are formed between the conductive layers 35a and 35b, that is, between the wirings W1 and W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device of FIG. 67 will be described.

  First, as shown in FIG. 68, the process until the wiring W1 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the third embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are corroded by a chemical solution of H ₂ SO ₄ and H ₂ O _2. If the material is not used, the carbon layer is preferably etched using the resist as a mask.

  Thereafter, the mask material is removed, and barrier layers 27a and 27b made of, for example, a laminate of titanium and titanium nitride are formed by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the barrier layer 27 by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  By chemical mechanical polishing (CMP), the barrier layers 27a and 27b and the metal layers 28a and 28b are left only in the grooves between the carbon layers, and the wiring W1 is formed. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the carbon layer and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods of patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 69, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 70, the insulating layer 30 exposed at the bottom of the trench is etched using anisotropic etching to form a via hole reaching the wiring W1.

  A barrier layer 34 composed of, for example, a laminate of titanium and titanium nitride is formed on the carbon layer 44, in a groove between the carbon layers 44, and in a via hole of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy or the like is formed on the barrier layer 34 by sputtering or CVD.

  Next, as shown in FIG. 71, barrier layers 34a and 34b and a metal layer 35a are formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41 by chemical mechanical polishing (CMP) or etching, respectively. , 35b.

  Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 72 and 73, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of steps can be greatly reduced as compared with the manufacturing methods in the second to seventh embodiments.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  74 to 76 show a semiconductor device according to the tenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metal layers 35a, 35b such as copper and aluminum alloy, and U-shaped barrier layers 34a, 34b covering the bottom and side surfaces of the metal layers 35a, 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  A ring-shaped guard ring G is formed at the edge of each chip 48 along the edge of the chip. The guard ring G includes a barrier layer 27c and a metal layer 28c formed in the cavity 31, a barrier layer 34c and a metal layer 35c formed in the cavity 38, and a conductive layer 33c formed in the insulating layers 30 and 32. It consists of.

  The barrier layer 27c and the metal layer 28c formed in the cavity 31 have the same configuration as the wiring W1, and the barrier layer 34c and the metal layer 35c formed in the cavity 38 have the same configuration as the wiring W2, and an insulating layer The conductive layer 33c formed in the layers 30 and 32 has the same configuration as the conductive layers (contact plugs) 33a and 33b.

  As shown in FIG. 77, the conductive layer 33c in the insulating layers 30 and 32 may be omitted.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip 48. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wirings W1 and W2 via the cavities 31 and 38 from the edge of the chip after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wirings W1 and W2 in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the second embodiment described above.

  78 and 79 show a semiconductor device according to the eleventh embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a, 28b such as copper and aluminum alloy, and U-shaped barrier layers 27a, 27b covering the bottom and side surfaces of the metals 28a, 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 includes metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b that cover the bottom and side surfaces of the metals 35a and 35b.

  The wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Further, a ring-shaped guard ring G is formed at the edge of each chip along the edge of the chip. The guard ring G includes a barrier layer 27c and a metal 28c formed in the cavity 31, a barrier layer 34c and a metal 35c formed in the cavity 38, and a conductive layer 33c formed in the insulating layers 30 and 32. Composed.

  The barrier layer 27c and the metal layer 28c formed in the cavity 31 have the same configuration as the wiring W1, and the barrier layer 34c and the metal layer 35c formed in the cavity 38 have the same configuration as the wiring W2, and an insulating layer The conductive layer 33c formed in the layers 30 and 32 has the same configuration as the conductive layers (contact plugs) 33a and 33b.

  79, the conductive layer 33c in the insulating layers 30 and 32 may not be provided.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip 48. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wirings W1 and W2 via the cavities 31 and 38 from the edge of the chip after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wirings W1 and W2 in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the above-described third embodiment.

  FIG. 80 shows a semiconductor device according to the twelfth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed.

  However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Shelf-like insulating layers 36 and 37 are formed above the columnar conductive layers 33a and 33b. The insulating layers 36 and 37 are supported by the conductive layers 33a and 33b. A space (cavity) 40 is formed between the columnar conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the positions and cross-sectional areas of the conductive layers 33a and 33b, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when the cavity 40 is provided, and is also important as a base when further wiring is stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  A ring-shaped guard ring G is formed at the edge of each chip 48 along the edge of the chip. The guard ring G includes a barrier layer 27 c and a metal layer 28 c formed in the cavity 31, and a conductive layer 33 c formed in the cavity 40.

  The barrier layer 27c and the metal layer 28c formed in the cavity 31 have the same configuration as the wiring W1, and the conductive layer 33c formed in the cavity 40 has the same configuration as the conductive layers (contact plugs) 33a and 33b. ing.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the wirings W1, and between the conductive layers (contact plugs of the upper and lower wirings) 33a and 33b. In addition, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the wiring W1 and the conductive layers 33a and 33b are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wiring W1 and the conductive layers 33a and 33b from the edge of the chip through the cavities 31 and 40 after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wiring W1 and the conductive layers 33a and 33b in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the above-described fourth embodiment.

  FIG. 81 shows a semiconductor device according to the thirteenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed.

  However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Shelf-like insulating layers 36 and 37 are formed above the columnar conductive layers 33a and 33b. The insulating layers 36 and 37 are supported by the conductive layers 33a and 33b. A space (cavity) 40 is formed between the columnar conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 is composed of a silicon oxide layer, a silicon nitride layer, or the like. The insulating layer 37 is important when the cavity 40 is provided, and is also important as a base when further wiring is stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Further, a ring-shaped guard ring G is formed at the edge of each chip 48 along the edge of the chip. The guard ring G includes a barrier layer 27 c and a metal layer 28 c formed in the cavity 31, and a conductive layer 33 c formed in the cavity 40.

  The barrier layer 27c and the metal layer 28c formed in the cavity 31 have the same configuration as the wiring W1, and the conductive layer 33c formed in the cavity 40 has the same configuration as the conductive layers (contact plugs) 33a and 33b. ing.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the wirings W1, and between the conductive layers (contact plugs of the upper and lower wirings) 33a and 33b. In addition, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the wiring W1 and the conductive layers 33a and 33b are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wiring W1 and the conductive layers 33a and 33b from the edge of the chip through the cavities 31 and 40 after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wiring W1 and the conductive layers 33a and 33b in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the fifth embodiment described above.

  FIG. 82 shows a semiconductor device according to the fourteenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The upper portion of the insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a refractory metal such as tungsten are formed. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

Insulating layers 42 and 43 are formed on the conductive layers 33a and 33b. The insulating layers 42 and 43 are supported by the conductive layers 33a and 33b. A cavity 40 is formed between the conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 42 determines the positions and cross-sectional areas of the conductive layers 33a and 33b, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 43 is important when the cavity 40 is provided between the conductive layers 33a and 33b, and is important as a base when the wiring W2 is stacked on the insulating layer 43. The insulating layer 43 is made of, for example, a silicon oxide film.

  The wiring W2 is disposed on the insulating layer 43 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metal layers 35a, 35b such as copper and aluminum alloy, and U-shaped barrier layers 34a, 34b covering the bottom and side surfaces of the metal layers 35a, 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Further, a ring-shaped guard ring G is formed at the edge of each chip along the edge of the chip. The guard ring G includes a barrier layer 27 c and a metal 28 c formed in the cavity 31, a barrier layer 34 c and a metal 35 c formed in the cavity 38, and a conductive layer 33 c formed in the cavity 40. .

  The barrier layer 27c and the metal 28c formed in the cavity 31 have the same configuration as the wiring W1, and the barrier layer 34c and the metal 35c formed in the cavity 38 have the same configuration as the wiring W2 and are formed in the cavity 40. The conductive layer 33c has the same configuration as the conductive layers (contact plugs) 33a and 33b.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 33a and 33b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Accordingly, it is possible to avoid a situation where moisture H ₂ O reaches the wirings W1, W2 and the conductive layers 33a, 33b from the edge of the chip through the cavities 31, 38, 40 after cutting out individual chips from the wafer.

That is, by providing the guard ring G, the wirings W1, W2 and the conductive layers 33a, 33b in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the sixth embodiment described above.

  FIG. 83 shows a semiconductor device according to the fifteenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, columnar conductive layers 33a and 33b made of a high melting point metal such as tungsten or tantalum are formed. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

An insulating layer 43 is formed on the conductive layers 33a and 33b. The insulating layer 43 is supported by the conductive layers 33a and 33b. A cavity 40 is formed between the conductive layers 33a and 33b. The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 43 is important when the cavity 40 is provided between the conductive layers 33a and 33b, and is important as a base when the wiring W2 is stacked on the insulating layer 43. The insulating layer 43 is made of, for example, a silicon oxide film.

  The wiring W2 is disposed on the insulating layer 43 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metal layers 35a, 35b such as copper and aluminum alloy, and U-shaped barrier layers 34a, 34b covering the bottom and side surfaces of the metal layers 35a, 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

  Further, a ring-shaped guard ring G is formed at the edge of each chip along the edge of the chip. The guard ring G includes a barrier layer 27 c and a metal layer 28 c formed in the cavity 31, a barrier layer 34 c and a metal layer 35 c formed in the cavity 38, and a conductive layer 33 c formed in the cavity 40. ing.

  The barrier layer 27c and the metal layer 28c formed in the cavity 31 have the same configuration as the wiring W1, the barrier layer 34c and the metal layer 35c formed in the cavity 38 have the same configuration as the wiring W2, and the cavity 40 The conductive layer 33c formed in the above has the same configuration as the conductive layers (contact plugs) 33a and 33b.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 33a and 33b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Accordingly, it is possible to avoid a situation where moisture H ₂ O reaches the wirings W1, W2 and the conductive layers 33a, 33b from the edge of the chip through the cavities 31, 38, 40 after cutting out individual chips from the wafer.

That is, by providing the guard ring G, the wirings W1, W2 and the conductive layers 33a, 33b in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the seventh embodiment described above.

  FIG. 84 shows a semiconductor device according to the sixteenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  With reference to FIG. 84, a semiconductor device according to this embodiment will be described.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  Further, a ring-shaped guard ring G is formed at the edge of each chip along the edge of the chip. The guard ring G includes a barrier layer 27c and a metal 28c formed in the cavity 31, and a barrier layer 34c and a metal 35c formed in the cavities 38 and 40.

  The barrier layer 27c and the metal 28c formed in the cavity 31 have the same configuration as the wiring W1, and the barrier layer 34c and the metal 35c formed in the cavities 38 and 40 have the same configuration as the wiring W2.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wirings W1, W2 from the edge of the chip via the cavities 31, 38, 40 after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wirings W1 and W2 in the chip can be protected against moisture H ₂ O.

  In addition, the semiconductor device in this embodiment can be easily formed by using the manufacturing method in the above-described eighth embodiment.

  FIG. 85 shows a semiconductor device according to the seventeenth embodiment of the present invention.

  This semiconductor device is formed on each of a plurality of chips 48 formed on the wafer 47 as shown in FIG.

  A semiconductor device according to this embodiment will be described with reference to FIG.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  Further, a ring-shaped guard ring G is formed at the edge of each chip along the edge of the chip. The guard ring G includes a barrier layer 27c and a metal 28c formed in the cavity 31, and a barrier layer 34c and a metal 35c formed in the cavities 38 and 40.

  The barrier layer 27c and the metal 28c formed in the cavity 31 have the same configuration as the wiring W1, and the barrier layer 34c and the metal 35c formed in the cavities 38 and 40 have the same configuration as the wiring W2.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, a ring-shaped guard ring G is formed at the edge of the chip. Therefore, it is possible to avoid a situation in which moisture H ₂ O reaches the wirings W1, W2 from the edge of the chip via the cavities 31, 38, 40 after each chip is cut out from the wafer.

That is, by providing the guard ring G, the wirings W1 and W2 in the chip can be protected against moisture H ₂ O.

  The semiconductor device in this embodiment can be easily formed by using the manufacturing method in the ninth embodiment described above.

  FIG. 86 shows a semiconductor device according to the eighteenth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove protection layers 50a and 50b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 50a and 50b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metals 35a and 35b such as copper and aluminum alloy, and U-shaped groove-shaped wiring protective layers 51a and 51b covering the bottom and side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 51a and 51b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 51a and 51b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

In addition, since at least the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31 and 38 is removed. , W2 does not reach the metal directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device of FIG. 86 will be described.

  First, as shown in FIG. 87, a field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  Next, as shown in FIG. 88, a carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  Next, as shown in FIG. 89, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed with a thickness of about 0.05 μm on the carbon layer 39 by sputtering. Here, the mask material 29 is formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

  Next, as shown in FIG. 90, a resist is applied on the mask material 29, and this resist is patterned using PEP (photo etching process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off. The pattern of the mask material 29 is the same as the pattern of the wiring.

  Next, as shown in FIG. 91, the carbon layer 39 is etched by anisotropic etching using the mask material 29 as a mask.

  In this embodiment, the carbon layer 39 is etched by PEP without directly etching the carbon layer 39, using the mask material 29 processed by PEP as a mask.

The reason for this is as follows. The resist used for PEP is removed by oxygen plasma treatment (asher) or a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . However, when the resist is removed by the oxygen plasma treatment, the patterned carbon layer 39 is removed at the same time. On the other hand, when the resist is removed with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ , the conductive layers (only in the case of a refractory metal) 26a and 26b are simultaneously removed.

  Therefore, when the conductive layers 26a and 26b are refractory metal, the carbon layer 39 is preferably etched using the mask material 29 processed by PEP as a mask.

  Next, as shown in FIG. 92, a wiring protective layer 50 made of, for example, molybdenum is formed on the insulating layer 25 and the mask material 29 by sputtering or CVD.

  Next, as shown in FIG. 93, a metal 28 made of copper, aluminum alloy, or the like is formed on the wiring protective layer 50 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 94, the wiring protective layers 50a and 50b and the metals 28a and 28b are left only in the trenches between the carbon layers 39 by chemical mechanical polishing (CMP) to form the wiring W1. .

  Note that the wiring W1 may be formed by using anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIG. 95, an insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 96 and 97, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 29 and 30 can be prevented from bursting due to the expansion of the volume of the carbon layer 39, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 29 and 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 29 and 30 and decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 98, an insulating layer 32 (eg, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 99, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 100, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 101, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, the mask material 36 is patterned using PEP (photo etching process) and anisotropic etching. Using the mask material 36 as a mask, the carbon layer is etched by anisotropic etching. For example, wiring protective layers 51 a and 51 b made of molybdenum are formed on the insulating layer 32 and the mask material 36 by sputtering or CVD.

  Metals 35a and 35b made of copper, aluminum alloy or the like are formed on the wiring protection layers 51a and 51b by sputtering or CVD. By chemical mechanical polishing (CMP), the wiring protective layers 51a and 51b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, thereby forming the wiring W2.

  Note that the wiring W2 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 37 is formed on the mask material 36 and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 86 can be easily provided.

  FIG. 102 shows a semiconductor device according to the nineteenth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove protection layers 50a and 50b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 50a and 50b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metal layers 35a and 35b such as copper and aluminum alloy, and U-shaped groove-shaped wiring protection layers 51a and 51b covering the bottom and side surfaces of the metal layers 35a and 35b.

  The wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  Further, for example, it can be composed of titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 51a and 51b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

In addition, since at least the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31 and 38 is removed. , W2 does not reach the metal directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device of FIG. 102 will be described.

  First, as shown in FIG. 103, the process until the carbon layer 39 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the eighteenth embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer 39 with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using this mask material as a mask, the carbon layer 39 is etched by anisotropic etching.

  The reason why the carbon layer 39 is etched by PEP without directly etching the carbon layer 39 using the mask material processed by PEP as a mask is the reason described in the manufacturing method in the second embodiment described above. Is the same.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer 39 is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer 39 is preferably etched using a resist as a mask.

  Thereafter, the mask material is removed, and the wiring protective layer 50 made of, for example, molybdenum is formed on the insulating layer 25 and the carbon layer 39 by sputtering or CVD.

  Next, as shown in FIG. 104, a metal layer 28 made of copper, aluminum alloy, or the like is formed on the wiring protective layer 50 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 105, the wiring protective layers 50a and 50b and the metals 28a and 28b are left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP) to form the wiring W1. .

  Note that the wiring W1 may be formed by using anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIG. 106, an insulating layer (for example, a silicon oxide layer) 30 is formed on the carbon layer 39 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 107 and 108, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the explosion of the insulating layer 30 due to the expansion of the volume of the carbon layer 39 can be prevented. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 30 or decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 109, an insulating layer 32 (for example, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 110, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 111, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 112, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, the mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. The carbon layer is etched by anisotropic etching using the mask material as a mask. The mask material is removed, and wiring protective layers 51a and 51b made of, for example, molybdenum are formed on the insulating layer 32 and the carbon layer by sputtering or CVD.

  Metal layers 35a and 35b made of copper, aluminum alloy or the like are formed on the wiring protective layers 51a and 51b by sputtering or CVD. By chemical mechanical polishing (CMP), the wiring protective layers 51a and 51b and the metal layers 35a and 35b are left only in the grooves between the carbon layers, thereby forming the wiring W2.

  Note that the wiring W2 may be formed by using anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 102 can be easily provided.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 113 shows a semiconductor device according to the twentieth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove protection layers 50a and 50b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 50a and 50b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and wiring protection layers 51a and 51b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 51a and 51b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 51a and 51b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, since at least the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31, 38 and 40 is The metal of the wiring W1, W2 does not reach directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device in FIG. 113 will be described.

  First, as shown in FIG. 114, the same processes as those in the eighteenth embodiment are performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material 29 is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material 29 as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, wiring protection layers 50a and 50b made of, for example, molybdenum are formed in the grooves formed on the mask material 29 and the carbon layer by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the wiring protective layers 50a and 50b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  By chemical mechanical polishing (CMP), the wiring protective layers 50a and 50b and the metal layers 28a and 28b are left only in the grooves between the carbon layers, thereby forming the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods of patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 115, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 116, the insulating layer 30 exposed at the bottom of the trench is removed by anisotropic etching, and a via hole reaching the wiring W1 is formed.

  A wiring protective layer 51 made of, for example, molybdenum is formed on the carbon layer 44, in a groove between the carbon layers 44, and in a via hole of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy or the like is formed on the wiring protective layer 51 by sputtering or CVD.

  Next, as shown in FIG. 117, the wiring protective layers 51a and 51b and the metals 35a and 35b are respectively formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41 by chemical mechanical polishing (CMP). To remain.

  Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 118 and 119, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of steps can be greatly reduced as compared with the manufacturing methods in the second to seventh embodiments.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  FIG. 120 shows a semiconductor device according to the twenty-first embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 includes metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove protection layers 50a and 50b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 50a and 50b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, metal layers 35a and 35b such as copper and aluminum alloy and wiring protection layers 51a and 51b covering the bottom and side surfaces of the metal layers 35a and 35b are formed. A wiring W2 is formed.

  The wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  The wiring protective layers 51a and 51b can be made of, for example, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum, an alloy thereof, molybdenum, or the like. That is, the wiring protective layers 51a and 51b may be anything as long as they are conductive, hardly corroded by chemicals, and hardly oxidized.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, since at least the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31, 38 and 40 is The metal of the wiring W1, W2 does not reach directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device of FIG. 120 will be described.

  First, as shown in FIG. 121, the same process as the manufacturing method in the nineteenth embodiment is performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are corroded by a chemical solution of H ₂ SO ₄ and H ₂ O _2. If the material is not used, the carbon layer is preferably etched using the resist as a mask.

  Thereafter, the mask material is removed, and wiring protection layers 50a and 50b made of, for example, molybdenum are formed on the insulating layer 25 and the carbon layer by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the wiring protective layers 50a and 50b by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  By chemical mechanical polishing (CMP), the wiring protective layers 50a and 50b and the metal layers 28a and 28b are left only in the grooves between the carbon layers, thereby forming the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods of patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 122, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 123, the insulating layer 30 exposed at the bottom of the trench is removed by anisotropic etching, and a via hole reaching the wiring W1 is formed.

  A wiring protective layer 51 made of, for example, molybdenum is formed on the carbon layer 44, in a groove between the carbon layers 44, and in a via hole of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy or the like is formed on the wiring protective layer 51 by sputtering or CVD.

  Next, as shown in FIG. 124, the wiring protective layers 51a and 51b and the metal layers 35a and 35a are formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41 by chemical mechanical polishing (CMP), respectively. 35b remains. Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 125 and 126, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of steps can be greatly reduced as compared with the manufacturing methods in the second to seventh embodiments.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 127 shows a semiconductor device according to the twenty-second embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metal layers 28a and 28b such as copper and aluminum alloy, and wiring protection layers 50a and 50b covering the side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 50a and 50b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metals 35a and 35b such as copper and aluminum alloy, and wiring protection layers 51a and 51b covering the side surfaces of the metals 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 51a and 51b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 51a and 51b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 36 determines the pattern of the wiring W2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

In addition, since the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31 and 38 is generated by It does not reach the W2 metal directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the side surfaces of the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device of FIG. 127 will be described.

  First, as shown in FIG. 128, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  Next, as shown in FIG. 129, a carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  Next, as shown in FIG. 130, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer 39 to a thickness of about 0.05 μm by sputtering. Here, the mask material 29 is formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

  Next, as shown in FIG. 131, the mask material 29 is patterned using PEP (photo etching process) and anisotropic etching. The pattern of the mask material 29 is the same as the pattern of the wiring.

  Next, as shown in FIG. 132, the carbon layer 39 is etched by anisotropic etching using the mask material 29 as a mask.

  In this embodiment, the carbon layer 39 is etched by PEP without directly etching the carbon layer 39, using the mask material 29 processed by PEP as a mask.

The reason for this is as follows. The resist used for PEP is removed by oxygen plasma treatment (asher) or a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . However, when the resist is removed by the oxygen plasma treatment, the patterned carbon layer 39 is removed at the same time. On the other hand, when the resist is removed with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ , the conductive layers (only in the case of a refractory metal) 26a and 26b are simultaneously removed.

  Therefore, when the conductive layers 26a and 26b are refractory metal, the carbon layer 39 is preferably etched using the mask material 29 processed by PEP as a mask.

  Next, as shown in FIG. 133, wiring protection layers 50a and 50b made of, for example, silicon oxide are formed on the insulating layer 25, the mask material 29, and the carbon layer 39 by sputtering or CVD, for example. It is formed on the side wall of the groove. Further, the wiring protection layers 50a and 50b are etched, and the wiring protection layers 50a and 50b are left only on the side walls of the grooves formed in the carbon layer 39.

  Next, as shown in FIG. 134, a metal layer 28 made of copper, aluminum alloy or the like is formed on the wiring protective layer 50 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 135, the wiring protective layers 50a, 50b and the metals 28a, 28b are left only in the trenches between the carbon layers 39 by chemical mechanical polishing (CMP) to form the wiring W1. .

  Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIG. 136, an insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 137 and 138, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 29 and 30 can be prevented from bursting due to the expansion of the volume of the carbon layer 39, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 29 and 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 29 and 30 and decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 139, an insulating layer 32 (eg, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 140, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 141, conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded only in the via hole using a selective growth method. Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 142, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) 36 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, the mask material 36 is patterned using PEP (photo etching process) and anisotropic etching. Using the mask material 36 as a mask, the carbon layer is etched by anisotropic etching.

  Wiring protection layers 51a and 51b made of, for example, silicon oxide are formed on the side walls of the carbon layer by sputtering or CVD and RIE, for example.

  Metals 35a and 35b made of copper, aluminum alloy, or the like are formed on the carbon layer and in the grooves provided in the carbon layer by sputtering or CVD. By chemical mechanical polishing (CMP), the wiring protection layers 51a and 51b and the metals 35a and 35b are left only in the grooves between the carbon layers, thereby forming the wiring W2.

  Note that the wiring W2 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 37 is formed on the mask material 36 and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 127 can be easily provided.

  FIG. 143 shows a semiconductor device according to the twenty-third embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metal layers 28a and 28b such as copper and aluminum alloy, and wiring protection layers 50a and 50b covering the side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 50a and 50b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer. In the insulating layer 32, a contact hole reaching the wiring W1 is formed.

  Conductive layers 33a and 33b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 33a and 33b may be made of a material other than the refractory metal.

  The wiring W2 is disposed on the insulating layer 32 and connected to the conductive layers 33a and 33b. The wiring W2 is composed of metals 35a and 35b such as copper and aluminum alloy, and wiring protection layers 51a and 51b covering the side surfaces of the metals 35a and 35b.

  The wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  The wiring protective layers 51a and 51b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 51a and 51b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2. A space (cavity) 38 is formed between the wirings W2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 37 is important when providing the cavities 38 between the wirings W2, and is also important as a foundation for stacking layers on the insulating layer 37. The insulating layer 37 is composed of, for example, a silicon oxide layer.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

In addition, since the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31 and 38 is generated by It does not reach the W2 metal directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the side surfaces of the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device in FIG. 143 will be described.

  First, as shown in FIG. 144, the process until the carbon layer 39 is formed on the insulating layer 25 is performed by the same method as the manufacturing method in the eighteenth embodiment described above.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer 39 with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using this mask material as a mask, the carbon layer 39 is etched by anisotropic etching.

  The reason why the carbon layer 39 is etched by PEP without directly etching the carbon layer 39 using the mask material processed by PEP as a mask is the reason described in the manufacturing method in the second embodiment described above. Is the same.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer 39 is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer 39 is preferably etched using a resist as a mask.

  Thereafter, the mask material is removed, and the wiring protective layer 50 made of, for example, silicon oxide is formed on the insulating layer 25 and the carbon layer 39 by sputtering or CVD.

  Next, as shown in FIG. 145, the wiring protection layer is etched by RIE, and the wiring protection layers 50 a and 50 b are left only on the side walls of the grooves of the carbon layer 39. A metal layer 28 made of copper, aluminum alloy, or the like is formed on the carbon layer 39 and in the groove formed in the carbon layer 39 by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  Next, as shown in FIG. 146, the wiring protective layers 50a and 50b and the metal layers 28a and 28b are left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP) to form the wiring W1. To do.

  Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIG. 147, an insulating layer (for example, silicon oxide layer) 30 is formed on the carbon layer 39 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the oxygen O ₂ gas is contained in the reaction gas when the insulating layer 30 is formed, and therefore the carbon layer 39 may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Next, as shown in FIGS. 148 and 149, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the explosion of the insulating layer 30 due to the expansion of the volume of the carbon layer 39 can be prevented. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 30 or decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 150, an insulating layer 32 (eg, TEOS containing fluorine) 32 having a low dielectric constant is formed on the insulating layer 30 by CVD.

  Next, as shown in FIG. 151, via holes reaching the wiring W1 are provided in the insulating layers 30 and 32 by using PEP (photo etching process) and RIE (reactive ion etching).

  Next, as shown in FIG. 152, conductive layers 33a and 33b made of a refractory metal such as tungsten or tantalum are embedded only in the via hole using a selective growth method.

  Note that a material other than the refractory metal may be embedded in the via holes of the insulating layers 30 and 32.

  Next, as shown in FIG. 153, the wiring W2 is formed by a process similar to the process used when forming the wiring W1.

  That is, first, a carbon layer is formed on the insulating layer 32 by sputtering. Here, the thickness of the carbon layer is set to a value equal to the thickness of the wiring W2. A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering.

  Thereafter, the mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. The carbon layer is etched by anisotropic etching using the mask material as a mask. The mask material is removed, and wiring protection layers 51a and 51b made of, for example, silicon oxide are formed on the sidewalls of the carbon layer trenches by sputtering or CVD and RIE.

  Metals 35a and 35b made of copper, aluminum alloy, or the like are formed on the carbon layer and in the groove formed in the carbon layer by sputtering or CVD. By chemical mechanical polishing (CMP), the wiring protective layers 51a and 51b and the metals 35a and 35b are left only in the trenches of the carbon layer to form the wiring W2.

An insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer and the wiring W2 by sputtering. Thereafter, the carbon layer is ashed, and the carbon layer is converted into a cavity 38 filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the above-described manufacturing method, the carbon layer is used for the insulating layer having the grooves for forming the wirings W1 and W2, and after the wiring is formed in the grooves, the carbon layer is ashed to be filled with the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 143 can be easily provided.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 154 shows a semiconductor device according to the twenty-fourth embodiment of the invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metal layers 28a and 28b such as copper and aluminum alloy, and wiring protection layers 50a and 50b covering the side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 50a and 50b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 50a and 50b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 29 determines the pattern of the wiring W1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, wiring composed of metal layers 35a and 35b such as copper and aluminum alloy and wiring protection layers 51a and 51b covering the side surfaces of the metal layers 35a and 35b. W2 is formed.

  The wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  The wiring protective layers 51a and 51b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 51a and 51b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The cavities 31, 38, 40 may be filled with air by contacting the cavities 31, 38, 40 with air at the time of manufacture or by providing holes in the package.

According to the semiconductor device having the above structure, between the wiring W1 is oxygen O ₂ and the cavity 31 of mixed gas or air-filled carbon dioxide CO ₂ is formed, between the wires W2 is oxygen O ₂ and carbon dioxide A cavity 38 filled with a mixed gas of CO ₂ or air is formed.

Furthermore, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, since the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31, 38, and 40 It does not reach the W1 and W2 metals directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the side surfaces of the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device in FIG. 154 will be described.

  First, as shown in FIG. 155, the same processes as those in the above-described twenty-second embodiment are performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material 29 is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material 29 as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using the mask material 29 processed by PEP as a mask, and the conductive layers 26a and 26b are made of a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . When the material is not corroded, the carbon layer is preferably etched using a resist as a mask.

  Thereafter, a wiring protective layer made of, for example, silicon oxide is formed on the carbon layer and in the groove formed in the carbon layer by sputtering or CVD. The wiring protective layer is etched by RIE, and the wiring protective layers 50a and 50b are left only on the sidewalls of the grooves formed in the carbon layer. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the wiring protective layer 50 by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  By chemical mechanical polishing (CMP), the wiring protection layers 50a and 50b and the metals 28a and 28b are left only in the grooves between the carbon layers, thereby forming the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods of patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 156, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 157, the insulating layer 30 exposed at the bottom of the trench is removed by anisotropic etching, and a via hole reaching the wiring W1 is formed.

  For example, wiring protection layers 51 a and 51 b made of silicon oxide are formed on the side walls of the trenches of the carbon layer 44 and the side walls of the via holes of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy, or the like is formed on the carbon layer 44, in the groove of the carbon layer 44, and in the via hole of the carbon layer 41 by sputtering or CVD.

  Next, as shown in FIG. 158, the wiring protective layers 51a and 51b and the metals 35a and 35b are respectively formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41 by chemical mechanical polishing (CMP). To remain. Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 159 and 160, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of manufacturing steps can be reduced.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  FIG. 161 shows a semiconductor device according to the twenty-fifth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and connected to the conductive layers 26a and 26b. The wiring W1 is composed of metal layers 28a and 28b such as copper and aluminum alloy, and wiring protection layers 50a and 50b covering the side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  The wiring protective layers 50a and 50b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 50a and 50b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1. A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 30 is important when the cavities 31 are provided between the wirings W1, and is also important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  In the insulating layer 30, a contact hole reaching the wiring W1 is formed. In the contact hole and on the contact hole, wiring composed of metal layers 35a and 35b such as copper and aluminum alloy and wiring protection layers 51a and 51b covering the side surfaces of the metal layers 35a and 35b. W2 is formed.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  The wiring protective layers 51a and 51b can be made of, for example, an insulator such as silicon oxide or silicon nitride, titanium nitride, an alloy of titanium and tungsten, a transition metal such as platinum or an alloy thereof, or molybdenum. That is, the wiring protective layers 51a and 51b may be anything as long as they are hardly corroded by chemicals and hardly oxidized.

  An insulating layer (for example, a silicon oxide layer) 43 is formed between the upper and lower portions of the wiring W2. The insulating layer 43 is supported by the wiring W2. The lower portion of the wiring W2 has a columnar shape, and the upper portion of the wiring W2 has a linear shape and is disposed on the insulating layer 43.

An insulating layer (for example, silicon oxide layer) 37 is formed on the wiring W2. A space (cavity) 40 is formed between the lower portions of the wiring W2 (between the upper and lower wirings W1 and W2). The cavity 40 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

A space (cavity) 38 is formed between the upper portions of the wiring W2 (between the left and right wirings W2). The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

Further, a cavity 40 filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ is formed between the conductive layers 35a and 35b, that is, between the wiring W1 and the wiring W2.

  The mixed gas has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

Further, since the side surfaces of the wirings W1 and W2 are covered with the wiring protection layers 50a and 50b; 51a and 51b, the moisture H ₂ O that has entered from the edge of the chip through the cavities 31, 38, and 40 It does not reach the W1 and W2 metals directly.

Therefore, the individual wirings W1 and W2 can be protected from moisture H ₂ O.

  Further, if the package on which the semiconductor device (chip) in this embodiment is mounted is provided with a hole for connecting the outside and inside of the package, the cavities 31 and 38 are filled with air. As the air circulates, the heat generated in the chip is efficiently discharged to the outside of the package.

  Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, since the side surfaces of the wirings W1, W2 are covered with the wiring protective films 50a, 50b; 51a, 51b, hillocks are hardly generated in the wirings W1, W2.

  Next, a method for manufacturing the semiconductor device of FIG. 161 will be described.

  First, as shown in FIG. 162, the same process as that in the above-described twenty-third embodiment is performed until the wiring W1 is formed on the insulating layer 25.

  That is, the field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  A carbon (carbon) layer is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer is set to a value (for example, about 0.7 to about 0.2 μm) equal to the thickness of the internal wiring of the LSI.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) is formed on the carbon layer with a thickness of about 0.05 μm by sputtering. The mask material is patterned using PEP (Photo Etching Process) and anisotropic etching. Using the mask material as a mask, the carbon layer is etched by anisotropic etching.

  The reason why the carbon layer is etched by using PEP as a mask without directly etching the carbon layer by PEP is the same as the reason described in the manufacturing method in the second embodiment. It is.

Therefore, when the conductive layers 26a and 26b are refractory metals, the carbon layer is etched using a mask material processed by PEP as a mask, and the conductive layers 26a and 26b are corroded by a chemical solution of H ₂ SO ₄ and H ₂ O _2. If the material is not used, the carbon layer is preferably etched using the resist as a mask.

  Thereafter, the mask material is removed, and wiring protective layers 50a and 50b made of, for example, silicon oxide are formed on the side walls of the groove formed in the carbon layer by sputtering or CVD. Metal layers 28a and 28b made of copper, aluminum alloy or the like are formed on the carbon layer and in the grooves formed in the carbon layer by sputtering or CVD.

  The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten or tantalum.

  By chemical mechanical polishing (CMP), the wiring protection layers 50a and 50b and the metals 28a and 28b are left only in the grooves between the carbon layers, thereby forming the wiring W1. Note that the wiring W1 may be formed by anisotropic etching or isotropic etching instead of CMP.

An insulating layer (for example, silicon oxide layer) 30 is formed on the mask material 29 and the wiring W1 by sputtering. Here, it is better not to form the insulating layer 30 by the CVD method. This is because the reaction gas used to form the insulating layer 30 contains oxygen O ₂ gas, and thus the carbon layer may be removed when the insulating layer 30 is formed.

  In addition, the thickness of the insulating layer 30 is in the range of 0.01 to 0.1 μm when the insulating layer 30 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 30. Good. However, the optimum thickness of the insulating layer 30 varies depending on the type and quality of the insulating layer 30.

Thereafter, the carbon layer is incinerated, and the carbon layer is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  After forming the wiring W1 by the above process, the carbon layer 41 is formed on the insulating layer 30 by sputtering. Further, an insulating layer (for example, a silicon oxide layer) 43 is formed on the carbon layer 41 with a thickness of about 0.05 μm by sputtering.

The insulating layer 43 should not be formed by a CVD method. This is because the reaction gas used to form the insulating layer 43 contains oxygen O ₂ gas, and therefore the carbon layer 41 may be removed when the insulating layer 43 is formed.

  In addition, the thickness of the insulating layer 43 is in the range of 0.01 to 0.1 μm when the insulating layer 43 is a silicon oxide layer, which is convenient for ashing without rupture of the insulating layer 43. Good. However, the optimum thickness of the insulating layer 43 varies depending on the type and quality of the insulating layer 43.

  Subsequently, a carbon layer 44 is formed on the insulating layer 43 by sputtering.

  Thereafter, the carbon layer 44 is patterned, and a groove for forming a wiring is provided in the carbon layer 44. There are two methods for patterning the carbon layer 44: a method using PEP (Photo Etching Process) and RIE, and a method of patterning a mask material processed by PEP and RIE into a mask.

  In this embodiment, a method using PEP and RIE will be described. That is, a resist 45 is formed on the carbon layer 44. After patterning the resist 45, the carbon layer 44 is etched by anisotropic etching using the resist 45 as a mask to form a groove in the carbon layer 44.

Thereafter, the resist 45 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 44 to disappear, this oxygen plasma treatment is not used for the removal of the resist 45.

  Next, as shown in FIG. 163, a resist 46 is formed again on the carbon layer 44. After the resist 46 is patterned, the insulating layer 43 and the carbon layer 41 exposed at the bottom of the groove are etched by anisotropic etching using the resist 46 as a mask.

Thereafter, the resist 46 is removed using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . Since the oxygen plasma treatment causes the carbon layer 46 to disappear, the oxygen plasma treatment is not used for removing the resist 46.

  Next, as shown in FIG. 164, the insulating layer 30 exposed at the bottom of the groove is etched by anisotropic etching to form a via hole reaching the wiring W1 at a part of the bottom of the groove.

  For example, wiring protection layers 51 a and 51 b made of silicon oxide are formed on the side walls of the trenches of the carbon layer 44 and the side walls of the via holes of the carbon layer 41 by sputtering or CVD. Further, a metal layer 35 made of copper, aluminum alloy, or the like is formed on the carbon layer 44, in the groove of the carbon layer 44, and in the via hole of the carbon layer 41 by sputtering or CVD.

  Next, as shown in FIG. 165, the wiring protective layers 51a and 51b and the metal layers 35a and 35a are formed in the grooves between the carbon layers 44 and in the via holes of the carbon layer 41, respectively, by chemical mechanical polishing (CMP). 35b remains. Further, an insulating layer (for example, silicon oxide layer) 37 is formed on the carbon layer 44 to a thickness of about 0.05 μm by sputtering.

  The thickness of the insulating layers 37 and 43 is in the range of 0.01 to 0.1 μm when the insulating layers 37 and 43 are silicon oxide layers, but is ashed without rupture of the insulating layers 37 and 43. Convenient to do. However, the optimum thickness of the insulating layers 37 and 43 differs depending on the type and quality of the insulating layers 37 and 43, respectively.

Next, as shown in FIGS. 166 and 167, the carbon layers 41 and 44 are simultaneously ashed by heat treatment or oxygen plasma treatment in an oxygen atmosphere, and the carbon layer 41 is mainly composed of oxygen O ₂ and carbon dioxide CO _2. And the carbon layer 44 is converted into a cavity 38 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves or via holes for forming the wirings W1 and W2, and the carbon layer is formed after the wirings are formed in the grooves and the via holes. It is converted into a cavity filled with gas by ashing.

  Further, since the wiring W2 is directly connected to the wiring W1 without using a contact plug, the number of manufacturing steps can be reduced.

Thus, in the semiconductor device with a multilayer wiring structure, satisfy the same layer (left and right) mixed gas or air oxygen O ₂ and carbon dioxide CO ₂ in the wiring between and oxygen O ₂ between the wirings of different layers (up and down) And carbon dioxide CO ₂ mixed gas or air.

  The mask material is removed after patterning the carbon layer and before ashing the carbon layer. Therefore, ashing of the carbon layer can be performed quickly and accurately.

  FIG. 168 shows a semiconductor device according to the twenty-sixth embodiment of the present invention.

  An insulating layer 25 is formed on the semiconductor substrate (for example, a silicon wafer) 21. On the insulating layer 25, a wiring W1 is formed. The wiring W1 includes, for example, metals 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metals 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

  The interval between the adjacent wirings W1 is H. When this interval H is very wide, a dummy wiring D1 is formed between the wirings W1.

  The dummy wiring D1 is composed of, for example, metal layers 28d and 28d such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27d and 27d covering the bottom and side surfaces of the metal layers 28d and 28d.

  The dummy wiring D1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27d and 27d can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 29 and 30 are formed on the wiring W1. The insulating layers 29 and 30 are supported by the wiring W1 and the dummy wiring D1. A space (cavity) 31 is formed between the wiring W1 and the dummy wiring D1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The dummy wiring D1 is for preventing the insulating layers 29 and 30 from collapsing into the cavity 31, and does not have a function as a normal wiring.

  The insulating layer 29 determines the pattern of the wiring W1 and the dummy wiring D1, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 30 is important when the cavity 31 is provided between the wiring W1 and the dummy wiring D1, and is important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer.

  On the insulating layer 32, a wiring W2 is formed. The wiring W2 includes, for example, metal layers 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  The interval between the adjacent wirings W2 is H. When the distance H is very wide, a dummy wiring D2 is formed between the wirings W2.

  The dummy wiring D2 includes, for example, metal layers 35d and 35d such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34d and 34d covering the bottom and side surfaces of the metal layers 35d and 35d.

  The dummy wiring D2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34d and 34d can be composed of, for example, a laminate of titanium and titanium nitride.

Insulating layers 36 and 37 are formed on the wiring W2. The insulating layers 36 and 37 are supported by the wiring W2 and the dummy wiring D2. A space 38 is formed between the wiring W2 and the dummy wiring D2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The dummy wiring D2 is for preventing the insulating layers 36 and 37 from collapsing into the cavity 38, and does not have a function as a normal wiring.

  The insulating layer 36 determines the patterns of the wiring W2 and the dummy wiring D2, and is composed of, for example, a silicon oxide layer or a silicon nitride layer. The insulating layer 37 is important when the cavity 38 is provided between the wiring W2 and the dummy wiring D2, and is important as a base when the layers are stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  In addition, when the interval H between adjacent wirings W1 is very wide, a dummy wiring D1 is formed between the wirings W1. Similarly, when the distance H between adjacent wirings W2 is very wide, a dummy wiring D2 is formed between the wirings W2.

  Therefore, a situation in which the insulating film on the wirings W1 and W2 collapses into the cavities 31 and 38 does not occur.

  FIG. 169 shows a semiconductor device according to the twenty-seventh embodiment of the present invention.

  An insulating layer 25 is formed on the semiconductor substrate (for example, a silicon wafer) 21. On the insulating layer 25, a wiring W1 is formed. The wiring W1 includes, for example, metal layers 28a and 28b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27a and 27b covering the bottom and side surfaces of the metal layers 28a and 28b.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

  The interval between the adjacent wirings W1 is H. When this interval H is very wide, a dummy wiring D1 is formed between the wirings W1.

  The dummy wiring D1 is composed of, for example, metal layers 28d and 28d such as copper and aluminum alloy, and U-shaped groove-like barrier layers 27d and 27d covering the bottom and side surfaces of the metal layers 28d and 28d.

  The dummy wiring D1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27d and 27d can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 30 is formed on the wiring W1. The insulating layer 30 is supported by the wiring W1 and the dummy wiring D1. A space (cavity) 31 is formed between the wiring W1 and the dummy wiring D1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The dummy wiring D1 is for preventing the insulating layer 30 from collapsing into the cavity 31, and does not have a function as a normal wiring.

  The insulating layer 30 is important when the cavity 31 is provided between the wiring W1 and the dummy wiring D1, and is important as a base when the layers are stacked on the insulating layer 30. The insulating layer 30 is made of, for example, a silicon oxide film.

  An insulating layer 32 is formed on the insulating layer 30. The insulating layer 32 is composed of, for example, a silicon oxide layer.

  On the insulating layer 32, a wiring W2 is formed. The wiring W2 includes, for example, metal layers 35a and 35b such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34a and 34b covering the bottom and side surfaces of the metal layers 35a and 35b.

  Note that the wiring W2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of, for example, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34a and 34b can be composed of, for example, a laminate of titanium and titanium nitride.

  The interval between the adjacent wirings W2 is H. When the distance H is very wide, a dummy wiring D2 is formed between the wirings W2.

  The dummy wiring D2 includes, for example, metals 35d and 35d such as copper and aluminum alloy, and U-shaped groove-like barrier layers 34d and 34d covering the bottom and side surfaces of the metals 35d and 35d.

  The dummy wiring D2 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 34d and 34d can be composed of, for example, a laminate of titanium and titanium nitride.

An insulating layer 37 is formed on the wiring W2. The insulating layer 37 is supported by the wiring W2 and the dummy wiring D2. A space 38 is formed between the wiring W2 and the dummy wiring D2. The cavity 38 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The dummy wiring D2 is for preventing the insulating layer 37 from collapsing into the cavity 38, and does not have a function as a normal wiring.

  The insulating layer 37 is important when the cavity 38 is provided between the wiring W2 and the dummy wiring D2, and is important as a base when the layers are stacked on the insulating layer 37. The insulating layer 37 is made of, for example, a silicon oxide film.

According to the semiconductor device having the above structure, between wires W1 are formed cavities 31 which mixed gas is filled in the oxygen O ₂ and carbon dioxide CO ₂ is between wires W2 are oxygen O ₂ and carbon dioxide CO ₂ A cavity 38 filled with the mixed gas is formed.

  The mixed gas has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  In addition, when the interval H between adjacent wirings W1 is very wide, a dummy wiring D1 is formed between the wirings W1. Similarly, when the distance H between adjacent wirings W2 is very wide, a dummy wiring D2 is formed between the wirings W2.

  Therefore, a situation in which the insulating film on the wirings W1 and W2 collapses into the cavities 31 and 38 does not occur.

  FIG. 170 shows a semiconductor device according to the twenty-eighth embodiment of the present invention.

  An insulating layer (for example, silicon oxide layer) 12 is formed on the semiconductor substrate (for example, silicon wafer) 11. The wiring 13 is disposed on the insulating layer 12. The wiring 13 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

A plate-like insulating layer 14 that does not fill between the wirings 13 is formed on the wirings 13 with the wirings 13 as columns. That is, a space (cavity) 15 is formed between the wirings 13. The cavity 15 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 14 is made of, for example, silicon oxide, zirconium oxide, hafnium oxide, chromium oxide, or the like.

  It should be noted that the cavity 15 may be filled with air by making the cavity 15 come into contact with air at the time of manufacture or by providing a hole in the package.

  Further, a coupling layer 61 is formed between the wiring 13 and the insulating layer 14. The coupling layer 61 serves to firmly bond the wiring 13 and the insulating layer 14 to each other.

  The coupling layer 61 is composed of a metal constituting the wiring 13 and a material such as silicon, zirconium, hafnium, or chromium.

According to the semiconductor device having the above configuration, the space between the wirings 13 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings 13 is filled with an insulating layer such as a silicon oxide layer. Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  In addition, since the coupling layer 61 is formed between the wiring 13 and the insulating layer 14, the wiring 13 and the insulating layer 14 are firmly coupled to each other by the coupling layer 61. Accordingly, a semiconductor device having sufficient strength can be provided even if the space between the wirings is hollow.

  Next, a method for manufacturing the semiconductor device of FIG. 170 will be described.

  First, as shown in FIG. 171, the insulating layer 12 is formed on the semiconductor substrate 11. A carbon (carbon) layer 16 is formed on the insulating layer 12 by sputtering or the like. Here, the thickness of the carbon layer 16 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 17 is formed on the carbon layer 16 by sputtering or CVD. Here, when the mask material 17 is made of an oxide, the mask material 17 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 16 may disappear due to oxygen contained in the reaction gas.

  Next, as shown in FIG. 172, a resist is applied on the mask material 17, and this resist is patterned by using PEP (photo etching process). Further, the mask material 17 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, the carbon layer 16 is etched by anisotropic etching using the mask material 17 as a mask, and a groove is formed in the carbon layer 16.

  The carbon layer 16 may be etched using a resist as a mask.

The resist is peeled off with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . This is because the resist can be removed by oxygen plasma treatment, but if the oxygen plasma treatment is used, the carbon layer 16 also disappears.

  Next, as shown in FIG. 173, a conductive layer made of copper or the like is formed on the entire surface of the semiconductor substrate 11 by a CVD method or a sputtering method. The conductive layer is left only in the groove between the carbon layers 16 by chemical mechanical polishing (CMP), and the wiring 13 is formed.

  Note that the wiring 13 may be formed by using anisotropic etching or isotropic etching instead of CMP.

  Thereafter, the mask material 17 is peeled off.

  Next, as shown in FIG. 174, a silicon layer (amorphous silicon, polycrystalline silicon, etc.) 60 is formed on the wiring 13 and the carbon layer 16 by sputtering.

Next, as shown in FIGS. 175 and 176, the carbon layer 16 is ashed, and the carbon layer 16 is converted into a cavity 15 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layer 16 is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). This method has the advantage of preventing the burst of the insulating layer 14 due to the expansion of the volume of the carbon layer 16 because the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds slowly, but has the disadvantage that the processing time becomes long. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 14 may burst due to the expansion of the volume of the carbon layer 16. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 14 or decreasing the temperature of the oxygen plasma treatment.

  During the ashing of the carbon layer 16, the silicon layer 60 changes to the insulating layer (silicon oxide layer) 14. That is, oxygen used for ashing the carbon layer 16 reacts with the silicon layer 60 to form the insulating layer 14.

  At the same time, a coupling layer 61 is formed between the wiring 13 and the insulating layer 14. The bonding layer 61 is formed by the reaction of the material (copper, aluminum, etc.) constituting the wiring 13 with silicon when the carbon layer 16 is ashed.

  Note that the layer provided on the wiring 13 before the ashing treatment is not limited to the silicon layer. That is, any material may be used as long as it changes into an insulating layer when the carbon layer 16 is ashed and reacts with a material constituting the wiring to form a bonding layer.

  As such a material, for example, hafnium, zirconium, chromium and the like can be considered.

  According to the above method, a carbon layer is used as an insulating layer having a groove for forming a wiring, and after the wiring is formed in the groove, the carbon layer is ashed to be converted into a gas-filled cavity. ing. Accordingly, the semiconductor device in FIG. 170 can be easily provided. Further, when the carbon layer is ashed, the silicon layer changes to an insulating layer, and a bonding layer is formed between the silicon layer and the wiring, so that the silicon layer and the wiring are firmly bonded. Therefore, it is possible to improve the mechanical strength of the semiconductor device in which the space between the wirings is hollow.

  FIG. 177 shows a semiconductor device according to the twenty-ninth embodiment of the invention.

  An insulating layer (for example, silicon oxide layer) 12 is formed on the semiconductor substrate (for example, silicon wafer) 11. The wiring 13 is disposed on the insulating layer 12. The wiring 13 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

  A metal layer 62 is formed between the insulating layer 12 and the wiring 13. The metal layer 62 is made of a material such as zirconium, hafnium, beryllium, magnesium, scandium, titanium, manganese, cobalt, nickel, yttrium, indium, barium, lanthanum, cerium, ruthenium, lead, bismuth, thorium, and chromium.

A space (cavity) 15 is formed between the wirings 13. The cavity 15 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  A metal oxide layer 63 is formed on the side wall of the wiring 13 and the cavity 15 between the wirings. The metal oxide layer 63 is made of an oxide of the material that forms the metal layer 62. Note that a metal nitride layer may be provided instead of the metal oxide layer on the side wall of the wiring 13 and the cavity 15 between the wirings. In this case, the metal nitride layer is made of a nitride of the material constituting the metal layer 62.

  An insulating layer 64 is formed on the wiring 13 and the metal oxide layer 63. The insulating layer 64 is made of, for example, silicon oxide, zirconium oxide, hafnium oxide, chromium oxide, or the like.

  It should be noted that the cavity 15 may be filled with air by making the cavity 15 come into contact with air at the time of manufacture or by providing a hole in the package.

According to the semiconductor device having the above configuration, the space between the wirings 13 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings 13 is filled with an insulating layer such as a silicon oxide layer. Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  A metal oxide layer 63 is formed on the side wall of the wiring 13 and the cavity 15 between the wirings. Since the metal oxide layer 63 is excellent in mechanical strength, a semiconductor device having sufficient strength can be provided even if the space between the wirings is a cavity 15.

  Next, a method for manufacturing the semiconductor device in FIG. 177 will be described.

  First, as shown in FIG. 178, the insulating layer 12 is formed on the semiconductor substrate 11. A carbon (carbon) layer 16 is formed on the insulating layer 12 by sputtering or the like. Here, the thickness of the carbon layer 16 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 17 is formed on the carbon layer 16 by sputtering or CVD. Here, when the mask material 17 is made of an oxide, the mask material 17 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 16 may disappear due to oxygen contained in the reaction gas.

  Next, a resist is applied on the mask material 17, and this resist is patterned by using PEP (Photo Etching Process). Further, the mask material 17 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, the carbon layer 16 is etched by anisotropic etching using the mask material 17 as a mask, and a groove is formed in the carbon layer 16.

  The carbon layer 16 may be etched using a resist as a mask.

The resist is peeled off with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . This is because the resist can be removed by oxygen plasma treatment, but if the oxygen plasma treatment is used, the carbon layer 16 also disappears.

  Thereafter, the mask material 17 is peeled off.

  Next, as shown in FIG. 179, a metal layer 62 is formed on the entire surface of the semiconductor substrate 11, that is, on the inner surface and the upper surface of the groove of the carbon layer 16, by the CVD method or the sputtering method. The metal layer 62 is made of a material such as zirconium, hafnium, beryllium, magnesium, scandium, titanium, manganese, cobalt, nickel, yttrium, indium, barium, lanthanum, cerium, ruthenium, lead, bismuth, thorium, and chromium. .

  Subsequently, a conductive layer made of copper, aluminum, or the like is formed on the metal layer 62 by a CVD method or a sputtering method. The conductive layer is left only in the groove between the carbon layers 16 by chemical mechanical polishing (CMP), and the wiring 13 is formed.

  Note that the wiring 13 may be formed by using anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIGS. 180 and 181, the carbon layer 16 is ashed, and the carbon layer 16 is converted into a cavity 15 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layer 16 is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). This method has the advantage of preventing the burst of the insulating layer 14 due to the expansion of the volume of the carbon layer 16 because the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds slowly, but has the disadvantage that the processing time becomes long. is there.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 16 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, there is a possibility that the insulating layer 14 may burst due to the expansion of the volume of the carbon layer 16. There is a disadvantage that it becomes high. However, this drawback can be avoided by improving the quality of the insulating layer 14 or decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 182, selective oxidation treatment (temperature of about 450 ° C., time of about 30 minutes) is performed in an oxygen atmosphere, and a part of the metal layer 62, that is, the side wall of the wiring 13 and the cavity 15 between the wirings The metal layer 62 present thereon is oxidized. As a result, the metal layer 62 on the side wall of the wiring 13 and the cavity 15 between the wirings is changed to the metal oxide layer 63.

Note that the temperature and time of the selective oxidation treatment are determined on the condition that the metal layer 62 existing immediately below the wiring 13 is not oxidized. The atmosphere may be an H ₂ , H ₂ O atmosphere or the like.

  In the present embodiment, the selective oxidation treatment is performed, but in place of this, a nitridation treatment in a nitrogen atmosphere may be performed. In this case, the metal layer 62 on the side wall of the wiring 13 and the cavity 15 between the wirings is changed to a metal nitride layer.

  In the present embodiment, the ashing of the carbon layer 16 and the oxidation of the metal layer 62 are performed in separate steps, but they may be performed in the same step. For example, when the metal layer 62 is made of hafnium, if the ashing treatment is performed in an oxygen atmosphere at a temperature of about 400 ° C. for about 1 hour, the ashing of the carbon layer 16 and the sidewalls of the wiring 13 and Only the metal layer 62 on the cavity 15 between the wirings is oxidized.

  Next, as shown in FIG. 183, an insulating layer 64 having a low dielectric constant is formed on the wiring 13 and the metal oxide layer 63 by a CVD method or a sputtering method. The insulating layer 64 can be made of silicon oxide to which fluorine is added.

  According to the above method, a carbon layer is used as an insulating layer having a groove for forming a wiring, and after the wiring is formed in the groove, the carbon layer is ashed to be converted into a gas-filled cavity. ing. Therefore, the semiconductor device in FIG. 177 can be easily provided. Further, the metal layer 62 on the side wall of the wiring 13 and the cavity 15 between the wirings is converted into a metal oxide layer 63 by selective oxidation treatment. Since the metal oxide layer 63 has excellent mechanical strength, even if the space between the wirings is the cavity 15, the cavity 15 is not crushed.

  FIG. 184 shows a semiconductor device according to the thirtieth embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wiring W1 is disposed on the insulating layer 25 and the conductive layers 26a and 26b. A metal layer 62 is formed between the wiring W1 and the insulating layer 25 and the conductive layers 26a and 26b.

  The metal layer 62 is made of a material such as zirconium, hafnium, beryllium, magnesium, scandium, titanium, manganese, cobalt, nickel, yttrium, indium, barium, lanthanum, cerium, ruthenium, lead, bismuth, thorium, and chromium.

  Accordingly, the wiring W1 is electrically connected to the conductive layers 26a and 26b. The wiring W1 is composed of metals 28a and 28b such as copper and aluminum alloy.

  Note that the wiring W1 is not limited to a metal such as copper or an aluminum alloy, and may be composed of a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten. The barrier layers 27a and 27b can be composed of, for example, a laminate of titanium and titanium nitride.

A space (cavity) 31 is formed between the wirings W1. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  A metal oxide layer 63 is formed on the side wall of the wiring W1 and on the cavity 31 between the wirings. The metal oxide layer 63 is formed by oxidizing the material constituting the metal layer 62.

  Note that a metal nitride layer may be provided instead of the metal oxide layer 63 on the side wall of the wiring W1 and the cavity 31 between the wirings. In this case, the metal nitride layer is formed by nitriding the material constituting the metal layer 62.

  An insulating layer 64 having a low dielectric constant is formed on the wiring W1 and the metal oxide layer 63. The insulating layer 64 can be made of, for example, silicon oxide containing fluorine.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the wirings W1.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device in FIG. 184 will be described.

  First, as shown in FIG. 185, a field oxide layer 22 is formed on the semiconductor substrate 21 by the LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  Next, as shown in FIG. 186, a carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  Next, as shown in FIG. 187, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer 39 to a thickness of about 0.05 μm by sputtering.

  Here, when the mask material 29 is made of an oxide, the mask material 29 is preferably formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

  Next, as shown in FIG. 188, a resist is applied on the mask material 29, and this resist is patterned using PEP (photo etching process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off. The pattern of the mask material 29 is the same as the pattern of the wiring.

  Next, as shown in FIG. 189, the carbon layer 39 is etched by anisotropic etching using the mask material 29 as a mask.

  In this embodiment, the carbon layer 39 is etched by PEP without directly etching the carbon layer 39, using the mask material 29 processed by PEP as a mask.

The reason for this is as follows. The resist used for PEP is removed by oxygen plasma treatment (asher) or a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . However, when the resist is removed by the oxygen plasma treatment, the patterned carbon layer 39 is removed at the same time. On the other hand, when the resist is removed with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ , the conductive layers (only in the case of a refractory metal) 26a and 26b are simultaneously removed.

  Therefore, when the conductive layers 26a and 26b are refractory metal, the carbon layer 39 is preferably etched using the mask material 29 processed by PEP as a mask.

  Thereafter, the mask material 29 is removed.

  Next, as shown in FIG. 190, a metal layer 62 is formed on the inner surface of the groove XX formed in the carbon layer 39 and the upper surface of the carbon layer 39 by sputtering or CVD. The metal layer 62 is made of a material such as zirconium, hafnium, beryllium, magnesium, scandium, titanium, manganese, cobalt, nickel, yttrium, indium, barium, lanthanum, cerium, ruthenium, lead, bismuth, thorium, and chromium.

  Next, as shown in FIG. 191, a metal 28 made of copper, aluminum alloy, or the like is formed on the metal layer 62 by sputtering or CVD. The wiring is not limited to a metal such as copper or an aluminum alloy, but may be a semiconductor such as polysilicon containing impurities, or a high melting point metal such as tungsten.

  Next, as shown in FIG. 192, the metals 28a and 28b are left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP), thereby forming the wiring W1. Note that the wiring W1 may be formed by using anisotropic etching or isotropic etching instead of CMP.

Next, as shown in FIGS. 193 and 194, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 29 and 30 can be prevented from bursting due to the expansion of the volume of the carbon layer 39, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 29 and 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 29 and 30 and decreasing the temperature of the oxygen plasma treatment.

  Next, as shown in FIG. 195, selective oxidation (temperature: about 450 ° C., time: about 30 minutes) is performed in an oxygen atmosphere, and a part of the metal layer 62, that is, the side wall of the wiring 13 and the cavity 15 between the wirings. The metal layer 62 present thereon is oxidized. As a result, the metal layer 62 on the side walls of the wirings 28 a and 28 b and the cavity 31 between the wirings is changed to the metal oxide layer 63.

Note that the temperature and time of the selective oxidation treatment are determined on the condition that the metal layer 62 existing immediately below the wirings 28a and 28b is not oxidized. The atmosphere may be an H ₂ , H ₂ O atmosphere or the like.

  In the present embodiment, the selective oxidation treatment is performed, but in place of this, a nitridation treatment in a nitrogen atmosphere may be performed. In this case, the metal layer 62 on the side walls of the wirings 28a and 28b and the cavity 31 between the wirings is changed to a metal nitride layer.

  In the present embodiment, the ashing of the carbon layer 39 and the oxidation of the metal layer 62 are performed in separate steps, but they may be performed in the same step. For example, when the metal layer 62 is made of hafnium, if the ashing process is performed in an oxygen atmosphere at a temperature of about 400 ° C. for about 1 hour, the ashing of the carbon layer 39 and the wirings 28a and 28b are performed simultaneously. Only the metal layer 62 on the cavity 31 between the side walls and the wiring is oxidized.

  Next, as shown in FIG. 196, an insulating layer 64 having a low dielectric constant is formed on the wirings 28a and 28b and the metal oxide layer 63 by a CVD method or a sputtering method. The insulating layer 64 can be made of silicon oxide to which fluorine is added.

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves for forming the wirings 28a and 28b, and after the wiring is formed in the grooves, the carbon layer is ashed to fill the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 184 can be easily provided. In addition, the metal layer 62 on the side walls of the wirings 28 a and 28 b and the cavity 31 between the wirings is converted into a metal oxide layer 63 by selective oxidation. Since the metal oxide layer 63 has excellent mechanical strength, even if the space between the wirings is the cavity 31, the cavity 31 is not crushed.

  As described above, in each of the embodiments described above, the ashing of the carbon layer is performed in an oxygen atmosphere.

  197 and 198 show the ashing process of the carbon layer in the case where a metal such as copper is used for the wiring.

  When copper or the like is used for the wiring 13, a protective metal layer 65 is formed on the side and bottom surfaces of the wiring 13 in order to prevent the reaction between the wiring 13 and the carbon layer 16. The protective metal layer 65 can be made of, for example, a laminate of titanium and titanium nitride, titanium nitride silicon, or the like.

However, an insulating layer 14 that transmits oxygen (O ₂ ) such as a silicon oxide layer is formed on the wiring 13 in order to incinerate the carbon layer 16.

  Therefore, when the carbon layer 16 is ashed, the upper surface of the wiring 13 is inevitably oxidized, and a metal oxide layer 66 is formed. The metal oxide layer 66 increases the resistance value of the wiring 13 or decreases the reliability of the wiring 13.

  In the following embodiments, a semiconductor device and a method for manufacturing the semiconductor device are provided in which the wiring 13 is not oxidized when the carbon layer is ashed.

  FIG. 199 shows a semiconductor device according to the thirty-first embodiment of the present invention.

  A field oxide layer (eg, silicon oxide layer) 22 is formed on a semiconductor substrate (eg, silicon wafer) 21. In the element region surrounded by the field oxide layer 22, a MOS transistor is formed. This MOS transistor has a gate electrode 23 and source / drain regions 24a and 24b.

  The insulating layer 25 covers the MOS transistor. The insulating layer 25 can be made of, for example, boron phosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

  The surface of the insulating layer 25 is flat. The surface of the insulating layer 25 can be flattened by chemical mechanical polishing (CMP). In the insulating layer 25, contact holes reaching the source / drain regions 24a and 24b are formed.

  Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded in the contact hole. However, the conductive layers 26a and 26b may be made of a material other than the refractory metal.

  The wirings 28a and 28b are disposed on the insulating layer 25 and the conductive layers 26a and 26b. The side surfaces and bottom surface of the wirings 28 a and 28 b are covered with a protective metal layer 65. The protective metal layer 65 can be made of a layer that does not allow oxygen to pass therethrough, for example, a laminate of titanium and titanium nitride, or titanium nitride silicon.

  The upper surfaces of the wirings 28a and 28b can be formed of a protective layer 67 that does not allow oxygen to pass therethrough, for example, a laminated layer of titanium and titanium nitride, a metal layer such as titanium nitride silicon, or an insulating layer such as silicon nitride. .

  That is, the protective layer covering at least the lower surface of the wirings 28a and 28b needs to be formed of a metal layer in order to be electrically connected to the conductive layers 26a and 26b. May be a metal layer or an insulating layer.

  The wirings 28a and 28b are made of a metal that is easily oxidized, such as copper.

A space (cavity) 31 is formed between the wirings 28a and 28b. The cavity 31 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  An insulating layer 68 is formed on the wirings 28a and 28b. The insulating layer 68 is made of silicon oxide or the like.

According to the semiconductor device having the above configuration, the cavity 31 filled with the mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air is formed between the wirings 28a and 28b.

  The mixed gas or air has a dielectric constant ε of about 1.0. Thereby, the dielectric constant can be drastically reduced as compared with the case where the space between the wirings W1 and the space between the wirings W2 are filled with an insulating layer such as a silicon oxide layer.

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Further, at least when the carbon layer is ashed, the wirings 28a and 28b are completely covered with a protective layer that does not allow oxygen to pass therethrough.

  Therefore, it is possible to prevent an increase in resistance value and a decrease in reliability of the wirings 28a and 28b.

  Next, a method for manufacturing the semiconductor device of FIG. 199 will be described.

  First, as shown in FIG. 200, a field oxide layer 22 is formed on a semiconductor substrate 21 by a LOCOS method. In the element region surrounded by the field oxide layer 22, for example, a MOS transistor having a gate electrode 23 and source / drain regions 24a and 24b is formed.

  An insulating layer (such as BPSG or PSG) 25 that completely covers the MOS transistor is formed on the entire surface of the semiconductor substrate 21. Thereafter, chemical mechanical polishing (CMP) is performed to flatten the surface of the insulating layer 25.

  Contact holes reaching the source / drain regions 24a and 24b are formed in the insulating layer 25 by PEP (photo-etching process). Conductive layers 26a and 26b made of a refractory metal such as tungsten are embedded only in the contact hole of the insulating layer 25 by a selective growth method.

  Note that a material other than the refractory metal may be embedded in the contact hole of the insulating layer 25.

  Next, as shown in FIG. 201, a carbon layer 39 is formed on the insulating layer 25 by sputtering. Here, the thickness of the carbon layer 39 is set to a value equal to the thickness of the internal wiring of the LSI (for example, about 0.7 to about 0.2 μm).

  Next, as shown in FIG. 202, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 29 is formed on the carbon layer 39 to a thickness of about 0.05 μm by sputtering.

  Here, when the mask material 29 is made of an oxide, the mask material 29 is preferably formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

  Next, as shown in FIG. 203, a resist is applied on the mask material 29, and this resist is patterned using PEP (photo etching process). Further, the mask material 29 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off. The pattern of the mask material 29 is the same as the pattern of the wiring.

  Next, as shown in FIG. 204, the carbon layer 39 is etched by anisotropic etching using the mask material 29 as a mask.

  In this embodiment, the carbon layer 39 is etched by PEP without directly etching the carbon layer 39, using the mask material 29 processed by PEP as a mask.

The reason for this is as follows. The resist used for PEP is removed by oxygen plasma treatment (asher) or a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . However, when the resist is removed by the oxygen plasma treatment, the patterned carbon layer 39 is removed at the same time. On the other hand, when the resist is removed with a chemical solution of H ₂ SO ₄ and H ₂ O ₂ , the conductive layers (only in the case of a refractory metal) 26a and 26b are simultaneously removed.

  Therefore, when the conductive layers 26a and 26b are refractory metal, the carbon layer 39 is preferably etched using the mask material 29 processed by PEP as a mask.

  Thereafter, the mask material 29 is removed.

  Next, as shown in FIG. 205, a protective metal layer 65 is formed on the inner surface of the groove XX formed in the carbon layer 39 and the upper surface of the carbon layer 39 by sputtering or CVD. The protective metal layer 65 is made of a laminate of titanium and titanium nitride, or a material such as titanium nitride silicon.

  Next, as shown in FIG. 206, a metal 28 made of a material that is easily oxidized, such as copper, is formed on the protective metal layer 65 by sputtering or CVD.

  Next, as shown in FIG. 207, the metal is left only in the grooves between the carbon layers 39 by chemical mechanical polishing (CMP) to form wirings 28a and 28b. Note that the wiring W1 may be formed by using anisotropic etching or isotropic etching instead of CMP.

  At this time, the upper surfaces of the wirings 28 a and 28 b are arranged at a slightly lower level than the upper surface of the carbon layer 39.

  Next, as shown in FIG. 208, a protective layer 67 that can prevent oxygen permeation in the range of 300 to 600 ° C. is formed on the wirings 28 a and 28 b and the carbon layer 39. The protective layer 67 can be composed of a laminate of titanium and titanium nitride, a metal layer such as titanium nitride silicon, or an insulating layer such as silicon nitride.

  The reason why oxygen permeation can be prevented in the temperature range of 300 to 600 ° C. is that the ashing of the carbon layer is performed in such a temperature range.

  Next, as shown in FIG. 209, CMP is performed to leave the protective layer 67 only on the wirings 28a and 28b. Here, the upper surface of the carbon layer 39 and the upper surface of the protective layer 67 are arranged on the same plane.

  Next, as shown in FIGS. 210 and 211, an insulating layer 68 having a thickness of about 0.05 μm is formed on the carbon layer 39 and the protective layer 67 by CVD or sputtering. Here, in the case where the insulating layer 68 is made of an oxide, the insulating layer 68 is preferably formed not by the CVD method but by the sputtering method in order to prevent the carbon layer 39 from disappearing.

Thereafter, the carbon layer 39 is ashed, and the carbon layer 39 is converted into a cavity 31 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . Ashing of the carbon layer 39 is achieved by using one of the following two methods.

The first is a heat treatment in an oxygen atmosphere (temperature 400 to 450 ° C., time 2 hours). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layers 29 and 30 can be prevented from bursting due to the expansion of the volume of the carbon layer 39, but the processing time is increased. There are drawbacks.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layer 39 converting to carbon dioxide CO ₂ proceeds rapidly, there is an advantage that the processing time is shortened. On the other hand, the insulating layers 29 and 30 may burst due to the volume expansion of the carbon layer 39. There is a disadvantage that the property becomes high. However, this drawback can be avoided by improving the quality of the insulating layers 29 and 30 and decreasing the temperature of the oxygen plasma treatment.

  According to the manufacturing method described above, the carbon layer is used for the insulating layer having the grooves for forming the wirings 28a and 28b, and after the wiring is formed in the grooves, the carbon layer is ashed to fill the gas. It has been converted into a cavity. Therefore, the semiconductor device in FIG. 199 can be easily provided. Further, at least during the ashing treatment, the wirings 28a and 28b are completely covered with a protective layer that does not transmit oxygen. Therefore, the wirings 28a and 28b are not oxidized during the ashing of the carbon layer 39, and an increase in resistance value and a decrease in reliability of the wirings 28a and 28b can be prevented.

  FIG. 212 shows a semiconductor device according to the thirty-second embodiment of the present invention.

  On a semiconductor substrate (for example, a silicon wafer) 71, an insulating layer (for example, a silicon oxide layer) 72 is formed. The wiring 73 is disposed on the insulating layer 72. The wiring 73 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

The insulating layer 74 completely covers the wiring 73. However, the insulating layer 74 is not in contact with the wiring 73. Therefore, a cavity 75 is provided between the wiring 73 and the insulating layer 74. The cavity 75 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 74 is made of, for example, silicon oxide, zirconium oxide, hafnium oxide, chromium oxide, or the like. An insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed on the insulating layer 74.

  Reference numeral 77 denotes a mask material used for patterning the wiring 73. By the way, the cavity 75 may be filled with air by making it contact with air at the time of manufacture or by providing a hole in the package.

According to the semiconductor device having the above configuration, the wiring 73 is covered with the insulating layer 74. In addition, a space 75 between the wiring 73 and the insulating layer 74 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0.

  That is, since the cavity 75 is formed at least at the corners of the wiring 73 where charges are likely to concentrate, the dielectric constant is extremely reduced compared to the case where the wiring 73 is completely filled with an insulating layer such as a silicon oxide layer. Can be reduced. Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device in FIG. 212 will be described.

  First, as shown in FIG. 213, the insulating layer 72 is formed on the semiconductor substrate 71. A metal layer 73a is formed on the insulating layer 72 by sputtering or the like. Here, the thickness of the metal layer 73a is set to 0.7 to 0.2 μm. The metal layer 73a can be made of aluminum, copper, titanium, titanium nitride, or the like.

  Further, the carbon layer 80a is formed on the metal layer 73a by sputtering or the like. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 77 is formed on the carbon layer 80a by a sputtering method or a CVD method. Here, when the mask material 77 is made of an oxide, the mask material 77 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 80a may disappear due to oxygen contained in the reaction gas.

  Next, as shown in FIG. 214, a resist is applied on the mask material 77, and this resist is patterned using PEP (photo etching process). Further, the mask material 77 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer and the metal layer are etched by anisotropic etching using the mask material 77 as a mask to form the wiring 73.

Note that the resist is peeled off using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . This is because the resist can be removed by oxygen plasma treatment, but if the oxygen plasma treatment is used, the carbon layer 16 also disappears.

  Next, as shown in FIG. 215, a carbon layer 80b is formed on the sidewalls of the wiring 73 and the wiring 73 by sputtering or the like. The carbon layer 80 b is etched by anisotropic etching, and the carbon layer 80 b is left only on the side wall portion of the wiring 73.

  First, as shown in FIGS. 216 and 217, a thickness of about 0.05 μm is formed on the entire surface of the semiconductor substrate 71, that is, on the insulating layer 72, the carbon layer 80 b, and the mask material 77 by sputtering or CVD. Insulating layer (for example, silicon oxide) 74 is formed.

  Here, when the insulating layer 74 is made of an oxide, the insulating layer 74 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layers 80a and 80b may disappear due to oxygen contained in the reaction gas.

Thereafter, the carbon layers 80a and 80b are ashed, and the carbon layers 80a and 80b are converted into cavities 75 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layers 80a and 80b is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). In this method, since the reaction of the carbon layers 80a and 80b converting into carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layer 74 can be prevented from bursting due to the expansion of the volume of the carbon layers 80a and 80b. There is a drawback of lengthening.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layers 80a and 80b converting to carbon dioxide CO ₂ proceeds quickly, there is an advantage in that the processing time is shortened. There is a drawback that it is more likely to occur. However, this drawback can be avoided by improving the quality of the insulating layer 74 and decreasing the temperature of the oxygen plasma treatment.

  It should be noted that the cavity 75 may be filled with air by contacting the cavity 75 with air at the time of manufacture, or by making a hole in the package.

  Next, as illustrated in FIG. 218, an insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed over the insulating layer 74. Note that the surface of the insulating layer 76 is planarized by a CMP method or the like.

  According to the above-described method, the carbon layers 80a and 80b formed on the side surface and the upper surface of the wiring 73 are incinerated so that at least the periphery of the wiring 73 becomes a cavity. Therefore, the semiconductor device in FIG. 212 can be easily provided. Further, in this embodiment, since a cavity is provided in the edge portion of the wiring 73 where charge is easily accumulated, it is effective in reducing the parasitic capacitance between the wirings.

  FIG. 219 shows a semiconductor device according to the thirty-third embodiment of the present invention.

  On a semiconductor substrate (for example, a silicon wafer) 71, an insulating layer (for example, a silicon oxide layer) 72 is formed. The wiring 73 is disposed on the insulating layer 72. The wiring 73 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

The insulating layer 74 completely covers the wiring 73. However, the insulating layer 74 is not in contact with the wiring 73. Therefore, a cavity 75 is provided between the wiring 73 and the insulating layer 74. The cavity 75 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 74 is made of, for example, silicon oxide, zirconium oxide, hafnium oxide, chromium oxide, or the like. An insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed on the insulating layer 74.

  It should be noted that the cavity 75 may be filled with air by contacting the cavity 75 with air at the time of manufacture, or by providing a hole in the package.

According to the semiconductor device having the above configuration, the wiring 73 is covered with the insulating layer 74. In addition, a space 75 between the wiring 73 and the insulating layer 74 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0.

  That is, since the cavity 75 is formed at least at the corners of the wiring 73 where charges are likely to concentrate, the dielectric constant is extremely reduced compared to the case where the wiring 73 is completely filled with an insulating layer such as a silicon oxide layer. Can be reduced. Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

  Next, a method for manufacturing the semiconductor device in FIG. 219 will be described.

  First, as shown in FIG. 220, the insulating layer 72 is formed on the semiconductor substrate 71. A metal layer 73a is formed on the insulating layer 72 by sputtering or the like. Here, the thickness of the metal layer 73a is set to 0.7 to 0.2 μm. The metal layer 73a can be made of aluminum, copper, titanium, titanium nitride, or the like.

  Further, the carbon layer 80a is formed on the metal layer 73a by sputtering or the like. Further, a mask material (for example, a silicon oxide layer or a silicon nitride layer) 77 is formed on the carbon layer 80a by a sputtering method or a CVD method. Here, when the mask material 77 is made of an oxide, the mask material 77 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 80a may disappear due to oxygen contained in the reaction gas.

  Next, as shown in FIG. 221, a resist is applied on the mask material 77, and this resist is patterned using PEP (photo etching process). Further, the mask material 77 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, and the carbon layer and the metal layer are etched by anisotropic etching using the mask material 77 as a mask to form the wiring 73. Thereafter, when the mask material 77 remains, the mask material 77 is peeled off.

Note that the resist is peeled off using a chemical solution of H ₂ SO ₄ and H ₂ O ₂ . This is because the resist can be removed by oxygen plasma treatment, but if the oxygen plasma treatment is used, the carbon layer 16 also disappears.

  Next, as shown in FIG. 222, a carbon layer 80b is formed on the sidewalls of the wiring 73 and the wiring 73 by sputtering or the like. The carbon layer 80 b is etched by anisotropic etching, and the carbon layer 80 b is left only on the side wall portion of the wiring 73.

  First, as shown in FIGS. 223 and 224, an insulating layer (for example, about 0.05 μm thick) is formed on the entire surface of the semiconductor substrate 71, that is, on the insulating layer 72 and the carbon layers 80a and 80b by sputtering or CVD. , Silicon oxide, etc.) 74 is formed.

  Here, when the insulating layer 74 is made of an oxide, the insulating layer 74 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layers 80a and 80b may disappear due to oxygen contained in the reaction gas.

Thereafter, the carbon layers 80a and 80b are ashed, and the carbon layers 80a and 80b are converted into cavities 75 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layers 80a and 80b is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). In this method, since the reaction of the carbon layers 80a and 80b converting into carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layer 74 can be prevented from bursting due to the expansion of the volume of the carbon layers 80a and 80b. There is a drawback of lengthening.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layers 80a and 80b converting to carbon dioxide CO ₂ proceeds quickly, there is an advantage in that the processing time is shortened. There is a drawback that it is more likely to occur. However, this drawback can be avoided by improving the quality of the insulating layer 74 and decreasing the temperature of the oxygen plasma treatment.

  It should be noted that the cavity 75 may be filled with air by contacting the cavity 75 with air at the time of manufacture, or by making a hole in the package.

  Next, as illustrated in FIG. 225, an insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed over the insulating layer 74. Note that the surface of the insulating layer 76 is planarized by a CMP method or the like.

  According to the above-described method, the carbon layers 80a and 80b formed on the side surface and the upper surface of the wiring 73 are incinerated so that at least the periphery of the wiring 73 becomes a cavity. Therefore, the semiconductor device in FIG. 212 can be easily provided. Further, in this embodiment, since a cavity is provided in the edge portion of the wiring 73 where charge is easily accumulated, it is effective in reducing the parasitic capacitance between the wirings.

  FIG. 226 shows a semiconductor device according to the thirty-fourth embodiment of the present invention.

  On a semiconductor substrate (for example, a silicon wafer) 71, an insulating layer (for example, a silicon oxide layer) 72 is formed. The wiring 73 is disposed on the insulating layer 72. The wiring 73 is made of a metal such as copper or an aluminum alloy, a semiconductor such as polysilicon containing impurities, or a refractory metal such as tungsten.

The insulating layer 74 completely covers the wiring 73. However, the insulating layer 74 is in contact with the upper surface of the wiring 73 and is not in contact with the side surface. Therefore, a cavity 75 is provided between the side surface of the wiring 73 and the insulating layer 74. The cavity 75 is mainly filled with a gas having a dielectric constant ε of about 1.0, that is, a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ .

  The insulating layer 74 is made of, for example, silicon oxide, zirconium oxide, hafnium oxide, chromium oxide, or the like. An insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed on the insulating layer 74.

  It should be noted that the cavity 75 may be filled with air by contacting the cavity 75 with air at the time of manufacture, or by providing a hole in the package.

According to the semiconductor device having the above configuration, the wiring 73 is covered with the insulating layer 74. In addition, a space 75 between the side surface of the wiring 73 and the insulating layer 74 is mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air. The mixed gas or air has a dielectric constant ε of about 1.0. Therefore, the dielectric constant can be lowered as compared with the case where the space between the wirings 73 is completely filled with an insulating layer such as a silicon oxide layer, and the improvement of the integration degree of the element and the improvement of the performance of the LSI can be achieved simultaneously.

  Next, a method for manufacturing the semiconductor device in FIG. 226 will be described.

  First, as shown in FIG. 227, the insulating layer 72 is formed on the semiconductor substrate 71. A metal layer 73a is formed on the insulating layer 72 by sputtering or the like. Here, the thickness of the metal layer 73a is set to 0.7 to 0.2 μm. The metal layer 73a can be made of aluminum, copper, titanium, titanium nitride, or the like.

  A mask material (for example, a silicon oxide layer or a silicon nitride layer) 77 is formed on the metal layer 73a by sputtering or CVD.

  Next, as shown in FIG. 228, a resist is applied on the mask material 77, and this resist is patterned using PEP (photo etching process). Further, the mask material 77 is patterned using the patterned resist as a mask. Thereafter, the resist is peeled off, the mask layer 77 is used as a mask, the metal layer is etched by anisotropic etching, and the wiring 73 is formed. Thereafter, when the mask material 77 remains, the mask material 77 is peeled off.

  In the present embodiment, the metal layer 73a may be directly etched using a resist as a mask without using a mask material.

  Next, as shown in FIG. 229, a carbon layer 80b is formed on the sidewalls of the wiring 73 and the wiring 73 by sputtering or the like. The carbon layer 80 b is etched by anisotropic etching, and the carbon layer 80 b is left only on the side wall portion of the wiring 73.

  First, as shown in FIGS. 230 and 231, a thickness of about 0.05 μm is formed on the entire surface of the semiconductor substrate 71, that is, on the insulating layer 72, the carbon layer 80 b, and the wiring 73 by sputtering or CVD. An insulating layer (for example, silicon oxide) 74 is formed.

  Here, when the insulating layer 74 is made of an oxide, the insulating layer 74 is preferably formed by a sputtering method. This is because when the CVD method is used, the carbon layer 80b may disappear due to oxygen contained in the reaction gas.

Thereafter, the carbon layer 80b is ashed, and the carbon layer 80b is converted into a cavity 75 mainly filled with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ . The ashing of the carbon layer 80b is achieved by using one of the following two methods.

The first is a heat treatment (temperature 400 to 450 ° C., time 2 hours) in an oxygen atmosphere (refers to an atmosphere containing oxygen, for example, in the air). In this method, since the reaction of the carbon layers 80a and 80b converting into carbon dioxide CO ₂ proceeds slowly, there is an advantage that the insulating layer 74 can be prevented from bursting due to the expansion of the volume of the carbon layers 80a and 80b. There is a drawback of lengthening.

The second is oxygen plasma treatment (asher). In this method, since the reaction of the carbon layers 80a and 80b converting to carbon dioxide CO ₂ proceeds quickly, there is an advantage in that the processing time is shortened. There is a drawback that it is more likely to occur. However, this drawback can be avoided by improving the quality of the insulating layer 74 and decreasing the temperature of the oxygen plasma treatment.

  It should be noted that the cavity 75 may be filled with air by contacting the cavity 75 with air at the time of manufacture, or by making a hole in the package.

  Next, as illustrated in FIG. 232, an insulating layer 76 having a low dielectric constant, for example, a silicon oxide layer containing fluorine is formed over the insulating layer 74. Note that the surface of the insulating layer 76 is planarized by a CMP method or the like.

  According to the above-described method, the carbon layer 80b formed on the side surface and the upper surface of the wiring 73 is incinerated so that at least the side wall of the wiring 73 becomes a cavity. Therefore, the semiconductor device in FIG. 226 can be easily provided.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, the following effects can be obtained.

Cavities filled mainly with a mixed gas of oxygen O ₂ and carbon dioxide CO ₂ or air are formed between the left and right wirings or between the upper and lower wirings, respectively. The mixed gas or air has a dielectric constant ε of about 1.0. As a result, the dielectric constant can be drastically reduced as compared with the case where an insulating layer such as a silicon oxide layer is filled between wirings of the same layer (left and right) and between wirings of different layers (upper and lower).

  Accordingly, it is possible to simultaneously improve the integration degree of the elements and the performance of the LSI.

In addition, if a ring-shaped guard ring is formed at the edge of the chip, after each chip is cut out from the wafer, moisture H ₂ O reaches the wiring from the edge of the chip through the cavity. Can be avoided. That is, by providing the guard ring, the wiring in the chip can be protected against moisture H ₂ O.

Further, if at least the side surface of the wiring is covered with the wiring protective layer, the moisture H ₂ O that has entered from the edge of the chip through the cavity does not reach the wiring metal directly. Therefore, each wiring can be protected from moisture H ₂ O.

  If a package for mounting a semiconductor device (chip) as described above is provided with a hole for connecting the outside and inside of the package, the air in the cavity circulates and the heat generated in the chip -Efficiently discharged outside. Therefore, it is possible to provide a semiconductor device in which defects due to heat hardly occur.

  Further, hillocks can be prevented by covering the wiring with a wiring protective layer.

  The cavities between the wirings can be easily formed by ashing the carbon layer using annealing or oxygen plasma treatment in an oxygen atmosphere.

  In order to increase the mechanical strength of the semiconductor device, a material that reacts with the wiring such as silicon may be provided on the carbon layer and the wiring. Also, the mechanical strength of the semiconductor device can be increased by providing a metal oxide layer on the cavity.

  In order to prevent the wiring from being oxidized during the ashing of the carbon layer, the wiring may be surrounded by a protective layer that does not transmit oxygen.

  Surrounding the wiring with a cavity is effective in reducing the parasitic capacitance between the wirings at the same level.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device of FIG. 1. The perspective view which shows the semiconductor device in connection with the 2nd Embodiment of this invention. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a perspective view showing a step of the method for manufacturing the semiconductor device of FIG. 7. The perspective view which shows the semiconductor device in connection with the 3rd Embodiment of this invention. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. FIG. 24 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 23. The perspective view which shows the semiconductor device in connection with the 4th Embodiment of this invention. FIG. 35 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 34. FIG. 35 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 34. FIG. 35 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 34. FIG. 35 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 34. FIG. 35 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 34. The perspective view which shows the semiconductor device in connection with the 5th Embodiment of this invention. FIG. 41 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 40. FIG. 41 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 40. FIG. 41 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 40. FIG. 41 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 40. FIG. 41 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 40. The perspective view which shows the semiconductor device in connection with the 6th Embodiment of this invention. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. FIG. 47 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 46. The perspective view which shows the semiconductor device in connection with the 7th Embodiment of this invention. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. FIG. 54 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 53. The perspective view which shows the semiconductor device in connection with the 8th Embodiment of this invention. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. FIG. 61 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 60. The perspective view which shows the semiconductor device in connection with the 9th Embodiment of this invention. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. FIG. 68 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 67. The figure which shows the wafer in connection with the 10th-17th embodiment of this invention. The figure which shows a part of wafer concerning 10th-17th embodiment of this invention. The perspective view which shows the semiconductor device in connection with the 10th Embodiment of this invention. The perspective view which shows the semiconductor device in connection with the 10th Embodiment of this invention. The perspective view which shows the semiconductor device in connection with the 11th Embodiment of this invention. The perspective view which shows the semiconductor device in connection with the 11th Embodiment of this invention. The perspective view which shows the semiconductor device in connection with the 12th Embodiment of this invention. A perspective view showing a semiconductor device concerning a 13th embodiment of the present invention. The perspective view which shows the semiconductor device concerning the 14th Embodiment of this invention. The perspective view which shows the semiconductor device concerning the 15th Embodiment of this invention. The perspective view which shows the semiconductor device concerning the 16th Embodiment of this invention. A perspective view showing a semiconductor device concerning a 17th embodiment of the present invention. The perspective view which shows the semiconductor device concerning the 18th Embodiment of this invention. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. FIG. 87 is a perspective view showing a step in the method for manufacturing the semiconductor device in FIG. 86. A perspective view showing a semiconductor device concerning a 19th embodiment of the present invention. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. FIG. 110 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 102. A perspective view showing a semiconductor device concerning a 20th embodiment of the present invention. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. FIG. 114 is a perspective view showing a step of the method for manufacturing the semiconductor device in FIG. 113. A perspective view showing a semiconductor device concerning a 21st embodiment of the present invention. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. FIG. 121 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 120. A perspective view showing a semiconductor device concerning a 22nd embodiment of the present invention. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. FIG. 127 is a perspective view showing a step of the method of manufacturing the semiconductor device in FIG. 127. A perspective view showing a semiconductor device concerning a 23rd embodiment of the present invention. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. FIG. 143 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 143. A perspective view showing a semiconductor device concerning a 24th embodiment of the present invention. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. FIG. 157 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 154. A perspective view showing a semiconductor device concerning a 25th embodiment of the present invention. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. 161 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 161. FIG. A perspective view showing a semiconductor device concerning a 26th embodiment of the present invention. FIG. 38 is a perspective view showing a semiconductor device according to a twenty-seventh embodiment of the present invention. A sectional view showing a semiconductor device concerning the 28th embodiment of the present invention. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. 170 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 170. FIG. A sectional view showing a semiconductor device concerning a 29th embodiment of the present invention. FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; FIG. 178 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 177; The perspective view which shows the semiconductor device in connection with 30th Embodiment of this invention. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. FIG. 184 is a perspective view showing one step in a method for manufacturing the semiconductor device in FIG. 184. Sectional drawing which shows 1 process of the ashing process of a carbon layer. Sectional drawing which shows 1 process of the ashing process of a carbon layer. A perspective view showing a semiconductor device concerning the 31st embodiment of the present invention. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. 199 is a perspective view showing one step in a method for manufacturing the semiconductor device of FIG. 199. FIG. A sectional view showing a semiconductor device concerning a 32nd embodiment of the present invention. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. FIG. 222 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 212. A sectional view showing a semiconductor device concerning a 33rd embodiment of the present invention. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. FIG. 219 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. A sectional view showing a semiconductor device concerning the 34th embodiment of the present invention. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 226 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device in FIG. The perspective view which shows the conventional semiconductor device.

Explanation of symbols

  11, 71: Semiconductor substrate, 12, 14, 72, 74, 76: Insulating layer, 13, 73, W1, W2: Wiring, 15, 75: Cavity, 16, 39, 41, 44, 80a, 80b: Carbon layer 17, 77: Mask material, 21: Semiconductor substrate, 22: Field oxide layer, 23: Gate electrode, 24a, 24b: Source / drain region, 25, 32: Insulating layer, 26a-26c, 33a to 33c: Conductive layer, 27a to 27d, 34a to 34d: Barrier layer, 28a to 28d, 35a to 35d: Metal, 29, 30, 36, 37, 42, 43: Insulating layer, 31, 38, 40: Cavity 32: Insulating layer 45, 46: Resist 47: Wafer 48: Chip 49: Dicing line 50a, 50b, 51a, 51b: Arrangement Protective layer, 60: Silicon layer, 61: Alloy layer, 62: Metal layer, 63: Metal oxide layer, 64, 68: Insulating layer, 65: Protective metal layer, 66: Oxidized layer, 67: Protective layer, G: Ga -Dring, D1: Dummy wiring.

Claims (17)

Oxygen is provided between the semiconductor substrate, the first insulating layer formed on the semiconductor substrate, the plurality of first wirings formed on the first insulating layer, and the plurality of first wirings. A plurality of first insulating layers formed on the plurality of first wirings and a plurality of first insulating layers formed on the second insulating layers on the plurality of first wirings, respectively. The contact holes, the plurality of columnar conductive layers formed in and on the plurality of first contact holes, respectively, and the plurality of conductive layers so as to form a cavity containing oxygen between the plurality of conductive layers. A third insulating layer formed on the plurality of layers; a plurality of second contact holes formed on the third insulating layer on the plurality of conductive layers; and the plurality of second contact holes. on the inner Oyobi, further said third plurality of second lines are respectively formed on the insulating layer A semiconductor device characterized by comprising a fourth insulating layer between the plurality of the second wiring is formed on the second wiring of said plurality such that the cavity containing oxygen.   2. The semiconductor device according to claim 1, wherein the plurality of conductive layers and the plurality of second wirings integrally have a damascene structure.   The cavity between the plurality of first wirings, the cavity between the plurality of conductive layers, and the cavity between the plurality of second wirings are filled with a mixed gas of oxygen and carbon dioxide, respectively. The semiconductor device according to claim 1, wherein:   Air is filled in the cavities between the plurality of first wirings, the cavities between the plurality of conductive layers, and the cavities between the plurality of second wirings, respectively. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein surfaces of the second, third, and fourth insulating layers are flat. The semiconductor device according to claim 1,
A portion having a configuration similar to the configuration of the plurality of first wirings and formed on the first insulating layer so as to surround the plurality of first wirings;
A portion formed on the third insulating layer so as to surround the plurality of second wires, and a configuration of the plurality of conductive layers; A guard ring having a similar configuration and including a portion formed between the plurality of first wirings and the plurality of second wirings so as to surround the plurality of conductive layers; A semiconductor device characterized by the above. The semiconductor device according to claim 1,
A dummy wiring having a configuration similar to the configuration of the plurality of first wirings, formed between the plurality of first wirings, and supporting the second insulating layer;
A semiconductor device having a configuration similar to the configuration of the plurality of second wirings, and a dummy wiring formed between the plurality of second wirings and supporting the fourth insulating layer. apparatus.   In the case where a bonding layer for bonding the plurality of first wirings and the second insulating layer is provided, and the second insulating layer is made of silicon oxide, the bonding layer includes the first wiring 2. The semiconductor device according to claim 1, comprising a reaction product with wiring.   Forming a first insulating layer on the semiconductor substrate; forming a first solid layer on the first insulating layer; and forming a plurality of first grooves in the first solid layer. A step of forming a plurality of first wirings by embedding a first conductor in the plurality of first grooves, and oxidizing the first solid layer and the plurality of first wirings. Forming a second insulating layer made of a material, and oxidizing the first solid layer by allowing oxygen to pass through the second insulating layer and reacting with the first solid layer, thereby oxidizing the first solid layer. A step of converting the solid layer into a first gas layer, a step of forming a second solid layer on the second insulating layer, and a plurality of the solid layers on the second solid layer and the second insulating layer. Forming a plurality of first contact holes reaching the first wiring of the first wiring, and a second conductor in the plurality of first contact holes. Forming a plurality of columnar conductive layers by embedding a body, forming a third insulating layer made of the oxide on the second solid layer and the plurality of conductive layers, and the third A step of forming a third solid layer on the insulating layer, a step of forming a plurality of second grooves in the third solid layer, and a plurality of layers reaching the plurality of conductive layers in the third insulating layer. Forming a second contact hole, and embedding a third conductor in the plurality of second grooves and the plurality of second contact holes to form a plurality of second wirings. A step of forming, a step of forming a fourth insulating layer made of the oxide on the third solid layer and the plurality of second wirings, and the third and fourth insulating layers with oxygen. And oxidizes the second and third solid layers by reacting them with the second and third solid layers. The method of manufacturing a semiconductor device characterized by comprising the step of converting the second and third solid layer to the second and third gas layers.   Forming a first insulating layer on the semiconductor substrate; forming a first solid layer on the first insulating layer; and forming a plurality of first grooves in the first solid layer. A step of forming a plurality of first wirings by embedding a first conductor in the plurality of first grooves, and oxidizing the first solid layer and the plurality of first wirings. Forming a second insulating layer made of a material, and oxidizing the first solid layer by allowing oxygen to pass through the second insulating layer and reacting with the first solid layer, thereby oxidizing the first solid layer. A step of converting the solid layer into a first gas layer, a step of forming a second solid layer on the second insulating layer, and a third layer made of the oxide on the second solid layer Forming an insulating layer; forming a third solid layer on the third insulating layer; and forming a plurality of second grooves in the third solid layer. Forming a plurality of contact holes reaching the plurality of first wirings in the third insulating layer, the second solid layer, and the second insulating layer; and A step of embedding a second conductor in the two grooves and the plurality of contact holes to simultaneously form a plurality of second wirings and a plurality of columnar conductive layers; and on the third solid layer; Forming a fourth insulating layer made of the oxide on the plurality of second wirings, and allowing the oxygen to permeate the third and fourth insulating layers to form the second and third solid layers. And a step of oxidizing the second and third solid layers by reacting with each other to convert the second and third solid layers into second and third gas layers. Device manufacturing method.   The first, second and third solid layers are carbon layers, and by ashing the carbon layer, between the plurality of first wires, between the plurality of second wires, and 11. The method for manufacturing a semiconductor device according to claim 9, wherein a space filled with a mixed gas of oxygen and carbon dioxide is formed between the plurality of conductive layers.   11. The plurality of first grooves and the plurality of second grooves are formed by anisotropic etching using a resist as a mask, and the resist is peeled off by a chemical solution. The manufacturing method of the semiconductor device of description.   The plurality of first grooves and the plurality of second grooves are formed by anisotropic etching using an insulating mask as a mask, and the insulating mask is formed by anisotropic etching using a resist as a mask, The method for manufacturing a semiconductor device according to claim 9, wherein the resist is peeled off by a chemical solution.   The method of manufacturing a semiconductor device according to claim 13, wherein when the insulating mask is made of an oxide, the insulating mask is formed by a sputtering method.   The said 2nd, 3rd, and 4th insulating layer is formed by sputtering method, respectively when the said 2nd, 3rd, and 4th insulating layer is comprised from an oxide. A method for manufacturing a semiconductor device according to 9 or 10.   11. The method of manufacturing a semiconductor device according to claim 9, wherein the oxidation of the first, second and third solid layers is achieved by heat treatment or oxygen plasma treatment in an oxygen atmosphere.   11. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of filling the first, second, and third gas layers with air.

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