JP4472725B2 - Logic module and logic emulation module - Google Patents

Description

  The present invention relates to a technology for developing a large-scale integrated circuit using a logic emulator for performing logic verification.

  In recent years, an increase in the number of gates, an increase in the number of pins, and a reduction in size of a large scale integrated circuit (LSI) applied to an information processing apparatus such as a server have progressed.

  In order to improve the logic verification accuracy of LSIs when designing such logic elements such as LSIs, hardware emulation using FPGA (Field Programmable Gate Array), which is a programmable LSI, in addition to conventional software simulation technology Is applied to LSI logic verification. However, with the recent increase in the number of gates of LSI internal circuits, a large number of FPGAs are required for logic verification. As an example of such an apparatus for logic verification, there is a technique described in Patent Document 1 (Japanese Patent Laid-Open No. 6-3414).

  The technology described in Japanese Patent Application Laid-Open No. 6-3414 is a pseudo-realization of logic for verification in an emulation device that is connected to a target machine (actual machine: logic verification target) and performs hardware operation check. The pseudo LSI device includes a plurality of FPGAs, a nonvolatile memory that stores circuit data for verification, a transfer unit that performs data transfer between the FPGA and the nonvolatile memory, and a power supply unit. Even when the device is disconnected from the emulation device, the pseudo LSI device can hold the circuit data.

As a method for mounting such an LSI, there is a multi-chip module in which a plurality of LSIs are mounted as bare chips on a substrate. Also, an LSI package called CSP (chip size package) in which a bare chip is mounted using a solder ball through a substrate called a carrier can be easily mounted and replaced with a projected area equivalent to the bare chip and a conventional manufacturing method. It is used as an effective means. In multi-chip modules and CSPs, the amount of heat generation per unit area increases with higher integration and logic scale expansion, so a cooling structure that efficiently dissipates heat generated by logic LSIs is required.
JP-A-6-3414

  However, the FPGA and the LSI to be developed have different package sizes, connection structures, and pin arrangements, and thus there has been a problem that the logic verification target board for mounting the FPGA has to be redesigned. In other words, since the package structure of the FPGA is a general PGA (pin grid array), QFP (quad flat package), or BGA (ball grid array), in order to combine a plurality of FPGAs, the board size to be mounted must be increased. In other words, it is necessary to construct an emulation device that logically divides into a plurality of boards and connects them via a backplane board. In this case, some connection means is required between the development target LSI and the logic board.

  An object of the present invention is to provide a logic module for logic verification that can be used as it is without redesigning a board to be verified, and a technique for developing an LSI using the logic module.

  Another object of the present invention is to provide a technique for realizing efficient heat conduction cooling of a multichip module.

  The present invention includes at least one switching LSI capable of programming a connection between circuits and an FPGA that realizes logic by programming on one or both sides of a substrate using a gate provided therein. Further, a logic module is configured in which a connector that is electrically connected to the outside is mounted on at least one side of the peripheral portion of the substrate, and the FPGA and the connector are connected via a switching LSI.

  In the present invention, the logic board subject to logic verification includes a connector for connecting to the logic module, a connector for connecting to the logic module, and a terminal land on which the development target LSI is mounted. Are connected one to one.

  By connecting the connector of the logic module and the connector on the logic board and mounting the logic module on the logic board to be verified, the logic verification is performed using the logic board on which the LSI to be developed is actually mounted. Can be performed. Further, after the logic verification, it is possible to remove the logic module and mount the development target LSI on the logic board for evaluation.

  Further, when an FPGA is required, the logic modules are continuously connected in two or more stages via external connection connectors on the logic modules. In this way, it is possible to further expand the logical scale with the same mounting area.

  Further, when the number of external terminals of the LSI mounted on both sides of the logic module is different, the LSI is converted into a certain land layout by a substrate called a carrier. By arranging both sides of the logic module in the same land arrangement, the same signal terminal land, the same power source, and the ground terminal land can be connected only by the through-through hole of the logic module board, and the wiring design is facilitated.

  In addition, the present invention attaches a heat sink to the four corners of the logic module via metal spacers, and deforms and closely adheres to the LSI and various LSIs such as FPGA and switching LSI mounted on the logic module following the shape of the LSI. A heat conductive sheet having elasticity is provided. The heat generated by the LSI is radiated through the heat conductive sheet and the heat radiating plate. Since the heat conductive sheet deforms following the shape of the LSI, even if LSIs having different heights are mounted on the same surface of the substrate, the difference in height can be absorbed. In addition, a cooling structure that does not hinder component placement and wiring design is realized by attaching heat sinks to the four corners of the logic module via metal spacers.

  Further, when the logic module has a multi-stage configuration, heat generated by the lower logic module is conducted to the upper radiator plate by a heat conduction sheet that can be freely bent. Such a configuration enables efficient cooling even when the logic module has a multi-stage configuration.

  According to the present invention, a plurality of logic LSIs are mounted on one logic module, and these connections are connected directly and using a switching LSI, thereby enabling efficient wiring with a minimum necessary mounting space and making a small module. be able to. In addition, a multi-stage configuration using an external connection connector, the logic scale per unit area can be expanded, and the logic board can be directly connected to the logic board to be verified, and the logic board can be developed without redesign after the logic verification. The target LSI can be mounted and evaluated. In addition, efficient cooling with reduced thermal stress and reduced stress on the LSI chip can be performed not only in a single module but also in a multi-stage module without hindering component placement. In addition, there is a degree of freedom in wiring with respect to the connection between a programmable LSI that can program logic and a logic module that includes a switching LSI that can program connection, and the number of pins of the switching LSI can be reduced. In addition, control is possible from both the device interface connector and the external interface connector.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1-3 show a first embodiment of the logic module of the present invention. 1 is a front view of the logic module as viewed from above, FIG. 2 is a back view as viewed from below, and FIG. 3 is a cross-sectional view.
In FIG. 1, a plurality of logic LSIs 4 a such as FPGA are mounted on the surface of the module substrate 2 via a substrate 36 called a carrier. The carrier 36 will be described with reference to FIGS. 4 and 5. Further, a connector 3 that is electrically connected to the outside is mounted on the peripheral edge of the module substrate 2.

  In FIG. 2, a plurality of logic LSIs 4 b such as switching LSIs are mounted on the back surface of the module substrate 2 via carriers 36. In this embodiment, four connectors are provided. By mounting a plurality of connectors in this way, it is possible to secure more terminals as output terminals from the logic LSI 4b and to easily replace them. It is.

  FIG. 3 shows a cross section of the logic module 1. In this embodiment, the logic LSI 4 is mounted with a BGA connected by solder balls arranged in a grid at a certain interval, but the mounting area is reduced by using a BGA in which the solder ball array is narrower than the conventional 1.27 mm interval. It can be reduced and the logical scale per unit area can be increased. Such BGA is called FBGA (Fine Pitch BGA) or CSP, and the solder ball spacing is 1.0mm, 0.8mm, 0.75mm, 0.65mm, 0.5mm from LSI manufacturer to JEDEC, EIJA. Proposed. Further, as in this embodiment, it is possible to cope with large-scale logic verification by mounting a plurality of logic LSIs 4 on both sides.

  In FIG. 3, the mounting positions of the logic LSIs 4a and 4b and the connectors mounted on both surfaces of the module substrate 2 are opposed to each other on the front and back sides. This point will be described with reference to FIGS.

  4 and 5 are enlarged views of a cross section of the logic module 1, and are diagrams illustrating an example of a wiring connection method of the logic LSIs 4a and 4b.

  First, FIG. 4 is an example of a case where one-to-one connection is made between the logic LSIs 4a and 4b mounted on the front and back facing positions. On both surfaces of the module substrate 2, lands 31 and outer layer wiring layers 32 connected to the terminals of the logic LSIs 4 a and b through the carrier 36 are arranged. The outer wiring layer 32 is arranged in a cross shape at the center of the module substrate 2, for example. The board module 2 is connected to both surfaces by using through-through holes 34 that arbitrarily connect each wiring layer such as the land 31 and the outer wiring layer 32.

  FIG. 5 shows an example in the case where it is necessary to connect not only between the logic LSIs 4a and 4b at the relative positions but also with other logic LSIs 4a and 4b. In FIG. 5, non-penetrating through holes 35 for connecting the outer wiring layer 32 and the inner wiring layer 33 are provided on both surfaces. The connection with the logic LSIs 4a and 4b at the non-relative positions is performed by the non-through hole 35 and the inner wiring layer 33 that connects the non-through hole 35 and the through hole 34 inside the module substrate 2.

  4 and 5, even if the number of external terminals of the logic LSIs 4a and 4b mounted on the respective surfaces is different due to the different functions of the front surface side and the back surface side of the logic module 1, the carrier 36 is used to provide a certain amount. The land placement is converted to the land layout, and the mounting positions facing each other are realized. For example, if the land of the same signal, the same power supply terminal, and the GRD terminal of the logic LSI 4a mounted on the front surface side and the logic LSI 4b mounted on the back surface side are set to the relative positions, they are directly connected by the through through hole 34. This makes wiring design easier. When the same signal terminal land, the same power source, and the GRD terminal land are not in a positional relationship facing each other, as shown in FIG. 5, the through through hole 34 provided at an arbitrary position through the inner wiring layer 33 from the non-through through hole 35. Can be connected through.

  Although not shown in the present embodiment, the logic LSIs mounted on the same surface are connected to the outer layer wiring layer 32 from the non-through hole 35 via the inner layer wiring layer 33. Accordingly, the wiring area between the logic LSIs 4a and 4b is an arrangement area of the component mounting land 31 and the through through hole 34 connected from the non-through through hole 35 via the inner wiring layer 33. Therefore, the logic module can be miniaturized.

  In this embodiment, a hole-on pad that forms a through hole immediately below the component mounting land 31 is used, but the through hole may be provided at a position offset from the component mounting land 31.

  The illustrated module substrate 2 is a sequential laminated substrate in which two multilayer substrates having through through holes for connecting the outer wiring layer 32 and one or more inner wiring layers 33 are bonded together and further through through holes are formed. However, it goes without saying that it can be realized even with a build-up substrate having a through-through hole and a non-through-through hole that is linearly connected from the outer wiring layer to a desired inner wiring layer.

  FIG. 6 is a cross-sectional view of the logic board 21 on which the logic module 1 is mounted. The logic board 21 to be subjected to logic verification includes a stack type receptacle connector 22 for connecting the logic module 1, a land 63 for mounting the connector, and a land 62 for mounting the LSI 61 to be developed. The logic module 1 has a size corresponding to the LSI 61 to be developed, and the land 62 is arranged below the position where the module 1 is mounted.

  In FIG. 6, when the terminal of the LSI 61 to be developed connected to the land 62a and the terminal 63a of the connector 22 connected to a terminal with a connector on the logic module 1 have the same function, for example, a GRD terminal. The land 62a is connected to the connector 22a via the through-hole 64 and the wiring 65 on the back surface of the logic board 21. Similarly, the land 62b and the terminal 63b are also connected via the wiring 66 on the surface of the logic board 21. Thus, the land 63 for mounting the connector and the land 62 for mounting the LSI 61 to be developed are connected one-to-one. As described above, the land 62 on which the logic module 1 is mounted and the land 63 on which the connector is mounted are connected on a one-to-one basis, so that both the logic module 1 and the LSI 61 to be developed are mounted on the logic board 21. It becomes possible.

  FIG. 7 shows an example of mounting the development target LSI 61 on the logic board 21.

  Thus, after logic verification, it is possible to remove the logic module 1 and mount the development target LSI 61 for evaluation, and there is no need to redesign the logic board 21. Further, the connector 22 can be left on the logic board 21 without being removed, and the connector 22 can be used as a waveform observation terminal when the development target LSI 61 is evaluated.

  FIG. 8 shows an example of mounting the logic module 1 of the present invention on the logic board 21.

  The logic module and the logic board 21 are connected by a connector 23 mounted on the back surface of the logic module 1 and a connector 22 mounted on the logic board 21 in a relative positional relationship with the connector 23. In this embodiment, the connector 23 mounted on the back side of the logic module 1 is a stack type plug connector 23, and the connector on the logic board 21 side is a stack type receptacle connector 22.

  A connector 22b for loading the logic module 1 may be further provided on the surface of the logic module 1. The connector 22b for loading does not have to be the same as the connector on the logic board 21, but for example, when the same stack type receptacle connector 22 as the connector mounted on the logic board 21 is mounted at a position relative to the back side connector, Two or more stages of logic modules 24 having the same function or logic modules 25 having different functions can be connected in succession, so that the logic scale can be expanded and the functions can be expanded by a multi-stage configuration.

  FIG. 9 shows an example of a loading method of the logic modules 1.

  FIG. 9A shows an example in which logic modules 1, 24, and 25 are stacked on one side of the logic board 21. The logic modules to be loaded need not have the same function. Even if logic modules having different functions, for example, a circuit for setting a configuration at the time of logic verification or a logic module provided with a memory circuit are loaded. Good.

  Further, as described above, the front-side connector and the rear-side connector of the logic module 1 can be connected in multiple stages and in any order if the power supply, GRD terminal and control terminal such as clock and reset signal are arranged at opposite positions. it can.

  Furthermore, the connector on the surface of the uppermost logic module 25 can be used as a waveform observation terminal for logic verification.

  FIG. 9 b shows an example in which the logic module 1 is mounted on both sides of the logic board 21. The logic board 21 includes a connector for connecting to the logic module 1 at a relative position between the front surface and the back surface. In this way, the logic module 1 can be mounted on both sides of the logic board 21. In this embodiment, the logic module mounted on the back side of the logic board 21 is one stage, but it is needless to say that it can have a multi-stage configuration as in the front side.

  Next, the internal structure of the logic module 1 of the present invention will be described with reference to FIGS.

  FIG. 10 is a schematic diagram of one embodiment of the wiring of the logic part of the logic module 1 according to the present invention.

  The logic module 1 includes, for example, FPGAs 101a to 101d that are programmable LSIs that can program logic, switching LSIs 102a to 102d that can program connections, device interface connectors 103a to 103d, external interface connectors 104a to 104d, and logic signals between the elements. The wiring 108-112 is comprised.

  In the FPGAs 101a to 101d, in order to operate a large-scale logic using the logic module 1, a plurality of logical data obtained by dividing the logic is programmed. In order to connect the logic divided into the FPGAs 101a to 101d, connection between the programmable LSIs 101a to 101d is necessary. In the case of a 1: 1 net that connects two FPGAs 101a to 101d, the programmable LSIs 101a to 101d are connected by a logic signal wiring 107 that connects 1: 1. In the case of a net connecting two or more FPGAs such as 1: 2, the signal wiring 108 is connected via the switching LSIs 102a to 102d.

  The switching LSIs 102a to 102d connect the FPGAs 101a to 101d, the device interface connectors 103a to 103d, and the external interface connectors 104a to 104b by a program. FIG. 11 shows a schematic diagram of an internal circuit of the switching LSI 102a.

  In FIG. 11, the switching LSI 102a includes MOS transistors 200a to 200d and storage elements 201a to 201d. In addition, logic signal wirings 108a to 108d are connected to the switching LSI 102a, and the logic signal wirings 108a to 108d are connected to, for example, FPGAs 101a to 101d, respectively.

  For example, the logic signal wiring 108a is connected to the logic signal wirings 108b to 108d inside the switching LSI 102a by MOS transistors a to d. When a 1: 2 net is formed by connecting the logic signal wiring 108a and the logic signal wirings 108b and c, logic data is written to the storage elements 201a and 201b so that the MOS transistors 200a and 200b are turned on. Further, logic data is written to the memory elements 201c and 201d so that the MOS transistors 200c and 200d are turned off. As a result, the logic signal wirings 108a, 108c and 108d are connected. In this manner, a desired connection can be configured by writing connection data to the storage elements 201a to 201d of the switching LSI 102a.

  Returning to FIG. 10, the device interface connectors 103a to 103d are connectors for connecting the logic module 1 and the device. Signal wiring 109 is directly connected to the device interface connectors 103a to 103d from the programmable LSIs 101a to 101d. When the connector pin arrangement is limited, the signal wiring 111 can be selected and connected by the switching LSIs 102a to 102d via the signal wiring 108.

The external interface connectors 104a and 104b are connectors that connect the logic module 1 and the outside. Similarly to the device interface connectors 103a to 103d, the external interface connectors 104a to 104b are connected to the signal wiring 110 that can be directly connected and to the signal wiring by the switching LSIs 102a to 102d via the signal wiring 108. The case where 112 is selected and connected can be considered.
Further, when an oscilloscope for observing signals between the RAM module and the FPGAs 101a-d is connected to the external interface connectors 104a-b, it is also possible to connect via the signal wiring 110 and the signal wirings 108a-d. It is.

  In the case of a connection method in which all the wirings between the FPGAs 101a to 101d are routed to the switching LSIs 102a to 102d via the signal wirings 108a to 108d, the degree of freedom of wiring is increased, but the number of I / O pins of the switching LSIs 102a to 102d is limited. There was a problem that has been. Further, in the case of the connection method in which the FPGAs 101a to 101d are wired only by the logic signal wiring 107, there is a problem that the pin arrangement of the FPGAs 101a to 101d is not flexible and the logic mounting rate is lowered. In the present invention, it is possible to mount the FPGA and the switching LSI on both sides of the logic module 1 so as to be in relative positions, and by effectively using both connection methods, the wiring of the switching LSI can be provided while giving freedom to the wiring. The effect that the number of pins can be reduced can be obtained.

  FIG. 12 shows an example of the wiring of the control unit when the logic module 1 has the configuration of the logic unit shown in FIG. 10. In the stacked structure as shown in FIG. In this example, the logic module 1b and the control logic board 160 are connected and mounted on the logic board 21.

  In the logic module 1a, the logic data write control signal wiring is composed of control signal wirings 130a to 136a of the FPGAs 101a to 101d and control signal wirings 120a to 126a of the switching LSIs 102a to 102d.

  Similarly, in the logic module 1b, the logic data write control signal wiring is composed of the control signal wirings 130b to 136b of the FPGAs 101e to f and the control signal wirings 120b to 126b of the switching LSIs 102e to f.

  The control circuit logic board 160 is composed of ROMs 164a-b and control circuits 163a-b in which logic data is written.

  The logic data programmed in the FPGAs 101e-h is first output from the ROM 164b to the control signal wiring 134b via the control circuit 163b, the control signal wiring 130b, the FPGA 101e, and transmitted to the next-stage FPGAs 101f-h. Further, the data is transmitted from the logic module 1b to the logic module 1a via the control signal wiring 131a. Similarly to the logic module 1b, the logic module 1a is also transmitted from the control signal wiring 130a to the FPGA ab to b101 via the control signal wirings 134a to 136a, and the control signal wirings 132a to 132b via the external wiring 141. Then, the control circuit logic board 160 returns. Signals to be controlled in parallel to the FPGA 101 are controlled by the control signal wirings 133b and 133a via the control circuit logic board 160.

  Thus, logical writing is possible even if a plurality of logical modules are mounted on the logical module. Further, the same control signal wiring is connected to the external interface connectors 104a and 104b and the device interface connectors 103a and 103b as terminals. With such a configuration, the logic of the control circuit logic board 160 can be mounted on the device board 170 and controlled. Thus, by connecting the control signal to the device interface connector 103 and the external interface connector 104, control can be performed from both connectors.

  Further, when one logic module 1a is controlled, a signal to be continuously controlled is input to the control circuit logic board 170 through each of the FPGAs 101a to 101d and the control signal wiring 131a via the control signal wiring 130a. The external wiring 141 of 170 becomes unnecessary.

  Although the logic data is described only for the control circuit logic board 160, it is also possible to connect a terminal such as a personal computer and the external terminal 151 and control from the personal computer instead of the control circuit logic board 160.

  FIG. 13 is a diagram showing another embodiment of the logic module of the present invention.

  In the logic module 81, a plurality of logic LSIs 4 are mounted in a cavity portion 83 formed on one side or both sides of a module substrate 82, and terminal lands 84 electrically connected to the outside are provided on the peripheral portion of the substrate. The height of the logic LSI 4 can be absorbed by the depth of the cavity, and the external connection terminal land can be connected to the logic board and the logic modules having the same function or different functions can be connected in multiple stages.

  The terminal lands 84 on both sides are arranged so that the power supply, the GRD terminal, and the control terminals for the clock, reset signal, and the like are opposed to each other. By doing in this way, it is possible to connect in multiple stages and in any order. For example, solder is used to connect the terminal lands 84.

  In connection with solder, the self-alignment property by the surface tension of solder can be utilized. That is, even if there is a slight shift in the mounting position, the shift can be absorbed using the self-alignment property. For example, if the amount of displacement of the mounting position is about 1/3 of the land diameter, the self-arament effect can be sufficiently expected.

Next, the cooling structure of the logic module 1 will be described with reference to FIGS.
FIG. 14 is a diagram showing an example of the cooling structure of the logic module of the present invention.

  First, in FIG. 14A, the heat sink 42 is attached to the four corners on the logic module 1 through the metal spacers 43, and the cooling fins or the cooling fans 44 are installed on the heat sink 42. A heat conductive sheet 41 is further interposed between the logic LSI 4 such as FPGA mounted on the logic module 1 and the heat radiating plate 42. The heat conductive sheet 41 has elasticity that can be deformed and adhered following the shape of the logic LSI 4. The heat generated from the logic LSI 4 is conducted to the heat radiating plate 42 and cooled by the cooling fins or the cooling fan 44. The heat conductive sheet 41 is, for example, silicon rubber in which metal particles such as silver having high heat conductivity are added and dispersed as a filler. The heat sink is, for example, copper or aluminum. The metal spacer is a brass plated with nickel.

  FIG. 14B is a cross-sectional view showing an example of the metal spacer 43.

  Since the metal spacer 43 is provided with a screw hole 47 and a tap 48 is cut, the metal spacer 43 can be connected. The heat sink 42 is attached to the metal spacer 43 using screws 45. Further, when the logic module 1 is fixed to the logic board 21, the metal spacer 43 is used and the nut 46 is tightened on the back surface of the logic board 21.

  As described above, the thermal conductive sheet 41 can absorb the difference in the heights of a plurality of LSIs on the same surface and can be cooled in a batch, and in particular, a machine for LSI chips when flip-chip mounting LSI chips face down. Heat conduction cooling with reduced mechanical stress.

  Furthermore, if the thermal expansion coefficients of the heat radiating plate 42 and the module substrate 2 are approximated, it is possible to suppress one of them from being bent and deformed due to the difference in thermal expansion coefficient. Further, the adhesion between the LSI chip and the heat conductive sheet and between the heat conductive sheet and the heat radiating plate can be improved, and the heat radiation effect can be enhanced. For example, the thermal expansion coefficient of a general glass epoxy substrate is around 15 ppm / ° C., and the copper plate is 17 ppm / ° C., which are almost the same. Therefore, effective cooling can be performed by using these materials.

  In addition, since the metal spacers are provided at the four corners of the module substrate, the arrangement of components and wiring are not hindered, and the design of the logic module becomes easy.

  The example shown in FIG. 14 uses a single logic module as an example, but a similar cooling structure can also be applied to a multi-stage logic module.

  FIG. 15 is a diagram illustrating an example of a cooling structure for a logic module having a multi-stage configuration.

  In FIG. 15, the cooling structure of the logic module 1 on the lower surface is the same as that in FIG. The heat generated by the LSI on the back surface of the upper logic module 1 is conducted to the heat sink 42 on the front surface side of the lower logic module 1. One end of a heat conductive sheet 51 that can be freely bent is attached to the heat radiating plate 42 with a heat conductive adhesive 52. The other end of the heat conductive sheet 51 is attached to a heat sink on the upper surface side with a heat conductive adhesive 52. In this way, heat conduction can be performed efficiently. The material of the heat conductive sheet 51 that can be bent freely is, for example, a structure similar to a flexible substrate in which a copper foil having a thickness of several hundreds of μm is attached to a polyimide tape, or a graphite sheet obtained by crystallizing a polymer plastic sheet by high-temperature treatment. is there. Examples of the latter include PGS (Pyrolytic Graphite Sheet) of Matsushita Electric Industrial Co., Ltd.

  FIG. 16 is a developed view of a heat sink with a thermally conductive sheet that can be freely bent, and FIG. 17 is a sectional view thereof.

  In this way, the heat generation of the lower logic module 1 and the heat generation of the LSI on the back surface of the upper logic module 1 are conducted to the heat radiation plate of the upper logic module 1 by the heat conduction sheet 51 having flexibility. It can be cooled by cooling fins or cooling fans 44 attached to the heat radiating plate.

It is a top view of one embodiment of the logic module of the present invention. It is a reverse view of one Example of the logic module of this invention. It is sectional drawing of one Example of the logic module of this invention. It is a figure which shows an example of the wiring connection method of the logic module of this invention. It is a figure which shows an example of the wiring connection method of the logic module of this invention. It is sectional drawing of the part which mounts the logic module on a logic board. It is the figure which mounted development object LSI on the logic board. It is a figure which shows the example of mounting to the logic board of the logic module of this invention. It is a figure which shows the example of mounting of the multistage structure of the logic module of this invention. It is a conceptual diagram which shows the logic part wiring example of a logic module. It is a conceptual diagram which shows the example of an internal circuit of switching LSI. It is a conceptual diagram which shows the example of a control part wiring of a logic module. It is a figure which shows the other Example of the logic module of this invention. It is a figure which shows an example of the cooling structure of a logic module of this invention, and an example of a metal spacer. It is a figure which shows an example of the cooling structure of the logic module of a multistage structure. It is an example of the expanded view of the heat sink which affixed the heat conductive sheet which has flexibility. It is an example of sectional drawing of the heat sink which affixed the heat conductive sheet which has flexibility.

Explanation of symbols

1 ... logic module,
2 ... Module board,
3. External connector,
4… Logic LSI,
4a: Logic LSI on the surface side of the logic module,
4b: Logic LSI on the back side of the logic module,
21 ... Logic board
22 ... Stack type receptacle connector,
23 ... Stack type plug connector,
24. Logic module with the same function,
25 ... logic modules with different functions,
31 ... Land with LSI terminals,
32 ... outer wiring layer,
33 ... inner wiring layer,
34 ... through hole,
35 ... non-through hole,
36 ... carrier substrate,
41 ... heat conductive sheet having elasticity,
42 ... radiator plate,
43. Metal spacer,
44 ... cooling fins or cooling fans,
45 ... Screw,
46 ... nuts,
47 ... screw holes,
48 ... Tap,
51. Heat conductive sheet having flexibility,
52 ... Thermally conductive adhesive,
61 ... LSI to be developed,
62 ... Land where the LSI terminal to be developed is mounted,
63 ... Land for mounting the stack type receptacle connector terminal,
81. Logic modules of other embodiments,
82 ... Module substrate with cavity,
83 ... cavity part,
84: External connection terminal land,
101 ... Programmable LSI,
102: switching LSI,
103: Device interface connector,
104: External interface connector,
105: Device interface signal,
106: External interface signal,
107-112 ... logic signal wiring,
108a to 108d, logic signal wirings 120a to 126a, 120b to 126b, control signal wirings,
130a to 136a, 130b to 136b ... wiring for control signals,
140, 141 ... external wiring,
150, 151 ... external terminals,
160 ... control circuit logic board,
161: Control circuit interface connector,
162 ... control circuit external interface connector,
163... Control circuit,
164 ... ROM,
170: Device boards 200a to 200d ... MOS switches,
201a-201d ... Memory element

Claims (11)

A logic emulation module,
A plurality of programmable logic elements;
A plurality of switching elements programmable to connect between the plurality of programmable logic elements;
A plurality of connectors for electrically connecting to the outside of the logic emulation module;
A board for mounting the plurality of programmable logic elements, the switching elements and the plurality of connectors;
Is placed on the board, it has a wiring for transmitting data between the emulation,
The wiring includes at least wiring that directly couples the plurality of connectors and a plurality of programmable logic elements, and wiring that couples the plurality of connectors and the plurality of programmable logic elements via the plurality of switching elements. Including
The logic emulation module realizes at least an operation logically equivalent to an operation of a part of an integrated circuit to be developed mounted on a logic board prepared for logic verification,
Each of the plurality of programmable logic elements is directly connected to all of the other plurality of programmable logic elements and all of the plurality of switching elements.
This is a logic emulation module. The logic emulation module according to claim 1, wherein the plurality of programmable logic elements and the plurality of switching elements are mounted on a front surface and a back surface of the board. The plurality of programmable logic elements are mounted facing the front and back surfaces of the board, and the front and back surfaces of the board are assigned to the plurality of programmable logic elements, and the surface of the board 3. The logic emulation module according to claim 2, wherein lands are arranged facing each other and the back faces, and the lands facing each other are connected by a through hole. The plurality of programmable logic elements are mounted on a surface of the board, and the plurality of switching elements and a plurality of connectors for connecting to the logic board are mounted on a back surface of the board. Item 4. The logic emulation module according to Item 3. The logic emulation module according to claim 1, wherein the plurality of connectors are mounted on a front surface and a back surface of the board. 6. The logic emulation module according to claim 5, wherein the terminals of the plurality of connectors are arranged such that at least a power supply line and a ground line are arranged at positions where the front surface and the back surface of the substrate face each other, and are connected by a through hole. A logic module mounted on at least one side of the logic board,
A plurality of programmable logic elements;
A plurality of programmable logic elements and a plurality of connectors for transmitting input and output signals;
A plurality of switching elements for controlling connections between the plurality of programmable logic elements;
A land mounted on the logic board and supporting an integrated circuit to be developed;
The plurality of programmable logic elements are connected to the plurality of connectors or a plurality of switching elements,
Logic data for logic verification is programmed into the plurality of programmable logic elements,
Each of the plurality of programmable logic elements is directly connected to all of the other plurality of programmable logic elements and all of the plurality of switching elements;
The plurality of connectors are mounted on the same end of the first surface and the second surface of the logic board;
A logic module , wherein a part of terminals facing each other of the plurality of connectors mounted on the first surface and the second surface of the logic board transmits the same signal . A logic module mounted on at least one side of the logic board,
A plurality of programmable logic elements;
A plurality of programmable logic elements and a plurality of connectors for transmitting input and output signals;
A plurality of switching elements for controlling connections between the plurality of programmable logic elements;
A land mounted on the logic board and supporting an integrated circuit to be developed;
The plurality of programmable logic elements are connected to the plurality of connectors or a plurality of switching elements,
Logic data for logic verification is programmed into the plurality of programmable logic elements,
Each of the plurality of programmable logic elements is directly connected to all of the other plurality of programmable logic elements and all of the plurality of switching elements;
The plurality of programmable logic elements are mounted on at least a portion of a first surface of the logic board;
The plurality of switching elements are mounted on a second surface of the logic board facing the plurality of programmable logic elements;
A second board having a desired land arrangement inserted between the plurality of programmable logic elements or the plurality of connectors and the logic board;
A part of terminals for the plurality of programmable logic elements treated as the same signal and a part of terminals for the plurality of switching elements are connected by a through hole provided in the second board. logic module, wherein the <br/> that. A logic module,
A plurality of programmable logic elements programmed with logic therein;
A plurality of switching elements that are internally programmed for connection relationships;
A board supporting the plurality of programmable logic elements and a plurality of switching elements;
A connector for transmitting signals to the plurality of programmable logic elements and switching elements;
A first wiring connecting each of the plurality of programmable logic elements and all of the plurality of switching elements;
A second wiring interconnecting each of the plurality of programmable logic elements;
A third wiring connecting the plurality of programmable logic elements and the connector;
A fourth wiring connecting the plurality of switching elements and the connector;
The logic module, wherein the first to fourth wirings are used to connect logic signals constituting logic. The connector is composed of a first connector and a second connector arranged to face each other on the board,
Opposing first terminals of the first connector and the second connector transmit a first control signal connected in parallel to the plurality of programmable logic elements and the plurality of switching elements,
Opposing second terminals of the first connector and the second connector transmit an input signal of a second control signal connected in series to the plurality of programmable logic elements and the plurality of switching elements,
Opposing third terminals of the first connector and the second connector transmit an output signal of a second control signal connected in series to the plurality of programmable logic elements and the plurality of switching elements. The logic module of claim 9 , wherein   A plurality of terminal lands for connecting terminals of the plurality of programmable logic elements;
  The plurality of terminal lands and the connector are disposed in a peripheral portion of the board on which the plurality of programmable logic elements are mounted,
  The plurality of terminal lands and the terminals of the connector are connected one-to-one,
  Each of the connectors is a multi-stage connection type connector.
The logic module according to claim 9.

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