JP4466853B2 - Organic ferroelectric memory and manufacturing method thereof - Google Patents

Description

  The present invention relates to an organic ferroelectric memory and a method for manufacturing the same.

As a ferroelectric memory, a structure of a ferroelectric capacitor including an inorganic ferroelectric layer such as a Pb (Zr, Ti) O ₃ (PZT) system or SrBiTa ₂ O ₉ (SBT) is well known. The inorganic ferroelectric layer needs to be annealed at a high temperature of 600 ° C. or higher when it is formed. For this reason, the substrate for forming the ferroelectric capacitor is limited to one having heat resistance, and it is impossible to use a glass substrate or a flexible substrate as the substrate. Furthermore, since the inorganic ferroelectric layer contains heavy metals such as Pb and Bi, it is harmful to the environment and its handling is complicated.
Japanese Patent Application Laid-Open No. 5-89661

  One of the objects of the present invention is to realize a reduction in size / capacity and an easy manufacturing process in an organic ferroelectric memory and a manufacturing method thereof.

(1) An organic ferroelectric memory according to the present invention comprises:
A drive circuit section including a first thin film transistor;
A second thin film transistor having a source / drain electrode, an organic semiconductor layer, a gate insulating layer and a gate electrode; a lower electrode; an organic ferroelectric layer; and an upper electrode; and one of the source / drain electrodes is electrically A memory cell unit including a ferroelectric capacitor connected to the memory cell;
Including
The memory cell unit is stacked above the drive circuit unit. According to the present invention, since the memory cell unit is stacked above the drive circuit unit, it is possible to prevent an increase in planar area and to realize a reduction in memory size and capacity. In addition, since an organic ferroelectric layer is used for the ferroelectric capacitor and an organic semiconductor layer is used for the second thin film transistor, a low temperature process of, for example, 150 ° C. or lower is possible for the entire memory cell portion. Therefore, the restriction on the heat resistance of the substrate for forming the memory is relaxed, and the degree of freedom in selecting the substrate is improved. Further, since the organic ferroelectric material can be processed with low energy by a liquid phase process, the manufacturing process can be facilitated. Furthermore, there is no problem of environmental load due to heavy metals, it can be easily disposed of and it is easy to handle. In the present invention, the B layer is provided above the specific A layer means that the B layer is provided directly on the A layer and the B layer via another layer on the A layer. Is provided. The same applies to the following inventions.
(2) In this organic ferroelectric memory,
The ferroelectric capacitor may be disposed in an upper layer than the second thin film transistor.
(3) In this organic ferroelectric memory,
The organic semiconductor layer is formed above the source / drain electrodes,
The gate insulating layer is formed above the organic semiconductor layer,
The gate electrode may be formed above the gate insulating layer.
(4) In this organic ferroelectric memory,
The source / drain electrodes are formed above the organic semiconductor layer,
The gate insulating layer is formed above the source / drain electrodes,
The gate electrode may be formed above the gate insulating layer.
(5) In this organic ferroelectric memory,
The gate insulating layer is formed above the gate electrode,
The source / drain electrodes are formed above the gate insulating layer,
The organic semiconductor layer may be formed above the source / drain electrodes.
(6) In this organic ferroelectric memory,
The gate insulating layer is formed above the gate electrode,
The organic semiconductor layer is formed above the gate insulating layer,
The source / drain electrodes may be formed above the organic semiconductor layer.
(7) In this organic ferroelectric memory,
The organic semiconductor layer may be formed of a fluorene-thiophene copolymer.
(8) In this organic ferroelectric memory,
At least one of the lower electrode and the upper electrode may be formed of a conductive organic material. According to this, since the conductive organic material is more flexible than a normal metal, the hysteresis characteristics of the ferroelectric capacitor are improved.
(9) In this organic ferroelectric memory,
The organic ferroelectric layer is formed of any one of poly (vinylidene fluoride / trifluoroethylene), poly (vinylidene fluoride), (vinylidene fluoride / trifluoroethylene) co-oligomer, vinylidene fluoride oligomer, and odd-number nylon. May be.
(10) In this organic ferroelectric memory,
The first thin film transistor may be a low temperature polysilicon thin film transistor.
(11) In this organic ferroelectric memory,
The first thin film transistor may be an organic semiconductor thin film transistor.
(12) A method for manufacturing an organic ferroelectric memory according to the present invention includes:
(A) forming a first thin film transistor;
(B) forming a second thin film transistor having a source / drain electrode, an organic semiconductor layer, a gate insulating layer, and a gate electrode;
(C) forming a ferroelectric capacitor having a lower electrode, an organic ferroelectric layer, and an upper electrode electrically connected to one of the source / drain electrodes;
Including
The memory cell portion including the second thin film transistor and the ferroelectric capacitor is stacked above the drive circuit portion including the first thin film transistor. According to the present invention, since the memory cell unit is stacked above the drive circuit unit, it is possible to prevent an increase in planar area and to realize a reduction in memory size and an increase in capacity. In addition, since an organic ferroelectric layer is used for the ferroelectric capacitor and an organic semiconductor layer is used for the second thin film transistor, a low temperature process of, for example, 150 ° C. or lower is possible for the entire memory cell portion. Therefore, the restriction on the heat resistance of the substrate for forming the memory is relaxed, and the degree of freedom in selecting the substrate is improved. Moreover, since the organic ferroelectric material can be formed with low energy by a liquid phase process, the manufacturing process can be facilitated. Furthermore, there is no problem of environmental load due to heavy metals, it can be easily disposed of and it is easy to handle.
(13) In this method of manufacturing an organic ferroelectric memory,
In the step (a), the first thin film transistor may be formed by a low temperature polysilicon process.
(14) In this method of manufacturing an organic ferroelectric memory,
The steps (b) and (c) may be performed by a liquid phase process. Thereby, an inexpensive and easy manufacturing process can be realized.
(15)
In this organic ferroelectric memory,
In the step (b), each of the source / drain electrodes, the organic semiconductor layer, the gate insulating layer, and the gate electrode may be formed in a predetermined pattern by a droplet discharge method. Thereby, since a pattern can be directly formed, the manufacturing process can be facilitated.
(16) In this organic ferroelectric memory,
In the step (c), each of the lower electrode, the organic ferroelectric layer, and the upper electrode may be formed in a predetermined pattern by a droplet discharge method. Thereby, since a pattern can be directly formed, the manufacturing process can be facilitated.
(17) In this organic ferroelectric memory,
In the step (c), the organic ferroelectric layer is formed by ashing the organic ferroelectric layer using the upper electrode having the predetermined pattern as a mask, by forming the upper electrode to have a predetermined pattern. The layer may be patterned. According to this, by using the upper electrode as a mask, it is not necessary to form a mask for patterning the organic ferroelectric layer, and the manufacturing process can be facilitated.
(18) In this organic ferroelectric memory,
After the step (a), further comprising forming a first insulating layer above the first thin film transistor;
After the step (b), further comprising forming a second insulating layer above the second thin film transistor;
The deposition temperature of the second insulating layer may be lower than the deposition temperature of the first insulating layer. According to this, for example, damage due to heat of the organic semiconductor layer can be reduced.
(19) In this organic ferroelectric memory,
Performing a step including at least the step (a) on the first substrate, forming a transfer layer including the drive circuit portion above the first substrate,
The method may further include transferring the transferred layer to the second substrate by at least one transfer step. According to this, it is possible to satisfy both the conditions required for the manufacturing process (such as process resistance) and the conditions required for the finished product (such as flexibility), and to improve the degree of freedom of substrate selection.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 20 are diagrams showing a method of manufacturing an organic ferroelectric memory according to the present embodiment. FIGS. 21 and 22 are diagrams showing an organic ferroelectric memory and a circuit thereof according to the present embodiment, respectively. It is.

(Manufacturing method of organic ferroelectric memory)
In the present embodiment, a storage capacitor type (for example, a so-called one-transistor one-capacitor type) organic ferroelectric memory is manufactured. The method of manufacturing the organic ferroelectric memory includes a process for forming the drive circuit unit 180 and a process for forming the memory cell unit 182.

  (1) As shown in FIGS. 1 to 9, the drive circuit unit 180 including the first thin film transistor 110 is formed.

  (1-1) First, as shown in FIG. 1, a first substrate 100 is prepared. In the example shown in this embodiment mode, the first substrate 100 is a transfer substrate and is a substrate used only in a manufacturing process. A transferred layer 190 including at least the drive circuit unit 180 (for example, including the drive circuit unit 180 and the memory cell unit 182) is formed on the first substrate 100 by a process described later. The transferred layer 190 on the first substrate 100 is finally transferred to the second substrate 200 (see FIG. 20). By applying the transfer technique, it is possible to satisfy both conditions required for the manufacturing process (such as process resistance) and conditions required for the finished product (such as flexibility).

  The material of the first substrate 100 is not limited as long as it has resistance (heat resistance) to the manufacturing process of the organic ferroelectric memory. For example, the first substrate 100 may have a strain point equal to or higher than the maximum temperature of the manufacturing process (for example, about 400 ° C. to 600 ° C.). Further, the first substrate 100 may have light transmittance. The first substrate 100 is a glass substrate (for example, quartz glass, Corning 7059, Nippon Electric Glass OA-2), a semiconductor substrate (for example, a silicon substrate), a metal substrate, or a resin substrate if it has heat resistance. Also good.

  If necessary, the separation layer 102 is formed over the first substrate 100. The separation layer 102 is for facilitating peeling of the first substrate 100 in a transfer process described later. The separation layer 102 may be one that loses the binding force due to light absorption, or may be one that loses the binding force due to other physical / chemical action. The separation layer 102 may be an adhesive layer that loses adhesive force by heat or light. Examples of the material of the separation layer 102 include semiconductors such as amorphous silicon, ferroelectrics, various oxide ceramics, organic polymer materials, low melting point metals, and UV curable adhesive materials.

An insulating layer (for example, a SiO ₂ layer) 104 may be formed on the first substrate 100 (the separation layer 102 in FIG. 1). The insulating layer 104 can be formed by a plasma CVD method using, for example, TEOS (Tetra Ethyl Ortho Silicate (Si (OC ₂ H ₅ ) ₄ )), which is an organic silicon material, as a raw material. The insulating layer 104 has functions such as protection of the first thin film transistor 110, light shielding, insulation, and prevention of migration. Alternatively, the first thin film transistor 110 may be formed directly on the first substrate 100 (or the separation layer 102) without forming the insulating layer 104.

  (1-2) As shown in FIGS. 2 to 6, the first thin film transistor 110 is formed. The first thin film transistor 110 can be formed by a low temperature poly-silicon (LTPS) process. For example, a glass substrate can be used as the first substrate 100 by setting the process temperature to about 600 ° C. or lower (for example, about 400 ° C. or lower).

  First, as illustrated in FIG. 2, the thin film semiconductor layer 112 is formed over the insulating layer 104. For example, an amorphous silicon layer is formed by a CVD method, and after dehydrogenation annealing is performed as necessary, the amorphous silicon layer is polycrystallized by laser annealing with an excimer laser or the like. Thus, a polysilicon layer is formed as the thin film semiconductor layer 112. Thereafter, as shown in FIG. 3, patterning is performed by dry etching, for example, to form a thin film semiconductor layer (polysilicon layer) 114 having a predetermined pattern. When a liquid silicon material is used, a silicon thin film can be formed by a liquid phase process, and a direct pattern can be formed by using a droplet discharge method such as an ink jet method.

Next, as shown in FIG. 4, a gate insulating layer (eg, SiO ₂ layer) 116 is formed on at least the thin film semiconductor layer 114. The gate insulating layer 116 can be formed by, for example, a TEOS-CVD method. Thereafter, as shown in FIG. 5, a gate electrode 118 (for example, Al, MoW alloy, Cr electrode, etc.) is formed by patterning, and a predetermined impurity is doped into the thin film semiconductor layer 114 using the gate electrode 118 as a mask to activate the impurity. Annealing for. Thus, as shown in FIG. 6, impurity regions (source and drain regions) 114a and 114b are formed in the thin film semiconductor layer 114. Note that the gate insulating layer includes at least a portion overlapping with the gate electrode, for example, a portion overlapping with the gate electrode and a portion around the portion. The same applies to the following description.

  As shown in FIG. 6, the first thin film transistor 110 includes a thin film semiconductor layer 114, a gate insulating layer 116, and a gate electrode 118. The structure of the first thin film transistor 110 is not limited to the above-described top gate type (coplanar type), and may be, for example, a bottom gate type in which the gate electrode 118 is disposed on the first substrate 100 side. The first thin film transistor 110 is not limited to the low-temperature polysilicon thin film transistor described above, and other forms may be applied.

  (1-3) As shown in FIG. 7, the first insulating layer 120 is formed on the first thin film transistor 110.

  The first insulating layer 120 can be formed at about 300 ° C. by TEOS-CVD, for example. The first insulating layer 120 can be formed by a method usually used in a process for forming a low-temperature polysilicon thin film transistor. The first insulating layer 120 is formed so as to cover the first thin film transistor 110. Thereafter, contact holes 122 and 124 are formed in the first insulating layer 120. The contact hole 122 is a through hole for connecting the first thin film transistor 110 and a later-described wiring layer 130 (see FIG. 8) to each other. The contact hole 124 is a through hole for connecting the first thin film transistor 110 and a second thin film transistor 150 (described later) (see FIG. 13) to each other. One impurity region 114 a of the thin film semiconductor layer 114 is exposed from the contact hole 122, and the other impurity region 114 b of the thin film semiconductor layer 114 is exposed from the contact hole 124. The contact holes 122 and 124 can be formed by, for example, a dry etching method.

  (1-4) As shown in FIGS. 8 and 9, contact layers 126, 128, and 134, a wiring layer 130, and the like that are electrically connected to the first thin film transistor 110 are formed.

  First, contact layers 126 and 128 are formed in the contact holes 122 and 124 of the first insulating layer 120. The contact layers 126 and 128 may be formed only inside the contact holes 122 and 124, as shown in FIG. 8, for example, or not only inside the contact holes 122 and 124, but also the upper surface of the first insulating layer 120. You may form so that it may reach. The contact layers 126 and 128 include, for example, a thin barrier layer (for example, a Ti layer or a TiN layer) formed on the interface with the insulating material, and a conductive layer (for example, a W layer or Al layer) formed on the inner side of the barrier layer. Layer). After forming a conductive material on the entire surface of the first insulating layer 120 including the insides of the contact holes 122 and 124, the contact layers 126 and 128 are formed by combining the CMP method and the etching method if necessary. Can do. Note that the material of the contact layers 126 and 128 is not limited as long as they have conductivity. Also, a barrier layer is not essential.

  Next, the wiring layer 130 is formed on the region including the contact layer 126. The wiring layer 130 can be formed from a metal material such as aluminum. For example, the wiring layer 130 having a predetermined pattern is formed by forming a material to be the wiring layer 130 on the entire surface by sputtering or CVD, and then etching. The wiring layer 130 is electrically connected to the first thin film transistor 110 (specifically, the impurity region 114a) through the contact layer 126.

  After that, as illustrated in FIG. 9, the insulating layer 132 is formed so as to cover the wiring layer 130 and the contact layer 128, and the contact layer 134 is formed in the contact hole of the insulating layer 132. The content of the first insulating layer 120 can be applied to the description of the insulating layer 132. In addition, the above description can be applied to the description of the contact hole and the contact layer 134. The contact layer 134 is electrically connected to the first thin film transistor 110 (specifically, the impurity region 114b) through the contact layer 128.

  (1-5) In this way, the drive circuit unit 180 including the first thin film transistor 110 can be formed on the first substrate 100 (more precisely, the separation layer 102). The drive circuit unit 180 is for driving a memory cell unit 182 described later. In the example illustrated in FIG. 9, the driver circuit portion 180 includes at least a first thin film transistor 110, contact layers 126, 128, and 134 and a wiring layer 130 that are electrically connected to the first thin film transistor 110. . In many cases, the drive circuit unit 180 includes a plurality of first thin film transistors 110. The drive circuit unit 180 is a part in which elements required to achieve a predetermined drive function are gathered.

  (2) As shown in FIGS. 10 to 17, a memory cell unit 182 including the second thin film transistor 150 and the ferroelectric capacitor 160 is formed. The second thin film transistor 150 is an organic semiconductor thin film transistor, and the ferroelectric capacitor 160 is an organic ferroelectric capacitor. In the example shown below, the second thin film transistor 150 is formed, and then the ferroelectric capacitor 160 is formed.

  (2-1) As shown in FIG. 10, the source electrode 140 and the drain electrode 142 are formed. In the example shown in FIG. 10, the drain electrode 142 is electrically connected to the contact layer 134.

  The source electrode 140 and the drain electrode 142 can be formed by a droplet discharge method in which ink 138 is discharged from a droplet discharge portion (for example, a printer head) 136. The ink 138 may be a dispersion liquid (for example, metal ink) containing conductive fine particles. Examples of the conductive fine particles include metal fine particles such as gold, silver, copper, palladium, nickel, aluminum, and tantalum, fine particles of conductive oxide, and other fine particles such as a superconductor. The fine particles are not particularly limited in size, and are particles that can be discharged together with the dispersion. The conductive fine particles may be coated with a coating material such as organic matter in order to suppress the reaction. The dispersion may be difficult to dry and re-dissolvable. The conductive fine particles may be uniformly dispersed in the dispersion. Further, a solvent in which a conductive organic material is dissolved may be used as the discharge liquid. Examples of the conductive organic material include a mixture of polyethylenedioxanethiophene (PEDOT), which is a conductive polymer, and polystyrene sulfonate, or polyaniline. If necessary, a treatment for volatilizing the dispersion and a treatment (heating) for bonding (for example, sintering) the conductive fine particles to each other are performed.

  As the droplet discharge method, an inkjet method, a gel jet (registered trademark) method, or a dispenser method can be applied. For example, according to the ink jet method, by applying a technique that has been put to practical use for an ink jet printer, ink can be provided at high speed and without waste. By applying the droplet discharge method, the source electrode 140 and the drain electrode 142 having a predetermined pattern can be directly formed without using expensive and time-consuming photolithography technology and etching technology.

  Before applying the ink 138, the upper surface of the base (insulating layer 132) may be surface-treated as necessary. For example, a liquid repellent treatment is performed on a region other than a region for forming the source electrode 140 and the drain electrode 142. Accordingly, even when the ejected ink 138 is not dropped on the region for forming the source electrode 140 and the drain electrode 142, the source electrode 140 and the drain electrode 142 having a predetermined pattern can be formed.

  Note that the film formation method of the source electrode 140 and the drain electrode 142 is not limited to the above-described droplet discharge method, and a spin coating method can be applied as another liquid phase process, or a sputtering method or an evaporation method. A known method such as a plating method can also be applied.

  (2-2) As shown in FIG. 11, the organic semiconductor layer 144 is formed on the source electrode 140 and the drain electrode 142. The liquid containing the material of the organic semiconductor layer 144 is used, and the organic semiconductor layer 144 can be formed by a liquid phase process (for example, a spin coat method or a droplet discharge method). For example, the organic semiconductor layer 144 having a predetermined pattern may be directly formed by applying the above-described droplet discharge method. That is, as shown in FIG. 11, the organic semiconductor layer 144 is formed in a predetermined pattern so that a hole 145 exposing the source electrode 140 is formed. As a material of the organic semiconductor layer 144, for example, F8T2 which is one of fluorene-thiophene copolymers can be given. As the organic semiconductor layer, any of the following high molecular organic semiconductor materials and low molecular organic semiconductor materials can be used.

  Examples of the polymer organic semiconductor material include poly (3-alkylthiophene) (poly (3-hexylthiophene) (P3HT), poly (3-octylthiophene), poly (2,5-thienylenevinylene) (PTV). ), Poly (para-phenylene vinylene) (PPV), poly (9,9-dioctylfluorene-co-bis-N, N ′-(4-methoxyphenyl) -bis-N, N′-phenyl-1,4 -Phenylenediamine) (PFMO), poly (9,9 dioctylfluorene-co-benzothiadiazole) (BT), fluorene-triallylamine copolymer, triallylamine-based polymer, fluorene-thiophene copolymer, poly (3,4) -Ethylenedioxythiophene / styrene sulfonic acid) (PEDOT / PSS), polythiophene, poly (thio Phenylenevinylene), poly (2,2'-thienylpyrrole), polyaniline and the like.

  Examples of the low molecular organic semiconductor include C60, metal phthalocyanines, substituted derivatives thereof, acene molecular materials such as anthracene, tetracene, pentacene, and hexacene, or α-oligothiophenes. Include quarterthiophene (4T), sexithiophene (6T), octithiophene (8T), dihexylquarterthiophene (DH4T), dihexylxithiophene (DH6T), and the like.

  By using an organic material as the material for the semiconductor layer, a low-temperature process can be performed, and for example, the semiconductor layer can be formed very easily compared to the case of using silicon. Note that the organic semiconductor layer 144 may be formed by an LB (Langmuir-Blodgett) method, an LSMCD (Liquid Source Misted Chemical Deposition) method, or the like.

  (2-3) As shown in FIG. 12, a gate insulating layer 146 is formed on the organic semiconductor layer 144. The gate insulating layer 146 can be formed using a liquid containing a material for the gate insulating layer 146 by a liquid phase process (for example, a spin coating method or a droplet discharge method). For example, the above-described droplet discharge method may be applied to directly form the gate insulating layer 146 having a predetermined pattern. That is, as shown in FIG. 12, the gate insulating layer 146 is formed in a predetermined pattern so that the hole 147 exposing the source electrode 140 is formed.

  The deposition temperature of the gate insulating layer 146 is preferably lower than the deposition temperature of the organic semiconductor layer 144. For example, when a polymer material such as polymethyl methacrylate (PMMA) is used, the gate insulating layer 146 can be formed at a lower temperature than the organic semiconductor layer 144.

  (2-4) As shown in FIG. 13, the gate electrode 148 is formed on the gate insulating layer 146. The liquid containing the material of the gate electrode 148 can be used to form the gate electrode 148 by a liquid phase process (eg, spin coating or droplet discharge method). For example, the above-described droplet discharge method may be applied to directly form the gate electrode 148 having a predetermined pattern. The material described for the source electrode 140 and the drain electrode 142 can be applied to the material of the gate electrode 148. For example, the same material as that of the source electrode 140 and the drain electrode 142 may be used. If necessary, a treatment for volatilizing the dispersion and a treatment (heating) for bonding (for example, sintering) the conductive fine particles to each other are performed. Other film formation methods for the gate electrode 148 include sputtering, vapor deposition, plating, and the like.

  Further, depending on the material of the gate insulating layer 146, a receiving layer (not shown) may be formed in a region other than the region for forming the gate electrode 148 before the gate electrode 148 is formed. For example, when the gate insulating layer 146 is made of a material having high water repellency and the liquid material of the gate electrode 148 is water-soluble, it is difficult to apply the gate electrode 148 in a desired shape. Therefore, a receiving layer made of polyvinylphenol (PVPh) or the like is formed in advance in a region other than the region for forming the gate electrode 148, and the liquid material of the gate electrode 148 is poured into the groove portion where the receiving layer is not formed. Thus, the gate electrode 148 having a desired shape can be formed more easily.

  Thus, the second thin film transistor 150 can be formed. The second thin film transistor 150 includes a source electrode 140, a drain electrode 142, an organic semiconductor layer 144, a gate insulating layer 146, and a gate electrode 148. The second thin film transistor 150 illustrated in FIG. 13 has a so-called top gate / bottom contact structure.

  (2-5) As shown in FIG. 14, the second insulating layer 152 is formed on the second thin film transistor 150.

  The deposition temperature of the second insulating layer 152 may be lower than the deposition temperature of the first insulating layer 120. That is, the material of the second insulating layer 152 may be a material that can be formed at a temperature lower than the film forming temperature of the first insulating layer 120 (and the heat resistant temperature of the organic semiconductor layer 144). Specifically, when the organic semiconductor layer 144 is made of F8T2, since the annealing temperature is about 100 ° C., it is preferable that the second insulating layer 152 can be formed at 100 ° C. or less. For example, tetramethylsilane (TMS), polymethyl methacrylate (PMMA), photocurable resin (for example, UV curable resin), or the like can be given. By using these, damage to the organic semiconductor layer 144 due to heat can be reduced.

  Examples of the film forming method include a CVD method, a spin coating method, a droplet discharge method, and an LSMCD method. For example, as shown in FIG. 14, the second insulating layer 152 having a predetermined pattern may be directly formed by applying the above-described droplet discharge method. Specifically, the second insulating layer 152 is formed in a predetermined pattern so that the hole 154 exposing the source electrode 140 is formed. The source electrode 140 is exposed from the contact hole formed by the holes 145, 147 and 154.

  (2-6) As shown in FIG. 15, the contact layer 156 is formed. The contact layer 156 is formed so as to penetrate the second insulating layer 152 and be electrically connected to the second thin film transistor 150 (for example, the source electrode 140). Specifically, the contact layer 156 is formed so as to fill a contact hole made up of the holes 145, 147 and 154.

  The contact layer 156 may be formed by a liquid phase process (for example, a droplet discharge method) using a liquid containing the material of the contact layer 156. The contact layer 156 may be formed only inside the contact hole, or may be formed not only inside the contact hole but also reaching the upper surface of the second insulating layer 152. In the latter case, for example, the contact layer 156 and the ferroelectric capacitor 160 lower electrode 162 may be formed integrally (continuously). If the ink amount and the ink application region are controlled by the droplet discharge method, the contact layer 156 and the lower electrode 162 can be formed by the same droplet discharge step. Therefore, the manufacturing process can be simplified. Alternatively, after the contact layer 156 is formed, the lower electrode 162 may be separately formed by the same or different technique. Note that the above-described content can be applied to the details of the material of the contact layer 156 and the film formation method.

  (2-7) As shown in FIG. 16, a ferroelectric capacitor 160 having a lower electrode 162, an organic ferroelectric layer 164, and an upper electrode 166 is formed. The ferroelectric capacitor 160 is electrically connected to one of the source electrode 140 and the drain electrode 142 via the contact layer 156.

  For example, the lower electrode 162 and the contact layer 156 are electrically connected to each other. The material of the lower electrode 162 and the film formation method can apply the contents of the source electrode 140 and the like. In particular, if the material of the lower electrode 162 is a conductive organic material, the conductive organic material is more flexible than a normal metal. Therefore, when the material is used as a base of the organic ferroelectric layer 164, the ferroelectric capacitor 160 Good hysteresis characteristics.

  Next, an organic ferroelectric layer 164 is formed on the lower electrode 162. Examples of the organic ferroelectric material for the organic ferroelectric layer 164 include poly (vinylidene fluoride / trifluoroethylene), polyvinylidene fluoride, (vinylidene fluoride / trifluoroethylene) co-oligomer, vinylidene fluoride oligomer, and odd number. Nylon etc. are mentioned. For example, a poly (vinylidene fluoride-trifluoroethylene) copolymer having a VDF: TrFE ratio of 75:25 is dissolved in a solvent (for example, a ketone-based solvent) to obtain a predetermined solution, and then the region including the lower electrode 162 is formed. And annealed at about 140 ° C. to 150 ° C. for crystallization. In the case of an organic ferroelectric material, annealing can be performed at an extremely low temperature as compared with an inorganic ferroelectric material. Therefore, the degree of freedom in selecting the first substrate 100 used in the manufacturing process is high. Further, the manufacturing process can be facilitated by low energy treatment. Furthermore, since the orientation of the organic ferroelectric material does not depend much on the base (lower electrode 162), the degree of freedom in selecting the material of the lower electrode 162 can be improved. In addition, since the organic ferroelectric material does not contain heavy metal, there is no problem of environmental load, and handling that can be easily disposed of is easy.

  Examples of the method for forming the organic ferroelectric layer 164 include a vacuum deposition method, a spin coating method, an LB (Langmuir-Blodgett) method, the above-described droplet discharge method, and an LSMCD (Liquid Source Misted Chemical Deposition) method. According to the droplet discharge method, the organic ferroelectric layer 164 having a predetermined pattern can be directly formed. Similarly, in the case of the LSMCD method, a predetermined pattern can be directly formed by combining selective growth techniques. In the case of other methods, the organic ferroelectric layer 164 may be patterned by etching as necessary.

  Thereafter, an upper electrode 166 is formed on the organic ferroelectric layer 164. As the material and formation method of the upper electrode 166, the contents of the lower electrode 162 described above can be applied. For example, if the material of the upper electrode 166 is a conductive organic material, the hysteresis characteristic of the ferroelectric capacitor 160 is improved as described above. In the case of the upper electrode 166, it is preferable to form the film with low power so that the organic ferroelectric layer 164 serving as a base is not damaged. That is, when the upper electrode 166 is formed by a droplet discharge method, damage to the organic ferroelectric layer 164 due to high energy particles in a sputtering method or the like can be reduced, which is effective.

  (2-8) Thereafter, as shown in FIG. 17, a third insulating layer 170 is formed on the ferroelectric capacitor 160. The third insulating layer 170 may be an interlayer insulating layer for further forming a device thereon, or may be an uppermost passivation layer. The third insulating layer 170 is formed so as to cover the ferroelectric capacitor 160. The deposition temperature of the third insulating layer 170 may be lower than the deposition temperature of the first insulating layer 120 (and the deposition temperature of the organic ferroelectric layer 164). According to this, for example, damage due to heat of the ferroelectric capacitor 160 can be reduced. The content of the second insulating layer 152 can be applied to the material and the deposition method of the third insulating layer 170.

  It should be noted that not only the step of forming the third insulating layer 170 but also the step of forming the ferroelectric capacitor 160 and the subsequent steps, annealing at a temperature higher than the film formation temperature of the organic ferroelectric layer 164 (specifically, the temperature during crystallization). It is preferable not to perform the treatment. By doing so, damage to the ferroelectric capacitor 160 due to heat can be reduced.

  (2-9) Thus, the memory cell part 182 including the second thin film transistor 150 and the ferroelectric capacitor 160 can be formed. The second thin film transistor 150 functions as a selection transistor that selects on / off of charge accumulation in the ferroelectric capacitor 160. The memory cell unit 182 includes at least a second thin film transistor 150, a ferroelectric capacitor 160, and a contact layer 156 that electrically connects both. In many cases, the memory cell unit 182 includes a plurality of sets of the second thin film transistor 150 and the ferroelectric capacitor 160 to form a memory cell array unit. As shown in FIG. 17, the ferroelectric capacitor 160 may be disposed in the upper layer of the second thin film transistor 150. Alternatively, the second thin film transistor 150 can be disposed in the upper layer of the ferroelectric capacitor 160.

  Through the above steps, the transfer layer 190 including the driver circuit portion 180 and the memory cell portion 182 can be formed over the first substrate 100. The memory cell unit 182 is stacked above the drive circuit unit 180. In other words, the memory cell portion 182 is disposed so as to overlap with a part or all of the region of the drive circuit portion 180.

  The film formation process in the memory cell portion 182 described above can be performed by a liquid phase process. In particular, if the droplet discharge method is applied, it is possible to manufacture using the same discharge device by simply changing the droplet material, so that an extremely inexpensive and easy manufacturing process can be realized.

  According to the present embodiment, since the memory cell unit 182 is stacked above the drive circuit unit 180, an increase in the planar area can be prevented, and the memory can be reduced in size and capacity. Further, since the organic ferroelectric layer 164 is used for the ferroelectric capacitor 160 and the organic semiconductor layer 144 is used for the second thin film transistor 150, a low-temperature process of, for example, 150 ° C. or less as a whole becomes possible. Therefore, the restriction on heat resistance of the substrate for forming the memory (first substrate 100) is relaxed, and the degree of freedom in selecting the substrate is improved. In addition, since the organic ferroelectric material can be processed with low energy, the manufacturing process can be facilitated. Furthermore, there is no problem of environmental load due to heavy metals, it can be easily disposed of and it is easy to handle.

  (3) When the transfer technique is applied, as shown in FIGS. 18 to 20, the transferred layer 190 is formed on the second substrate 200 as a finished product by at least one transfer process (two times in the figure). Transcript.

  For example, as shown in FIG. 18, the transferred layer 190 on the first substrate 100 (separation layer 102) is transferred to another substrate (for example, a glass substrate) 172. In that case, the substrate 172 and the transferred layer 190 may be bonded by an adhesive layer (not shown) (for example, a photo-curing adhesive layer). After that, as shown in FIGS. 19 and 20, the bonding force of the separation layer 102 is lost or reduced, and the first substrate 100 and the separation layer 102 are peeled sequentially or simultaneously. The method for eliminating or reducing the bonding strength of the separation layer 102 is as described above. Finally, a part of the transferred layer 190 (for example, the insulating layer 104) is exposed, and the transferred layer 190 is transferred to the second substrate 200. The coupling means for the transfer layer 190 and the second substrate 200 is not limited, and the method described above can be applied.

  Thus, the transfer layer 190 (the drive circuit portion 180 and the memory cell portion 182) can be formed over the second substrate 200. The second substrate 200 may be made of a material that has lower heat resistance (for example, a lower strain point) than the first substrate 100. The second substrate 200 may be a flexible substrate such as a polyimide resin, or may be a glass substrate having lower heat resistance than the first substrate 100. Alternatively, the second substrate 200 may be one in which an electro-optical element such as a liquid crystal element or an EL element, or other electronic components are mounted or incorporated. Also in this case, if the electro-optical element or the electronic component of the second substrate 200 has low heat resistance, it is effective to perform the above-described transfer process.

  Note that, unlike the above, the transfer layer 190 may be directly transferred from the first substrate 100 to the second substrate 200 by one transfer. In that case, the memory cell portion 182 and the drive circuit portion 180 are sequentially arranged from the second substrate 200 side.

(Structure of organic ferroelectric memory)
Thus, an organic ferroelectric memory 1000 can be formed as shown in FIG. The organic ferroelectric memory 1000 includes a drive circuit unit 180 and a memory cell unit 182. The details thereof are as described in the manufacturing method described above.

  The organic ferroelectric memory 1000 operates based on the circuit scheme of FIG. Referring to the circuit diagram of FIG. 22, the word line (WL) is electrically connected to the gate electrode 148 of the second thin film transistor 150, and the bit line (BL) is electrically connected to the drain electrode 142 of the second thin film transistor 150. The plate line (PL) is electrically connected to the upper electrode 166 of the ferroelectric capacitor 160. The first thin film transistor 110 is electrically connected to either the word line or the bit line (the bit line in FIG. 21), and drives the memory cell portion 182.

  The organic ferroelectric memory according to the present embodiment includes contents that can be derived from the manufacturing method described above.

(First modification)
23 to 25 are views showing a first modification of the present embodiment, and are diagrams for explaining an organic ferroelectric memory and a manufacturing method thereof. 24 and 25 show only the portion of the second thin film transistor. In this modification, the structure of the second thin film transistor is different from that described above.

  (1) As shown in FIG. 23, the second thin film transistor 250 has a so-called bottom gate / top contact type structure. Specifically, the gate insulating layer 246 is formed over the gate electrode 248, the organic semiconductor layer 244 is formed over the gate insulating layer 246, and the source electrode 240 and the drain electrode 242 are formed over the organic semiconductor layer 244. Note that the above-described contents can be applied to these materials and film formation methods. Also in this modification, the memory cell portion 282 is stacked above the drive circuit portion 180.

  In the example illustrated in FIG. 23, the gate electrode 248 is electrically connected to the first thin film transistor 110. In this modification, the gate electrode 248 is the lowermost layer of the second thin film transistor 250, so that the electrical connection between the gate electrode 248 and the first thin film transistor 110 is easily achieved.

  One of the source electrode 240 and the drain electrode 242 (in FIG. 23, the source electrode 240) is electrically connected to the ferroelectric capacitor 160. In the present modification, the source electrode 240 and the drain electrode 242 are the uppermost layer of the second thin film transistor 250, and thus, for example, electrical connection between the source electrode 240 and the ferroelectric capacitor 160 is easily achieved.

  (2) In the example shown in FIG. 24, the second thin film transistor 350 has a so-called top gate / top contact type structure. Specifically, the source electrode 340 and the drain electrode 342 are formed over the organic semiconductor layer 344, the gate insulating layer 346 is formed over the source electrode 340 and the drain electrode 342, and the gate electrode 348 is formed over the gate insulating layer 346. Yes. Note that the above-described contents can be applied to these materials and film formation methods. In addition, FIG. 21 can be referred to for electrical connection to each of the first thin film transistor and the ferroelectric capacitor.

  (3) In the example shown in FIG. 25, the second thin film transistor 450 has a so-called bottom gate / bottom contact type structure. Specifically, the gate insulating layer 446 is formed over the gate electrode 448, the source electrode 440 and the drain electrode 442 are formed over the gate insulating layer 446, and the organic semiconductor layer 444 is formed over the source electrode 440 and the drain electrode 442. Yes. Note that the above-described contents can be applied to these materials and film formation methods. In addition, FIG. 23 can be referred to for electrical connection to each of the first thin film transistor and the ferroelectric capacitor.

(Second modification)
FIG. 26 and FIG. 27 are diagrams showing a second modification of the present embodiment, and are diagrams for explaining an organic ferroelectric memory and a manufacturing method thereof.

  This modification differs from the above in that the second thin film transistor is an organic semiconductor thin film transistor. According to this, it is possible to form the entire film formation process of the organic ferroelectric memory by a liquid phase process (for example, a droplet discharge process). In the case of an organic semiconductor thin film transistor, a low temperature process is possible, so that an organic ferroelectric memory can be manufactured directly on a product substrate without using a transfer step, for example.

  (1) As shown in FIG. 26, the first thin film transistor 510 includes a source electrode 511, a drain electrode 512, an organic semiconductor layer 514, a gate insulating layer 516, and a gate electrode 518. The contents described above can be applied to these materials and film formation methods.

  In the example shown in FIG. 26, the first thin film transistor 510 has a so-called top gate / bottom structure, and the details of the second thin film transistor 150 can be applied to the details thereof. Alternatively, the structure of the first thin film transistor 510 is not limited to the top gate / bottom type, and may be a top gate / top contact type, a bottom gate / top contact type, or a bottom gate / bottom type. It may be a contact type. In this modification, too. The memory cell unit 182 is stacked above the drive circuit unit 580.

  Note that the first and second thin film transistors 510 and 150 may have the same transistor structure, constituent material, and film formation method.

  (2) As shown in FIG. 27, the memory cell unit 282 shown in FIG. 23 may be combined with the drive circuit unit 580 shown in FIG. In that case, the transistor structures of the first and second thin film transistors 510 and 250 may be different. For example, in the example shown in FIG. 27, the first thin film transistor 510 has a bottom gate / top contact type structure, and the second thin film transistor 250 has a top gate / bottom contact type structure.

(Third Modification)
FIG. 28 is a diagram showing a third modification of the present embodiment, and is a circuit diagram of an organic ferroelectric memory. In the above description, an example of a one-transistor one-capacitor type has been described. However, the present invention is not limited to this, and can be applied to a so-called two-transistor two-capacitor type organic ferroelectric memory. According to this memory structure, in addition to the effects described above, there is a feature that the operation margin is high and it is strong against characteristic variations caused by manufacturing processes and the like. Alternatively, the contents of the present invention may be applied to another storage capacity type other than the above-described 1T1C type and 2T2C type.

(Fourth modification)
FIGS. 29 to 32 are views showing a fourth modification of the present embodiment and showing a method for manufacturing an organic ferroelectric memory. In this modification, the patterning method of the ferroelectric capacitor 160 is different from that described above.

  First, as shown in FIG. 29, a lower electrode 162a, an organic ferroelectric layer 164a, and an upper electrode 166a are sequentially laminated in a region including a predetermined pattern and its periphery. Thereafter, as shown in FIG. 30, the upper electrode 166 is formed by patterning. For example, patterning can be performed by wet etching. Alternatively, the upper electrode 166 having a predetermined pattern may be directly formed on the organic ferroelectric layer 164a by a droplet discharge method.

  Thereafter, as shown in FIG. 30, the organic ferroelectric layer 164a is ashed using the upper electrode 166 having a predetermined pattern as a mask. That is, a region exposed from the mask (upper electrode 166) in the organic ferroelectric layer 164a is volatilized and removed by a reactive gas (for example, plasma oxygen gas). Thus, as shown in FIG. 31, the organic ferroelectric layer 164 can be formed in the same pattern as the upper electrode 166.

  Alternatively, by patterning the upper electrode 166 by dry etching, the organic ferroelectric layer 164 may be simultaneously patterned by the same action as ashing.

  As shown in FIG. 32, the ferroelectric capacitor 160 can be formed by patterning the lower electrode 162 by a predetermined method.

  According to this modification, by using the upper electrode 166 as a mask, it is not necessary to form a mask for patterning the organic ferroelectric layer 164, and the manufacturing process can be facilitated.

(Other variations)
Although an example in which the transfer technique is applied has been described in the above manufacturing method, the drive circuit portion and the memory cell portion may be formed directly on the substrate (second substrate 200) as a finished product. In that case, it is preferable that the substrate to be used has heat resistance with respect to the formation process of the driver circuit portion and the memory cell portion.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the organic ferroelectric memory which concerns on embodiment of this invention. 1 is a diagram showing an organic ferroelectric memory according to an embodiment of the present invention. 1 is a circuit diagram of an organic ferroelectric memory according to an embodiment of the present invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention. It is a figure which shows the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... 1st board | substrate 110 ... 1st thin-film transistor 120 ... 1st insulating layer 140 ... Source electrode 142 ... Drain electrode 144 ... Organic-semiconductor layer 146 ... Gate insulating layer 148 ... Gate electrode 150 ... 2nd thin-film transistor 152 ... 1st 2. Insulating layer 160 ... Ferroelectric capacitor 162 ... Lower electrode 164 ... Organic ferroelectric layer 166 ... Upper electrode 170 ... Third insulating layer 180 ... Drive circuit part 182 ... Memory cell part 190 ... Transfer layer 200 ... First 2 substrate 240 ... source electrode 242 ... drain electrode 244 ... organic semiconductor layer 246 ... gate insulating layer 248 ... gate electrode 250 ... second thin film transistor 282 ... memory cell portion 342 ... drain electrode 346 ... gate insulating layer 348 ... gate electrode 350 ... Second thin film transistor 442 ... Drain electrode 444 ... Organic semiconductor layer 446 ... Gate insulating layer 450 ... Second thin film transistor 510 ... First thin film transistor 518 ... Gate electrode 580 ... Drive circuit section

Claims (19)

A drive circuit section including a first thin film transistor;
A second thin film transistor having a source / drain electrode, an organic semiconductor layer, a gate insulating layer and a gate electrode; a lower electrode; an organic ferroelectric layer; and an upper electrode; and one of the source / drain electrodes is electrically A memory cell unit including a ferroelectric capacitor connected to the memory cell;
Including
The memory cell unit is an organic ferroelectric memory stacked above the drive circuit unit. The organic ferroelectric memory according to claim 1, wherein
The ferroelectric capacitor is an organic ferroelectric memory arranged in an upper layer than the second thin film transistor. The organic ferroelectric memory according to claim 1 or 2,
The organic semiconductor layer is formed above the source / drain electrodes,
The gate insulating layer is formed above the organic semiconductor layer,
An organic ferroelectric memory, wherein the gate electrode is formed above the gate insulating layer. The organic ferroelectric memory according to claim 1 or 2,
The source / drain electrodes are formed above the organic semiconductor layer,
The gate insulating layer is formed above the source / drain electrodes,
An organic ferroelectric memory, wherein the gate electrode is formed above the gate insulating layer. The organic ferroelectric memory according to claim 1 or 2,
The gate insulating layer is formed above the gate electrode,
The source / drain electrodes are formed above the gate insulating layer,
An organic ferroelectric memory in which the organic semiconductor layer is formed above the source / drain electrodes. The organic ferroelectric memory according to claim 1 or 2,
The gate insulating layer is formed above the gate electrode,
The organic semiconductor layer is formed above the gate insulating layer,
An organic ferroelectric memory in which the source / drain electrodes are formed above the organic semiconductor layer. The organic ferroelectric memory according to any one of claims 1 to 6,
The organic ferroelectric memory, wherein the organic semiconductor layer is formed of a fluorene-thiophene copolymer. The organic ferroelectric memory according to any one of claims 1 to 7,
An organic ferroelectric memory, wherein at least one of the lower electrode and the upper electrode is formed of a conductive organic material. The organic ferroelectric memory according to any one of claims 1 to 8,
The organic ferroelectric layer is formed of any one of poly (vinylidene fluoride / trifluoroethylene), poly (vinylidene fluoride), (vinylidene fluoride / trifluoroethylene) co-oligomer, vinylidene fluoride oligomer, and odd-number nylon. , Organic ferroelectric memory. The organic ferroelectric memory according to any one of claims 1 to 9,
The organic ferroelectric memory, wherein the first thin film transistor is a low-temperature polysilicon thin film transistor. The organic ferroelectric memory according to any one of claims 1 to 9,
The organic ferroelectric memory, wherein the first thin film transistor is an organic semiconductor thin film transistor. (A) forming a first thin film transistor;
(B) forming a second thin film transistor having a source / drain electrode, an organic semiconductor layer, a gate insulating layer, and a gate electrode;
(C) forming a ferroelectric capacitor having a lower electrode, an organic ferroelectric layer, and an upper electrode electrically connected to one of the source / drain electrodes;
Including
A method of manufacturing an organic ferroelectric memory, comprising: laminating a memory cell portion including the second thin film transistor and the ferroelectric capacitor above a drive circuit portion including the first thin film transistor. In the manufacturing method of the organic ferroelectric memory of Claim 12,
A method of manufacturing an organic ferroelectric memory, wherein in the step (a), the first thin film transistor is formed by a low-temperature polysilicon process. In the manufacturing method of the organic ferroelectric memory according to claim 12 or 13,
A method of manufacturing an organic ferroelectric memory, wherein the steps (b) and (c) are performed by a liquid phase process. The organic ferroelectric memory according to any one of claims 12 to 14,
A method of manufacturing an organic ferroelectric memory, wherein in the step (b), each of the source / drain electrodes, the organic semiconductor layer, the gate insulating layer, and the gate electrode is formed in a predetermined pattern by a droplet discharge method. The organic ferroelectric memory according to any one of claims 12 to 15,
A method of manufacturing an organic ferroelectric memory, wherein in the step (c), each of the lower electrode, the organic ferroelectric layer, and the upper electrode is formed in a predetermined pattern by a droplet discharge method. The organic ferroelectric memory according to any one of claims 12 to 15,
In the step (c), the organic ferroelectric layer is formed by ashing the organic ferroelectric layer using the upper electrode having the predetermined pattern as a mask, by forming the upper electrode to have a predetermined pattern. A method of manufacturing an organic ferroelectric memory, wherein a layer is patterned. The organic ferroelectric memory according to any one of claims 12 to 17,
After the step (a), further comprising forming a first insulating layer above the first thin film transistor;
After the step (b), further comprising forming a second insulating layer above the second thin film transistor;
The method for manufacturing an organic ferroelectric memory, wherein a film forming temperature of the second insulating layer is lower than a film forming temperature of the first insulating layer. The organic ferroelectric memory according to any one of claims 12 to 18,
Performing a step including at least the step (a) on the first substrate, forming a transfer layer including the drive circuit portion above the first substrate,
A method for manufacturing an organic ferroelectric memory, further comprising transferring the transfer layer to a second substrate by at least one transfer step.

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