JP4466230B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus suitable for performing high-definition image display.

  In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among these, in an electro-optical device such as a liquid crystal device of an active matrix driving method by TFT driving, TFD driving, etc., a large number of pixels corresponding to a large number of scanning lines and data lines arranged in the vertical and horizontal directions and their intersections. An electrode or the like is provided on the TFT array substrate or the like.

  A scanning signal is sequentially supplied to each scanning line from a scanning line driving circuit. On the other hand, the image signal is supplied to the data line by the sampling circuit driven by the data line driving circuit. That is, the data line driving circuit is configured to supply the sampling circuit driving signal to the sampling circuit that samples the image signal on the image signal line for each data line in parallel with the sequential supply operation of the scanning signal. Yes.

  The data line driving circuit generally includes a plurality of latch circuits (shift register circuits), sequentially shifts a transfer signal supplied at the beginning of a horizontal scanning period according to a clock signal, and outputs this as a sampling signal. Is. Similarly, the scanning line driving circuit includes a plurality of latch circuits, and sequentially shifts the transfer signal supplied at the beginning of the vertical scanning period in accordance with the clock signal and outputs it as a scanning signal. The sampling circuit includes a sampling switch provided for each data line, samples an image signal supplied from the outside according to a sampling signal from the data line driving circuit, and supplies it to each data line. is there.

  By the way, in recent years, the pixel pitch has been miniaturized and the driving frequency has been increased in order to meet the general demand for improving the quality of a display image.

  However, as described above, if the drive frequency is increased while the transfer signal sequentially output from the shift register circuit is simply used as a sampling signal, the sampling time assigned to each sampling circuit is shortened. For this reason, the result that sampling capability in each sampling circuit is insufficient is caused. On the other hand, increasing the transistor characteristics such as TFT (Thin Film Transistor) constituting the sampling circuit or improving the wiring characteristics such as resistance and time constant of the various wirings will increase the production cost and decrease the yield. I will invite you.

  Therefore, recently, in order to cope with the higher frequency of the dot clock, one image signal is serial-parallel converted (phase expansion) into a plurality of m systems, and these m image signals are simultaneously converted according to the sampling signal. A technique for sampling and supplying to m data lines has been developed.

In Patent Document 1, a capacitor is formed between the power supply wiring and the ground pattern, and this capacitor stabilizes the power supply voltage of the shift register circuit so that a high voltage can be applied to the source signal line. A technique that enables application of a high voltage is disclosed. Thereby, high-contrast display is possible.
Japanese Patent Laid-Open No. 11-142913

  By the way, in recent years, high definition images and fine pixel pitches have been promoted, and it is necessary to arrange a large number of scanning lines and data lines on a display panel at a narrow pitch and drive them at a high frequency. It has become.

  Moreover, in the phase development described above, it is necessary to increase the number of image signal lines in the display panel by the number of phase developments. The number of image signal lines routed on the substrate in order to perform the phase expansion is remarkably increased, and the wiring of sampling circuit drive signal lines that need to cross above or below the image signal is complicated. For these reasons, noise due to the influence of adjacent signal lines cannot be ignored.

  That is, in the display panel, it is necessary to route the above-described plurality of wirings in a relatively narrow area, and the video wiring for transmitting the image signal and the LCCOM wiring for transmitting the potential LCCOM of the common electrode are arranged adjacent to each other. Then, the fluctuation of the image signal flowing through the video wiring is transmitted to the LCCOM wiring by the coupling capacitance between the video wiring and the LCCOM wiring, and the LCCOM voltage also fluctuates. That is, as the level of the image signal rises and falls, the LCCOM voltage also rises and falls, and there is a problem that image quality deterioration such as display unevenness due to luminance reduction occurs.

  The present invention has been made in view of such problems, and it is an electric device that can suppress the fluctuation of the reference potential and improve the image quality by forming a capacitor between the wiring for transmitting the reference potential and the power supply wiring. An object is to provide an optical device and an electronic apparatus.

  The electro-optical device according to the present invention includes a display unit that drives a pixel based on an image signal supplied to a pixel electrode arranged in a matrix via a signal line and a reference voltage supplied to a common electrode, A reference voltage wiring for supplying a reference voltage to the common electrode, a power supply wiring for applying a predetermined fixed potential, and a capacitance forming region constituting a capacitor between the reference voltage wiring and the power supply wiring, To do.

  According to such a configuration, the display unit drives the pixels based on the image signal supplied to the pixel electrodes arranged in a matrix and the reference voltage supplied to the common electrode. A reference voltage wiring for supplying a reference voltage to the common electrode is capacitively coupled to the power supply wiring through a capacitor. The fluctuation of the reference voltage wiring is suppressed by the power supply wiring that applies a fixed potential. Thereby, the occurrence of uneven brightness can be suppressed, and the image quality is improved.

  Further, a plurality of capacitance forming regions constituting the capacitor are provided between the reference voltage wiring and the power supply wiring.

  According to such a configuration, a change in the reference voltage at each position of the display unit can be suppressed by the plurality of capacitors, and uneven brightness can be further reduced.

  The electro-optical device according to the present invention includes a display unit that drives a pixel based on an image signal supplied to a pixel electrode arranged in a matrix via a signal line and a reference voltage supplied to a common electrode, First and second reference voltage lines for supplying a reference voltage to the common electrode, first and second power supply terminals to which the predetermined fixed potential is supplied, and a predetermined voltage connected to the first power supply terminal A first power supply wiring for applying a fixed potential; a second power supply wiring connected to the second power supply terminal for applying a predetermined fixed potential; and the first reference voltage wiring and the first power supply wiring. A first capacitance forming region constituting a first capacitor therebetween, and a second capacitance forming region constituting a second capacitor between the second reference voltage wiring and the second power supply wiring. It is characterized by having.

  According to such a configuration, the display unit drives the pixels based on the image signal supplied to the pixel electrodes arranged in a matrix and the reference voltage supplied to the common electrode. The first reference voltage wiring for supplying the reference voltage to the common electrode is capacitively coupled to the first power supply wiring through the first capacitor. Similarly, the second reference voltage wiring is capacitively coupled to the second power supply wiring via the second capacitor. Variations in the first and second reference voltage wirings are suppressed by the first and second power supply wirings that apply a fixed potential. Thereby, the occurrence of uneven brightness can be suppressed, and the image quality is improved.

  The first capacitance formation region and the second capacitance formation region include the capacitance of the first capacitor and the first power supply wiring from the first capacitance formation region to the first power supply terminal. Based on the first time constant based on the wiring resistance of the second power supply wiring, the capacitance of the second capacitor, and the wiring resistance of the second power supply wiring from the second capacitance forming region to the second power supply terminal. It is characterized in that it is arranged at a position where the time constant of 2 substantially coincides.

  According to such a configuration, the fluctuation of the first reference voltage wiring is based on the capacitance of the first capacitor and the wiring resistance of the first power wiring from the first capacitance forming region to the first power supply terminal. This corresponds to the first time constant. In addition, the fluctuation of the second reference voltage wiring includes the second time constant based on the capacitance of the second capacitor and the wiring resistance of the second power supply wiring from the second capacitance forming region to the second power supply terminal. Depending on. Since the first and second time constants substantially coincide with each other, fluctuations in the first and second reference voltage wirings can be controlled with the same characteristics to effectively suppress the occurrence of luminance unevenness.

  In addition, the first capacitance formation region and the second capacitance formation region are arranged on both sides of the display unit in a plane and symmetrical to each other in the horizontal or vertical direction in plan view. And

  Further, the first capacitance forming region and the second capacitance forming region are arranged in an outer peripheral region of the display portion and in the vicinity of a corner portion.

  According to these configurations, the first time constant and the second time constant can be substantially matched. Thereby, fluctuations in the first and second reference voltage wirings are controlled with the same characteristics, and the occurrence of luminance unevenness is effectively suppressed.

  The display unit includes an element substrate on which the pixel electrode is disposed and a common substrate on which the common electrode is disposed, and liquid crystal is sealed between the element substrate and the common substrate disposed to face each other. The first capacitance formation region and the second capacitance formation region are arranged in at least a part of a formation region of a sealing material that connects the element substrate and the common substrate. .

  According to such a configuration, since the first capacitance formation region and the second capacitance formation region are formed in the formation region of the sealing material that occupies a relatively large area, a sufficient capacitance can be ensured. The fluctuations in the first and second reference voltage wirings can be sufficiently suppressed.

  In addition, a storage capacitor formed in the formation region of the display portion is further provided, and the first and second capacitors are formed of the same film as the storage capacitor.

  According to such a configuration, the first and second capacitors can be formed in the same process as the manufacturing process of the storage capacitor formed in the formation region of the display unit, and the first manufacturing process is not increased. Variations in the first and second reference voltage wirings can be suppressed.

  In addition, the storage capacitor is configured by using a semiconductor layer that constitutes a switching element that drives the pixel electrode, and one of the upper electrode and the lower electrode of the first and second capacitors is the semiconductor. It is characterized by being formed of the same film as the layer.

  According to such a configuration, the storage capacitor is configured using the semiconductor layer, and it is possible to prevent an increase in the steps required for forming the storage capacitor and the first and second capacitors.

  The storage capacitor is formed in a layer different from a semiconductor layer constituting a switching element for driving the pixel electrode, and one of the upper electrode and the lower electrode of the storage capacitor is connected to the pixel electrode, and the other is a predetermined one. It is connected to a fixed potential point.

  According to such a configuration, since the storage capacitor is formed in a layer different from the semiconductor layer, the degree of freedom in designing the storage capacitor is increased, and a sufficient capacity can be obtained.

  The display unit includes an element substrate on which the pixel electrode is disposed and a common substrate on which the common electrode is disposed, and liquid crystal is sealed between the element substrate and the common substrate disposed to face each other. The first capacitance formation region and the second capacitance formation region are configured such that a rubbing trajectory passing through the first and second capacitance formation regions is not applied to the display unit in the rubbing process on the element substrate. It is characterized by being arranged in.

  According to such a configuration, during the rubbing process, the rubbing trajectory that has passed through the first and second capacitance forming regions does not pass through the display unit. Thereby, the rubbing failure caused by the unevenness of the first and second capacitance forming regions occurs only in the portion other than the display portion and does not occur in the display portion, so that it is possible to prevent the image quality from deteriorating.

  According to another aspect of the invention, there is provided an electronic apparatus using the electro-optical device as a display unit.

  According to such a configuration, since the fluctuation of the reference voltage is suppressed, the image quality of the display means can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram showing an outline of a circuit arrangement and a wiring pattern according to the first embodiment of the present invention. The present embodiment is applied to a liquid crystal device as an electro-optical device. FIG. 2 is a plan view of the liquid crystal device, which is the electro-optical device of the present embodiment, viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the element substrate and the counter substrate are bonded to each other and the liquid crystal is sealed is cut along the line HH ′ in FIG. FIG. 4 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device. FIG. 5 is a plan view for explaining the configuration of the element in the capacitance forming region in FIG. 1, and FIG. 6 is an explanatory view showing a cross section of FIG. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

  First, an overall configuration of a liquid crystal device which is an electro-optical device according to the present embodiment will be described with reference to FIGS. In FIG. 2, the wiring connecting the elements is shown in a simplified manner.

  As shown in FIGS. 2 and 3, the liquid crystal device includes, for example, a quartz substrate, a glass substrate, a TFT substrate 10 using a silicon substrate, and a counter substrate using a glass substrate or a quartz substrate, for example. The liquid crystal 50 is sealed between the two. The TFT substrate 10 and the counter substrate 20 that are arranged to face each other are bonded together by a sealing material 52.

  On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix to form a display area 10a. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. On the pixel electrode 9 a of the TFT substrate 10, an alignment film 16 that has been subjected to a rubbing process is provided. On the other hand, an alignment film 22 subjected to a rubbing process is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. The alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example.

  FIG. 4 shows an equivalent circuit of elements on the TFT substrate 10 constituting the pixel. As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to cross each other, and a pixel electrode is formed in a region partitioned by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.

  The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 makes it possible to hold the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. The storage capacitor 70 improves the voltage holding characteristic and enables image display with a high contrast ratio.

  A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. The data line 6a has a laminated structure including an aluminum film, and the scanning line 11a is made of, for example, a conductive polysilicon film. The scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a '(see FIG. 9) in the semiconductor layer 1a. That is, the pixel switching TFT 30 is configured by disposing the gate electrode 3a and the channel region 1a 'connected to the scanning line 11a so as to face each other at the intersection of the scanning line 11a and the data line 6a.

  As shown in FIGS. 2 and 3, the counter substrate 20 is provided with a light shielding film 53 as a frame for partitioning the display area. As described above, a transparent conductive film such as ITO is formed on the entire surface of the counter substrate 20 as the counter electrode 21, and a polyimide-based alignment film 22 is formed on the entire surface of the counter electrode 21. The alignment film 22 is rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules.

  In a region outside the light shielding film 53, a sealing material 52 that encloses liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 52 is missing in a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed. Liquid crystal is injected from the liquid crystal injection port 108 into the gap between the element substrate 10 and the counter substrate 20 bonded together. After the liquid crystal injection, the liquid crystal injection port 108 is sealed with a sealing material 109.

  In an area outside the sealing material 52, an image signal is supplied to the data line 6a at a predetermined timing to drive the data line 6a and an external connection terminal 102 for connection to an external circuit. Are provided along one side of the TFT substrate 10. Scan line drive circuits 103 and 104 are provided along two sides adjacent to the one side to drive the gate electrode 3a by supplying scan signals to the scan line 11a and the gate electrode 3a at a predetermined timing. The scanning line driving circuits 103 and 104 are formed on the TFT substrate 10 at positions facing the light shielding film 53 inside the sealing material 52. Further, on the TFT substrate 10, wiring lines 105 that connect the data line driving circuit 101, the scanning line driving circuits 103 and 104, the external connection terminal 102, and the vertical conduction terminal 107 are provided to face the three sides of the light shielding film 53. It has been.

  The vertical conduction terminals 107 are formed on the four TFT substrates 10 at the corners of the sealing material 52. Between the TFT substrate 10 and the counter substrate 20, there is provided a vertical conductive material 106 whose lower end is in contact with the vertical conduction terminal 107 and whose upper end is in contact with the counter electrode 21. 10 and the counter substrate 20 are electrically connected.

  FIG. 1 shows a circuit arrangement and a wiring pattern of the liquid crystal device shown in FIGS. As shown in FIG. 1, in the center of the liquid crystal device, a display region 10a composed of pixels formed in a matrix is arranged. As described above, each pixel is configured by the TFT 30, the pixel electrode 9a, the storage capacitor 70 (not shown in FIG. 1) and the like on the TFT substrate 1 side, and is configured by the counter electrode 21 and the like on the counter substrate 20 side. Is done.

  A drive circuit 120 is disposed around the display area 10a. The driving circuit 120 includes scanning line driving circuits 103 and 104 and a data line driving circuit 101. The driving circuit 120 can be configured by combining a TFT 30 for driving a pixel with a P-channel TFT and an N-channel TFT formed by a common manufacturing process, thereby improving manufacturing efficiency and reducing manufacturing costs. It is possible to achieve reduction, uniform device characteristics, and the like.

  FIG. 1 shows an example in which 6-phase expansion is adopted for driving the display area 10a. In this case, the input image signal is supplied to the video signal lines VID1 to VID6 in parallel every 6 pixels. The video signal lines VID1 to VID6 are respectively data lines D1 to D6, D7 to D12,... (Hereinafter referred to as Dn1 to Dn6) of 1 · n columns to 6 · n columns (n = 1, 2,. 4 data lines 6a).

  The data line driving circuit 101 groups six data lines Dn1 to Dn6 for six pixels (pixels) into one group (block), and connects the video lines VID1 to VID6 to the data lines Dn1 to Dn6 belonging to these groups. The supplied image signal is sampled by 6 pixels and supplied simultaneously. In FIG. 1, for simplification of the drawing, only the switches S1, Sn2,... For determining the sampling timing are shown as sampling circuits. The data line driving circuit 101 is formed adjacent to one side of the display region 10a and in a region corresponding to the one side.

  On the other hand, in the example of FIG. 1, the scanning line driving circuits 103 and 104 are arranged on both sides of the display area 10a in the horizontal direction. The scanning line driving circuits 103 and 104 are connected to each scanning line 11a wired in the display area 10a, and sequentially supply an ON pulse to each scanning line 11a in the display area 10a every horizontal scanning period.

  Power supply terminals TV1 and TV2 and reference power supply terminals TF1 and TF2 are formed on the side of the display area 10a near the area where the data line driving circuit 101 is formed. A power supply voltage VSSY is supplied to the power supply terminals TV1 and TV2, and a reference voltage LCCOM supplied to the counter electrode 21 is supplied to the reference power supply terminals TF1 and TF2. The scanning line drive circuits 103 and 104 are connected to each other by a common wiring 111 formed along one horizontal side of the display area 10a. The power supply terminal TV1 is connected to the common line 111 via the power supply line LV1 along one side in the vertical direction of the display area 10a. The power supply terminal TV2 is connected to the common wiring 111 via the power supply wiring LV2 along the other side in the vertical direction of the display area 10a.

  The power supply voltage VSSY supplied to the power supply terminal TV1 is supplied as a negative power supply voltage to the scanning line driving circuit 103 via the power supply wiring LV1. The scan line driver circuit 103 supplies a negative power supply voltage VSSY (eg, 0 V) to scan lines other than the scan line to which the on-pulse is supplied in the scan period. Similarly, the power supply voltage VSSY supplied to the power supply terminal TV2 is supplied as a negative power supply voltage to the scanning line driving circuit 104 via the power supply wiring LV2. The scan line driver circuit 104 supplies a negative power supply voltage VSSY (for example, 0 V) to scan lines other than the scan line to which the on-pulse is supplied in the scan period.

  At the four corners of the display area 10a, the vertical conduction terminals 107 (shaded portions) are formed on the four TFT substrates 10 at the corners of the sealing material 52.

  The reference power supply terminal TF1 is connected to one end of an LCCOM wiring LF1 as a reference voltage wiring, and the LCCOM wiring LF1 is also connected to two vertical conduction terminals 107 disposed on one side in the horizontal direction of the display area 10a. The LCCOM wiring LF1 is wired adjacent to the power supply wiring LV1 that transmits the power supply voltage VSSY. Further, the reference power supply terminal TF2 is connected to one end of the LCCOM wiring LF2, and the LCCOM wiring LF2 is also connected to the two vertical conduction terminals 107 arranged on one side in the horizontal direction of the display area 10a. The LCCOM wiring LF2 is wired adjacent to the power supply wiring LV2 that transmits the power supply voltage VSSY.

  In the present embodiment, a capacitance forming region is formed between the transmission line of the power supply voltage VSSY and the transmission line of the reference voltage LCCOM. In the example of FIG. 1, a capacitance forming region 113 is provided between the power supply line LV1 that transmits the power supply voltage VSSY and the LCCOM line LF1 that transmits the reference voltage LCCOM, and the power supply line LV2 that transmits the power supply voltage VSSY and the reference voltage LCCOM. An example is shown in which a capacitance forming region 114 is provided between the LCCOM wiring LF2 for transmitting the signal. Capacitors C1 and C2 are formed in the capacitance forming regions 113 and 114, respectively.

  In the present embodiment, these two capacitance forming regions 113 and 114 include a time constant based on the capacitance of the capacitor C1 and the wiring resistance of the power supply wiring LV1 extending from the capacitance forming region 113 to the power supply terminal TV1, and the capacitor C2. The capacitor is formed at a position where the time constant based on the wiring resistance of the power supply wiring LV2 extending from the capacity forming region 114 to the power supply terminal TV2 substantially matches.

  In the example of FIG. 1, capacitance forming regions 113 and 114 are formed at mutually symmetrical positions on both sides in the horizontal direction of the display region 10a. For example, capacitors C1 and C2 that capacitively couple between the transmission line of the power supply voltage VSSY and the transmission line of the reference voltage LCCOM are formed in the vicinity of the two vertical conduction terminals 107 in the vicinity of one side in the vertical direction of the display area 10a.

  5 and 6 show the configuration of the capacitance forming region in FIG. Note that the two capacitance formation regions 113 and 114 have the same configuration, and only one capacitance formation region 113 will be described. FIG. 5 shows the planar shape of the capacitance forming region 113, and FIG. 6 shows the cross-sectional shape of FIG.

  In the capacitance forming region 113, it is assumed that the power supply wiring LV1 that transmits the power supply voltage VSSY and the LCCOM wiring LF1 that transmits the reference voltage LCCOM are formed in parallel in the same wiring layer. A lower electrode 122 is formed on the insulating layer 125 below the wiring layer. An insulating layer 126 is formed on the lower electrode 122, and an upper electrode 121 is formed on the insulating layer 126. On the upper electrode 121, a power supply wiring LV1 and an LCCOM wiring LF1 are formed via an insulating layer 127.

  A contact hole 124 is formed by an opening communicating the insulating layers 126 and 127. In addition, an opening is formed in the insulating layer 127 and a contact hole 123 is formed.

  The lower electrode 122 is connected to the power supply wiring LV1 that transmits the power supply voltage VSSY through the contact hole 124, and the upper electrode 121 is connected to the LCCOM wiring LF1 that transmits the reference voltage LCCOM through the contact hole 123. Thus, in the capacitance forming region 113, the capacitor C1 is formed by the lower electrode 122, the insulating layer 126, and the upper electrode 121 between the power supply wiring LV1 that transmits the power supply voltage VSSY and the LCCOM wiring LF1 that transmits the reference voltage LCCOM. The

  In the embodiment configured as described above, the LCCOM wiring LF1 that connects the reference voltage LCCOM is capacitively coupled to the power supply wiring LV1 that transmits the power supply voltage VSSY via the capacitor C1. The LCCOM wiring LF1 is connected to the power supply terminal TV1 to which the stable power supply voltage VSSY is applied, and the fluctuation of the reference voltage LCCOM is remarkably suppressed. The same applies to the LCCOM wiring LF2. The power supply wiring LV2 and the LCCOM wiring LF2 are capacitively coupled by the capacitor C2, and the LCCOM wiring LF2 is connected to the power supply terminal TV2 to which the stable power supply voltage VSSY is applied, and the reference voltage LCCOM. Fluctuations are significantly suppressed.

  FIG. 7 is an explanatory diagram for explaining the effect of forming a capacitor. FIG. 7 schematically shows a state of luminance unevenness by hatching. A rougher shaded line indicates a smaller change in luminance of the display image than the input image signal. Note that CL and CR in FIG. 7 correspond to the capacitors C1 and C2, respectively.

  FIG. 7A shows an example in which the fluctuation of the reference voltage LCCOM is almost completely suppressed by the capacitor CL. As shown in FIG. 7A, since the fluctuation of the reference voltage LCCOM is suppressed almost completely by the capacitor CL, the same luminance change can be caused over the entire screen. That is, in this case, luminance unevenness does not occur.

  In addition, the LCCOM wiring may slightly fluctuate due to the influence of a signal transmitted through a video signal line or the like. FIGS. 7B and 7C are for explaining the influence of the change in the reference voltage LCCOM in this case.

  In FIG. 7B, for example, when only one capacitor CL is provided on only one side of the display area 10a, or the positions of the two capacitors CL and CR (not shown in FIG. 7B) are asymmetric. Etc.

  When the capacitor CL is provided only on one side, the influence of the signal flowing in the video signal line differs between the left and right scanning line driving circuits 103 and 104. On the left side of the screen where the fluctuation of the reference voltage LCCOM is suppressed by the capacitor CL, a sufficient luminance change according to the image signal can be obtained, and on the right side of the screen where the fluctuation of the reference voltage LCCOM is not suppressed, a sufficient luminance change is obtained. I can't get it. In the region 131 of FIG. 7B, the luminance change is the smallest. Therefore, in this case, the luminance change differs between the left and right sides of the screen, resulting in uneven luminance.

  The fluctuation of the reference voltage LCCOM is caused by the capacitance of the capacitor C1 and the wiring resistance from the capacitance forming region 113 to the power supply terminal TV1 because the LCCOM wires LF1 and LF2 are capacitively coupled to the power supply wires LV1 and LV2 by the capacitors C1 and C2. The time constant is based on the time constant based on the wiring resistance from the capacitance of the capacitor C2 and the capacitance forming region 114 to the power supply terminal TV2. Therefore, when the positions of the two capacitors C1 and C2 are asymmetric, the amount of fluctuation of the reference voltage LCCOM transmitted through the left and right LCCOM wirings is different from each other, and the luminance unevenness similar to that in FIG. Occurs.

  On the other hand, in the present embodiment, as in FIG. 7C, the wiring resistances from the capacitance forming regions 113 and 114 to the power supply terminals TV1 and TV2 are the same, and the capacitances of the capacitors C1 and C2 are also the same. The time constants are made to coincide with each other. Thereby, the fluctuation amount of the reference voltage LCCOM transmitted by the LCCOM wiring LF1 and the reference voltage LCCOM transmitted by the LCCOM wiring LF2 are substantially the same. Therefore, in this case, as shown in FIG. 7C, the change in luminance is symmetrical on the left and right of the screen, and the luminance unevenness is reduced in the central portion 132 in the horizontal direction of the screen. Can be suppressed.

FIG. 8 is an explanatory diagram for explaining the relationship between the position of the capacitance forming region and rubbing.
In the capacitance forming regions 113 and 114, since the lower electrode 122, the upper electrode 121, and the like are formed, irregularities are formed on the surfaces of the alignment films 16 and 22. When a rubbing roll (not shown) passes through the capacitance forming regions 113 and 114 in the rubbing process, the rubbing tip of the rubbing cloth may be disturbed and rubbing failure may occur.

  Therefore, in the present embodiment, the capacitance forming regions 113 and 114 are formed at positions where the rubbing trajectory passing through the capacitance forming regions 113 and 114 does not reach the display region 10a or the display effective region. In FIG. 8, the arrow indicates the direction of the rubbing locus. The capacity forming areas 113 and 114 are formed outside the four corners of the display area, and the rubbing locus that has passed through the capacity forming areas 113 and 114 does not pass through the display area 10a. As a result, even when the hair tips of the rubbing cloth are disturbed in the capacity forming regions 113 and 114, the disturbance of the hair tips does not affect the rubbing of the display region 10a, and image quality deterioration due to rubbing failure can be prevented. it can.

  As described above, in this embodiment, a capacitor is formed between the LCCOM wiring and the power supply wiring, and fluctuations in the LCCOM wiring can be suppressed to prevent occurrence of luminance unevenness. In addition, the capacitors are provided at two symmetrical positions on both sides of the display area in the horizontal direction, and the occurrence of uneven brightness is ensured by matching the time constants between the LCCOM wires and the power supply terminals. It is preventing. Furthermore, since the capacitor is formed at a position where the rubbing trajectory passing through the capacitance forming region does not reach the display region 10a, image quality deterioration due to rubbing failure does not occur. Thus, luminance unevenness can be suppressed and high image quality can be achieved.

  In the present embodiment, the example in which the two capacitance forming regions are arranged at positions symmetrical to each other in the horizontal direction on both sides of the display region has been described. However, depending on how the LCCOM wiring and the power supply wiring are routed, for example, It is also conceivable to arrange them at positions symmetrical to each other in the vertical direction on both sides of the display area.

  In addition, it is obvious that the amount of variation of the LCCOM wiring can be controlled by appropriately setting the capacitance of the capacitor configured in each capacitance forming region.

FIG. 9 is a schematic cross-sectional view showing a second embodiment of the present invention.
The capacitors C1 and C2 in the first embodiment can be formed simultaneously with the process of forming the storage capacitor 70 in the display area 10a. FIG. 9 shows the configuration of the capacitance forming region 140 in this case. Note that the number and arrangement positions of the capacitance forming regions are the same as in the first embodiment, and the same configuration is used for each capacitor as in the first embodiment.

  First, the structure of one pixel in the display area 10a will be described with reference to FIG. As shown in FIG. 9, the liquid crystal device is configured to have a laminated structure from the lowermost first layer to the uppermost sixth layer in the display region 10 a, and the layers are arranged between the layers. A base insulating film 12 and first to fourth interlayer insulating films 41 to 44 for insulation are formed.

  The lowermost first layer includes, for example, a metal containing at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of a simple substance, an alloy, a metal silicide, a polysilicide, a laminate of these, or conductive polysilicon is provided. The scanning line 11a is planarly patterned in a stripe shape in the scanning line direction and has a protruding portion extending along the data line 6a. Note that the protrusions extending from the adjacent scanning lines 11a are not connected to each other, and therefore, each scanning line 11a is divided by one. Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row.

  A base insulating film 12 made of, for example, a silicon oxide film is formed on the first layer, and a TFT 30 forming the second layer is formed on the base insulating film 12.

  As shown in FIG. 9, the TFT 30 constituting the second layer is composed of a semiconductor layer 1 a that is a polysilicon film, a gate insulating film 2, and a gate electrode 3. The semiconductor layer 1a has an LDD (Lightly Doped Drain) structure, and a channel region 1a ′ in which a channel is formed by an electric field from the gate electrode 3a, a low concentration source region 1b, a low concentration drain region 1c, and a high concentration source. The region 1d and the high concentration drain region 1e are configured.

  In the second layer, a relay electrode 719 is also formed of the same film as the gate electrode 3a. A contact hole 12cv is formed in the base insulating film 12, and the gate electrode 3a stacked above the contact hole 12cv includes a concavely formed portion on the lower side. Then, the gate electrode 3a is formed so as to fill the entire contact hole 12cv, and the scanning line 11a and the gate electrode 3a in the same row have the same potential. Although not shown in FIG. 9, a side wall portion 3b formed integrally with the gate electrode 3a is extended.

  On the TFT 30, the gate electrode 3a and the relay electrode 719, for example, silicate glass films such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorous silicate glass), A first interlayer insulating film 41 made of a silicon nitride film, a silicon oxide film, or the like, or preferably NSG is formed. A storage capacitor 70 is formed on the first interlayer insulating film 41 as a third layer.

  The storage capacitor 70 constituting the third layer includes a lower electrode 71, a dielectric film 75, and a capacitor electrode 300 as an upper electrode. The lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. As the lower electrode 71, a single layer film or a multilayer film containing a metal or an alloy can be adopted. In the example of FIG. 9, the lower electrode 71 has a function as a pixel potential side capacitor electrode and a function of relaying the pixel electrode 9 a and the high concentration drain region 1 e of the TFT 30.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to a later-described fifth shield layer 400 having a fixed potential.

  As shown in FIG. 9, the dielectric film 75 has a two-layer structure including a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer. The dielectric film 75 may be formed of a relatively thin silicon oxide film such as an HTO (High Telperature oxide) film, an LTO (Low Telperature oxide) film, or a silicon nitride film having a thickness of about 5 to 200 nm. Good. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better, as long as sufficient film reliability is obtained.

  In the example of FIG. 9, since the silicon nitride film 75b having a relatively large dielectric constant is formed, the capacitance value of the storage capacitor 70 can be increased, and the silicon oxide film 75a is formed. It is possible to prevent the pressure resistance of the storage capacitor 70 from being lowered. Thus, by making the dielectric film 75 have a two-layer structure, it is possible to enjoy two conflicting effects.

  A contact hole 83 is formed in the first interlayer insulating film 41, and the high concentration drain region 1 e of the TFT 30 and the lower electrode 71 of the storage capacitor 70 are electrically connected by the contact hole 83. ing. A contact hole 881 is also opened in the first interlayer insulating film 41, and the lower electrode 71 of the storage capacitor 70 and the relay electrode 719 are electrically connected by the contact hole 881. .

  On the storage capacitor 70 constituting the third layer, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma CVD method using TEOS gas is formed. A second interlayer insulating film 42 is formed. On the second interlayer insulating film 42, a data line 6a constituting the fourth layer is provided.

  The data lines 6a constituting the fourth layer are formed in a stripe shape so as to coincide with the direction in which the semiconductor layer 1a of the TFT 30 extends.

  In the example of FIG. 9, the data line 6a is formed as a film having a three-layer structure in order from the lower layer: a layer 41A made of aluminum, a layer 41TN made of titanium nitride, and a layer 401 made of a silicon nitride film. The silicon nitride layer 401 is patterned to a slightly larger size so as to cover the lower aluminum layer 41A and titanium nitride layer 41TN. The data line 6a contains aluminum, which is a relatively low resistance material, to facilitate supply of image signals to the TFT 30 and the pixel electrode 9a. In addition, the data line 6a is provided with a silicon nitride layer 401 that is relatively excellent in preventing moisture from entering, so that the moisture resistance of the TFT 30 can be improved, and the life of the TFT can be extended. Note that a plasma silicon nitride film is preferably used as the silicon nitride layer 401.

  In addition, a shield layer relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a. The shield layer relay layer 6a1 and the second relay electrode 6a2 are formed in the same process as the data line 6a, and in order from the lower layer are a three-layer structure of a layer made of aluminum, a layer made of titanium nitride, and a layer made of plasma nitride film. It is a film | membrane which has.

  A contact hole 801 is opened in the second interlayer insulating film 42, and the contact hole 801 electrically connects the shield layer relay layer 6 a 1 and the capacitor electrode 300 that is the upper electrode of the storage capacitor 70. It has become. Further, a contact hole 81 is opened in the first and second interlayer insulating films 41 and 42, and the contact hole 81 electrically connects the high concentration source region 1d of the TFT 30 and the data line 6a. It has become. In addition, a contact hole 882 is formed in the first and second interlayer insulating films 41 and 42, and the contact hole 882 electrically connects the relay electrode 719 and the second relay electrode 6a2. Yes.

  In FIG. 9, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is once detoured to the lower relay electrode 719 and pulled out to the upper layer through the contact hole 882. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9 a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. As a result, the etching rates of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be easily controlled, and the degree of freedom in designing the film thickness and the like can be increased.

  On the fourth layer, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a third interlayer insulating film formed by a plasma CVD method using TEOS gas 43 is formed. On the third interlayer insulating film 43, a shield layer 400 constituting the fifth layer is formed.

  The shield layer 400 constituting the fifth layer is formed in a lattice shape in plan view. A part of the shield layer 400 is formed so as to cover the data line 6a and wider than the data line 6a. The shield layer 400 is set to a fixed potential by being electrically connected to a constant potential source. The constant potential source may be a positive power source or a negative power source supplied to the data line driving circuit 101 described later, or a constant potential (LCCOM) supplied to the counter electrode 21 of the counter substrate 20. Absent.

  As described above, since the shield layer 400 is formed so as to cover the entire data line 6a and at a fixed potential, the influence of capacitive coupling generated between the data line 6a and the pixel electrode 9a. Can be eliminated. That is, it is possible to avoid the potential of the pixel electrode 9a from fluctuating in response to the energization of the data line 6a, thereby reducing the possibility of causing display unevenness along the data line 6a on the image. be able to. Since the shield layer 400 is formed in a lattice shape, it is possible to prevent unnecessary capacitive coupling from occurring in the portion where the scanning line 11a extends.

  Further, a third relay electrode 402 as a relay layer is formed on the fifth layer as the same film as the shield layer 400. The shield layer 400 and the third relay electrode 402 have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

  A contact hole 803 is opened in the third interlayer insulating film 43, and the shield layer 400 and the shield layer relay layer 6 a 1 are electrically connected by the contact hole 803. A contact hole 804 is also opened in the third interlayer insulating film 43. Through the contact hole 804, the third relay electrode 402 and the second relay electrode 6a2 are electrically connected.

  The shield layer relay layer 6a1 and the titanium nitride layer of the second relay electrode 6a2 have a function as a barrier metal for preventing etching through when the contact holes 803 and 804 are opened.

  On the fifth layer, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma TEOS film formed by a plasma CVD method using TEOS gas is used. A fourth interlayer insulating film 44 is formed. On the fourth interlayer insulating film 44, pixel electrodes 9a constituting the sixth layer are formed in a matrix. A contact hole 89 is formed in the fourth interlayer insulating film 44.

  The pixel electrode 9 a constituting the sixth layer is electrically connected to the third relay electrode 402 via the contact hole 89. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of ITO or the like. When aluminum and ITO are directly connected, electric corrosion occurs between the two, and preferable electrical connection cannot be realized due to disconnection of aluminum or insulation due to formation of alumina. On the other hand, in the example of FIG. 9, since titanium nitride and ITO are connected, the contact resistance is low and good connectivity can be obtained.

  An alignment film 16 is formed on the pixel electrode 9a. The surfaces of the third and fourth interlayer insulating films 43 and 44 are planarized by CMP (Chemical Mechanical Polishing) processing or the like.

  On the other hand, the capacitor forming region 140 has a capacitor formed by the same structure as the storage capacitor 70. That is, the power supply wiring 141 is formed on the base insulating film 12 on the substrate 10, and the first interlayer insulating film 41 is formed on the power supply wiring 141. The power supply wiring 141 is formed of the same film as the gate electrode 3a. A capacitor 142 is formed on the first interlayer insulating film 41. The capacitor 142 is formed in the same process as the capacitor 70, and has a lower electrode, an insulating film, and an upper electrode that are the same film as the lower electrode 71, the dielectric film 300, and the capacitor electrode 300, respectively.

  A second interlayer insulating film 42 is formed on the capacitor 142, and an LCCOM wiring 144 is formed on the second interlayer insulating film 42. The LCCOM wiring 144 is formed in the same process as the aluminum layer 41A of the data line 6a. The LCCOM wiring 144 may also be formed in a multilayer structure similar to the data line 6a in the display area 10a.

  A contact hole 145 is formed in the first interlayer insulating film 41, and a contact hole 146 is formed in the second interlayer insulating film 42. The contact hole 145 is opened in the same process as the contact hole 83 formed in the display area 10a, and the contact hole 146 is opened in the same process as the contact hole 801 formed in the display area 10a.

  The lower electrode of the capacitor 142 is connected to the power supply wiring 141 through the contact hole 143, and the upper electrode is connected to the LCCOM wiring 144 through the contact hole 146. In this way, a capacitor similar to that of the first embodiment can be formed.

  By adopting the configuration of FIG. 9 in this way, it is possible to form a capacitor between the LCCOM wiring and the power supply wiring by the same process as the process of forming each layer in the display region 10a.

  FIG. 10 is a schematic cross-sectional view showing an example in which a capacitor is formed in the same process as the process of forming the semiconductor layer and the gate electrode constituting the TFT.

  In the example of FIG. 10, in the element region 150, a gate electrode 154 is formed on the semiconductor layer 152 through a gate insulating film 153. The source region of the semiconductor layer 152 is connected to the data line 156 through the contact hole 155. The drain region of the semiconductor layer 152 is connected to the pixel electrode 161 through the contact hole 160.

  An upper electrode 157 is also formed on the semiconductor layer 152 with an insulating film 153 interposed therebetween. In the example of FIG. 10, a storage capacitor is formed by the semiconductor layer 152, the insulating film 153, and the upper electrode 157. The upper electrode 157 is connected to the capacitor line 159 through the contact hole 158.

  On the other hand, in the capacitance forming region 151, a lower electrode 162 formed of the same film as the semiconductor layer 152 is formed. An insulating film 163 formed of the same film as the gate insulating film 153 is formed on the lower electrode 162, and an upper electrode 164 formed of the same film as the gate electrode 154 is formed on the insulating film 163. Yes. An LCCOM wiring 166 is formed on the upper electrode 164 via an interlayer insulating film 165.

  These lower electrode 162, insulating film 163, and upper electrode 164 form a capacitor. A power supply wiring (not shown) is formed of the same film as the lower electrode 162, and the lower electrode 162 is connected to the power supply wiring. Further, the upper electrode 164 is connected to the LCCOM wiring 166 through the contact hole 165.

  Thus, even in this case, it is possible to form a capacitor between the power supply wiring and the LCCOM wiring 166 in the capacitance forming region by using the manufacturing process of the display region 150.

  FIG. 11 is an explanatory view showing a third embodiment of the present invention. FIG. 11A shows a layout of a liquid crystal device that is an electro-optical device according to the third embodiment, and FIG. 11B shows an enlarged plan view of a portion 190 of FIG. 11A. FIG. 11C shows a cross-sectional shape taken along the line BB ′ of FIG. This embodiment is an example in which at least a part of a formation region of a sealing material used for bonding substrates is a capacitance formation region. FIG. 11 shows an example in which the entire region of the sealing material forming region (sealing region) disposed on both sides in the horizontal direction of the panel is a capacitance forming region.

  In general, a photo-curing adhesive is used as the sealing material. In this case, in order to keep the curing speed constant, a method may be employed in which a light blocking function is formed by forming a member having a light shielding function in the seal region in a slit structure. The present embodiment is applied to this case.

  The liquid crystal panel 181 is provided with an input terminal arrangement region 182 at the edge of one side in the vertical direction. A data line drive circuit formation region 183 is provided adjacent to the input terminal arrangement region 182. On the other side of the liquid crystal panel 181 in the vertical direction, an inspection circuit formation region 186 is provided along the display region 180 in the center of the panel, and a seal region 189 is provided on the edge side.

  A scanning line driving circuit forming region 184 is provided along the display region 180 in the center of the panel on the edge of one side in the horizontal direction of the liquid crystal panel 181, and a seal region 187 is provided on the edge side. Further, a scanning line driving circuit forming region 185 is provided along the display region 180 in the center of the panel on the edge of the other side in the horizontal direction of the liquid crystal panel 181, and a seal region 188 is provided on the edge side.

  In the present embodiment, the entire seal regions 187 and 188 are set as capacitance forming regions for forming capacitors for capacitively coupling the LCCOM wiring and the power supply wiring. FIG. 11B is an enlarged view of a part 190 of FIG. 11A. As shown in FIG. 11B, in the seal region 188, input wirings 191 of a plurality of scanning line driving circuits are provided. It extends in the vertical direction of the panel. In a region outside the input wiring 191 of the scanning line driving circuit, an LCCOM wiring 196 is provided adjacent to the input wiring 191 of the scanning line driving circuit. The LCCOM wiring 196 is formed along the entire length of the seal region 188, and the LCCOM wiring 196 is also branched in the horizontal direction of the liquid crystal panel 181 and extended in a comb shape. The upper electrode 192 is configured by the comb-shaped portion. The upper electrode 192 constitutes an end portion 193 by connecting the tips of the comb-shaped portions in common.

  As shown in FIG. 11C, a power supply wiring 197 is wired below the LCCOM wiring 196 via an insulating film 195. The power supply wiring 197 is also formed along the entire length of the seal region 188. The power supply wiring 197 also branches in the horizontal direction of the liquid crystal panel 181 and extends in a comb shape. The lower electrode 194 is configured by the comb-shaped portion. The lower electrode 194 has a comb-shaped tip connected in common.

  The comb-shaped portion of the upper electrode 196 and the comb-shaped portion of the lower electrode 194 are opposed to each other with the insulating film 195 interposed therebetween, and are provided in the entire seal region 188. These lower electrode 194, insulating film 195 and upper electrode 196 form a capacitor. Thus, in the present embodiment, the entire seal region 188 becomes a capacitance formation region, and a relatively large capacitor is formed.

  Note that a capacitor having the same configuration as that of FIGS. 11B and 11C is also formed below the seal region 187.

  As described above, in the present embodiment, a very wide region, that is, the entire seal region adjacent to the left and right edge portions of the liquid crystal panel is used as a capacitance forming region, and the capacitance of the capacitor that capacitively couples the power supply wiring and the LCCOM wiring is set. Can be large enough. Thereby, it is possible to increase the time constant and further suppress the fluctuation of the LCCOM wiring. It should be noted that it is not always necessary to use the entire sealing area as the capacity forming area, and it is obvious that only a part of the sealing area may be used as the capacity forming area.

  Further, although FIG. 11 illustrates an example in which the power supply wiring is wired on the lower layer side and the LCCOM wiring is wired on the upper layer side, it is obvious that any of these wirings may be the upper layer or the lower layer. Further, the materials constituting the power supply wiring and the LCCOM wiring are not particularly limited.

  Note that this embodiment shows an example in which the present invention is applied to a structure in which a comb-like LCCOM wiring is formed in a seal region, but electrodes similar to the lower electrode 122 and the upper electrode 121 shown in FIGS. 5 and 6 are used. It is also possible to form a capacitor by forming the entire sealing region.

  In each of the above embodiments, the insulating film between the lower electrode and the upper electrode may be formed sufficiently thick as a capacitor in the capacitance forming region. In this case, the charge density between the lower electrode and the upper electrode can be kept low, and the breakdown voltage of the capacitor can be improved and the lifetime can be extended.

(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail as a light valve will be described. FIG. 12 is an explanatory diagram of a projection type color display device.

  In FIG. 12, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device having a drive circuit mounted on a TFT array substrate, and each has a light bulb 100R for RGB. , 100G and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, the light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. The light is divided into B and led to the light valves 100R, 100G and 100B corresponding to the respective colors. In particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

  The electro-optical device of the present invention is applied not only to a passive matrix liquid crystal display panel but also to an active matrix liquid crystal panel (for example, a liquid crystal display panel including a TFT (thin film transistor) or a TFD (thin film diode) as a switching element). It is possible to apply similarly. In addition to liquid crystal display panels, electroluminescence devices, organic electroluminescence devices, plasma display devices, electrophoretic display devices, devices using electron emission (such as Field Emission Display and Surface-Conduction Electron-Emitter Display), DLP ( The present invention can be similarly applied to various electro-optical devices such as Digital Light Processing (aka DMD: Digital Micromirror Device).

Explanatory drawing which shows the outline of the circuit arrangement | positioning and wiring pattern which concern on the 1st Embodiment of this invention. FIG. 3 is a plan view of the liquid crystal device, which is the electro-optical device according to the present embodiment, viewed from the counter substrate side together with each component formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the element substrate and the counter substrate are bonded to each other and the liquid crystal is sealed is cut along the line HH ′ in FIG. 2. FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device. FIG. 2 is a plan view for explaining a configuration of an element in a capacitor formation region in FIG. 1. Explanatory drawing which shows the cross section of FIG. Explanatory drawing for demonstrating the effect by forming a capacitor | condenser. Explanatory drawing for demonstrating the relationship between the position of a capacity | capacitance formation area, and rubbing. The typical sectional view showing the 2nd embodiment of the present invention. The typical sectional view showing the example in the case of forming a capacitor in the same process as the film formation process of the semiconductor layer which constitutes TFT, and the gate electrode. Explanatory drawing which shows the 3rd Embodiment of this invention. Explanatory drawing which shows the liquid crystal projector which is an example of the electronic device in this embodiment.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10a ... Display area, 101 ... Data line drive circuit, 103, 104 ... Scan line drive circuit, 107 ... Vertical conduction terminal, TV1, TV2 ... Power supply terminal, TF1, TF2 ... Reference power supply terminal, LV1, LV2 ... Power supply wiring, LF1 , LF2 ... LCCOM wiring.

Claims (9)

A display unit for driving pixels based on an image signal supplied to the pixel electrodes arranged in a matrix form via a signal line and a reference voltage supplied to the common electrode;
First and second reference voltage wirings for supplying a reference voltage to the common electrode;
First and second power supply terminals to which a predetermined fixed potential is supplied , and first and second power supply wirings connected to the first and second power supply terminals, respectively.
A first capacitance forming region constituting a first capacitor between the first reference voltage wiring and the first power supply wiring;
A second capacitance forming region constituting a second capacitor between the second reference voltage wiring and the second power supply wiring ;
The first capacitance formation region and the second capacitance formation region are the capacitance of the first capacitor and the wiring of the first power supply wiring from the first capacitance formation region to the first power supply terminal. A second time based on the first time constant based on the resistance, the capacitance of the second capacitor, and the wiring resistance of the second power supply wiring from the second capacitance forming region to the second power supply terminal. An electro-optical device, wherein the electro-optical device is disposed at a position that substantially matches a time constant . The first capacitor forming region and the second capacitor forming region are arranged on both sides of the display unit in a plane and symmetrically with each other in the horizontal or vertical direction in plan view. The electro-optical device according to claim 1 . 2. The electro-optical device according to claim 1 , wherein the first capacitance formation region and the second capacitance formation region are arranged in an outer peripheral region of the display unit and in the vicinity of a corner portion. The display unit includes an element substrate on which the pixel electrode is disposed and a common substrate on which the common electrode is disposed, and liquid crystal is sealed between the element substrate and the common substrate that are disposed to face each other. ,
Wherein the first capacitor forming region and the second capacitor forming region, claim, characterized in that disposed on at least a portion of the formation region of the sealing material for connecting the common substrate and the element substrate 1 The electro-optical device according to 1. A storage capacitor formed in the display region;
The electro-optical device according to claim 1 , wherein the first and second capacitors are formed of the same film as the storage capacitor. The storage capacitor has an electrode configured using a semiconductor layer that constitutes a switching element that drives the pixel electrode,
6. The electro-optical device according to claim 5 , wherein one of the upper electrode and the lower electrode of the first and second capacitors is formed of the same film as the semiconductor layer. The storage capacitor is formed in a layer different from a semiconductor layer constituting a switching element for driving the pixel electrode,
6. The electro-optical device according to claim 5 , wherein one of an upper electrode and a lower electrode of the storage capacitor is connected to the pixel electrode, and the other is connected to a predetermined fixed potential point. The display unit includes an element substrate on which the pixel electrode is disposed and a common substrate on which the common electrode is disposed, and liquid crystal is sealed between the element substrate and the common substrate that are disposed to face each other. ,
The first capacitance formation region and the second capacitance formation region are arranged at a position where a rubbing trajectory passing through the first and second capacitance formation regions is not applied to the display unit in the rubbing process for the element substrate. The electro-optical device according to claim 1 . Electronic device characterized by using as a display unit an electro-optical device according to claims 1 to 8.

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