JP4455636B2 - Active matrix display device and drive control method thereof - Google Patents

Description

  The present invention relates to a drive circuit that outputs a current signal. The present invention also relates to a display device using the same.

  An active matrix display device using organic electroluminescence (EL) elements has a higher gradation of individual pixels than the simple matrix method, in which the electrodes are arranged in a grid and the light emission is controlled only by on / off operation. Therefore, a display with a high contrast ratio and a high response speed can be realized.

  The EL display device includes an image display unit in which pixels are arranged, and a drive circuit for processing signal information such as a video signal input from the outside and sending the information to each pixel of the image display unit. The drive control circuit built in the same display panel as the image display unit is usually configured using a thin film transistor (TFT). Also, TFTs are mainly used as active elements for controlling the light emission state of EL elements in each pixel. However, because of the characteristics of TFTs, the variation between elements is larger than that of CMOS transistors, and the correlation cannot be guaranteed even in close proximity. Therefore, if the circuit design is not made so as to control the driving state reliably, Even if the pixels are caused to emit light uniformly, uneven brightness occurs.

  In Patent Document 1, a pixel circuit is configured by using four TFTs, and a transistor for controlling a current flowing in an EL element is controlled by a plurality of gate lines and a single source line, without using a source follower configuration. A pixel circuit configuration is disclosed in which the influence of the kink current of the transistor is suppressed to reduce the fluctuation of the current value stored in the pixel circuit.

  As shown in FIG. 13, the circuit disclosed in Patent Document 2 includes a current detection circuit 105 that detects a current flowing through the organic EL element 103 in the pixel circuit, an output voltage of the current detection circuit 105, and a sample hold circuit 101. An error amplifier circuit 102 that amplifies a difference between the output voltages of the current detection circuit 104 and inputs the difference to the current control circuit 194 is configured so that the output voltage of the current detection circuit 104 and the output voltage of the sample hold circuit 101 are equalized by a negative feedback operation. The brightness is controlled to be uniform.

  Patent Document 3 discloses a configuration as shown in FIG. Instead of providing a current detection circuit for each pixel, a current measurement element 110 is provided for each supply line of the power supply 108, and the current of the drive elements in a row is measured by the current measurement element 110 according to the control state of the scan driver 111. A configuration is disclosed in which data is stored in the storage unit 108 later, and is fed back to the image data after being calculated by the arithmetic element 107 and the external data driver 106.

  Various display elements are known in addition to EL elements. Patent Document 4 discloses a configuration in which an electron-emitting device is driven by a current signal.

Japanese Patent Laid-Open No. 2003-66865 JP 2002-91377 A JP 2002-278513 A US Pat. No. 6,195,076

  The problem to be solved by the present invention is to realize a simple configuration capable of evaluating the output of the drive circuit.

A first aspect of the present invention is a pixel circuit having a thin film transistor for controlling light emission of an EL element and a capacitor provided at a gate of the thin film transistor, and a voltage corresponding to an input current signal is the capacitor. In an active matrix display device in which a plurality of pixel circuits that are held in a matrix and emit light from the EL element based on the current signal are arranged in a matrix,
A plurality of current signal generating circuits configured using thin film transistors, converting the input video signal voltage and generating the current signals to be input to each of the plurality of pixel circuits via data lines;
A signal output line to which outputs of the plurality of current signal generation circuits are connected in common;
A control circuit that controls each of the plurality of current signal generation circuits to a current output state in which an output of a specific current signal generation circuit can be evaluated from a current value output through the signal output line;
A correction circuit for detecting current signals output from the plurality of current signal generation circuits via a signal output line, and correcting a video signal voltage input to the current signal generation circuit according to a detection result; ,
Comprising
A blocking unit provided on the data line, for blocking connection between the current signal generating circuit and the plurality of pixel circuits;
A switch unit for connecting the current signal generation circuit and the signal output line;
Have
The plurality of current signal generation circuits and the plurality of pixel circuits in a period in which current signals output from the plurality of current signal generation circuits are detected via the signal output lines by the cutoff unit and the switch unit. And the plurality of current signal generation circuits are simultaneously connected to the signal output line.
Furthermore, the EL element is an organic EL element.
The corrected video signal voltage is supplied to the plurality of current signal generation circuits from a DAC provided in an external control circuit.
Further, the pixel circuit includes a thin film transistor for turning off the thin film transistor capacitor connecting the gate and drain, a thin film transistor capacitor connecting the drain of the said data lines TFT, a current flowing through the electroluminescent element of the thin film transistor And further comprising.

  In the present invention, a drive circuit that can be evaluated can be realized with a simple configuration.

The first embodiment according to the present application is configured as follows. That is,
A plurality of current signal generating circuits for outputting a current signal to each of the plurality of output units;
A current signal output line to which outputs of the plurality of current signal generation circuits are connected in common;
A control circuit for controlling each of the plurality of current signal generation circuits to a current signal output state capable of evaluating a specific output of the current signal generation circuit from a current value output via the current signal output line;
A correction value output circuit that evaluates an output of a specific current signal generation circuit from a current value output via the current signal output line, and outputs a correction value according to the evaluation result;
A correction circuit for correcting the video signal supplied to the current signal generation circuit with the correction value;
A driving circuit having

  Here, it is preferable that the control circuit supplies a predetermined signal to the specific current signal generation circuit and supplies a signal different from the predetermined signal to the other current signal generation circuits in common. Can be adopted. For example, the first current signal generation circuit which is one of the plurality of current signal generation circuits is used as a specific current signal generation circuit to supply a predetermined signal, and the other current signal generation circuits are different in common. Supply the signal. The result obtained at that time is taken as the first result. Next, the second current signal generation circuit different from the first current signal generation circuit is used as a specific current signal generation circuit to supply the predetermined signal, and the other current signal generation circuits are supplied with the common signal. To do. The result obtained at that time is defined as a second result. By comparing the first result and the second result, it is possible to compare and evaluate the first current signal generation circuit and the second current signal generation circuit.

  Also, here, the evaluation of the output of the current signal generation circuit means that the difference between the output value of the current signal generation circuit, the output of another current signal generation circuit, or the difference from a predetermined reference value is detected directly or indirectly. Say to do.

  In particular, the control circuit supplies a predetermined signal to the specific current signal generation circuit and supplies a signal different from the predetermined signal to the other current signal generation circuit, and the different signal However, the current value of the current signal output from each of the other current signal generation circuits supplied with the different signal is the current value of the current signal output from the specific current signal generation circuit supplied with the predetermined signal. It is possible to suitably employ a configuration that is a signal that is sufficiently smaller than. With this configuration, the output of a current signal generation circuit other than the specific current signal generation circuit to be evaluated can be ignored. Further, even when the output of another current signal generation circuit cannot be ignored, an operation for processing the output as a background becomes easy, or the accuracy of the result of the operation can be increased. .

  In each of the above embodiments, a configuration further including a switch that realizes a state in which the current signal output line and the plurality of current signal generation circuits are simultaneously connected can be suitably employed. This switch can suitably adopt a configuration that is a switch group including switches provided corresponding to each of the plurality of current signal generation circuits. A configuration in which the current signal output from the current signal generation circuit is supplied to the current signal output line in the middle of the current path between the current signal generation circuit and the display element to which the current signal output from the current signal generation circuit is supplied. In this configuration, it is desirable to leave the current signal generation circuit and the current signal output line in a disconnected state when it is not necessary to evaluate the output of the current signal generation circuit. It is desirable to arrange a switch so that the disconnected state can be realized. In the present invention, each of the plurality of current signal generation circuits is set in a current signal output state in which the output of the specific current signal generation circuit can be evaluated from the current value output through the current signal output line. Use a control circuit to control.

  Therefore, this switch does not have to be capable of individually controlling the connection relationship between each current signal generation circuit and the current signal output line. Even when individual switches are provided between the individual current signal generation circuits and the current signal lines, these switches can be controlled by a common control signal.

  In each of the above embodiments, each of the plurality of current signal generation circuits has a plurality of switches for controlling connection relations between the current signal output lines, and the plurality of switches have a common control signal. It is possible to suitably employ a configuration that is controlled by.

  In each of the above embodiments, each of the plurality of current signal generation circuits has a plurality of switches that respectively control connection relationships between the plurality of output units, and the plurality of switches have a common control signal. It is possible to suitably employ a configuration that is controlled by. As described above, the current signal output from the current signal generation circuit is caused to flow through the current signal output line in the middle of the current path between the current signal generation circuit and the display element to which the current signal output from the current signal generation circuit is supplied. However, when the evaluation is performed by guiding the output of the current signal generation circuit to the current signal output line, the configuration in which the output of the current signal generation circuit is not shunted to the display element side is desirable. By providing a switch between the data line to which the display element is connected and the current signal generation circuit, the current signal to be evaluated can be prevented from being shunted to the data line side.

  In the present invention, expressions such as output of a current signal are used. However, these expressions are not limited to a configuration in which current flows in a specific direction. For example, a current signal generation circuit outputs a current signal. The case includes both the case where the current as the current signal flows out of the current signal generation circuit and the case where the current flows into the current signal generation circuit.

  In each of the above embodiments, the drive circuit is a circuit for driving a display device having a display element, and the display device has at least a part of the display element formed on a substrate, and the current signal generation A configuration in which the circuit and the current signal output line are formed on the substrate can be suitably employed.

  In each of the above embodiments, the current signal generation circuit includes at least a circuit that outputs a current signal having a current value obtained by squaring the value of the input signal, and the correction value output circuit is obtained by the evaluation. A configuration that outputs a correction value obtained by calculating the square root of the ratio between the output evaluation value of the specified current signal generation circuit and the reference value can be suitably employed. In particular, the correction value output circuit includes an arithmetic circuit for calculating the square root, and the calculation is performed in accordance with the value of the ratio between the output evaluation value and the reference value. A configuration that is an approximate calculation can be suitably employed.

  Further, the present application is an invention of a display device, the driving circuit of each of the above inventions, a plurality of data lines connected to the plurality of output portions of the driving circuit, and a plurality of data lines connected to the plurality of data lines, respectively. The invention of a display device having a display element is included.

  As this display device, a display device in which a plurality of display elements are arranged in a matrix can be suitably used. In that case, the plurality of data lines are used as a plurality of modulation signal lines, and in addition, a plurality of scanning lines constituting a matrix wiring are provided together with the plurality of modulation signal lines, and a plurality of the display arranged in a matrix by the matrix wiring A configuration for driving the element can be suitably employed. In this case, a scanning circuit for sequentially selecting scanning lines may be provided.

  Note that the current signal generation circuit, the current signal output line, the switch, and the like of the drive circuit can be arranged on a substrate that forms at least a part of the display element. It is not necessary to take the form connected with the output part of the circuit by a special connection element. In that case, an arbitrary position between the portion where the display element of the data line is connected and the circuit constituting the driving circuit is the output section.

  As the display element in the present invention, various elements that can be driven by a current signal can be used. For example, an EL element can be particularly preferably used as a display element.

Further, the present application includes the following inventions as inventions of a method for evaluating a drive circuit. That is,
A method for evaluating a drive circuit including a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units,
Connecting the outputs of the plurality of current signal generation circuits to a common current signal line;
Controlling each of the plurality of current signal generation circuits to a current signal output state such that the output of the specific current signal generation circuit can be evaluated from a current value output via the current signal output line;
Evaluating a specific output of the current signal generation circuit from a current value output via the current signal output line;
The evaluation method of the drive circuit which has these.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration relating to a correction path of a drive circuit according to a preferred embodiment of the present invention. In the figure, 1 is a drive control circuit, 2 is a total current detection circuit, 3 is a column current measurement circuit, 4 is a column current storage circuit, 5 is a reference current detection circuit, 6 is a correction gain determination circuit, and 7 is a correction coefficient calculation circuit. , 8 are correction coefficient storage circuits, 9 is a video signal correction circuit, and 20 is a pixel circuit.

  In the drive circuit of this embodiment, a total current output circuit (included in the drive control circuit in FIG. 1) is provided between the column control circuit and the pixel circuit, and the current signal output from the column control circuit is supplied to the total current output circuit. The total current is output from the current output circuit, detected by the total current detection circuit 2, and the current signal data for each data line is measured in the column current measurement circuit 3 and stored in the column current storage circuit 4. Next, reference current signal data is selected from the column current storage circuit 4 via the reference column current detection circuit, and the reference current signal data and the column current storage circuit 4 are stored in the correction coefficient calculation circuit 7. A correction coefficient is obtained by performing arithmetic processing on the current signal data of each data line, and the correction coefficient is stored in the correction coefficient storage circuit 8. In response to the input of a new video signal, the video signal correction circuit 9 uses the correction coefficient of the corresponding data line stored in the correction coefficient storage circuit 8 for the data for each pixel included in the video signal. Make corrections. The corrected video signal obtained in the video signal correction circuit 9 is sent again to the drive control circuit 1 and sent to the pixel circuit 20 via the data line.

  In the present embodiment, a correction path from the output of the total current from the drive control circuit 1 to the input of the corrected video signal to the drive control circuit 1 is provided, and output from the column control circuit through the correction path. It is characterized by correcting variations in the current signal.

  FIG. 2 is a schematic diagram showing the configuration of a preferred embodiment of the display device of the present invention. In FIG. 2, only members necessary for understanding the present embodiment are shown. In FIG. 2, 13 is a total current output circuit, 14 is a column shift register (HSR), 15 is a row shift register (VSR), 16 is an operational amplifier, 17 is a comparator, 18 is a DAC, 19 is a column control circuit, and 21 is data. Line, 22 scanning line, 23 logic circuit, 24 DAC, 25 image display unit, 27 total current output terminal (Iout), 28 detection resistor (Rm), 29 comparison circuit, 30 display panel, Reference numeral 31 denotes an external control circuit, and the same members as those in FIG.

  The display device of this embodiment includes a display panel 30 and a drive circuit. The drive circuit is a drive control circuit 1 on the display panel 30, an external control circuit 31 outside the display panel 30, and an external control circuit 31 and a display. Necessary circuits such as a total current detection circuit 2 and a part of the column current measurement circuit 3 in the figure are provided between the panels 30.

  In the display panel 30, a drive control circuit 1 and an image display unit 25 driven by the drive control circuit 1 are arranged. The image display unit 25 of the present embodiment moves the pixel circuit 20 including active elements in the row direction. A set of three R, G, and B displays is the minimum display unit, and the display unit column includes N columns and M rows. Therefore, the number of pixel columns is (N × 3), and M × N × 3 pixel circuits 20 are arranged in a matrix. The pixel circuits 20 in each row are commonly connected to a scanning line 22, and each scanning line 22 is connected to a row shift register 15 constituting the scanning circuit. The pixel circuits 20 in each column are commonly connected to the data line 21, and each data line 21 is connected to the column control circuit 19 via the total current output circuit 13. In this embodiment, an EL element is used as the display element, and the pixel circuit 20 includes the EL element.

  In the display device shown in FIG. 2, when the column scanning clock KC and the column scanning start signal SPC are input to the first column shift register 14, a transition occurs every cycle or half cycle of the column scanning clock KC. A sampling signal is output from each shift register 14 and input to the corresponding column control circuit 19. A column control signal SC is input to the column control circuit 19 via the logic circuit 23. In each column control circuit 19, the video signal Video for a predetermined period is sampled by the sampling signal and the column control signal SC, and a corresponding current signal is output to the data line 21.

  When the row scanning clock KR and the row scanning start signal SPR are input to the first stage of the shift register 15, a scanning signal generated by transitioning every one cycle or half cycle of the row scanning clock KR passes through the scanning line 22. Are sequentially input to the pixel circuits 20 in each row.

  In the present invention, the column control circuit 19 includes a current signal generation circuit, and FIG. 3 shows an analog column control circuit having a simple configuration as a circuit configuration example of the column control circuit 19. In the figure, reference numeral 35 denotes a sampling hold circuit. Reference numeral 36 denotes a current signal generation circuit, which is a voltage-current conversion circuit that receives a voltage signal and outputs a signal (current signal) having a current value corresponding to the voltage value. SPa and SPb are sampling signals output from the shift register 14, CC1, CC2 and CC3 are column control signals SC output from the logic circuit 23, VB is a reference voltage bias signal, and REF is correlated with the video signal Video. This is a reference signal input.

  The video signal Video input to the sample hold circuit 35 in FIG. 3 is an image voltage signal of the corresponding color. Sampling signals SPa and SPb output from the column control circuit 19 are input to the sample and hold circuit 35. Further, the column control signals CC1 to CC3 are also input to the sample and hold circuit 35. The voltage signal v (data), the reference voltage bias signal VB, the column control signal CC3, and the reference signal REF output from the sample hold circuit 35 are input to the voltage-current conversion circuit 36, and the current signal i (data) is output. .

  The operation of the circuit of FIG. 3 will be described with reference to the time chart of FIG.

  In the period T1 which is a row cycle (horizontal scanning period), the column control signal CC1 becomes “L” (CC2 is “H”), the sampling signal SPa is output (SPb is not output), and the SPa of the corresponding column is output. In the generation period t1, the voltage signal v (data) is sampled and held in the sample hold circuit 35 by the difference voltage d1 between the video signal Video and the reference signal REF.

  Next, when the column control signal CC1 becomes “H” (CC2 is “L”) in the period T2, the voltage signal v (data) sampled and held in the period T1 is input to the current signal generation circuit 36, and the current signal It is converted to i (data) and output as i (m). In addition, the sampling signal SPb is output in the period T2, and the voltage signal v (data) is sampled and held by the difference voltage d2 between the video signal Video and the reference signal REF in the generation period t2 of the SPb in the corresponding column.

  Next, in the period T3, the column control signal CC1 becomes “L” again (CC2 is “H”), and v (data) sampled and held in the period T2 is input to the current signal generation circuit 36 and converted i ( data) is output.

  FIG. 5 shows another circuit configuration example of the column control circuit 19. In the figure, M1 to M4, M6 to M10 and M12 are n-type TFTs, M5 and M12 are p-type TFTs, C1 to C4 are capacitors, SPa and SPb are sampling signals, Vcc is a power supply, and P1 to P6 are column control signals. is there. Hereinafter, the source, drain, and gate of the transistor are referred to as / S, / D, and / G, respectively.

  In the circuit of FIG. 5, the video signal Video is input to M1 / S and M7 / S, and the sampling signals SPa and SPb are input to M1 / G and M7 / G, respectively. M1 / D is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the other end of the capacitor C2 whose one end is grounded, and M3 / G, and M3 / S is grounded. M3 / D and M3 / G are connected to M2 / D and M2 / S, and P1 is input to M2 / G. M3 / D is connected to M4 / S, M4 / D is connected to M5 / D, M5 / S is connected to Vcc, and M5 / D and M5 / G are short-circuited. P2 is input to M4 / G. Further, M6 / S is connected to M3 / D, M6 / D is connected to the current signal i (data) terminal, and P3 is input to M6 / G.

  On the other hand, M7 / D is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the other end of C4 whose one end is grounded and M9 / G, and M9 / S is grounded. M9 / D and M9 / G are connected to M8 / D and M8 / S, and P4 is input to M8 / G. M9 / D is connected to M10 / S, M10 / D is connected to M11 / D, M11 / S is connected to Vcc, and M11 / D and M11 / G are short-circuited. P5 is input to M10 / G. Further, M9 / D is connected to M12 / S, M12 / D is connected to a current signal i (data) terminal, and P6 is input to M12 / G. The gate size (width: W, length: L) and capacitance of each transistor are M1 = M7, M2 = M8, M3 = M9, M4 = M10, M5 = M11, M6 = M12, C1 = C3, C2 = C4 relationship.

  FIG. 6 shows a timing chart of the operation of the circuit of FIG. In the figure, M3 / G and M9 / G indicate gate voltages of M3 and M9, respectively. FIG. 6 shows the operation related to the video signals for two rows.

Just before time t1, SPa = L, SPb = L,
P1 = L, P2 = L, P3 = H, P4 = L, P5 = H, P6 = L,
It is. Therefore, each transistor
M1: off, M2: off, M4: off, M6: on,
M7: off, M8: off, M10: on, M12: off. At this time, M3 and M9 are driven by the holding voltages Va1 and Vb1 charged in the capacities associated with the respective gates, and the M3 / D current Ia1 is output as a current signal i (data). The M9 / D current is supplied to M11 / D and M11 / G and becomes a constant value.

Time t1
SPa = H, P2 = H, P3 = L, P5 = L, and P6 = H, and the video signal Video is the blanking signal VBL in the blanking period. Therefore, each transistor
M1: on, M2: off, M4: on, M6: off,
M7: off, M8: off, M10: off, M12: on,
It becomes. At this time, the M9 / D current Ib1 driven by the Mb / G voltage Vb1 is output as a current signal i (data) instead of the M3 / D current Ia1. Since the current signal i (data) passes through the column length of the image display unit 25 and is connected to the EL elements corresponding to a large number of pixel circuits 20 in each column, a large parasitic capacitance must be driven. Transition Ia1 → Ib1 takes time. Prior to time t2, P1 = H, M2: is turned on, and M3 / G is charged by M5 in a short time from this time to time t2.

Time t2
Since P2 = L and M4 is turned off, the charging operation of M3 / G by M5 stops, and M3 / G performs a self-discharge operation so as to approach the threshold voltage Vth of itself.

Time t3
SPa = L and M1 is turned off. Prior to time t4, P1 = L and M2 = off, and at this point, the self-discharge operation of M3 ends. During this period from time t4 to time t4, both M2 and M4 are turned off, and the M3 / D current rapidly changes to the L level. Therefore, M3 / G has a slight voltage as shown in FIG. Causes a descent.

Time t4
Since P2 = H and M4: is turned on, the M3 / D current rises again, and M3 / G rises again to almost return to the original state (Vrsa). Since M3 / G is near the threshold voltage Vth of itself at this time, M3 / D is almost zero.

~ Time t7
During the period from time t4 to t7, the sampling signal SPa corresponding to each column is generated. SPb is not generated. At time t5 to t6, the M3 / G voltage generated near the threshold voltage Vth after the sampling signal of the corresponding pixel column is generated and the blanking level (VBL) as a reference at this time The transition voltage ΔV1 is changed according to the signal level d1. ΔV1 is schematically represented by the following equation.
ΔV1 = d1 × C1 / (C1 + C2 + C (M3))

  C (M3) indicates an input capacity of M3 / G.

  When the corresponding SPa is changed to L, M1: is turned off, and the voltage M3 / G is again held by changing to Va2 which is slightly dropped due to the parasitic capacitance operation of M1.

Time t7
SPb = H, P2 = L, P3 = H, P5 = H, P6 = L, and the video signal Video is the blanking signal VBL in the blanking period. Therefore, each transistor
M1: off, M2: off, M4: off, M6: on,
M7: ON, M8: OFF, M10: ON, M12: OFF,
It becomes. At this time, the M3 / D current Ia2 driven by Va2 of the M3 / G voltage is output as a current signal i (data) instead of the M9 / D current Ib1. Since the video current data i (data) passes through the column length of the image display unit 25 and is connected to the EL elements corresponding to the large number of pixel circuits 20 in each column, a large parasitic capacitance must be driven. The supply transition Ib1 → Ia2 takes time. Prior to time t8, P4 = H and M8: is turned on, and M9 / G is charged by M11 in a short period from this time to time t8.

Time t8
Since P5 = L and M10 is turned off, the charging operation of M9 / G by M11 stops, and M9 / G performs a self-discharge operation so as to approach the threshold voltage Vth of itself.

Time t9
SPb = L and M7 is turned off. Prior to time t10, P4 = L and M8 = off, and at this point, the self-discharge operation of M9 ends. During the period from this time to time t10, both M8 and M10 are turned off, and the M9 / D current rapidly changes to the L level. Therefore, M9 / G has a slight voltage as shown in FIG. Causes a descent.

Time t10
Since P5 = H and M10: is turned on, the M9 / D current rises again, and M9 / G rises again to almost return to the original state (Vrsb). At this time point, M9 / D is almost 0 because M9 / G is near its own threshold voltage Vth.

~ Time t13
During the period from time t10 to t13, the sampling signal SPb corresponding to each column is generated. SPa is not generated. From time t11 to t12, a sampling signal of the corresponding pixel column is generated, and the M9 / G voltage held near its threshold voltage Vth is an image based on the blanking level (VBL) at this time. The transition voltage ΔV2 is changed according to the signal level d2. ΔV2 is schematically represented by the following equation.
ΔV2 = d2 × C3 / (C3 + C4 + C (M9))

  C (M9) indicates an input capacity of M9 / G.

  When the corresponding SPb is changed to L, M7 is turned off, and the voltage M9 / G is again held by changing to Vb2 which is slightly lowered by the parasitic capacitance operation of M7. Further, immediately before time t13, the video signal Video returns to the blanking level VBL.

  Thereafter, the operation from t1 to t12 is repeated with t13 as a new t1.

  In the circuit of FIG. 5, the capacitors C2 and C4 may be realized only by the gate input capacitors (channel capacitors) of M3 and M9. In this case, the capacitors C2 and C4 may not be provided. In FIG. 6, the change timings of P1 and P2 may be equal to SPa at times t1 and t3. Further, the change timings of P4 and P5 may be equal to SPb at times t8 and t11. In FIG. 5, there may be no M3 / D and M9 / D bias circuits and M3 / G and M9 / G charging circuits composed of P2, M4, M5 and P5, M10, and M11.

  With the above circuit and operation, the video signal Video can be converted into a line-sequential current signal i (data).

  The circuit configuration example of the column control circuit 19 described above is an analog system. However, when a digital circuit is used, the video signal Video becomes a plurality of data signals, and the sampling hold circuit holds each data signal. And outputs a plurality of voltage signals v (data). The voltage-current converter circuit is a current output type DA converter circuit using a weight current corresponding to each voltage signal that determines gm characteristics.

  Next, the pixel circuit 20 of the display device of the present invention will be described. In the present invention, the pixel circuit 20 includes an active element and is driven by a current setting method. Preferably, each pixel circuit 20 includes an EL element. As the active element, one or more TFTs are used.

  FIG. 7 shows a circuit configuration example of the pixel circuit 20. In the figure, 71 is an EL element, M1, M2 and M4 are p-type TFTs, M3 is an n-type TFT, C1 is a capacitor, RC1 and RC2 are scanning signals, and Vcc is a power supply.

  In the pixel circuit of FIG. 7, the data line 21 in the corresponding column is connected to M3 / S, and one of the scanning signal lines 22 in the corresponding row is connected to M3 / G, and the scanning signal RC1 is input. M3 / D is also connected to M2 / D and M4 / S, and one of the scanning signal lines 22 in the corresponding row is also connected to M4 / G, and the scanning signal RC1 is input. M1 / S is connected to the power supply Vcc, M1 / G is connected to the other end of the capacitor C1 whose one end is connected to the power supply Vcc and M2 / S, and M2 / G is connected to the other of the scanning signals 22 in the corresponding row. A scanning signal RC2 is input. M4 / D is connected to the current injection terminal of the EL element 71, and the other end of the EL element 71 is grounded (GND).

  The operation of the pixel circuit of FIG. 7 will be described with reference to the time chart of FIG.

  The current signal i (data) input to the pixel circuit of the corresponding column is updated and input to the data line 21 of the corresponding column for each row cycle.

  At time t0, the scanning signal RC1 of the corresponding row becomes “H” and the scanning signal RC2 becomes “L”, and i (data) at that time corresponds to the current driving capability of M1. The M1 / G voltage is generated and the capacitor C1 is charged. At this time, M4 is off, and no current is injected into the EL element 71.

  At time t1, the sum signal RC2 changes to “H”, M2 turns off and the M1 / G voltage is held, and at time t2, RC1 changes to “L” and M4 turns on, and the holding current of M1 Is injected into the EL element 71, the pixel circuit is disconnected from the current signal i (data), and a current proportional to the set current signal i (m) is supplied to the corresponding EL element 71 until M3 is turned on next time. Supply continuously.

  In the display device of the present invention, a total current output circuit 13 is disposed between the column control circuit 19 and the pixel circuit 20 in order to correct the variation in the current signal output from the column control circuit 19, and the output circuit Then, a correction path is formed and correction is performed.

  FIG. 9 shows a circuit configuration example of the total current output circuit 13 of the present embodiment. In the figure, 83 is a current signal output line to which the output of the current signal generation circuit 36 is commonly connected, 81 is a switch unit for controlling the connection relationship between the output of the current signal generation circuit 36 and the current signal output line 83, and 82 is Blocking units which are switch units for controlling the connection relationship between the current signal generating circuit 36 and the pixel side, 91a to 9Nc are data lines, M11 to M3N and M41 to M6N are transistors, Iout is total power, and CCx and CCy are total power This is a detection control signal.

  The total current output circuit 13 according to the present invention includes a switch unit 81 that outputs a current signal in common from a plurality of data lines 21 and a blocking unit 82 that blocks current flowing to the pixel circuit 20. In the present embodiment, a mode in which current signals are output from all the data lines 21 is shown.

  The switch unit 81 is composed of transistor groups M11 to M3N that connect the data lines 91a to 9Nc (corresponding to the data line 21 in FIG. 1) and the output line 83, and can be freely controlled to open and close. Is composed of blocking transistor groups M41 to M6N that are connected to each data line between the switch unit 81 and the pixel circuit 20 and are switches that can be controlled to be opened and closed. The data lines 91a to 9Nc connecting the column control circuit 19 and the pixel circuit 20 of the corresponding column are connected to M11 / S to M6N / S, and M11 / D to M3N / D are all connected to the output line 83 in common. The total current Iout is output from the output line 83. On the other hand, M41 / D to M6N / D are connected to the data lines 91a to 9Nc in the corresponding columns, respectively. M11 / G to M3N / G are all connected in common and the total current detection control signal CCx from the logic circuit 23 is input, and M41 / G to M6N / G are all connected in common and the total current from the logic circuit 23. A detection control signal CCy is input. Note that all transistors perform a switching operation, and the p-type and n-type limitations and configurations are not limited as long as they are appropriately controlled.

  The operation of the total current output circuit 13 of FIG. 9 will be described with reference to the time chart of FIG. The column control circuit 19 shown in FIG. 1 uses the circuit shown in FIG. 3 as an example, and all the circuits are in a current output state by the column control signal CC3.

  To correct the video signal by outputting the total current from the total current output circuit 13, a correction period is provided before the normal operation period, and M11 to M3N of the switch unit 81 of the total current output circuit 13 in the correction period. Are all turned on by CCx, and M41 to M6N of the blocking unit 82 are all turned off by CCy. As a result, the current signal output from the column control circuit 19 does not flow to the pixel circuit 20, but is all output from the output line 83.

  In the correction period, SPa, SPb, CC1, and CC2 of the column control circuit 19 are the same as the timing of FIG. 4 at the time of normal operation, but the video signal Video is applied to a predetermined data line in one horizontal scanning period. The first current signal is output only from the current signal generation circuit 36 that outputs the current signal, and the second current signal is output from the current signal generation circuit 36 that outputs the current signal to all other data lines. Set to be. In each horizontal scanning period, the current signal generating circuit 36 that outputs the first current signal is set to be sequentially changed. More specifically, for example, only one current signal generation circuit 36 outputs a first current signal having a predetermined level, and the other current signal generation circuit 36 has a second level lower than that of the first current signal. A video signal that outputs the current signal is input to each current signal generation circuit 36. For example, when the current signal generation circuit 36 (column control circuit 19) is a digital signal input method and the second current signal is set to 0, the current signal generation circuit 36 to output the second current signal. Digital data to be input to can be set to zero. In the video signal set as described above, the first current signal is sequentially input to all the data lines in the horizontal scanning period corresponding to the number of pixel columns. This control is performed by the control circuit 200 of FIG. The correction is performed during a correction period set in advance in the control circuit. A configuration in which correction is performed by designating a correction period to the control circuit from the outside can also be employed. The second current signal may have a significant current value, but here, the current value of the second current signal is set to be substantially zero. This facilitates later evaluation processing.

  In the time chart of FIG. 10, the video signal Video is set to a waveform such that a high level signal is sampled only for one data line in each horizontal scanning period T0 to T7. Therefore, all the column control circuits 19 sample the video signal Video by the same operation as usual, and output the current signal i (data). The i (data) is summed up by all the data lines from the sum current output circuit 13. The total current Iout output from the output line 83 as the current Iout and output in each row scanning period is mainly composed of the output current from the data line to which the first current signal is applied.

  Note that the number of data lines for inputting the first current signal in the row scanning period is not limited to one. Data lines for the minimum display unit may be used, and a combination of data lines for inputting the first current signal at the same time in one horizontal scanning period is appropriately selected, and the time required for the correction process can be reduced by combining a plurality of appropriate data lines. It is also possible to shorten the TFT variation, and to extract visually noticeable TFT variations. Further, the data lines included in the combination of the data lines may overlap in different scanning periods, and the order thereof is not limited.

  In the present embodiment, the total current detection circuit 2, the column current measurement circuit 3, the column current storage circuit 4, the reference column current detection circuit 5, the correction gain determination circuit 6, the correction coefficient calculation circuit 7, and the correction coefficient storage circuit 8 are current signals. A correction value output circuit is configured that evaluates the output of a specific current signal generation circuit 36 from the current value output via the output line 83 and outputs a correction value according to the evaluation result. Specifically, the output of the current signal generation circuit is evaluated by the total current detection circuit 2 and the column current measurement circuit 3, the correction value corresponding to the evaluation result is calculated by the correction coefficient calculation circuit 7, and the obtained correction value Is stored in a correction coefficient storage circuit 8 which is a correction value storage circuit, and a correction value is output from the correction coefficient storage circuit 8.

  The step of evaluating the output of the current signal generation circuit 36 is performed as follows.

  The total current Iout output from the total current output circuit 13 is output from the output terminal 27 in FIG. 2 and input to the total current detection circuit 2. In the total current detection circuit 2, one end of the detection resistor 28 is connected to the output terminal 27, and the other end of the detection resistor 28 is connected to the power source Vcc. The output terminal 27 is also connected to the positive side of the operational amplifier 16, and the negative side and the output side of the operational amplifier 16 are short-circuited. The output terminal of the operational amplifier 16 is connected to the negative side of the comparator 17 of the column current measurement circuit 3 in the next stage, and the output of the DAC 18 is input to the positive side of the comparator 17.

  The total current detected within the correction period is a period when the TEST signal input to the total current output circuit 13 is “H”, for example, currents corresponding to Vgs of M3 and M9 in the column control circuit of FIG. And the total current ΣI flows from the power source through the detection resistor 28, so that the potential of the output terminal 27 becomes Vout = Vcc−ΣI × Rm (Rm is the resistance value of the detection resistor 28). Note that the influence of the input impedance of the operational amplifier 16 is ignored. The potential of Vout is buffered by the configuration of the operational amplifier 16 and is directly input to the negative side of the comparator 17.

  Next, in FIG. 2, the column current measurement circuit 3 shows a successive approximation type circuit including the comparator 17, the DAC 18, and the comparison circuit 29. However, since this circuit is general and widely used, it is simplified. An explanation will be given.

  The output of the comparator 17 is a two-pole digital output of “H” and “L”, and the comparison circuit 29 compares Vout with the output value Vdac of the DAC 18 for determination. For example, when the DAC 18 is increased by the bit resolution from the lowest potential, the output of the comparator 17 is “L” when Vout> Vdac in the configuration of FIG. 2, but Vout <Vdac, and the output of the comparator 17 is “ When inverted to “H”, the digital data of the DAC 18 is stored in the column current storage circuit 4. In FIG. 2, Vout is input to the negative side of the comparator 17, but the polarity may be changed from that of the DAC 18 side. However, the output of the comparator 17 is also inverted. The value output from the comparison circuit 29 is a value obtained by evaluating the output of the current signal generation circuit, and this evaluation value corresponds to the current value output from the current signal generation circuit in a one-to-one relationship.

  The reference column current detection circuit 5 selects and stores reference current signal data from the current signal data of each data line stored in the column current storage circuit 4. There is no particular limitation on the selection criteria for the current signal data used as a reference.

  Using the reference current signal data stored in the reference column current detection circuit 5 and the current signal data of each data line stored in the column current storage circuit 4, the correction coefficient calculation circuit 7 performs an arithmetic process to each data line. A correction coefficient corresponding to is calculated. Specifically, the correction coefficient calculation circuit 7 is provided with a gain calculation circuit, the reference current is divided by the current signal data of the data line to be corrected, the division result is square rooted, and the square root calculation result is the coefficient k. And the gain calculation result obtained is used as a correction coefficient. It is calculated by the following formula (1).

Hsample: correction coefficient for each data line Isample: current signal data for each data line Iref: reference current signal data k: coefficient

  In the above equation (1), when performing the route calculation by logic calculation, an approximation by the binary theorem in which the coefficients are divided according to the division value x = Iref / Isample in order to perform the calculation so as not to cause the most error. Perform by calculation. The calculation formula is shown in the following formula (2).

In the above equation (2), a and a ^1/2 are case division coefficients, and several patterns are prepared in advance. In the above formula (2), the closer the value of (ax) / a is to zero, the smaller the error in the calculation result.

FIG. 11 shows the configuration of the correction coefficient calculation circuit 7 of the present embodiment. In the figure, 10 is a division circuit, 11 is a case-dependent coefficient determination circuit, and 12 is an arithmetic operation circuit. X = Iref / Isample is calculated from “Isample” and “Iref” input to the dividing circuit 10 in FIG. 11, and the value of x is input to the case-dependent coefficient determining circuit 11. The case division coefficient determination circuit 11 determines case division coefficients a and a ^1/2 according to the value of x, and the arithmetic operation circuit 12 performs the calculation of the rightmost side of the above equation (2). Since the multiplication and division logic can be composed of general shifters and adders, the description of the operation is omitted here.

In the calculation of the above formula (2), the actual calculation result is shown in FIG. FIG. 12 shows the ratio between the result of calculating the route by the computer and the result using the binomial theorem. The closer to 1, the less error. The values to be calculated were set from 0.5 to 1.5, and eight combinations of coefficients a and a ^1/2 were prepared. The combinations are shown below. In FIG. 12, the curves shown in [1] to [8] are each subjected to an approximate calculation using the value a shown in the following table. The relationship between the ratio of the calculation result) and the result of the approximation calculation (vertical axis) and the value of x (horizontal axis) is shown.

  By sequentially selecting a coefficient closer to 1 in the value of x in the curve graph of each value of a, it is possible to obtain a calculation result that is not significantly different from the result by the computer.

  Thereby, based on the calculation result obtained by Expression (2), the result calculated by substituting for the route of Expression (1) and multiplying by the coefficient k is the correction coefficient Hsample, and the correction coefficient is stored in the correction coefficient memory. It is stored in the circuit 8.

  In the video signal correction circuit 9, the correction coefficient of the corresponding column stored in the correction coefficient storage circuit 9 is read in accordance with the video signal Video of the column to be sampled, and is corrected by multiplication. The multiplication result is output in accordance with the digital / analog system of the column control circuit 19. That is, if it is a digital system, it is output to the drive control circuit 1 as a digital signal, and if it is an analog signal, it is converted to an analog voltage by a DAC and output to the drive control circuit 1 in the same manner.

  The correction gain is determined by the value of the coefficient k in Equation (1). That is, when k = 1, the value obtained by the division and the route calculation becomes the correction coefficient as it is.

  When k <1, since the gain of the correction coefficient is smaller than 1, the correction is weakened. Therefore, the current signal unevenness cannot be completely suppressed by one correction. Therefore, the current signal unevenness can be more reliably suppressed by performing the above correction process a plurality of times and sequentially rewriting the correction coefficient stored in the correction coefficient storage circuit 8.

  When k> 1, the correction is strengthened contrary to the case of k <1. Therefore, the current signal unevenness may be reversed by one correction. Therefore, in this case as well, the current signal unevenness can be more reliably suppressed by performing the above correction process a plurality of times and sequentially rewriting the correction coefficient stored in the correction coefficient storage circuit 8.

  Note that if the gain is increased too much, there is a possibility that it will not converge, so the range of 1 <k <2 is selected.

  The gain may be selected and corrected in the device conditions and operation when the product is mounted. For example, at the time of product activation, it is possible to perform correction with a gain of 1 before the display panel is turned on, and then perform correction several times with a gain less than 1 or 1 <k <2. The selection of the gain is performed by the correction gain determination circuit 6.

  The correction period for determining the correction value can be set at the time of product activation, for example. It can also be set to be done regularly. When a memory that requires power supply for the memory holding operation is used as the correction coefficient storage circuit 8 that is a circuit for storing the correction value, the memory is lost when the power is turned off. What is necessary is just to determine a value. Alternatively, by adopting a memory (for example, E2PROM) that does not lose its memory even when the power is turned off, it is possible to realize a configuration that does not require determining the correction value every time the power is turned on after the power is turned off.

(Embodiment 2)
In the above-described embodiment, a configuration has been described in which the correction value is obtained during a preset correction period and the correction value is updated. In this embodiment, the correction value determination process is performed only once, and the correction value determined thereby is used without being updated. Specifically, the correction value determination process described in the above embodiment is performed before product shipment, and the correction value obtained thereby is stored in the correction value output circuit. In this embodiment, since it is not necessary to update the correction value, it is not necessary to use a rewritable memory. In this embodiment, each of the plurality of current signal generation circuits is controlled to a current signal output state in which the output of the specific current signal generation circuit can be evaluated from the current value output through the current signal output line. The control circuit 200 that does not need to have a drive circuit or a display device.

(Embodiment 3)
In this embodiment, the step of evaluating the output of each current signal generation circuit described in the above embodiment is performed during the manufacturing process of the drive circuit or the display device or after the manufacturing process is completed, and defective product determination is performed. . Specifically, if the variation in the output of each current signal generation circuit is large, the subsequent manufacturing process and shipment are canceled.

  In each of the above embodiments, an EL display device using EL elements has been described as an example. However, the display device of the present invention is not limited to this, and each pixel is displayed by a current signal. Any device that can be controlled is preferably applied.

It is a block diagram which shows the structure concerning the correction | amendment path | route of the drive circuit of this invention. It is the schematic which shows the structure of preferable one Embodiment of the display apparatus of this invention. It is a figure which shows the circuit structural example of a column control circuit. 4 is a time chart of the column control circuit of FIG. 3. It is a figure which shows the other circuit structural example of a column control circuit. 4 is a time chart of the column control circuit of FIG. 3. It is a figure which shows the circuit structural example of a pixel. It is a time chart of the pixel circuit of FIG. It is a figure which shows the circuit structural example of a total electric power output circuit. 10 is a time chart of the total power output circuit of FIG. 9. It is a figure which shows the structural example of a correction coefficient calculating circuit. It is a figure which shows the calculation result in a correction coefficient calculating circuit. It is a figure which shows the pixel circuit of the conventional EL display apparatus. It is a figure which shows the structure of the display panel of the conventional EL display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drive control circuit 2 Sum total current detection circuit 3 Column current measurement circuit 4 Column current memory circuit 5 Reference column current detection circuit 6 Correction gain determination circuit 7 Correction coefficient calculation circuit 8 Correction coefficient memory circuit 9 Video signal correction circuit 10 Division circuit 11 Case Dividing coefficient determination circuit 12 Four arithmetic operation circuits 13 Total current output circuit 14 Column shift register 15 Row shift register 16 Operational amplifier 17 Comparator 18 DAC
19 column control circuit 20 pixel circuit 21 data line 22 scanning line 23 logic circuit 24 DAC
25 Image display unit 27 Total current output terminal 28 Detection resistor 29 Comparison circuit 30 Display panel 31 External control circuit 35 Sample hold circuit 36 Current signal generation circuit 71 EL element 81 Switch unit 82 Blocking unit 83 Output line 91a to 9Nc Data line 101 Sample Hold circuit 102 Error amplifier circuit 103 EL element 104 Current control circuit 105 Current detection circuit 106 Data driver 107 Arithmetic element 108 Storage means 109 Power supply 110 Current measurement element 111 Scan driver 200 Control circuit C1 to C4 Capacitance CC1, CC2, CC3 Column control signal CCx, CCy Total current detection control signal i (data) Current signal gm Voltage current conversion circuit Iout Total current KC Column scan clock KR Row scan clock M1 to M12, M11 to M6N TFT
P1-P6 Column control signal RC1, RC2 Scan signal SC Column control signal SH Sample hold circuit SPC Column scan start signal SPa, SPb Sampling signal SPR Row scan start signal TEST Test signal VB Reference voltage bias signal v (data) Voltage signal Video Video signal

Claims (4)

A pixel circuit having a thin film transistor for controlling light emission of an electroluminescence element and a capacitor provided at a gate of the thin film transistor, wherein a voltage corresponding to an input current signal is held in the capacitor, and the current In an active matrix display device in which a plurality of pixel circuits that emit light from the electroluminescence element based on a signal are arranged in a matrix,
A plurality of current signal generating circuits configured using thin film transistors, converting the input video signal voltage and generating the current signals to be input to each of the plurality of pixel circuits via data lines;
A signal output line to which outputs of the plurality of current signal generation circuits are connected in common;
A control circuit that controls each of the plurality of current signal generation circuits to a current output state in which an output of a specific current signal generation circuit can be evaluated from a current value output through the signal output line;
A correction circuit for detecting current signals output from the plurality of current signal generation circuits via a signal output line, and correcting a video signal voltage input to the current signal generation circuit according to a detection result; ,
Comprising
A blocking unit provided on the data line, for blocking connection between the current signal generating circuit and the plurality of pixel circuits;
A switch unit for connecting the current signal generation circuit and the signal output line;
Have
The plurality of current signal generation circuits and the plurality of pixel circuits in a period in which current signals output from the plurality of current signal generation circuits are detected via the signal output lines by the cutoff unit and the switch unit. And the plurality of current signal generating circuits are simultaneously connected to the signal output line.   The active matrix display device according to claim 1, wherein the electroluminescence element is an organic electroluminescence element.   The active matrix display device according to claim 1, wherein the corrected video signal voltage is supplied to the plurality of current signal generation circuits from a DAC provided in an external control circuit. The pixel circuit includes a thin film transistor capacitor connecting the gate and drain of the thin film transistor, a thin film transistor capacitor connecting the drain of the said data lines TFT, a thin film transistor motor for turning off the current flowing through the electroluminescence element The active matrix display device according to claim 1, further comprising:

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