JP4454675B2 - Method for constructing a metal nitride film on a wafer - Google Patents

Description

Detailed Description of the Invention

  The present invention is directed to the field of integrated circuit manufacturing.

Conventional technology

  In the manufacture of integrated circuits, a deposition process is used to deposit a thin layer of insulating or conductive material on the wafer. Deposition is performed by various known processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD or sputtering).

In a CVD process, a wafer is loaded into a chemical vapor deposition chamber. In a conventional CVD process, a reactive gas is supplied to the wafer surface where a thermally induced chemical reaction occurs and a thin film layer is formed on the surface of the wafer to be processed. CVD applications include depositing titanium-containing compounds, such as titanium nitride, on a wafer from a process gas containing a metallo-organic compound. One such metal organic compound is tetrakis (dialkylamido) titanium (Ti (NR ₂ ) ₄ ) having the following structural formula.

Here, although each R is a different thing, it is an alkyl group, for example, is a C1-C5 alkyl group. For example, tetrakis (dimethylamido) titanium (TDMAT) having the formula Ti (N (CH ₃ ) ₂ ) ₄ is commonly used.

  An inert gas, such as helium, argon, nitrogen, or hydrogen, entrains the compound in the chamber and provides energy. This energy can be generated by a heat source in the case of thermal CVD and by a radio frequency (RF) signal source in the case of plasma enhanced CVD. The energized gas phase compound reacts with the wafer surface to produce a thin layer of material on the wafer. When a TDMAT gas phase compound is used, a titanium nitride film is formed on the wafer surface.

  In a sputtering process, a wafer is placed in a physical vapor deposition (PVD) chamber and the chamber is filled with a gas such as argon. A plasma with positively charged ions is generated from this gas by generating an electric field in the chamber. The positively charged ions are accelerated and collide with a target installed in the chamber. Thereby, atoms of the target material are separated from the target and deposited on the wafer, and a layer of the target material is formed on the wafer surface.

  In conventional sputtering processes, target material impact by positively charged ions is enhanced by applying a negative bias to the target material. This is realized by giving a high frequency signal to the electrode supporting the target material.

  A separate RF signal may be inductively coupled to the chamber to generate positively charged ions in the high density plasma PVD chamber. The high density plasma PVD chamber may have another RF signal coupled to the wafer support to improve the attraction of the target material to the wafer.

  A diffusion barrier may be deposited on the integrated circuit using a deposition chamber such as a CVD chamber or a PVD chamber. The diffusion barrier prevents contact metal such as aluminum or copper from diffusing into the active region of a semiconductor device built on a silicon substrate. This prevents interdiffusion of contact metal into the substrate. Unlike the insulating layer of material, the diffusion barrier provides a conductive path through which current can flow. For example, a diffusion barrier can be used to cover the top of the silicon substrate at the base of the contact hole.

  If the temperature of the integrated circuit exceeds 450 ° C., severe interdiffusion may begin to occur between the contact metal and the silicon substrate. If interdiffusion is left to occur, the contact metal will penetrate into the silicon substrate. As a result, an open contact occurs in the integrated circuit, and the integrated circuit becomes defective.

  In the manufacture of integrated circuits, aluminum and copper metallization processes are often used that operate at high temperatures in excess of 450 ° C. Therefore, it is desirable that the diffusion barrier has a strong ability to prevent diffusion of contact metals such as aluminum and copper.

  Conventionally, in order to meet this demand, the diffusion barrier has been made thicker. However, in the manufacture of integrated circuits, geometric relationships have become smaller. By reducing the geometric relationship, the size of the contact hole is also reduced, which makes it desirable for the nucleic acid barrier to be thinner and more conformal.

  FIG. 1 illustrates a diffusion barrier 100 between a conductive region 105 of a silicon substrate 101 and a contact plug 102. A contact hole 103 is formed in an insulating layer 104 made of a material such as silicon dioxide on the substrate 101. In order to ideally form the diffusion barrier 100, it is made thin and substantially conformal to the contour lines on the surface of the contact hole 103.

  When the diffusion barrier 100 is thin and the conformality is high, the contact metal 102 can form an ohmic contact having sufficient conductivity with the conductive region 105 of the silicon substrate. If the diffusion barrier 100 is too thick or does not form well as shown in FIG. 2, the contact metal 102 will not be able to form an ohmic contact with sufficient conductivity with the substrate region 105.

  In FIG. 2, the diffusion barrier 100 that is not well formed severely narrows the opening of the contact hole 103. The narrow opening makes it impossible to reach the base of the contact hole 103 when the contact metal 102 is formed. As a result, a void 106 is generated.

  In order to ensure a good ohmic contact between the contact metal 102 and the substrate region 105, it is desirable to minimize the resistance of the diffusion barrier 100. Typically, a resistivity value of 1000 μΩ-cm or less is allowed. One material that has been successfully used as a diffusion barrier is titanium nitride (TiN).

  However, some deposition processes, such as TDMAT, provide an unstable barrier layer with high resistivity. In the case of TDMAT, one of the causes is that a large part of the deposited barrier material is composed of carbon (hydrocarbon, carbide, etc.). Furthermore, titanium is a chemically reactive metal, but does not completely react with the film. It is desirable to reduce and stabilize the resistivity by treating such a layer of barrier material after deposition.

  In the manufacture of integrated circuits, it is desirable to perform successive manufacturing process steps ("in situ") in the same chamber, such as deposition and post-deposition processing. The in-situ operation reduces the amount of contamination that exposes the wafer by reducing the number of times that the wafer needs to be transferred between separate manufacturing equipment. In-situ operation also reduces the number of expensive manufacturing equipment that a semiconductor manufacturer needs to purchase and maintain.

  Therefore, it is desirable to construct a thin, highly conformal diffusion barrier with enhanced ability to inhibit the diffusion of contact metals such as aluminum and copper. It is further desirable that the diffusion barrier has a resistance that provides a good path for current conduction. It is also desirable to construct this diffusion barrier in situ.

  The apparatus and method according to the present invention provide for performing in situ construction of highly conformal diffusion barriers with improved resistivity. By implementing the embodiments of the present invention, the ability of the diffusion barrier to prevent the diffusion of contact metals such as aluminum and copper can be improved. Even if the diffusion barrier is improved in this way, its thickness and resistivity do not increase beyond the allowable limit.

  A semiconductor processing apparatus capable of implementing embodiments of the present invention may include a processing chamber, a showerhead, a wafer support, and RF signal means. In one embodiment of the present invention, the semiconductor wafer processing apparatus is capable of performing chemical vapor deposition.

  By providing a shower head, gas is supplied into the processing chamber. A wafer support is provided for supporting the wafer within the processing chamber. RF signal means may be coupled to both the showerhead and the wafer support to provide a first RF signal to the showerhead and a second RF signal to the wafer support. Alternatively, the RF signal means may be coupled only to the wafer support to provide an RF signal to the wafer support.

  The wafer support is supported in the processing chamber by a support arm. The support arm couples the RF signal means to the wafer support. Further, in order to measure the temperature of the wafer support, the support arm couples a thermocouple housed in the wafer support to the temperature measurement device. The thermocouple is electrically isolated from the RF signal means.

When practicing aspects of the present invention, a film may be built on the wafer. First, a layer of material is deposited on the wafer. This material may be a diatomic metal nitride (M _x N _y ) or a triatomic metal nitride silicide (M _x Si _y N _z ), where M is titanium Ti, zirconium Zr, hafnium Hf, Tantalum Ta, molybdenum Mo, tungsten W, or other metals may be used.) This material deposition operation can be accomplished by various means such as chemical vapor deposition or physical vapor deposition.

  After the material is deposited, the material is plasma annealed to reduce the resistivity of the layer of material. The plasma anneal may include exposing the material to an environment with ions and applying an electrical bias to the layer of material to cause the ions to bombard the material. Good.

  Alternatively, the annealing may consist of a number of annealing steps performed sequentially using different gases. For example, a mixed gas of nitrogen and hydrogen may be used in the first annealing step, and a mixed gas of nitrogen and helium may be used in the next annealing step. In this later annealing step, hydrogen molecules are removed from the material to reduce the resistivity.

  Once the annealing is complete, the layer of material may be oxidized. This oxidation increases the ability of this material to inhibit the diffusion of contact metals such as aluminum. Alternatively, exposing the annealed material layer to silane gas increases the ability of the material to inhibit the diffusion of contact metals such as copper.

  In accordance with the present invention, deposition, annealing and oxidation or silane exposure can all be performed in one chamber without removing the wafer from the chamber before all three operations are complete. Thus, deposition, annealing and oxidation or silane exposure to the material can be performed in situ.

BEST MODE FOR CARRYING OUT THE INVENTION

(A. Chamber for wafer processing)
1. Overview A conventional CVD chamber 10 is shown in combination with FIGS. 3 (a) and 3 (b). The CVD chamber 10 has a processing chamber 12 in which a wafer 14 is supported by a wafer support 16 such as a susceptor. Wafer support 16 is supported by a circular disk 18, which is typically made of a material such as alumina ceramic. The disk 18 rests on the free end 20 of the support arm 22. The support arm 22 forms a cantilever with its fixed end 24 attached to the stem 26. The stem 26 can be vertically displaced under the movement of the displacement mechanism 28. The displacement mechanism 28 is operated to move the support arm 20 vertically within the processing chamber 12.

  During processing of the wafer 14, gas is injected into the processing chamber 12 via the showerhead 36. The shower head 36 is mounted directly on the wafer 14 in a typical embodiment.

  In operation, the interior of the processing chamber 12 is heated by a set of infrared lamps 30 installed below the CVD chamber 10. The lamp 30 illuminates the interior of the processing chamber via a quartz window 32, which is positioned between the lamp 30 and the interior of the processing chamber 12. The lamp 30 serves to heat both the processing chamber 12 and the wafer support 16. As a result, the wafer 14 on the wafer support 16 is also heated.

  In order to increase the heating of the wafer support 16, a large number of holes 34 are formed through the ceramic support plate 18 as shown in FIG. The typical arrangement of holes 34 shown in FIG. 3 (b) makes it clear why this plate 18 is often referred to as a “Swiss cheese” plate.

  Thermal CVD wafer processing is very sensitive to wafer temperature. To ensure that the wafer is maintained at an appropriate temperature, the wafer temperature is measured by thermocouple 38. The thermocouple 38 is supported by the free end 20 of the support arm 22 and is installed in the main body of the wafer support 16. A thermocouple 38 is connected to a temperature measuring device 40 installed outside the processing chamber 12 by a conductive cable 42. The cable 42 typically runs along a hole formed within the center of the support arm 22.

  FIG. 4 illustrates a multi-chamber vacuum system suitable for performing the manufacture of wafers containing integrated circuits. Chamber A is for pre-cleaning a substrate on which an integrated circuit is to be formed. After pre-cleaning, the substrate is transferred to the CVD chamber B so that a film can be deposited on the substrate. Then, the substrate is transferred to the post-deposition processing chamber C in order to improve the quality of the deposited film.

  If it is desirable to “stuff” the membrane with a material that improves membrane operation, such as a diffusion barrier, the substrate may be transferred to chamber D where this “stuffing” can be performed. . For example, the film may be a layer of titanium nitride material, which is filled with oxygen, reducing the diffusibility of the film to aluminum. Filling the titanium nitride barrier layer with oxygen is disclosed in US Pat. No. 5,378,660, Ngan et al., Entitled “Barrier Layers and Aluminum Contacts”.

  Any of the systems described above can be used to implement aspects of the present invention. However, none of these systems provide the ability to perform deposition in a single chamber by performing material deposition on the wafer and post-deposition processing on the material to form a film. This post-deposition treatment may include annealing, oxidation, exposure to silicon, or a combination thereof.

  2. Chamber for In-Situ Operation FIG. 5 illustrates a semiconductor wafer processing chamber 110A according to the present invention. The wafer processing chamber 110A provides a series of deposition steps and post-deposition processing steps performed in-situ on the semiconductor wafer 114. In accordance with the present invention, the chamber 110A shown in FIG. 5 may be a chemical vapor deposition chamber as described in detail in US patent application Ser. Nos. 08 / 567,461 and 08 / 677,185.

  Wafer processing chamber 110A, in accordance with the present invention, eliminates the need to use multiple chambers for material deposition and processing. For example, a film may be formed on the wafer using the wafer processing chamber 110A by depositing material on the wafer and annealing the deposited material to stabilize and reduce resistance. As a result, the wafer is not exposed to damaging impurities outside the chamber 110A during film formation.

  As shown in FIG. 5, the semiconductor wafer processing chamber 110A has a processing chamber connected to ground. Within the processing chamber 112, the semiconductor wafer 114 may be supported on a wafer support 116, which is the same as the wafer support 16 as shown in FIGS. 3 (a) and 3 (b). There may be. The wafer support 116 may be a susceptor, pedestal, resistance heater, or other means suitable for supporting the wafer 114.

  In FIG. 5, the wafer support 116 is a susceptor, which is a type of wafer support often used when irradiating the wafer support 116 with a lamp. This susceptor is made of anodized aluminum and is a conventional alumina ceramic support plate 118 similar to the support plate 18 of FIG.

  The support plate 118, wafer support 116, and wafer 114 are supported together on the free end 120 of the cantilever alumina support arm 122. The fixed end 124 of the support arm 122 rests on a stem 126 that can move substantially vertically, which is electrically isolated from the processing chamber by an isolator 160. This vertically movable stem 126 can be displaced vertically under the movement of the displacement mechanism 128.

  The processing chamber 112 and its contents are heated by a conventional lamp 130 that irradiates the wafer support 116 through a conventional quartz window 132. The semiconductor wafer processing chamber 110A further includes a temperature measuring device 140. The temperature measuring device is connected to the wafer support 116 and senses the temperature of the wafer support 116. The pressure control unit 157 includes all of a vacuum pump, a pressure gauge, and a pressure regulating valve. The pressure control unit 157 adjusts the pressure in the processing chamber 112 and discharges both carrier gas and reaction by-products from the processing chamber 112.

  A showerhead 136 is disposed above the wafer support 116 in the processing chamber 112 and is electrically isolated from the chamber by an isolator 159. A process gas is supplied from the gas panel 52 to the shower head 136. The gas panel 52 is controlled by a gas panel controller 50 in the form of a computer.

  The semiconductor wafer processing chamber 110A has an RF source 142 for post-deposition annealing. The RF source 142 applies RF power to the showerhead 136 that functions as the first electrode and the wafer support 116 that functions as the second electrode. The RF source 142 has the ability to provide a signal having a frequency less than 1 MHz, and preferably has the ability to provide a signal having a frequency of 350 kHz. Providing the RF signal to the two electrodes 136 and 116 overcomes the difficulties that do not exist when providing RF signals to the two electrodes in other conventional semiconductor wafer processing chambers, such as PVD chambers.

  In the embodiment of the present invention, it is possible to prevent an excessive negative bias from being applied to the shower head 136. If an excessive negative bias is applied to the shower head 136, ion collision of the shower head 136 increases, and as a result, contaminant particles are generated.

  In conventional PVD chambers, it is desirable that the amount of ion bombardment of the target electrode be large. In conventional PVD chambers, a target electrode supports a target of the material to be deposited. Since the target electrode is given a large negative bias, the ions immediately collide with the target material and deposit the target material.

  Further, in a conventional sputtering process, it is not so important in the typical case to apply a negative bias to the wafer support and to control the wafer temperature. This is not true in the embodiments of the present invention. Controlling the negative bias on the wafer support 116 is desirable to optimize the ion flux towards the wafer 114. Setting the temperature of the wafer 114 accurately is desirable for both deposition and post-deposition processing of the deposited material.

  Accordingly, the wafer support 116 provides two functions: the function connected to the RF source 142 and the function of accommodating a thermocouple temperature sensing mechanism (not shown). The RF source 142 controls the negative bias supply to the wafer support 116 and the thermocouple monitors the temperature of the wafer 114.

  To obtain an accurate wafer temperature readout, the wafer support 116 and support arm 122 are designed to isolate the RF source signal from the thermocouple signal. Because of this isolation, both the thermocouple signal and the RF source signal are properly transmitted in the chamber 110A, so that the wafer 114 is properly biased and properly heated. Details of the wafer support arm 122 will be described below with reference to FIGS.

  (3. Wafer Support Arm) Referring to FIGS. 6-9 (b) schematically, a wafer 114 is supported on a wafer support 116, which is a conventional "Swiss cheese". It is supported on an alumina ceramic support plate 118. A thin quartz plate 119 is disposed between the support plate 118 and the wafer support 116. The quartz prevents arcing between the support plate 116 and other parts in the wafer processing chamber 110A. The quartz plate 119 is transparent to radiate the energy provided by the lamp 130. This allows the lamp 130 to heat the wafer support 116 quickly.

  Wafer support 116 is surrounded by quartz shield 150. Quartz shield 150 is placed on alumina support plate 118 (partially shown in FIG. 7) and extends above wafer support 116 with both wafer support 116 and wafer 114 present therein. A wafer receiving pocket is defined. The upper edge of the quartz shield 150 is chamfered outward so that the wafer 114 can be easily received when the wafer 114 is taken in and out of the wafer support 116. The quartz shield 150 has an important function of preventing the edge of the wafer support 116 from causing an arc.

  In the processing, the temperature of the wafer support 116 is measured by a thermocouple 152 installed in the wafer support 116. Thermocouple 152 is placed in an alumina nitride sheath 154 that fits snugly within the body of wafer support 116. The sheath 154 electrically insulates between the thermocouple 152 and the main body of the wafer support 116. The sheath 154 has a high electrical resistance but is a good heat conductor. Since the sheath 154 has a low heat capacity, it has low thermal inertia and is therefore suitable for use with the thermocouple 152. Further, the sheath 154 is chemically stable within the processing environment of the processing chamber 112.

  The thermocouple 152 is connected to the temperature measuring device 140 by a conductive cable 156. As will be described below, the cable 156 passes along the central portion of the support arm 122 and is electrically isolated from any high frequency energy within the processing chamber 112.

  Thermocouple 152 is placed in place by nickel spheres 158 crimped to conductive cable 156. The sphere 158 is held in a slot 160 formed in the key-shaped ceramic holding part 162. The key-shaped holding component 162 fits in a key shape in a groove 164 formed in the central projection stub 166 on the lower side of the wafer support 116. This arrangement ensures that the thermocouple 152 can be removed and replaced relatively easily if the wafer support 116 is separated from the support arm 122. The above configuration ensures that the electrical insulation between the wafer support 116 and the thermocouple 152 is maintained while the thermocouple is securely held in place within the body of the wafer support 116.

  Wafer support 116 is secured to support arm 122 by a pair of bolts 168 that are screwed into central stub 166. FIG. 8 shows that the support arm 120 is mainly composed of an inverted U-shaped ceramic portion 170. Bolts 168 pass through each of the holes that penetrate the horizontal portion of the U-shaped portion 170. To prevent the bolt from overloading the horizontal portion of the U-shaped portion 170, each head is spaced from the horizontal portion by a velvedia spring washer 174. It is important to prevent the head of the bolt 168 from overloading the ceramic U-shaped portion 170 because ceramics, particularly thin ceramics, are relatively brittle. Excessive loading forces can destroy the U-shaped portion 170.

  An RF conducting strip 180 passes along the support arm 122. The strip 180 is electrically connected to the lower stub 166 of the wafer support 116. The RF conductive strip 180 is coated with a high temperature, elastomeric dielectric material, polyimide, etc., such as a material available from DuPont Electric under the Pyralin trade name.

  This polyimide coating provides electrical insulation to the RF conductive strip 180. In addition, the RF conducting strip 180 is electrically isolated from the conductive cable 156 by a ceramic isolator 182. Details of the ceramic isolator will be described below with reference to FIGS. 10 (a) and 10 (b). Further, the RF conducting strip 180 is isolated from the interior of the processing chamber 112 by the “legs” of the inverted U-shaped portion 170 and by the isolator 184. Details of the isolator will be described below with reference to FIGS. 11 (a) and 11 (b).

  During assembly, the thermocouple 152 and associated sheath 154 are inserted into the wafer support 116. A thermocouple lead cable 156 is then fed into the U-shaped portion 170. Bolts 168 are used to secure wafer support 116 on U-shaped portion 170. An isolator is placed over the conductive cable 156 to insulate the conductive cable from the RF strip 180. The RF conductive strip 180 is then guided over the isolator 182 and the isolator 184 is disposed over the RF conductive strip 180.

  A flat ceramic retainer 186 is then inserted into a groove 188 formed proximate the free end of the “leg” of the U-shaped portion 170. The retainer 186 functions as a retainer for all the various components disposed in the body of the U-shaped portion 170. Details of the retainer 186 are shown in FIG.

  As shown in FIGS. 9A and 9B, the support arm 122 has a configuration in which a relatively thin portion has a portion enlarged at the free end 120 and the fixed end 122. The free end 120 of the support arm 122 has two bolt holes 172 that are formed on either side of a slot 190 formed in the upper surface of the free end 120. The slot 190 receives a key-like structure 192 that extends downward from a stub 166 at the bottom of the wafer support 116 to the wafer support 116. This key-like structure 192 fits into the slot 190 and further stabilizes the wafer support 116 when placed on the support arm 122. Details of the key-like structure 192 are shown in FIGS. The fixed end 124 of the support arm 122 is fixed to the vertical movable stem 194, details of which will be described with reference to FIG.

  10 (a) and 10 (b), it can be seen that the isolator 182 is in the form of a U-shaped channel with a conductive cable 156 therein. The U-shaped channel has an enlarged portion 196 at one end. This enlarged portion 196 covers the RF conducting strip 180 at the fixed end 124 of the support arm 122.

  As shown in FIGS. 11 (a) and 11 (b), the isolator 184 has an enlarged portion 198 that fits relatively tightly within the free end 120 of the support arm 122. . The enlarged portion 198 has a channel 200 therein. When the device is assembled, the RF conducting strip 180 is placed on the top surface 202 of the isolator 184. Further, the RF conductive strip 180 is deformed so as to be along a contour line inside the channel 200. This configuration is illustrated in FIG. 7 and separates the RF conducting strip 180 from the connecting bolt 168. As can be seen from FIG. 7, a suitable spacer component 204 is provided to fit within the channel 200 to provide electrical isolation between the RF conducting strip 180 and the bolt 168.

  Details of the retainer 186 are illustrated in FIG. The retainer 186 is generally spoon-shaped and has an enlarged portion 206 that is sized to be received in a groove formed in the free end 120 of the support arm 122. During assembly, the retainer 186 is inserted into the slot 188 from the free end 120 of the support arm 122.

  The fixed end 124 of the support arm 122 is connected to the stem 194 as illustrated in FIG. The stem 194 is a hollow tube and spreads at the upper end thereof to define a flange 210, and the fixed end 124 of the support arm 122 is bolted to the flange by a bolt 212. A disc spring washer 214 is provided between each bolt 212 and the fixed end 124 of the support arm 122 to prevent excessive load forces from acting between the bolt 212 and the ceramic fixed end 124.

  A stainless steel bellows 216 is disposed between the flange 210 and the lower wall of the processing chamber 112. Bellows 216 allows support arm 122 to move vertically up and down while simultaneously providing a seal around stem 194 as it passes through wall 218 of processing chamber 112.

  As pointed out earlier, the stem 194 is in the form of a hollow tube. A non-conductive tube 220 is disposed inside the tube forming the stem 194. The non-conductive tube 220 is typically made of polyimide and electrically insulates between the processing chamber 112 and the hollow RF conducting tube 222. The RF conducting tube 220 is connected to the RF source 142 and the RF conducting strip 180. A conductive cable that communicates between the thermocouple 152 and the temperature measurement device 140 passes through a central hole formed in the RF conductive tube 222.

  FIG. 14, together with FIG. 13, illustrates how the connection between the RF conducting strip 180 and the RF conducting tube 222 is made. As shown in FIG. 13, the RF conducting tube 222 extends at its upper end and defines a circular flange 224. The RF conductive strip 180 is illustrated in FIG. 14 but ends at a circular conductive hoop 226. When the support arm 122 is assembled, the hoop 226 is placed on the circular flange 224 of the RF conducting tube 222.

  This provides an RF conductive connection to the RF conductive strip 180 that is connected to the wafer support 116. This connection facilitates assembly and disassembly of the support arm 122. This connection also provides a fixed amount of rotational freedom (above the longitudinal access of the stem 194) when the fixed end 124 of the support arm 122 is placed on the flange 210 of the stem 194. .

  4. Matching Network In accordance with the present invention, the RF source is coupled to both the wafer support 116 and the showerhead 136 via a matching network 145. The matching network 145 is a resistor / inductor / capacitor network. Matching network 145 matches the load impedance to the source impedance to maximize the power provided by the source at a given frequency. The matching network 145 also divides the RF power into the wafer support 116 and the shower head 136 and sets the phase shift of the RF signal applied to the shower head 136 and the wafer support 116.

  A matching network 145 used in one embodiment of the present invention is illustrated in FIG. A matching network 145 shown in FIG. 15A includes a load matching transformer 70, two inductors 80 and 82, and two capacitors 72 and 74. Load matching transformer 70 is coupled at one end to RF source 142 and ground and at the other end to inductors 80 and 82. Inductor 80 is coupled to showerhead 136 via capacitor 72 and inductor 82 is coupled to wafer support 116 via capacitor 74.

  In the load matching transformer 70, the ratio of the primary winding to the secondary winding may be 1: 1 to 1: 4, and typically 1: 1.22. According to the present invention, the primary coil of the load matching transformer 70 may be 18 turns, and the secondary winding of the load matching transformer 70 may be 47 turns. Inductors 80 and 82 may each have an inductance of 50 μH, and capacitors 72 and 74 may each have a capacitance of 0.01 μF.

  By changing the winding ratio of the load matching transformer 70, the decomposition and movement shift of the RF signal between the shower head 136 and the wafer support 116 can be changed. Alternatively, as shown in FIG. 15B, the load matching transformer 71 may have a selectable ground tap 78. This selectable ground tap 78 allows the ground tap position to be selected and changed to change the resolution and movement shift of the RF signal between the showerhead 136 and the wafer support 116.

  Another example of the matching network 145 is shown in FIG. Both capacitor 72 and showerhead 136 are connected to ground via induction choke 83. Both capacitor 74 and wafer support 116 are connected to ground via induction choke 84. Each of the induction choke 83 and the induction choke 84 is 500 μH. When this specific example is used, no DC bias is applied to the shower head 136 and the wafer support 116.

  When using the processing chamber 112 for plasma annealing and / or oxidation, it is advantageous to couple the showerhead 136 and the wafer support 116 to the RF source 142 via the matching network 145. The phase shift of the RF signal in the showerhead 136 and wafer support 116 is set to improve the uniformity of the plasma generated during post-deposition processing. If the phase relationship between the signal of the showerhead 136 and the signal of the wafer support 116 is shifted, ions in the plasma are attracted toward the wafer support 116 rather than the grounded processing chamber 112. In addition, this phase shift increases the voltage potential between the showerhead 136 and the wafer support 116, thereby improving the uniformity of ion flux toward the wafer 114.

  By adjusting the power division of the signal to the showerhead 136 and the wafer support 116, the intensity of ion collision between the wafer 114 and the showerhead 136 can be controlled. Applying a negative bias to wafer support 116 during plasma generation generally increases the acceleration of ions toward wafer 114. If an excessive negative bias is applied to the wafer support 116, ions will collide with the wafer 114 with energy that will damage the wafer 114. If an excessive negative bias is applied to the showerhead 136 during plasma generation, generally, ions will collide with the showerhead 136 and contaminating particles are generated.

  In embodiments of the present invention, the selection of power splitting of the RF source 145 signal can be made by the operator of chamber 110A. This power split can be set so that the negative bias of the showerhead 136 and wafer support 116 minimizes the possibility of the aforementioned contamination and ion collisions that damage the wafer.

  In accordance with the present invention, the matching network 145 may be configured such that the signals supplied to the wafer support 116 and the showerhead 136 have the same power and frequency but are 180 degrees out of phase. This effectively couples RF power to the showerhead 136 and the wafer support 116 to convert the gas in the processing chamber 112 into plasma.

  Specific examples of the configuration of the RF split power include US Pat. No. 5,314,603 to Sugiyama et al., Entitled “Plasma processing apparatus capable of detecting and controlling actual RF power at electrodes in chamber” It can be understood with reference to U.S. Pat. No. 4,871,421 to Ogle et al., Entitled "Split Phase Driver for Plasma Etch System".

  (5. Chamber Operation) During the deposition process, the gas panel controller 50 causes the gas panel 52 to supply a CVD process gas such as TDMAT to the shower head 136. Process gas is introduced into the processing chamber 112 via the showerhead 136 and transported to the heated wafer 114. As a result, a thin layer of material is deposited on the upper surface of the wafer 114. When TDMAT is used, the thin film of material formed is titanium nitride TiN.

During post-deposition processing performed in the semiconductor processing chamber 110A, annealing, oxidation, or exposure to silicon may be performed as described below. During the plasma annealing process, plasma gas such as nitrogen, hydrogen, argon, or a mixture thereof is supplied to the shower head 136 by the gas panel 52 under the control of the gas panel controller 50. In the oxidation process after deposition, an oxygen-based gas such as an O ₂ or N ₂ / O ₂ mixture is supplied to the showerhead 136 by the gas panel 52 under the control of the gas panel controller 50. During the silicon exposure process, a silicon-based gas such as silane (SiH ₄ ) is supplied to the shower head 136 by the gas panel 52 under the control of the gas panel controller 50.

  In both the plasma annealing process and the oxidation process, the gas supplied by the showerhead 136 is converted into a plasma containing positively charged ions that react with the wafer 114. In the silicon exposure process, the gas is energized by heating the wafer 114 and the wafer support 116. Any carrier gas used in either deposition or post-deposition processing is exhausted from the processing chamber 112 by the pressure control unit 157 along with by-products of the deposition or post-deposition processing.

  6. Alternative Chamber Configuration FIG. 16 illustrates a semiconductor wafer processing chamber 110B that contains an alternative embodiment of the present invention for performing a process in accordance with the present invention. The semiconductor wafer processing chamber 110B is the same as the chamber 110A shown in FIG. 5 except that the showerhead 136 is not coupled to an RF source. The RF source 62 is coupled to the wafer support 116 via a matching network 63 and the showerhead 136 is grounded.

  The matching network 63 uses conventional means for matching the load impedance of the wafer support 116 to the impedance of the RF source 62. This matching maximizes the power provided by the RF source 62 at a given frequency. In accordance with the present invention, matching network 63 and RF source 62 provide an RF signal to wafer support 116 to provide sufficient RF energy to perform plasma annealing and oxidation without excessive negative bias to wafer 114. It may be configured to be able to.

  FIG. 17 illustrates a semiconductor wafer processing chamber 110C that includes an alternative embodiment of the present invention and that can perform processes in accordance with the present invention. The semiconductor wafer processing chamber 110C is the same as the chamber 110A shown in FIG. 5 except that the showerhead 136 is separately coupled to the RF source 143 and the wafer support 116 is separately coupled to the RF signal source 144. RF source 143 is coupled to showerhead 136 via matching network 146, and RF source 144 is coupled to wafer support 116 via matching network 147.

  Matching network 146 uses showerhead 136 and matching network 147 uses conventional means for matching wafer support 116 to the source impedance, respectively. This matching maximizes the power provided by each source at a given frequency. Preferably, RF sources 143 and 144 are coupled (not shown) so that the phase shift and power split between the RF signal applied to showerhead 136 and the RF signal applied to wafer support 116 can be controlled. In accordance with the present invention, matching circuitry 146 and 147 and RF source 143 and RF source 143 and RF signal to wafer support 116 and RF signal to showerhead 136 can be supplied at the same power and frequency and 180 degrees out of phase. 144 may be configured.

  In yet another embodiment of the invention, any of the wafer supports 116 of FIGS. 5, 16, or 17 may have a resistance heater. The resistance heater supports the wafer 114 and includes a resistance coil for heating the wafer 114.

  Numerous processes may be performed using the semiconductor wafer processing chamber shown in FIGS. In a further feature of the invention, a process is provided for forming a diffusion barrier. It will be appreciated that the process of the present invention is advantageously performed in the devices described above. However, it is further recognized that the methods disclosed herein can be performed using any number of suitable chambers.

(B. Construction of membrane)
1. Overview An embodiment of the present invention builds a film with improved resistance in an integrated circuit. One of the membranes that can be constructed here is a diffusion barrier. However, for the purpose of suppressing the diffusion of contact metals such as aluminum and copper, other films can be constructed using specific examples of the present invention.

  In accordance with the present invention, a layer of material is deposited on a substrate such as a semiconductor wafer. This material is then plasma annealed to reduce the resistivity of the deposited material. Subsequently, a new layer of material is deposited on the deposited layer. This material is also annealed to reduce the resistivity of the material. Material deposition and annealing may be repeated several times to form a film disposed on the top surface of the wafer.

In another embodiment of the invention, the material on the wafer to be packed (stuffed) with molecules is annealed. By performing this stuffing, the ability of the material to suppress the diffusion of contact metal such as aluminum or copper is improved. In order to improve the function of the film as a barrier against aluminum, stuffing may be performed by oxidizing the annealed material. In order to improve the function of the film as a barrier against copper, stuffing may be performed by exposing the annealed material to silane (SiH ₄ ). Alternatively, the diffusion of copper may be reduced by depositing a material that is a three-element metal nitride silicide.

  Another feature of the present invention is that it may be done in-situ with respect to film deposition, annealing and stuffing on the wafer.

  (2. Annealing to reduce film resistivity) In accordance with the present invention, a layer of material is deposited on the wafer and plasma annealed to reduce the resistivity so that the film is deposited on the wafer. It may be formed.

The deposition of the material film on the wafer is performed in a chamber capable of performing conventional CVD, for example, the chamber 10 in FIG. 3A, the chamber 110A in FIG. 5, the chamber 110B in FIG. 16, the chamber 110C in FIG. ,It can be carried out. The deposition of the titanium nitride material can be achieved using a metalloorganotitanium compound, preferably tetrakis (dialkylamido) titanium (Ti (NR ₂ ) ₄ ).

  A carrier gas, such as helium, argon, nitrogen or hydrogen, entrains the titanium compound in the chamber. Within the chamber, the titanium compound reacts with reactive species generated elsewhere, such as halogen radicals, ammonium radicals, hydrogen radicals, and the like. To facilitate titanium nitride deposition, the wafer temperature is set to about 200-600 ° C. and the processing chamber pressure is set to about 0.1-100 Torr.

  Since the deposited titanium nitride contains a considerable amount of carbon, the titanium nitride film has chemical reactivity. Therefore, if the membrane is exposed to air or other oxygen-containing gas, oxygen is absorbed by the membrane. Since this oxygen absorption cannot be controlled, the stability of the film is impaired, and the resistivity of the film deteriorates. This can reduce the reliability of devices formed on the wafer.

  After exposure to air, the sheet resistivity of the titanium nitride film increases from a value of about 10,000 μΩ-cm / sq to a value of about 100,000 μΩ-cm / sq. This is particularly undesirable when the deposited titanium nitride functions as a barrier to conductive contacts and vias. For the barrier layer, the resistivity is preferably on the order of less than about 1,000 μΩ-cm / sq.

  In accordance with the present invention, the deposited titanium nitride film is plasma annealed by an inert plasma containing high energy ions. These ions are obtained by applying a DC bias voltage to the wafer. The application of this DC bias voltage to the wafer may be performed by a low power RF source that couples to the wafer support and provides sufficient power to generate a plasma from the precursor gas. A voltage of about 100 to 1,000 volts is sufficient for applying a voltage to the wafer. For example, plasma may be generated by applying 400 volts having 100 watts of RF power. This is sufficient for the generation of high energy ions and sufficient for passivation or densification of the titanium nitride film so that it is stable over time.

  When a titanium nitride film annealed in accordance with the present invention is exposed to air, oxygen, or water vapor, oxygen is not absorbed or is absorbed in significantly less amounts than when no bias voltage is applied to the wafer. The titanium nitride film deposited and annealed according to the present invention has higher crystallinity, more nitrogen, oxygen and carbon than the titanium nitride film produced by conventional thermal CVD of metallo-organic titanium compounds The amount is low. The deposited titanium nitride film annealed according to the present invention also has a low and stable sheet resistivity.

  The exact mechanism of the present invention is not known. However, it is believed that the high energy ions impinge on the deposited material on the substrate being biased to increase the film density.

  (A. Nitrogen Plasma) In one embodiment of the present invention, the gas used to generate the plasma for annealing the deposited titanium nitride may be any gas, but does not contain oxygen and carbon, for example, Nitrogen, ammonia, argon or the like is preferable. Nitrogen is most effective for passivation of titanium nitride materials. Alternatively, ions generated from non-gas species such as an ion source may collide with the deposition material. Plasma treatment of the deposited titanium nitride does not adversely affect the particle performance, step coverage, deposition rate or barrier performance of the deposited material.

In a conventional vacuum chemical vapor deposition chamber 10, titanium nitride was deposited on a silicon wafer under the following conditions. The pressure in the processing chamber 12 was 0.45 Torr, and the temperature of the wafer support 16 was set to 420 ° C. The flow rate of helium was 40 sccm through a bubbler of Ti (NR ₂ ) ₄ and the flow rate of nitrogen dilution was set to 100 sccm. Following the titanium nitride deposition, an argon purge gas was flowed into the chamber at 200 sccm. A conventional CVD process for depositing titanium nitride is disclosed in US Pat. No. 5,246,881 issued to Sandhu et al. It is disclosed.

  As a result, titanium nitride was deposited at a deposition rate of about 425 angstroms per minute. As a result, the deposited titanium nitride film had a very uniform thickness, and the thickness variation of the four wafers was 3.03%. However, the sheet resistivity (average of four wafers) was as high as 11,360 μΩ-cm / sq. Also, the resistivity was unstable.

  FIG. 18 is a graph of sheet resistivity (Ω / sq) of deposited titanium nitride versus time. The measured value indicated by the square (□) is a value obtained from the film taken out from the deposition chamber after the desired film thickness is obtained. Measurements indicated by circles (○) are values obtained from films cooled to a temperature of 150 ° C. prior to removal from the deposition chamber. The sheet resistivity of the film indicated by the circle is lower than that of the film indicated by the square, but the stability of both films is low and the sheet resistivity increases with time. Such characteristics are not desirable for diffusion barriers.

  Rutherford backscattering measurement was performed on the deposited titanium nitride film. The resulting spectrum is given in FIG. Carbon peak C, nitrogen peak N and oxygen peak O are shown in the spectrum as being at the silicon interface. The content of various substances in titanium nitride is as follows. The carbon content is about 30%, the nitrogen content is about 24%, the oxygen content is about 25%, and the titanium content is about 23%. This indicates that the deposited titanium nitride film contains relatively high levels of carbon and oxygen impurities.

In an attempt to reduce the sheet resistivity of titanium nitride, the titanium nitride deposition method was changed by adding various gases during the deposition operation. The results are given in Table I of FIG. Titanium in the "Control" column of Table I was deposited using the method just described. The most successful attempt to reduce the sheet resistivity of titanium nitride is an attempt that included an inflow of NF ₃ (7 sccm) during deposition. As a result, the sheet resistivity was lowered to 2,200 μΩ-cm. However, the Rutherford backscattering spectrum of the NF ₃ treated material (see FIG. 23) shows that fluorine is included as an impurity in the film. Inclusion of fluorine is not desirable.

  Next, it was determined whether such treatment affects the sheet resistivity of the deposited titanium nitride using gas inflow and plasma treatment before and after deposition. In two cases, the plasma was ignited before and after chemical vapor deposition of titanium nitride. The plasma was generated at a low power of 100 watts and did not bias the substrate silicon wafer undergoing titanium nitride deposition. The results are summarized in Table II shown in FIG. Neither the pre-deposition treatment nor the post-deposition treatment had a significant effect on the sheet resistivity of the deposited titanium nitride. Thus, it is very difficult to predict by applying a bias voltage to the wafer in plasma to lower the sheet resistivity and stabilize it over time.

  The features of the present invention are further illustrated by the following examples, which are not to be construed as limiting the invention to the details described herein. A series of tests were performed in which a bias voltage of 400 volts was applied to a silicon wafer substrate having a titanium nitride layer. The titanium nitride layer was deposited on the wafer in the chamber 110B of FIG. 16 and annealed with plasma by applying RF power of about 100 watts. Deposition and bias application were cycled continuously. These two steps were cycled ~ 5 times. The thickness of the deposit, the number of cycles and the resistivity obtained over time are given in Table III of FIG. The “control” was deposited in 5 steps without stopping, and was not annealed in the plasma between deposition and others.

  The data in Table III shows that annealing after deposition of titanium nitride significantly reduced the resistivity of titanium nitride and dramatically improved its stability. In each example of Table III, the resistivity and the change over time of the resistivity are improved as compared to the “control” case. The initial resistivity of annealed titanium nitride is low, and the resistivity hardly increases over time.

  FIG. 24 is a graph of Auger analysis of the titanium nitride film of Example 1. This graph represents the atomic concentration of the element in the film with respect to the sputter edge depth (angstrom) of the film. Titanium nitride was biased twice for 30 seconds (see Table III). As shown in FIG. 24, the titanium concentration remains stable, but the graph clearly shows that the nitrogen concentration on the film surface is high while carbon and nitrogen remain low. This reduction in carbon and oxygen impurity levels is maintained for a depth of about 100 angstroms. At a depth of 400 Angstroms, if the film is first annealed with high energy ions, the nitrogen concentration will increase while the carbon and oxygen concentrations will decrease. The graph of FIG. 24 also shows the change in elemental composition of the film after annealing according to the present invention. Elemental analysis for depth is shown in Table IV of FIG.

  Since a 100 Å thick titanium nitride layer is suitable for the barrier layer, the post-deposition annealing is ideal for increasing the stability and decreasing the resistivity of the titanium nitride barrier layer. An Auger spectrum showing the surface elements present in the titanium nitride of Example 7 subjected to post-deposition annealing is shown in FIG. This spectrum shows that the bulk of the deposited film is titanium nitride and a small amount of titanium is present. Carbon and oxygen are present as impurities on the surface.

  However, as shown in FIG. 27, Auger sputtering analysis of the film of Example 7 shows that the oxygen concentration is significantly reduced to a low level in the bulk of the film. The only major impurity other than oxygen is carbon, which remains unaffected by the annealing process. At a depth of 200 angstroms, the element concentration (atomic percent) in the film is 2.8% oxygen, 20.9% carbon, 38.8% titanium, and 37.5% nitrogen. There was no silicon.

  For comparison, the surface Auger analysis of the control film is shown in FIG. 28, and the sputter Auger analysis of the control film is shown in FIG. The oxygen concentration in the control film is extremely high. At a depth of 200 angstroms, the element concentration (atomic percent) of the control film is 10.8% oxygen, 20.7% carbon, 41.0% titanium, and 27.5% nitrogen. There was no silicon.

  The surface Auger analysis of the titanium nitride film of Example 8 is shown in FIG. 30, and the sputter Auger analysis with respect to the depth (angstrom) is shown in FIG. The oxygen concentration of this film was low. At a depth of 43 angstroms, the element concentration (atomic percent) is 3.1% oxygen, 13.7% carbon, 40.0% titanium, and 43.2% nitrogen. There was no silicon.

Rutherford backscattering was used to determine the concentration (atomics / cm ³ ) of the control titanium nitride deposited film and the titanium nitride deposited film of the example. These data are summarized in Table V of FIG. As can be seen from the data in Table V, the concentration of the titanium nitride film increases as compared to the control film by plasma annealing including collision of deposited titanium nitride with high energy ions.

The present invention is not limited to a titanium nitride barrier film. The present invention also improves the chemical composition by improving the performance of other materials such as aluminum, copper, tantalum, tantalum pentoxide, silicides, and other nitrides. For example, the properties and chemical composition (M is Ti, Zr, Hf, Ta, Mo, W and other metals) of the two-element metal nitride M _X N _Y and the three-element silicidation metal M _X Si _Y N _Z are: It can be improved by implementing the features of the present invention. Substrates other than silicon wafers such as stainless steel, metal, oxide, glass and silicide can also be used.

  Deposition and plasma annealing can be performed in one CVD chamber with precursor gas and plasma functions, such as chambers 110A, 110B and 110C. When the chambers 110A, 110B, or 110C are used, annealing can be performed in the same chamber after titanium nitride is deposited. Alternatively, one or more chambers may be used when an apparatus such as that shown in FIG. 3 (a) is used in the practice of the present invention. If more than one chamber is used, it is preferable to maintain a vacuum while transferring the substrate from the CVD chamber 10 to the annealing chamber.

When plasma annealing of the deposited titanium nitride is performed in the chamber 110B, the following procedure can be performed thereafter. The wafer 114 is placed on the wafer support 116 and is spaced from the showerhead 136 by about 0.3-0.8 inches, preferably 0.6-0.7 inches. Energized ions are obtained by applying energy from an RF signal source to the substrate at about 350 kHz and power of 100-500 Watts. In other words, about 0.3 to 1.6 watts per square centimeter (cm ² ) of the surface area of the wafer 114.

  Negative power is applied to the wafer support 116 and the showerhead 136, the chamber walls are grounded, and a DC self-bias voltage of 50-1,000 volts is induced. The self-bias voltage is preferably 200-800 volts between the wafer 114 and ground. This is sufficient to attract ions and impact the surface of the wafer 114 with high energy. As a result, the deposited titanium nitride is passivated or densified and remains stable over time.

  FIG. 33 is a graph of atomic oxygen concentration versus air exposure time for two different layers of titanium nitride formed in accordance with the present invention. Both these titanium nitride films were deposited in the same chamber and plasma annealed. This chamber is similar to the chamber 110B described above.

By repeating the cycle of deposition and annealing for each film, a titanium nitride film having a thickness of 200 angstroms was formed. To do this, a 100 Å layer is deposited and then annealed, followed by a second 100 Å layer deposited and annealed. Annealing was performed using N ₂ plasma. The percentage of atomic oxygen was measured repeatedly for a period of 24 hours for the two films, which is reflected in plot 312.

  As can be seen from plot 312, the concentration of oxygen was initially about 2%. The concentration after 24 hours was less than 2.5%, indicating that the deposited film was very stable. In comparison, plot 314 illustrates an oxygen concentration measurement measured for a titanium nitride film deposited using conventional CVD without annealing. These films not only had a high oxygen concentration (15%) from the beginning, but also absorbed oxygen at a high rate. In addition, the film formed by the prior art has low stability, and the resistivity has increased remarkably over time. For comparison, point 316 in FIG. 34 illustrates a typical oxygen concentration (about 1%) of a titanium nitride film deposited by physical vapor deposition.

  34A to 34C are graphs of XPS spectra for different films, respectively. FIG. 34 (a) represents the spectrum of a 200 Å non-annealed film and shows that at 316 the level of organic bonded carbon is relatively high. In contrast to this, the measurement results of the 200 Å film used in the creation of FIGS. 34 (b) and 34 (c) indicate that the level of organic bonded carbon has decreased at 317 and 318, respectively. The formation of the film used for FIG. 34 (b) was accomplished by depositing a 100 Å titanium nitride layer, plasma annealing according to the present invention, and then depositing and annealing a second 100 Å layer of titanium nitride. It should be noted that FIG. 34 (c) shows four 50 Å thick layers of titanium nitride deposited and annealed sequentially.

FIGS. 35 (a) and (b) further illustrate the improvements of the present invention. FIG. 35 (a) shows the resistivity of vias using CVD titanium nitride films deposited and plasma annealed with N ₂ . These vias were first lined with a CVD titanium nitride adhesive layer and then filled with CVD tungsten plugs. FIG. 35 (a) is a graph of via resistivity versus film deposition thickness. This graph was created for 0.5 μm vias with an aspect ratio of about 2.5. As shown, the via resistivity (plot 320) for the plasma annealed film is substantially lower than the non-annealed conventional deposited film (plot 322). For comparison, a PVD deposited titanium nitride film is illustrated by arrow 324.

A similar improvement is illustrated by the graph of FIG. 35 (b) representing salicide contact resistance versus titanium nitride thickness. This graph is plotted for 0.5 μm vias with an aspect ratio of about 2.5. Plot 330 shows the resistance of a contact made by N ₂ plasma treatment according to the present invention. Plot 330 illustrates a resistance that is substantially lower than the resistance illustrated in plot 332 that represents the contact resistance obtained by conventional CVD deposition. For comparison, PVD titanium control contact resistance is given by arrow 334.

FIG. 36 illustrates the effect of the number of deposition and annealing cycles used to form one film of the desired thickness. In FIG. 36, a titanium nitride film with a total thickness of 200 Å was deposited by chemical vapor deposition and annealed with N ₂ plasma. In the first case, illustrated by plot 340, the process was performed in four cycles, in each of the four layers, a 50 Å thick layer was deposited and a plasma anneal was performed prior to deposition of the next layer. In the second case, illustrated by plot 342, two layers of 100 Å were deposited and annealed separately.

  The case shown by plot 340 shows a lower resistivity (500-600 μΩ-cm) than the case given by curve 342 (700-800 μΩ-cm). However, the resistivity of the film shown in both plots 340 and 342 is lower than the upper limit of 1000 μΩ-cm. In each case, the increase in resistivity after 8 days was almost the same in both cases and was less than 5%.

  Further tests were conducted to investigate the effect of plasma treatment process pressure on film resistivity and DC bias voltage. The result of this test is illustrated in FIG. FIG. 37 was created for a 200 Angstrom titanium nitride deposit that was applied for 60 seconds in plasma with an applied power of about 20 Watts.

  As shown in plot 350, the improved resistivity exhibited by the film produced by the process of the present invention is generally independent of process pressure. However, low resistivity was not achieved when the process pressure was lower than 200 mTorr.

  As illustrated in plot 352, as the process pressure was increased from about 200 mTorr to 1000 mTorr, the DC bias induced across the plasma was substantially reduced. Thereafter, it remained relatively constant at about 150 volts.

  FIG. 38 (a) illustrates the effect of processing time and frequency on membrane resistivity. A comparison of four different membranes with a total membrane pressure of 400 Angstroms was made. The film shown in plot 360 was formed by first depositing and annealing a 50 Å layer followed by 6 25 Å layers. Each of these layers has been deposited and annealed before the next layer. The second film indicated by plot 362 is formed by depositing and annealing four 50 angstrom layers, respectively. The third film indicated by plot 364 is formed by depositing and annealing two 100 angstrom layers, respectively. The last film shown in plot 366 is formed by depositing a layer of 200 Angstroms and then annealing according to the present invention.

  Numerous observations are possible from these plots in FIG. As the number of individual layers to make the final layer increases, the resistivity will decrease. In addition, if the individual layers are thinned, the influence of the plasma treatment time on the resistivity is reduced. FIG. 38B illustrates another example of the influence of the plasma processing time on the film resistivity.

In addition to reducing resistance and increasing film stability, the method of the present invention could be used for other purposes. Analysis of the film annealed with N ₂ plasma showed an increase in the amount of nitrogen near the surface of the film. This is probably because some of the nitrogen ions were embedded in the film and reacted with the film. Thus, this annealing process could be used to increase ions / molecules from the plasma into the film. In addition, this process could be used to eliminate or replace unwanted molecules / ions from the membrane. FIGS. 34 (b) to (c) show that ions colliding with the film expel carbon atoms.

  (B. Nitrogen / Hydrogen Plasma) In another embodiment of the invention, a mixed gas of nitrogen and hydrogen is used to generate plasma during plasma annealing of the film deposited on the wafer 114. As a first step, a titanium nitride film is deposited on the wafer 114 using a conventional thermal CVD process. Thereafter, the deposited material is annealed using plasma generated from a gas having a mixed gas of nitrogen and hydrogen.

  When these steps are performed using any of the chambers 110A, 110B, or 110C, the CVD process and the annealing may be performed in the same chamber. Alternatively, titanium nitride may be deposited on the wafer 114 in one chamber and the wafer 114 may be transferred into another chamber for post deposition plasma annealing.

  If chamber 110A is used, wafer 114 is placed on wafer support 116 and spaced approximately 0.3 to 0.8 inches, preferably 0.6 to 0.7 inches from showerhead 136. As described above, a layer of titanium nitride film may be deposited on the wafer 114. The initially deposited titanium nitride layer may be 50 to 200 angstroms thick.

  After deposition is complete, plasma annealing of the deposited material is initiated. A gas having a 3: 1 mixed gas of nitrogen and hydrogen is introduced into the processing chamber 112 through the shower head 136. The mixed gas of nitrogen and hydrogen is introduced at a nitrogen flow rate of about 30 sccm. The RF source 142 then provides 350 watts of RF power at 350 kHz via the matching network 145 to generate an RF signal to the wafer support 116 and the showerhead 136. The RF signal of the shower head 136 and the RF signal of the wafer support 116 are preferably 180 degrees out of phase.

  The above-mentioned mixed gas has a ratio of nitrogen to hydrogen of 3: 1, but any ratio can be used as long as it is between 3: 1 and 2: 1. In general, the higher the proportion of hydrogen in the mixed gas, the longer the film will have stability. However, if there is too much hydrogen in the plasma, the hydrogen combines with the carbon in the film to produce a polymer, increasing the resistivity of the film.

  Under the influence of the RF power supplied to the shower head 136 and the wafer support 116, positively charged nitrogen and hydrogen ions contained in the plasma are generated. The plasma is typically maintained for 10-30 seconds. As described above, the processing chamber 112 is grounded. The showerhead 136 obtains a negative bias of -100 to -400 volts, typically -200 volts. Wafer 114 gains a negative bias of -100 to -400 volts, typically -300 volts, due to self-bias. This negative bias voltage remains approximately constant during the time of the collision.

  During the collision time, positively charged ions from the plasma are accelerated by a voltage gradient at the surface of the wafer 114. As a result, ions collide with the wafer surface and penetrate to a depth of 50 to 100 angstroms. In addition, neutral atomic particles receiving energy may collide with the wafer 114.

  As a result of ion bombardment, compression of the deposited material can occur, reducing its thickness by 20-50%. This reduction depends on the wafer temperature and the plasma processing time and energy. If desired, a further layer of titanium nitride may be subsequently deposited and annealed. Each of the further formed layers preferably has a thickness of 50 to 100 angstroms.

After annealing is complete, the resulting annealed titanium nitride film exhibits numerous performance improvements. The oxygen content is reduced by 20-25% and oxygen only accounts for less than 1% of the deposition anneal material. The density of the film was less than 3.1 grams per cubic centimeter (3.1 g / cm ³ ) but increased to about 3.9 g / cm ³ . The fraction of carbon contained in the deposited film is reduced by 25% or more, and carbon only accounts for 3% of the deposited film. A change in the structure of the film occurs, and the resistivity of the film drops from 10,000 μΩ-cm before processing to 150 μΩ-cm. When the annealed film is exposed to oxygen, air, or water vapor, the amount of oxygen absorbed is significantly smaller than when the deposited film is not annealed. By plasma annealing, carbon and nitrogen in the film thus deposited are replaced with nitrogen from the plasma.

  It has been found that adding hydrogen to the plasma generating gas significantly reduces the amount of carbon that is driven out of the membrane by ion bombardment and coats the inside of the processing chamber 112. It would be beneficial to reduce the carbon coating of the processing chamber 112 because such carbon coating changes the impedance of the chamber and makes it difficult to accurately control the plasma. By reducing the carbon coating, the processing chamber 112 can be used more times until cleaning is required.

  FIG. 39A shows an Auger electron spectral depth profile for a titanium nitride film formed by depositing a titanium nitride layer having a thickness of 100 angstroms on the silicon dioxide layer and subsequently annealing. As shown in FIG. 39 (a), the carbon content and the oxygen content are uniform almost throughout the film, with 9 atomic percent for carbon and 2 atomic percent for oxygen. The resistivity of the annealed titanium nitride film is about 250 μΩ-cm.

  FIG. 39 (b) shows a further improvement when obtained by depositing and annealing a 50 Å layer of titanium nitride. FIG. 39B shows an Auger electron spectral depth profile for a titanium nitride film formed by depositing a titanium nitride layer having a thickness of 50 angstroms on the upper surface of the silicon dioxide layer and subsequently annealing. Again, the carbon and oxygen contents are uniform throughout the film, with 3 atomic percent for carbon and 1 atomic percent for oxygen. The ratio of titanium and nitrogen is higher than in the 100 angstrom process. The resistivity of the annealed titanium nitride film is about 180 μΩ-cm.

  (C. Nitrogen / Hydrogen / Rare Gas Plasma) In yet another embodiment of the present invention, the mixed gas of nitrogen and hydrogen used to generate the annealing plasma may be another gas such as argon, helium, or ammonia. May be included. Further, the ion collision treatment is improved by further including a rare gas. Since argon atoms are heavier than helium atoms, argon atoms will give better collision capabilities.

Furthermore, it is conceivable that the composition of a film made of a material other than titanium nitride may be changed by the same method as in the present invention. Other gases may be added to the plasma to alter the chemical composition of the film, either by inclusion in the film or by reacting with impurities present in the film. For example, NH ₃ and CH ₄ may be used. Oxygen-based plasma gases are more suitable for processing oxide films such as Ta ₂ O ₅ .

Although the present invention has been described for plasma impinging CVD deposited films, the present invention is also applicable to PVD deposited films. In addition, the present invention provides for the treatment of two-element metal nitride M _X N _Y and three-element silicidation metal M _X Si _Y N _Z (M is Ti, Zr, Hf, Ta, Mo, W and other metals). Significant uses have been found.

  The present invention can also be used to change the film morphology to an advantageous one. Thin barrier materials may be subjected to the high density ion bombardment of the present invention in order to improve the uniformity of their grain orientation. Since the grain orientation of the underlying layer affects the structure of the next deposited layer, the present invention can change the crystal structure and / or growth direction of the underlying layer to change the layer of the next deposited layer. Provides the ability to change and improve morphology.

  To control the morphology of multiple layers, deposit a thin nuclear interface layer less than 50 angstroms thick, then change it by high density ion bombardment, and deposit bulk or remaining film by standard techniques You can do it. The structure of the overlying layer can be determined by the structure of the underlying layer that has been changed previously.

  This can be illustrated with reference to FIG. For titanium nitride films, the preferred crystal and orientation has been determined to be <200>. If hydrogen is added to the plasma, the film can be improved by increasing the crystallinity. FIG. 40 is an X-ray diffraction for angular scanning of a conventional CVD titanium nitride layer 1000 Å thick deposited on a silicon wafer. A point on the curve representing the number of grains oriented in the <200> direction is indicated by a label 300. As can be seen from this graph, there is no clear TiN <200> peak. This indicates that crystalline TiN <200> is weak in a film formed using a conventional CVD process.

  FIG. 41 is an X-ray diffraction for angular scanning of a 1000 Å thick CVD titanium nitride layer deposited and annealed on a silicon wafer according to the present invention. This diffraction pattern indicates that the film is microcrystalline with a preferred orientation <200>, as indicated by label 350. Between 40 and 45 degrees, the number of grains oriented almost in the <200> direction is large. Furthermore, the peak 310 of FIG. 40 is significantly lower in FIG.

  (3. Subsequent annealing) In order to further reduce the resistivity of the deposited film, the plasma annealing process may be modified according to the present invention to include two successive plasma annealing steps. The first annealing step is performed using plasma generated from a mixed gas containing nitrogen and hydrogen as described above. The second plasma annealing step is performed to remove hydrogen from the annealed material because hydrogen has a high affinity for oxygen and thus increases the resistivity.

  The ions generated in the second plasma collide with the deposited and annealed material, driving off the hydrogen on the surface of the material as an unwanted byproduct from the film. The reduction of hydrogen reduces the affinity of the material for oxygen, which can lower the resistivity of the film and exhibit improved stability.

The gas used for generating the plasma in the subsequent second annealing step may include nitrogen or a mixed gas of any one of helium, argon, and neon and nitrogen. Helium is preferred because it promotes the ionization of nitrogen molecules and reduces the probability of recombination of N ⁺ , N ₂ ⁺ , N ₃ ⁺ and N ₄ ⁺ ions. A mixed gas of nitrogen and helium is preferred over using nitrogen alone because the ions in the helium-based plasma can improve ionization efficiency, thus promoting ion reactivity and penetration depth Can be increased. As the penetration depth increases, the amount of hydrogen that is expelled increases and the reduction in the resistivity of the deposited material can be maximized. Furthermore, if there is a small amount of helium, it is possible to fill voids left in the deposited material because hydrogen atoms exist, which are too small to be filled with nitrogen atoms.

  In accordance with the present invention, a wafer 114 is placed in a chamber, such as chamber 110A, and a layer of material is deposited on the wafer as described above. The deposited material may be titanium nitride for use as a diffusion barrier.

  After depositing the layer of material, a first annealing process of ion bombardment is performed. The wafer 114 is placed on the wafer support 116 but may be about 0.3 to 0.8 inches from the showerhead 136. Wafer 114 is preferably 0.6 to 0.7 inches from showerhead 136.

  The ion collision is realized by first moving the gas to the processing chamber 112 via the shower head 136. In one embodiment of the invention, the gas is a mixed gas of nitrogen and hydrogen with a nitrogen to hydrogen ratio of 2: 3 and is introduced into the processing chamber 112 at a nitrogen flow rate of about 600 sccm. The pressure in the processing chamber 112 is set to about 1.0 Torr and the wafer temperature is set to 350-450 ° C. In an alternative embodiment of the invention, the gas may comprise a gas mixture having a nitrogen to hydrogen ratio of 3: 1 to 1: 2.

  Following the first annealing process, the RF source 142 provides an RF signal to the showerhead 136 and the wafer support 116. Thereby, the gas generates a plasma containing positively charged ions. The RF source 142 supplies 350 watts of RF power at 350 kHz via the matching network 145 and generates RF signals that are 180 degrees out of phase to the wafer support 116 and the showerhead 136. Typically, the plasma is maintained for 20 seconds. Alternatively, the RF source 142 may provide 350 watts of RF power at a frequency of less than 1 MHz.

  By repeatedly cycling the voltage from the RF source 142, electrons become excessive in the vicinity of the wafer 114, which creates a negative bias on the wafer 114. Wafer support 116 can obtain a negative bias of −100 to −400 volts, typically −200 volts. The processing chamber 112 is grounded and the negative bias of the wafer 114 is -100 to -400 volts, typically -300 volts, which remains approximately constant during the time of the collision.

  During ion bombardment, positively charged ions from the plasma are accelerated by a voltage gradient at the surface of the wafer 114 and penetrate to a depth of 100-110 angstroms. In addition, neutral atomic particles receiving energy may collide with the wafer 114. When the first anneal for 20 seconds is complete, the process chamber 112 is purged.

  Next, a second annealing process is started. In one embodiment of the present invention, the plasma generating gas is only nitrogen. This gas is introduced into the processing chamber 112 at a nitrogen flow rate of about 500-1000 sccm. The pressure in the processing chamber 112 is set to about 1.0 Torr and the wafer temperature is set to 350-450 ° C.

  In an alternative embodiment of the invention, the gas may be a mixed gas of nitrogen and helium, and the ratio of nitrogen to helium may be 0.2-1.0. A gas including a combination of argon, neon, helium, or a mixed gas thereof and nitrogen may be used.

  Next, in a second anneal process, the RF source 142 provides an RF signal to the showerhead 136 and the wafer support 116. Thereby, plasma having positive charge is generated from the gas. The RF source 142 supplies 300 to 1,500 watts of RF power at 300 to 400 kHz via the matching network 145 and generates RF signals that are 180 degrees out of phase to the wafer support 116 and the showerhead 136. Let Typically, the plasma is maintained for 15 seconds. Alternatively, the RF source 142 may provide 300-1500 watts of RF power at a frequency of 13.5 MHz. The source power may be scaled based on the need to change the size of the wafer being processed.

  As in the first anneal case, repeated cycling of the voltage from the RF source 142 causes excess electrons in the vicinity of the wafer 114, which creates a negative bias on the wafer 114. The wafer support 116 can obtain a negative bias of −100 to −400 volts, typically −300 volts, and the showerhead 136 can have a negative bias of −100 to −400 volts, typically −200 volts. Can be obtained. The processing chamber 112 is grounded and the negative bias of the wafer 114 is -100 to -400 volts, typically -300 volts, which remains approximately constant during the time of the collision.

  During ion collision, positively charged ions from the plasma are accelerated by a voltage gradient at the surface of the wafer 114. The ions penetrate the surface of the wafer 114 and drive out the hydrogen molecules of the deposited and annealed material. In addition, neutral atomic particles receiving energy may collide with the wafer 114. When the second anneal for 15 seconds is complete, the process chamber 112 is purged.

  When nitrogen gas is used, the ions penetrate to a depth of 70-80 angstroms. When the gas is a mixed gas of nitrogen and helium, the ions penetrate to a depth of 100 to 125 angstroms. Therefore, if annealing is performed with a mixed gas of nitrogen and helium, more hydrogen molecules can be driven out than when annealing is performed using only nitrogen.

  The above CVD deposition and continuous annealing process is repeated to form a diffusion barrier of the desired thickness, for example 150-300 angstroms. A layer of 50-100 Å thick barrier material is deposited by sequential deposition and sequential annealing until the desired thickness is achieved.

  When the subsequent annealing process is performed in any one of the chambers 110A, 110B, and 110C, the deposition, the first annealing, and the second annealing may all be performed in the same chamber. Thus, deposition and continuous annealing may be performed in situ. However, the deposition and continuous annealing process steps need not be performed in-situ, and separate chambers may be used.

  Table VI of FIG. 42 reflects the experimental results obtained to compare the continuous annealing process with the one annealing process. To collect the data in Table VI, each set of wafers was processed according to another embodiment of the present invention. A 200 Å thick titanium nitride layer was formed on each wafer in accordance with the present invention.

  The first wafer was processed using nitrogen and hydrogen gases to generate an anneal plasma according to the single anneal process described above. The second wafer was processed by continuous annealing using a plasma gas containing only nitrogen. The third wafer was processed by continuous annealing using a plasma gas containing nitrogen and helium. The fourth wafer was processed by three-phase continuous annealing, ie, sequentially performing nitrogen-hydrogen plasma annealing for 15 seconds, nitrogen plasma annealing for 15 seconds, and nitrogen-hydrogen plasma annealing for 5 seconds.

  The second wafer, which was continuously annealed with nitrogen gas, was shown to have a significantly lower resistivity than the first wafer that was only subjected to one annealing step. The resistivity of the second wafer was 450 to 500 μΩ-cm, and the resistivity of the first wafer was 570 to 630 μΩ-cm. In addition, the second wafer had only a 7-8% increase in resistivity after 50 hours, while this increase in the first wafer was 11-12%.

  Even better results were confirmed for the third wafer using a mixed gas of nitrogen and helium in the second plasma annealing. The third wafer had a resistivity of 440-480 [mu] [Omega] -cm and increased only 3-7% in 50 hours. The third wafer had a low oxygen concentration. The reason why the oxygen concentration level of the third wafer was lower than that of the second wafer was that the ability to expel hydrogen from the titanium nitride layer of the nitrogen-helium mixed gas was superior.

  The fourth wafer was third annealed with a mixed gas of nitrogen and hydrogen, but the measured values of resistivity and resistivity degradation were close to the first wafer. This indicates that a hydrogen-excess state is created by reintroducing hydrogen after the second anneal. This excess of hydrogen detracts from the benefits realized in the second anneal.

  (4. Oxidation for reducing diffusivity) In addition to improving the resistivity of the film on the wafer, the following process is performed to prevent the contact metal from diffusing into the substrate under the film. Can be further deterred. In particular, the film will be processed to better inhibit aluminum diffusion.

  First, a layer of material is formed in-situ on the upper surface of the wafer 114 (without removing the wafer from the processing chamber 112 at any point during layer formation). In one embodiment of the invention, material deposition followed by annealing is performed in chamber 110A to form a film. Thermal CVD may be used to deposit a layer of material on the top surface of the wafer 114 so that the material can conform to the top surface of the wafer 114. During deposition, the pressure control unit 157 may be set so that the pressure in the processing chamber is 0.6 to 1.2 Torr, and the lamp 130 is set so that the temperature of the wafer 114 is 360 to 380 ° C. May be.

  In one embodiment of the present invention, the deposited material may be a barrier material, such as a two-element metal nitride such as titanium nitride (TiN). In another specific example of the present invention, a three-element metal nitride silicide may be used as a barrier material instead of the two-element metal nitride. The deposited material may be 50-300 angstroms thick, preferably 50-100 angstroms.

  After the barrier material is deposited, it is annealed through an ion bombardment process. Wafer 114 is placed on wafer support 116, but may be 0.3 to 0.8 inches from showerhead 136. Wafer 114 is preferably 0.6 to 0.7 inches from showerhead 136.

  In order to perform ion collision, first, a gas is introduced into the processing chamber 112 through the shower head 136. In one embodiment of the present invention, the gas is a mixed gas of nitrogen and hydrogen, which is introduced into the processing chamber 112 with a nitrogen to hydrogen ratio of 2: 3 and a nitrogen flow rate of about 400 sccm. The pressure in the processing chamber 112 is set to about 1.0 Torr, and the wafer temperature is set to 300-400 ° C. (preferably 360 ° C.).

  In another embodiment of the invention, the gas may comprise a gas having a nitrogen to hydrogen ratio of 3: 1 to 1: 2. Another gas in which nitrogen or hydrogen is combined with argon, helium, or ammonia may be used.

  Next, in an annealing process, the RF source 142 supplies an RF signal to the showerhead 136 and the wafer support 116, so that the gas 206 generates a plasma containing positively charged ions. The RF source 142 may supply 350 watts of RF power at 350 kHz via the matching network 145 to generate RF signals that are 180 degrees out of phase at the wafer support 116 and the showerhead 136. Typically, the plasma is maintained for 10-30 seconds. Alternatively, the RF source 142 may provide 350 watts of RF power at different frequencies below 1 MHz.

  A negative bias is generated on the wafer 114. The wafer support 116 can obtain a negative bias of -100 to -400 volts, typically -300 volts, and the showerhead 136 can be negative of -100 to -400 volts, typically -200 volts. A bias can be obtained. The processing chamber 112 is grounded and the negative bias of the wafer 114 is -100 to -400 volts, typically -300 volts, which remains approximately constant during the time of the collision.

  During ion bombardment, positively charged ions from the plasma are accelerated by a voltage gradient at the surface of the wafer 114 and penetrate to a depth of 50-200 angstroms. In addition, neutral atomic particles receiving energy may collide with the wafer 114.

  As a result of ion bombardment, the thickness of the deposited material of the barrier material is reduced by 20-50% depending on the substrate temperature and the plasma treatment time and energy. As described above, CVD deposition and annealing using a layer of barrier material having a thickness of 50-100 angstroms may be repeated to form a layer of material of a desired thickness.

  Alternatively, material deposition and annealing on the wafer 114 may be accomplished by a number of different means. US patent application Ser. No. 08 / 498,990, titled “Bias Plasma Annealing of Thin Films”, US Patent Application No. 08 / 567,461, Title “Plasma Annealing of Thin Films”, US Pat. Each of the "plasma bombardment" discloses a process for forming a layer of barrier material on the top surface of the wafer using a CVD process and a plasma anneal. Each of these applications is hereby incorporated by reference. Each of the processes disclosed in these applications can be used in embodiments of the present invention for forming a layer of material on a wafer.

  In one embodiment of the invention, the wafer is placed in an apparatus capable of performing physical vapor deposition and a layer of material is formed by a conventional sputtering process. In another embodiment of the invention, the wafer is placed in a chamber capable of chemical vapor deposition, a layer of material is formed by CVD, and no additional annealing is performed.

  In the manufacture of integrated circuits, aluminum is frequently used as a contact metal. Since aluminum has an affinity for oxygen, the diffusibility of aluminum in the oxygen-rich metal may be lowered. Thus, by permeating the material with oxygen, the layer of material formed on the wafer 114 can be processed to function as an improved diffusion barrier to the aluminum contact metal.

  To infiltrate the material with oxygen, the material on the wafer 114 is oxidized in situ (after forming the layer of material and without removal from the processing chamber 112 until oxidation is complete). That is, the entire process of forming the layer of material and oxidizing the layer of material can be performed in situ in one chamber. Oxidation is performed so that the grain boundaries of the material are oxidized but the grains of the material themselves are hardly oxidized.

  The grain boundary oxidation of the material may be performed in situ using a semiconductor wafer processing chamber 110A shown in FIG. After the material is formed (deposited and annealed) on the wafer 114, the wafer 114 is left in the processing chamber 112. A pressure control unit 157 sets the pressure in the processing chamber 112 to 0.5 to 1.0 Torr. The temperature of the wafer 114 is set to be 300 to 400 ° C. (preferably 360 ° C.).

A layer of material is exposed to an oxygen-containing gas such as N ₂ / O ₂ mixed gas or O _2. This gas is transferred into the processing chamber 112 through the shower head 136 at a flow rate of 100 to 1000 sccm. The gas 208 may contain both nitrogen and oxygen, and the nitrogen to oxygen mixing ratio may be 4: 1. The RF source 142 then provides signals to both the wafer support 116 and the showerhead 136 via the matching network 145 to convert the gas into a plasma containing positively charged oxygen ions.

  The RF source 142 supplies 350 watts of RF power through the matching network 145 at 350 kHz for about 20 seconds, generating RF signals that are 180 degrees out of phase at the showerhead 136 and the wafer support 116. Each of the showerhead 136, wafer support 116, and wafer 114 obtains a negative bias, as described above for the annealing process. As a result, positively charged oxygen ions are accelerated toward the wafer 114 and penetrate the surface of the material layer and adhere to the grain boundaries of the material.

After this oxidation is completed in one embodiment of the invention, the oxidized material layer is oxidized titanium nitride. This oxidized titanium nitride can function as an improved diffusion barrier with respect to a contact metal (for example, aluminum) having an affinity for oxygen. Alternatively, the material layer may be another two-element metal nitride M _X N _Y or a three-element silicon nitride metal M _X Si _Y N _Z (M is Ti, Zr, Hf, Ta, Mo, W and other metals) In this case, an improved diffusion barrier can be formed according to the present invention.

  In an alternative embodiment of the present invention, the same semiconductor wafer processing chamber 110A is used to thermally oxidize the material. An oxygen-containing gas such as oxygen, ozone, air or water is transferred into the processing chamber 112 via the shower head 136 at a flow rate of 100 to 1000 sccm. Next, the wafer 114 is heated to a temperature of 300 to 400 ° C. by the lamp 130, while the pressure in the processing chamber is set to 0.5 to 100 Torr (preferably 1.0 Torr).

  As a result, oxygen in the oxygen-containing gas permeates the surface of the barrier material layer and adheres to the grain boundary of the barrier material. One process for oxidizing the grain boundaries of the barrier material is disclosed in US Pat. No. 5,378,660, Ngan et al., Entitled “Barrier Layers and Aluminum Contacts,” which is hereby incorporated by reference. After forming and oxidizing the layer 200 of material, the wafer 114 is removed from the processing chamber 112.

  Although the formation and oxidation of a layer of material on the wafer 114 has been specifically described as being performed in the semiconductor wafer processing chamber 110A of FIG. 5, this process is not limited to being performed in the chamber 110A. This process can also be performed in any semiconductor wafer processing chamber for performing in-situ formation and oxidation processes in accordance with the present invention, such as chamber 110B in FIG. 16, chamber 110C in FIG.

  Conventionally, the diffusion barrier has been thickened to provide sufficient protection against contact metal diffusion. As a result of embodiments of the present invention, the diffusion barrier need not be thick to prevent contact metal diffusion. In a specific example of the present invention, the diffusion of contact metal (aluminum or the like) having affinity for oxygen is reduced by oxidation of the barrier metal. When the contact metal starts to diffuse into the oxide layer of the barrier material, the contact metal combines with oxygen ions, and these oxygen ions adhere to the grain boundaries of the barrier material. As a result, the contact metal cannot reach the region of the diffusion barrier below it.

  The chart in FIG. 43 (a) shows the chemical composition of the wafer at different depths after deposition and plasma annealing of a layer of barrier material according to the present invention without oxidation. FIG. 43 (b) includes a graph showing the chemical composition of the wafer at varying depths after depositing a layer of barrier material, plasma annealing and oxidizing according to the present invention.

  Each of these charts represents data taken from a wafer having a silicon substrate covered by a titanium nitride barrier layer. The wafer was examined by Auger electron spectroscopy. Each chart shows the atomic concentration for each compound when the depth of the wafer is different. As can be seen by comparing these two charts, the oxygen level at the top of the wafer, that is, the portion composed of the barrier material, is higher than that of the non-oxidized barrier material (FIG. 43A). (B)) is significantly higher.

  Due to the presence of oxygen in the barrier material, the contact metal such as aluminum becomes remarkably low in diffusibility by bonding with oxygen ions in the barrier material. Therefore, the oxidized barrier material (FIG. 43B) is better between the contact metal (such as aluminum) and the underlying silicon substrate than the non-oxidized barrier material (FIG. 43A). Provides a diffusion barrier.

  In addition, the sheet resistance of diffusion barriers formed according to embodiments of the present invention is not unacceptably compromised by the oxidation process. FIG. 44 illustrates a table that illustrates this fact. As shown in this table, a 200 Å layer of titanium nitride barrier material that has been deposited and plasma annealed but not oxidized according to the present invention has a sheet resistance value of 410 Ω / sq, a standard sheet resistance value. The deviation will be 2.2%. The resistivity of this barrier material layer is 820 μΩ-cm. A 200 Å layer of titanium nitride barrier material deposited and plasma annealed according to the present invention and oxidized for 20 seconds has a sheet resistance value of 630 Ω / sq, and the standard deviation of the sheet resistance value is 3.7%. Let's go. The resistivity of this barrier material layer is obtained as 1260 μΩ-cm.

  Also, the table of FIG. 44 shows the sheet resistance for a 300 Å layer of titanium nitride barrier material. After deposition and plasma annealing according to the present invention, a 300 Å layer of titanium nitride barrier material will have a sheet resistance value of 235 Ω / sq, with a standard deviation of the sheet resistance value of 2.0%. After deposition, plasma annealing and 20 seconds of oxidation according to the present invention, the 300 Å layer of titanium nitride barrier material has a sheet resistance value of 250 Ω / sq with a standard deviation of 2.7%. Would be. Thus, the resistivity of the 300 Å layer of non-oxidized barrier material would be 705 μΩ-cm, while the resistivity of the 300 Å layer of oxidized barrier material would be 750 μΩ-cm.

  The relative effectiveness of the non-oxidized and oxidized layers of the titanium nitride barrier material shown in the table of FIG. 44 was evaluated as follows. A 1000 Å layer of aluminum was deposited on a wafer having an unoxidized titanium nitride barrier material on the top surface and a wafer having an oxidized titanium nitride barrier material. After the deposition on the wafer, the aluminum was annealed in a furnace at 550 ° C. for 1 hour. Wafers with a 200 Å layer of non-oxidized titanium nitride barrier material and a wafer with a 300 Å layer were severely defective due to aluminum diffusion into the substrate of the wafer. Wafers with a 200 Å layer of titanium nitride barrier material deposited, plasma annealed and oxidized according to the present invention have only minor defects due to aluminum diffusion, while wafers with a 300 Å layer have no such defects. I was not able to admit.

  The data in FIGS. 43 (a), 43 (b) and 44 are only examples of the results that can be obtained by carrying out the embodiments of the present invention. The results shown in these diagrams are not meant to limit the embodiments of the present invention to achieving the same results or substantially the same results.

  5. Silicon enrichment to reduce diffusivity In another embodiment of the invention, the oxidation step is replaced by a silicon stuffing operation. By the operation of silicon stuffing, the diffusibility of the contact metal such as copper into the material layer (such as titanium nitride) covering the substrate is reduced. The ability of silicon to combine with nitrogen and fill the grain boundaries of the deposited titanium nitride is a mechanism that promotes improved barrier performance of titanium nitride.

  In accordance with the present invention, deposition and annealing of a material such as titanium nitride on the wafer is performed in the same manner as described above for a process that includes an oxidation step. Preferably, a 100 Å layer of titanium nitride is deposited. The thickness of the titanium nitride layer after annealing this material with a plasma containing a mixed gas of nitrogen and hydrogen is about 50 angstroms.

  The deposition and annealing of the titanium nitride material may be performed in either chamber 110A, 110B or 110C. Alternatively, another chamber or a group of chambers capable of performing the deposition step and the annealing step may be used. If chamber 110A, 110B or 110C is used, silicon stuffing may be performed in the same chamber where deposition and annealing were performed. As a result, the entire silicon stuffing process can be performed in situ.

After deposition and annealing, silicon stuffing is performed by exposing the annealed titanium nitride to silane (SiH ₄ ). Silane is flowed into chamber 110A for about 30 seconds at a flow rate of 30 sccm. During silane exposure, the chamber pressure is set to 1.2 Torr, the wafer support 116 is heated to 420 ° C., and nitrogen is flowed into the chamber 110A at a flow rate of 140 sccm. A 200 sccm argon purge inflow is employed. Following exposure to silane, an exhaust purge is performed to sweep residual SiH ₄ from chamber 10A and the supply line.

  During this exposure, silicon bonds to the titanium nitride surface and fills the grain boundaries of the deposited material. The stuffed silicon suppresses the diffusion of contact metal such as copper deposited thereafter.

  The steps of titanium nitride material deposition, annealing and silicon stuffing are repeated in succession until the film to be built is of the desired thickness. For the construction of a 200 Å film, titanium nitride deposition, annealing, and exposure are preferably performed a total of three times, and the titanium nitride deposited each time is a 100 Å layer. This results in the construction of a 150 Å thick titanium nitride layer stuffed with silicon. In order to reach the desired thickness of 200 Å, a final 100 Å titanium nitride cap layer is deposited and annealed to a thickness of 50 Å. The annealing of the titanium nitride cap layer may be performed using plasma containing both nitrogen and hydrogen as described above. This final deposited and annealed cap layer is not exposed to silane.

  The reason for not exposing the final portion of the deposited and annealed material to silane is due to the affinity of silane for oxygen. If silicon is introduced into the final surface cap of the titanium nitride film by exposure to silane, the resistivity of the film will be unacceptably high. After the film is capped with an annealed layer of titanium nitride, the resistivity of the film is about 520 μΩ-cm. If the top layer of titanium nitride is exposed to silane, the resistivity of the film will probably be very high.

  Rutherford backscattering spectroscopy analysis revealed that the film stuffed with silicon according to the present invention had the following characteristics. The Si content was 5 atomic percent, the Ti content was 35.2 atomic percent, the N content was 52.8 atomic percent, and the H content was 7 atomic percent. The Auger depth profile of a film formed according to the present invention is shown in FIG. According to this Auger depth profile, the nitrogen content and the titanium content are uniform, and the silicon content fluctuates. This is in line with the fact that the silicon-containing material to be capped with titanium nitride is 150 angstroms. I'm doing it.

  It should be noted that the above measurements and procedures are given as non-limiting examples of how to perform silicon stuffing according to the present invention. In another embodiment of the invention, the step of annealing the layer of material deposited on the substrate and the step of exposing the material to silane may be interchanged. As a result, a deposited material such as titanium nitride is first exposed to silane for silicon stuffing purposes, and then annealed using plasma to reduce the resistivity of the material. In addition, a deposition process other than CVD, such as sputtering, may be performed.

  As an alternative to silicon stuffing, a three-element silicified metal nitride such as titania silica carbonitride (TiSiCN) may be deposited instead of the titanium nitride material. The deposited silicon rich material can then be annealed to reduce the resistivity. Like the above process, deposition and annealing can be repeated to form a film with a desired thickness.

  In accordance with such embodiments of the present invention, a wafer is placed in a chamber in which a deposition process can be performed. This chamber may be any of chambers 110A, 110B or 110C capable of building a silicon rich film in situ. Alternatively, other chambers or chamber groups that can be used to perform the following steps for forming a silicon-rich film may be used.

  After placing the wafer in the chamber, titania silica carbonitride (TiSiCN) material is deposited on the wafer. This deposition operation may be performed using conventional thermal CVD using TDMAT. To introduce silicon, a volume of silane is flowed into the chamber. Compared to the volume used when depositing titanium nitride by CVD using TDMAT, it is accompanied by an equal volume of nitrogen diluent gas.

  In performing the deposition operation, the chamber pressure was set to 1.2 Torr, the wafer support temperature was set to 420 ° C., silane 10 sccm, He / TDMAT 70 sccm, and nitrogen dilution gas 90 sccm into the chamber. Let Argon purge is performed at a flow rate of 200 sccm. Deposition can be performed for 32 seconds to form a layer of material having a thickness of 100 angstroms. In the chemical vapor deposition of titanium nitride, silane is not used and the flow rate of nitrogen is 100 sccm.

  Following this deposition, TiSiCN is annealed using a nitrogen and hydrogen plasma as described above for processes involving oxygen stuffing. If it is desirable for the starting thickness of the deposited material to be 100 Å and the layer thickness to be 50 Å, this anneal includes an ion bombardment step that is performed for 20 seconds. Deposition and annealing are repeated in succession to build a film of the desired thickness. In one embodiment of the invention, a 200 Angstrom film is desirable. A layer of 100 Angstrom TiSiCN is deposited and then annealed to a layer of 50 Angstrom material. TiSiCN 100 angstrom deposition and annealing is performed four times to obtain the desired 200 angstrom film.

  In one example, the resulting 200 Angstrom film contained 15 atomic percent Si, 25.3 atomic percent Ti, 49.7 atomic percent N, and 10 atomic percent H by Rutherford backscattering spectroscopy. Indicated. The Auger depth profile of this film is shown in FIG. The Auger depth profile shows a uniform composition with a low carbon content of about 5 atomic percent and an oxygen content of 1 atomic percent. The resistivity of this film is 2,400 μΩ-cm. FIG. 47 shows a comparison in resistivity and composition between a 200 Å film formed using silicon stuffing and a 200 Å film formed by depositing titania silica carbonitride.

  The resistivity increases in exchange for obtaining a very silicon rich film to function as a diffusion barrier. A resistivity of 1,000 μΩ-cm is well tolerated as a diffusion barrier. The resistivity of the film may be reduced by reducing the amount of silane used in the deposition step. The best resistivity is obtained when silicon is stuffed into the layer of material after deposition and annealing, as described above. However, a diffusion barrier formed by stuffing silicon does not give the same strong deterrent effect as copper and a film formed by depositing a silicon-containing material. For example, a two-element metal nitride (such as titanium nitride) stuffed with silicon cannot prevent copper diffusion, and this also applies to a film constructed by depositing a three-element metal nitride silicide (such as TiSiCN). It is. The manufacturer of the integrated circuit can select a silicon enrichment method that best fits the manufacturer's requirements in film construction.

  It should also be noted that the deposition process employed in each of the silicon enrichment processes described above can be modified. Instead of chemical vapor deposition, other deposition processes such as sputtering may be used. Other ternary element metal nitride silicides than TiSiCN may be used in the embodiments of the present invention.

  Furthermore, the annealing step described above is not limited to using a plasma consisting only of nitrogen and hydrogen. Other plasma compositions that act to lower the resistivity of the deposited material may be used. An example of such a plasma is the plasma described above containing nitrogen, hydrogen and argon. This may be followed by annealing.

  In processes involving silicon stuffing by exposure to silane, this exposure step is not limited to receiving energy by heat. In an alternative embodiment of the invention, the plasma containing silicon ions can be generated by a silicon rich gas that is energized by an RF signal. Also, a bias may be applied to the wafer containing the material to be silicon stuffed to increase the impact of silicon on the material. When silicon stuffing is performed using plasma, the silicon stuffing may be performed before or after the material annealing step for reducing the resistivity.

  (C. Construction of film controlled by processor) The above-described material deposition, annealing, oxidation and silicon stuffing processes may be performed in a chamber controlled by a processor-based control unit. Reference numeral 48 denotes a control unit 600 that can be used in such a case. The control unit includes a processor unit 605, a memory 610, a mass storage device 620, an input control unit 670, and a display unit 650, all of which are connected to a control unit bus 625.

  The processor unit 605 may be a microprocessor or other engine capable of executing instructions stored in memory. The memory 610 may comprise a hard disk drive, random access memory (RAM), read only memory (ROM), a combination of RAM and ROM, or other memory. The memory 610 includes instructions that are executed by the processor unit 605 to prompt the execution of the process steps described above. The instructions in memory 610 may be in the form of program code. The program code can be adapted to any of a wide variety of programming languages. For example, the program code can be rewritten into C +, C ++, BASIC, Pascal, or various other languages.

  The mass storage device 620 stores data and instructions, and reads data and instructions from a processor-readable storage medium such as a magnetic disk or a magnetic tape. For example, the mass storage device 620 may be a hard disk drive, a floppy disk drive, a tape drive, or an optical disk drive. The mass storage device 620 stores and reads instructions according to instructions received from the processor unit. Data and instructions stored and read by the mass storage device 620 are used by the processor unit 605 to perform the process steps described above. First, data and instructions are read from the medium by mass storage device 620 and then transferred to memory 610 for use by processor unit 605.

  The display unit 650 provides information to the chamber operator in the form of a graphic display and alphanumeric characters under the control of the processor unit 605. The input control unit 670 couples a data input device, such as a keyboard, mouse, light pen, etc., to the control unit so that it can receive input from the chamber operator.

  The control unit bus 625 transfers data and control signals between all devices connected to the control unit bus 625. Here, the control unit bus is shown as one bus and directly connected to the device of the control unit 600, but the control unit bus 625 may be a set of buses. For example, the display unit 650, the input control unit 670 and the mass storage device 620 may be connected to the input-output peripheral bus, while the processor unit 605 and the memory 610 may be connected to the local processor bus. An output peripheral bus may be connected to form a control unit bus 625.

  The control unit 600 is connected to the elements of the chamber that are used to form the film on the substrate. Each such element may be connected to the control unit bus 625 to facilitate communication between the control unit 600 and these elements. These elements include a gas panel 52, a heating element such as a lamp 130, a pressure control unit 157, an RF source or source 62, 142, 143, 144, and a chamber temperature measurement device 140. In one embodiment of the present invention, the control unit 600 is the gas panel controller 50 required in the chambers 110A, 110B and 110C.

  The control unit 600 provides signals to these elements so that they perform the operations described above for the process steps of depositing materials, annealing, oxidizing and silicon stuffing on the substrate. The control unit 600 also receives signals from these elements to determine how to proceed with the control of execution of the aforementioned process steps. For example, the control unit 600 receives a signal from the temperature measurement device 140 and determines the amount of heat that the lamp 130 should provide to the chamber.

  FIG. 49 illustrates a sequence of process steps that can be performed by the processor unit 605 in response to instructions in the program code read from the memory 610. In starting the formation of the film on the substrate, a deposition step 700 is performed. In the deposition step 700, the processor unit 605 executes the instruction read from the memory 610. As a result of the execution of such instructions, the chamber elements operate to deposit a layer of material on the substrate as described above. For example, in response to the read instruction, the processor unit 605 causes the gas panel to supply precursor gas into the chamber, the lamp 130 heats the chamber, and the pressure control unit 157 sets the pressure in the chamber. Become.

  After the deposition element 700 is complete, the instructions read from the memory 610 cause the processor unit 605 to cause the chamber elements to perform an annealing step 701, such as one of the annealing processes described above. This annealing operation may include plasma annealing using any one of nitrogen, a mixed gas of nitrogen and hydrogen, and a mixed gas of nitrogen, hydrogen, and another gas (such as argon). Alternatively, the annealing step 701 may perform a continuous annealing step as described above.

  After completion of the annealing step 701, the control unit 600 is caused to perform an oxidation determination step 702 that determines whether or not an oxidation process step is performed. If not, step 703 reads an instruction from the memory and causes the processor unit 605 to determine whether to perform silicon stuffing. If silicon stuffing is not performed, the control unit 600 determines in step 706 whether another deposition operation should be performed. The deposition operation is performed until the thickness of the already deposited material is substantially equal to the desired film thickness. When the desired film thickness is reached, the process of building the film on the substrate is complete. Alternatively, a new deposition step 700 is performed.

  If it is determined in the oxidation determination step 702 that the oxidation is performed, the processor unit 605 causes the oxidation step 704 to be executed. In the oxidation step 704, the read instructions cause the processor unit 605 to cause the chamber elements to perform the operations necessary to perform the above-described deposition material oxidation process steps. This oxidation may be based on plasma or by heat. Once the oxidation step 704 is complete, the processor unit 605 determines whether a new deposition step 700 should be performed in step 706.

  If it is determined in step 703 to perform silicon stuffing, the process unit 605 causes the silicon stuffing step 705 to be executed. The processor unit 605 reads a silicon stuffing instruction in the memory 610 and executes it. In response to this command, the processor unit 605 activates the chamber elements in a manner that allows the silicon stuffing procedure described above to be performed. This silicon stuffing may be performed by exposing the deposited material to a silane gas energized by heat. Alternatively, silicon stuffing may be performed by exposing the deposited material to a silicon ion-containing environment generated by generating plasma using an RF signal. Once the silicon stuffing step 705 is complete, the deposition step 700 is repeated.

  FIG. 50 illustrates another sequence of process steps that the processor unit 605 may execute in response to program code instructions read from the memory 610. This sequence of process steps includes the same steps as shown in FIG. However, the order of the steps is changed, and the silicon stuffing step 705 is performed before the annealing step 701.

  Immediately after performing deposition step 700, processor unit 605 executes an instruction in step 703 to determine whether to perform silicon stuffing. If so, step 705 for silicon stuffing is performed, followed by step 701 for annealing. If not, annealing 701 is performed. After the annealing step 701, the processor unit 605 determines in step 702 whether to perform oxidation. If so, oxidation step 704 is performed. If not, it is determined in step 706 whether or not a new deposition is to be performed. Also, after performing oxidation step 704, such a determination is made in step 706. When a new deposition is required, the deposition step 700 is performed. Otherwise, the membrane construction process is complete.

  While the invention has been described with reference to specific embodiments so far, it will be appreciated that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention in the appended claims. It will be.

FIG. 3 illustrates an integrated circuit contact plug including a diffusion barrier. It is a figure which illustrates the contact hole of the integrated circuit blocked by the diffusion barrier. (A) is a diagram illustrating a chemical vapor deposition chamber, and (b) is a diagram illustrating a wafer support and support arm for the chamber shown in (a). It is a figure which illustrates a multi-chamber processing apparatus. FIG. 3 illustrates one specific example of a wafer processing chamber according to the present invention. It is a longitudinal cross-sectional view of the wafer support body and support arm which are shown by FIG. FIG. 7 is an enlarged view of the support arm supporting the wafer support in the cross-sectional view of the support arm of FIG. 6. FIG. 8 is a partial cross-sectional view taken along line 6-6 in FIG. (A) is a top view of the support arm shown in FIG. 6, (b) is a longitudinal cross-sectional view along line 7-7 in FIG. 9 (a). (A) is a top view of the thermocouple isolator of the support arm shown in FIG. 6, and (b) is a longitudinal sectional view taken along line 8-8 in FIG. 10 (a). (A) is a top view of the RF power strip isolator of the support arm shown in FIG. 6, and (b) is a front view that is a partial cross-sectional view of the isolator shown in FIG. 11 (a). FIG. 7 is a top view of a lower holding plate of the support arm of FIG. 6. It is sectional drawing which shows the detail in the support arm fixed end of FIG. FIG. 7 is a diagram representing details of a connector of an RF power strip disposed on the support arm of FIG. 6. (A)-(c) is a figure which illustrates the specific example of the matching network shown by FIG. FIG. 6 illustrates another specific example of a semiconductor wafer processing chamber according to the present invention. FIG. 5 illustrates yet another embodiment of a semiconductor wafer processing chamber according to the present invention. It is a graph with respect to time of the sheet resistance value about the titanium nitride film deposited using the conventional deposition process. It is a Rutherford backscattering spectrum chart of a titanium nitride film deposited on a silicon wafer using a conventional deposition process. FIG. It is a figure which shows Table II. It is a figure which shows Table III. It is a chart of Rutherford backscattering spectrum of a titanium nitride film deposited using chemical vapor deposition in which NF ₃ gas is introduced. 4 is a graph of Auger sputtering analysis of a titanium nitride film according to the present invention. It is a figure which shows Table IV. 4 is an Auger surface spectrum of elements of another titanium nitride film according to the present invention. 27 is a graph of atomic concentrations of various elements in the titanium nitride film of FIG. It is an Auger surface spectrum of the element of a control titanium nitride film. FIG. 29 is a graph of atomic concentrations of various elements in the control titanium nitride film of FIG. 28. 4 is an Auger surface spectrum of elements of another titanium nitride film according to the present invention. FIG. 31 is a graph of atomic concentrations of various elements in the titanium nitride film of FIG. 30. FIG. 2 is a graph illustrating oxygen absorption by a film produced in accordance with the present invention. (A)-(c) is a graph which illustrates reduction of the organic carbon content of the film | membrane performed according to this invention. (A)-(b) is a graph which shows that the film resistance of the via | veer and salicide contact formed according to this invention is improved. It is a graph which shows the resistivity of the film | membrane produced | generated by changing the number of cycles of deposition and a plasma processing. FIG. 5 is a graph plotting film resistivity and bias voltage as a function of plasma processing pressure. FIG. (A) is a graph showing the influence which annealing time and a frequency have on the resistivity of a film | membrane, (b) is a graph showing another example about the influence with respect to the film resistivity of annealing time. (A)-(b) is a graph of the Auger electron spectroscopy analysis depth profile about the titanium nitride film formed by depositing and annealing titanium nitride continuously. 4 is an X-ray diffraction graph for angular scanning of a conventional CVD titanium nitride layer 1000 Å thick deposited on a silicon wafer. 4 is an X-ray diffraction graph for angular scanning of a 1000 Å thick CVD titanium nitride layer deposited and annealed on a silicon wafer. It is a figure which shows Table VI. (A)-(b) is a graph which illustrates the chemical composition of the non-oxidation diffusion barrier (a) and the oxidation diffusion barrier (b) formed according to one specific example of the present invention. 3 is a graph illustrating diffusion barrier resistance characteristics formed according to an embodiment of the present invention. 4 is a graph illustrating an Auger depth profile of a film formed using silicon stuffing according to the present invention. 4 is a graph illustrating an Auger depth profile of a film formed by depositing a silicon-containing material according to the present invention. 47 is a graph comparing the resistivity and composition of the films shown in FIGS. 45 and 46. FIG. FIG. 3 is a block diagram illustrating a control unit for chamber control used to build a film on a substrate according to the present invention. 49 is a flowchart illustrating an operation sequence performed by the control unit of FIG. 48 according to an embodiment of the present invention. 49 is a flowchart illustrating a sequence of operations performed by the control unit of FIG. 48 according to another embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... CVD chamber, 12 ... Processing chamber, 14 ... Wafer, 16 ... Wafer support, 18 ... Disc, 20 ... Free end, 22 ... Support arm, 24 ... Fixed end, 26 ... Stem, 28 ... Displacement mechanism, 30 ... Lamp, 32 ... Window, 34 ... Hall, 36 ... Shower head, 38 ... Thermocouple, 40 ... Temperature measuring device, 42 ... Cable, 100 ... Diffusion barrier, 101 ... Silicon substrate, 102 ... Contact plug, 103 ... Contact hole, DESCRIPTION OF SYMBOLS 105 ... Conductive area | region, 106 ... Void, 110 ... Semiconductor wafer processing chamber, 112 ... Processing chamber, 114 ... Wafer, 116 ... Wafer support, 136 ... Shower head, 142 ... RF source.

Claims (10)

A method of constructing a metal nitride film on a wafer,
(A) forming the metal nitride film from a metallo-organic precursor on the wafer ,
(A1) depositing the metal nitride film on the wafer in a chamber;
(A2) treating the metal nitride film in a plasma containing nitrogen;
Comprising the steps of:
(B) exposing the metal nitride film to an environment containing silicon to form a metal nitride film stuffed with the silicon;
(C) forming a metal nitride cap layer on the silicon nitride stuffed metal nitride film of step (b);
With
The method wherein the cap layer is not exposed to an environment containing silicon. In between the front Symbol the steps as (a1) (a2), is not taken out the wafer from the chamber, The method according to claim 1.   The method of claim 1, wherein the environment of step (b) comprises silane. The method of claim 1 , wherein the nitrogen-containing plasma of step (a2) further contains hydrogen.   The method according to claim 4, wherein the nitrogen-to-hydrogen ratio contained in the nitrogen-containing plasma is between 3: 1 and 1: 2. It said step (a2) is,
( A2) processing the metal nitride film in a first plasma containing nitrogen and hydrogen, wherein the wafer is removed from the chamber between the step (a1) and the step (a2). Not further comprising a step,
The method of claim 1 , further comprising: (a3) after the step (a2), processing the metal nitride film in a second plasma consisting essentially of nitrogen and an inert gas.   The method of claim 6, wherein the inert gas of step (a3) is selected from the group of helium, argon and neon.   The method of claim 3, wherein step (b) is performed at a pressure of 1.2 Torr.   The method of claim 3, wherein step (b) is performed at a temperature of 420 ° C. The method of claim 1, wherein silicon is added to the metal nitride film during step (b).