JP4454566B2 - Program runaway monitoring circuit and method - Google Patents

Description

  The present invention relates to a technique for monitoring runaway of a program being executed on a program control processor.

  Various techniques for monitoring program runaway have been proposed. For example, Japanese Patent Application Laid-Open No. 63-298453 (Patent Document 1) does not depend on whether or not a single step of a program is executed, but includes a plurality of instruction code signatures of arbitrary steps and signature data obtained in advance. A program runaway monitoring circuit that detects runaway by comparing the two is disclosed. This runaway monitoring circuit has a linear feedback shift register (LFSR) for obtaining a signature of an executed instruction code, and an enable bit for judging whether or not the instruction code is taken into the LFSR is stored in the program memory. It has been added.

  In the runaway monitoring circuit disclosed in Japanese Patent Laid-Open No. 6-259288 (Patent Document 2), the next address is stored in advance with respect to the program address of the instruction of the CPU, and the next address and the CPU are actually generated. A runaway is detected when a mismatch occurs by always comparing the next program address.

  Japanese Patent Laid-Open No. 2000-57021 (Patent Document 3) provides a means for determining the operation state in the watchdog timer, and only when the watchdog timer is stopped by the standby control signal. A method for avoiding malfunction of the watchdog timer by stopping the supplied clock is disclosed.

JP-A-63-298453 JP-A-6-259288 JP 2000-57021 A

  The present invention provides a new program runaway monitoring method and circuit capable of reliably detecting a program runaway without depending on a watchdog timer or a single step of the program.

  According to the present invention, the presence or absence of a program runaway is detected using data on the bus used by the program control processor that is executing the program. For example, the information on the bus is read at a set time interval, the same information area is searched from the previous read information and the current read information, and the presence or absence of a program runaway is detected based on the search result.

A program runaway monitoring circuit according to the present invention includes bus information reading means for reading address information and data information on a bus used by a program control processor at a set timing, and a set of the read address information and data information as entry information. compares the first memory means and second memory means for storing alternately for each set timing, the first entry information and the second entry information stored in the second memory means being stored in the first memory means Comparison judging means for judging the presence or absence of the same information area, and monitoring means for monitoring the runaway of the program based on the judgment result of the comparison judging means.

  The bus information reading means can read address information and data information on the bus in accordance with an operation clock of the program control processor in response to an enable signal on the bus.

  The monitoring unit can detect a program runaway when a determination result indicating the presence of the same information area by the comparison determination unit occurs a plurality of times. Preferably, the monitoring means has counting means for counting the number of determination results indicating the presence of the same information area, and detects a program runaway when the count value exceeds a predetermined threshold value. In particular, it is desirable that the predetermined threshold is set to a value that can avoid misidentification of program runaway.

The program runaway monitoring method according to the present invention sequentially reads a set of address information and data information on the bus used by the program control processor at the timing set as entry information, and the first entry information read at the previous timing and this time The second entry information read at this timing is compared to search for the same information area, and the program runaway is monitored based on the presence or absence of the same information area.

According to the present invention, it is possible to detect the presence or absence of a program runaway using a set of address information and data information on a bus used by a program control processor as entry information . That is, the entry information on the bus read at the previous timing is compared with the entry information read at the current timing, and the program is determined based on whether or not the same information area exists between the information. Reliable monitoring of runaway is possible.

  In particular, by determining the program runaway when the determination indicating the presence of the same information area continues for a number of times exceeding a predetermined threshold, the detection accuracy of the runaway can be improved and the misunderstanding of the runaway can be reliably avoided. The reliability of runaway monitoring can be improved.

  FIG. 1 is a block diagram of a program runaway monitoring circuit according to an embodiment of the present invention. A CPU (Central Processing Unit) 1 is a program control processor that operates according to pre-programmed instructions, and receives various information such as control signals including address and data information B, CPU operation clock C, and enable signal A through a bus. Forward.

  The timer unit 2 provided in the program runaway monitoring circuit performs time measurement according to a clock supplied from the outside, and outputs a start notification to the reading unit 3 and stops time measurement when a time set from the outside elapses. The time measurement of the timer unit 2 is resumed by a notice of allowable capacity arrival from the memory unit 4 or 5 described later.

  The reading unit 3 reads the address and data information B from the bus according to the CPU operation clock C and the enable signal A. The read address and data information are stored in the memory unit 4 or the memory unit 5 that are alternately selected for each reading operation. The reading operation of the reading unit 3 is started by a start notification from the timer unit 2 and stopped by a notification of reaching an allowable capacity from the memory unit 4 or 5.

  The memory unit 4 and the memory unit 5 are memories each having a preset allowable capacity, and store the address and data information read by the memory unit 4 or 5 selected by the enable signal from the reading unit 3. When the memory units 4 and 5 accumulate the data up to the allowable capacity, they output an allowable capacity arrival notification to the timer unit 2, the reading unit 3, and the comparison determination unit 6, respectively.

  The comparison determination unit 6 compares the previous and current addresses and data information B stored in the memory unit 4 and the memory unit 5, respectively, and searches for the same information stored in the same order. If the same information in the same order exists, the comparison determination unit 6 outputs the same information detection notification to the counter monitoring unit 7.

  The counter monitoring unit 7 counts the number of identical information detection notifications, and outputs an alarm to the outside when the count value exceeds a predetermined threshold given from the outside.

  FIG. 2 is a state transition diagram for explaining the operation of the program runaway monitoring circuit according to the present embodiment.

  State S10: First, the timer unit 2 is activated and starts time measurement according to the external clock. When the set time elapses, the timer unit 2 stops time measurement and outputs a start notification.

  State S20: The reading unit 3 is activated by the start notification. The reading unit 3 reads the address and data information B from the bus according to the CPU operation clock C at a timing according to the enable signal A. The reading unit 3 selects a memory unit different from the previously selected memory unit, and stores the read address and data information in the selected memory unit 4 or 5.

  State S30: When an allowable capacity arrival notification is input from the memory unit 4 or 5, the reading unit 3 stops the reading operation. Then, in order to read the next information, the process returns to the state S10, the timer unit 2 is activated, and the above-described states S10 to S30 are repeated while alternately selecting the memory units 4 and 5. By executing the reading operation in this way, the previous reading information and the current reading information are alternately stored in the memory units 4 and 5.

  State S40: When an allowable capacity arrival notification is input from the memory unit 4 or 5, the comparison / determination unit 6 compares the previous and current addresses and the data information B stored in the memory unit 4 and the memory unit 5, respectively, in the same order. The presence or absence of the same stored data is determined. When the same information in the same order is detected, or when the information stored in the upper limit of the memory unit 4 or 5 matches, the comparison determination unit 6 outputs the same information detection notification to the counter monitoring unit 7. When the same data in the same order is detected, or when the address upper limit value of the memory unit 4 or 5 is reached during the search, the comparison / determination unit 6 stops the search operation. Details of the search operation of the comparison / determination unit 6 will be described later.

  State S50: The counter monitoring unit 7 monitors the occurrence of the same information detection notification and counts the number of times. The count value is compared with a predetermined threshold value, and when the count number exceeds the threshold value, the counter monitoring unit 7 determines that the program is out of control and notifies an alarm to the outside.

  Note that the period of the reading operation can be adjusted according to the set time of the timer unit 2, and the program runaway can be monitored at an appropriate frequency.

FIG. 3 is a schematic diagram for explaining the search operation of the comparison determination unit 6 in the present embodiment. The memory unit 4 has addresses (A1 ₀ , A1 ₁ , A1 ₂ ,... A1 _n ) read from the bus last time and data (D1 ₀ , D1 ₁ , D1 ₂ ,... D1 _n ) corresponding to the addresses. Are stored in order from the lower limit (Start) to the upper limit (End) of the memory unit 4. The memory unit 5 stores addresses (B1 ₀ , B1 ₁ , B1 ₂ ,... B1 _m ) read this time and data (E1 ₀ , E1 ₁ , E1 ₂ ,... E1 _m ) corresponding to the addresses. It is assumed that data are sequentially accumulated from the lower limit (Start) to the upper limit (End) of the unit 5. Here, m = n.

  The comparison determination unit 6 sequentially reads and compares the entry information from the memory unit 4 and the memory unit 5 and searches for the same data in the same order. Next, assuming the state of the memory shown in FIG. 3, the search operation of the comparison / determination unit 6 will be described in detail.

FIG. 4 is a flowchart schematically showing the flow of the search operation of the comparison / determination unit 6. When the comparison determination unit 6 inputs an allowable capacity arrival notification from the memory unit 5 in which the current read information is stored (step S101), the first entry information (A1 ₀ , D1 ₀ ) in the memory unit 4 in which the previous read information is stored. ) To search whether the same information exists in the memory unit 5. If not, the next entry information (A1 ₁ , D1 ₁ ) is read and the same search is repeated. Similarly, the above search is repeated until the same information is detected while sequentially reading data from the memory unit 4 with the entry information (A1 _n , D1 _n ) as the upper limit (step S102).

It is assumed that the entry information (A1 _i , D1 _i ) in the memory unit 4 matches the entry information (B1 _j , E1 _j ) in the memory unit 5 by this search. In the example of FIG. 3, it is assumed that the same information as the entry information (A1 ₃ , D1 ₃ ) in the memory unit 4 exists as entry information (B1 ₁ , E1 ₁ ) in the memory unit 5.

When this match is detected, the comparison / determination unit 6 reads the entry information following the matched entry information from the memory units 4 and 5, respectively. Here, the entry information (A1 _{i + 1} , D1 _{i + 1} ) in the memory unit 4 and the entry information (B1 _{j + 1} , E1 _{j + 1} ) in the memory unit 5 are read out respectively to determine whether or not they are the same. Determined. If (A1 _{i + 1} , D1 _{i + 1} ) = (B1 _{j + 1} , E1 _{j + 1} ), further subsequent data are read from the memory units 4 and 5, respectively. Here, the information (A1 _{i + 2} , D1 _{i + 2} ) in the memory unit 4 and the information (B1 _{j + 2} , E1 _{j + 2} ) in the memory unit 5 are read out to determine whether or not they are the same. The If (A1 _{i + 1} , D1 _{i + 1} ) ≠ (B1 _{j + 1} , E1 _{j + 1} ), the search is stopped at this point (step S105). Similarly, the operation of comparing the next entry information if it is the same is repeated until any entry information reaches the upper limit of the memory unit, and if it is not the same, the search is stopped at that time (step S103). .

When the entry information of one memory unit reaches the upper limit in this way, it is determined that the same entry information is stored in both memory units in the same order, and the same information detection notification is sent to the count monitoring unit 7 (step S1). S104). For example, as shown in FIG. 3, the entry information (A1 ₃ , D1 ₃ ) to (A1 _n , D1 _n ) of the area a of the memory unit 4 and the entry information (B1 ₁ , E1 ₁ ) of the area b of the memory unit 5 ~ (B1 _(m-2) , E1 _(m-2) ) are determined to match.

  If the upper limit entry information in one memory unit matches in step S102, the upper limit entry has been reached, so that it is determined as “all match” in step S103, and the same information detection notification is output to the count monitoring unit 7 Will be. However, this coincidence is not actually the same information detection. Therefore, it is desirable to avoid a situation in which an alarm is output to the outside only by such an identical information detection notification. Therefore, in this embodiment, a count threshold is set in the count monitoring unit 7 so that an alarm is not output unless the number of identical information detection notifications exceeds the set threshold.

  Thus, setting the threshold value in the count monitoring unit 7 has an advantage of improving the reliability of the runaway monitoring. When a program runaway occurs, the same information detection notification should be repeatedly output to the count monitoring unit 7, so setting the count threshold to an appropriate value can avoid misidentification of the program runaway, It is also possible to detect actual runaway quickly and reliably.

  In the above embodiment, as shown in step S103, the operation of comparing the next entry information if it is the same is repeated until any entry information reaches the upper limit of the memory unit. Even before reaching, it may be determined that “all match” if the same information area of a predetermined length continues.

  The program runaway monitoring circuit and method according to the present invention can be applied to a computer or an information processing apparatus using a CPU.

It is a block diagram of the program runaway monitoring circuit by one Embodiment of this invention. It is a state transition diagram for demonstrating operation | movement of the program runaway monitoring circuit by this embodiment. It is a schematic diagram for demonstrating the search operation | movement of the comparison determination part 6 in this embodiment. 7 is a flowchart schematically showing the flow of a search operation of a comparison / determination unit 6.

Explanation of symbols

1 CPU
2 Reading unit 3 Timer unit 4 Memory unit 5 Memory unit 6 Comparison determination unit 7 Count monitoring unit

Claims (13)

In the circuit that monitors the runaway of the program running on the program control processor,
Bus information reading means for reading address information and data information on the bus used by the program control processor at a set timing;
First memory means and second memory means for alternately storing the set of the read address information and data information as entry information at each set timing;
Comparison determination means for comparing the first entry information stored in the first memory means and the second entry information stored in the second memory means to determine the presence or absence of the same information area;
Monitoring means for monitoring program runaway based on the determination result of the comparison determination means;
A program runaway monitoring circuit comprising:   2. The program runaway monitoring according to claim 1, wherein the bus information reading means reads address information and data information on the bus according to an operation clock of the program control processor in response to an enable signal on the bus. circuit.   3. The program runaway monitoring circuit according to claim 1, wherein the same information area is an area in which a plurality of pieces of the same information are arranged in the same order.   The program according to any one of claims 1 to 3, wherein the monitoring unit detects a program runaway when a determination result indicating the presence of the same information area is generated a plurality of times by the comparison determination unit. Runaway monitoring circuit.   The monitoring means has counting means for counting the number of determination results indicating the presence of the same information area, and detects a program runaway when the count value exceeds a predetermined threshold value. The program runaway monitoring circuit according to claim 4.   6. The program runaway monitoring circuit according to claim 5, wherein the predetermined threshold value is set to a value that can prevent erroneous recognition of program runaway. In a method for monitoring runaway of a program running on a program control processor,
A set of address information and data information on the bus used by the program control processor is sequentially read at the timing set as entry information ,
The first entry information read at the previous timing and the second entry information read at the current timing are compared to search for the same information area,
Monitor the program runaway depending on the presence or absence of the same information area,
A program runaway monitoring method characterized by the above.   8. The program runaway monitoring method according to claim 7, wherein the same information area is an area in which a plurality of the same information is arranged in the same order.   9. The program runaway monitoring method according to claim 7 or 8, wherein a program runaway is detected when the same information area is searched a plurality of times.   10. The program runaway monitoring method according to claim 9, wherein a program runaway is detected when the same information area is searched a number of times exceeding a predetermined threshold. 11. The program runaway monitoring method according to claim 10, wherein the predetermined threshold value is set to a value that can prevent misperception of program runaway.   An information processing apparatus comprising the program runaway monitoring circuit according to claim 1.   An information processing apparatus adopting the program runaway monitoring method according to any one of claims 7-11.

Images