JP2020140592A - Information processing system - Google Patents

Abstract

To enable highly accurate detection of occurrence of an abnormal state in which an arithmetic processing unit to be monitored falls into an infinite loop, as compared with a case where a program counter value is simply monitored.SOLUTION: A control unit 31 receives, via an input unit 34, a confirmation signal transmitted from another CPU to be monitored. The control unit 31 reads, when a preset confirmation signal cannot be received from a CPU to be monitored for a preset period or longer, via the input unit 34, the program counter value from the CPU to be monitored. Then, the control unit 31 executes, when the read program counter value is periodically repeating a same change pattern, processing for returning the CPU to be monitored to a normal state.SELECTED DRAWING: Figure 2

Description

The present invention relates to an information processing system.

In Patent Document 1, when a match between a previously executed program address and a current program execution address is detected, whether or not the matching interval is equal is detected, and when an equal interval program execution address match is detected, , A runaway detection method is disclosed in which the number of repetitions of the match is counted, and when the count value exceeds a predetermined value, it is detected as a runaway state in an infinite loop.

Patent Document 2 states that in a dual processor system, a common memory provided between two processors can be used to autonomously recover to some extent even if a failure occurs in any of the processors so that the system function can be recovered. The trouble management method described above is disclosed.

Japanese Unexamined Patent Publication No. 10-161908 Japanese Unexamined Patent Publication No. 10-269097

An object of the present invention is information capable of detecting the occurrence of an abnormal state in which the arithmetic processing unit to be monitored falls into an infinite loop with higher accuracy than in the case of simply monitoring the value of the program counter. It is to provide a processing system.

The present invention according to claim 1 has a plurality of arithmetic processing units.
At least one of the plurality of arithmetic processing units
A receiving means for receiving a confirmation signal transmitted from the arithmetic processing unit to be monitored, and
A reading means for reading the value of the program counter in the arithmetic processing unit to be monitored, and
When the preset confirmation signal cannot be received from the arithmetic processing unit to be monitored for more than a preset period, the reading means reads the value of the program counter from the arithmetic processing unit to be monitored, and the program counter of the program counter is read. It is an information processing system provided with an execution means for executing a process for returning a monitored arithmetic processing unit to a normal state when a change pattern having the same value is periodically repeated.

The present invention according to claim 2 is to be monitored when the cycle in which the execution means repeats a change pattern in which the value of the program counter read from the arithmetic processing unit to be monitored has the same change pattern is shorter than a preset period. The information processing system according to claim 1, wherein the processing for returning the arithmetic processing unit to the normal state is executed.

The present invention according to claim 3 is the case where the fluctuation range when the value of the program counter read from the arithmetic processing unit to be monitored repeats the same change pattern is narrower than the preset value. The information processing system according to claim 1, wherein a process for returning the arithmetic processing unit to be monitored to a normal state is executed.

In the present invention according to claim 4, the number of repetitions when the value of the program counter read from the arithmetic processing unit to be monitored repeats the same change pattern by the execution means is equal to or more than a preset value. The information processing system according to claim 1, wherein the processing for returning the monitored arithmetic processing unit to a normal state is executed.

The present invention according to claim 5 is the information processing system according to any one of claims 1 to 4, wherein the executing means returns to a normal state by resetting the arithmetic processing unit to be monitored.

According to the sixth aspect of the present invention, the executing means returns to a normal state by rewriting the value of the program counter of the arithmetic processing unit to be monitored to the address in which the instruction for executing the processing for returning is stored. The information processing system according to any one of claims 1 to 4.

According to the seventh aspect of the present invention, before the return processing is executed by the execution means, the operating state is determined from the arithmetic processing unit determined to periodically repeat the same change pattern of the program counter value. The information processing system according to any one of claims 1 to 6, further comprising an acquisition means for acquiring the recorded history information.

According to the eighth aspect of the present invention, each of the plurality of arithmetic processing units stores information indicating an area in which an instruction to be executed next is stored as a value of a program counter, and a plurality of instructions stored in advance. The information processing system according to any one of claims 1 to 7, which is an arithmetic processing unit that is sequentially executed.

In the present invention according to claim 9, the plurality of arithmetic processing units are two arithmetic processing units, and in each of the two arithmetic processing units, one arithmetic processing unit monitors the other arithmetic processing unit. The information processing system according to claim 1, wherein a process for returning to a normal state by the other arithmetic processing unit is executed when one of the arithmetic processing units becomes an abnormal state by performing mutual monitoring. is there.

According to the first aspect of the present invention, the occurrence of an abnormal state in which the arithmetic processing unit to be monitored falls into an infinite loop is detected with high accuracy as compared with the case where the value of the program counter is simply monitored. It is possible to provide an information processing system capable of providing an information processing system.

According to the second aspect of the present invention, it is possible to provide an information processing system capable of preventing a normal operation from being erroneously determined as an abnormal state in an infinite loop.

According to the third aspect of the present invention, it is possible to provide an information processing system capable of preventing a normal operation from being erroneously determined as an abnormal state in an infinite loop.

According to the fourth aspect of the present invention, it is possible to provide an information processing system capable of preventing a normal operation from being erroneously determined as an abnormal state in an infinite loop.

According to the fifth aspect of the present invention, it is possible to provide an information processing system capable of returning to a normal state even when the arithmetic processing unit to be monitored falls into an infinite loop.

According to the sixth aspect of the present invention, it is possible to provide an information processing system capable of returning to a normal state without resetting even when the arithmetic processing unit to be monitored falls into an infinite loop.

According to the seventh aspect of the present invention, it is possible to clarify the cause of the monitored arithmetic processing unit falling into an infinite loop even after the monitored arithmetic processing unit is returned to a normal state. Information processing system can be provided.

According to the eighth aspect of the present invention, the occurrence of an abnormal state in which the arithmetic processing unit to be monitored falls into an infinite loop is detected with high accuracy as compared with the case where the value of the program counter is simply monitored. It is possible to provide an information processing system capable of providing an information processing system.

According to the ninth aspect of the present invention, when two arithmetic processing units monitor each other and perform mutual monitoring, the occurrence of an abnormal state in which one of the arithmetic processing units falls into an infinite loop is simply generated. It is possible to provide an information processing system capable of detecting with high accuracy as compared with the case of only monitoring the value of the program counter.

It is a figure which shows the system structure of the information processing system 10 of one Embodiment of this invention. It is a block diagram which shows the hardware structure of the CPU 20 in one Embodiment of this invention. It is a flowchart for demonstrating operation of CPU 20 of one Embodiment of this invention. It is a figure which shows the state when the CPU 20B falls into an infinite loop and becomes an abnormal state. It is a figure which shows how the CPU 20A which entered the check mode reads the value of the program counter 33B from the CPU 20B. It is a figure which shows an example of the case where the value of a program counter repeats the same change pattern periodically. It is a figure which shows a mode that the CPU 20A executes a reset process after acquiring the log information 37B from the CPU 20B.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a system configuration of an information processing system 10 according to an embodiment of the present invention.

As shown in FIG. 1, the information processing system of the present embodiment has two CPUs 20A and 20B which are arithmetic processing devices.

The CPUs 20A and 20B in the present embodiment are executing preset different processes. According to the two-CPU configuration such as the information processing system 10 of the present embodiment, there is an advantage that the processing efficiency can be improved by the division of roles and the load distribution, so that a system that requires high real-time performance can be obtained. It is an advantageous configuration when it is realized.

In a system having such a CPU, if the program executing the CPU cannot get out of the loop processing for some reason and falls into an infinite loop in which the same loop processing is continuously executed forever, the system Will hang up. Then, when the system is in such a hang-up state, the system does not accept operations by the user from the outside and cannot return to the normal state unless the main power supply is once turned off and reset.

In addition, when the system falls into such an infinite loop state, it does not accept operations from the outside, so it is not possible to acquire log information and clarify the cause. For this reason, it generally takes time to analyze a defect caused by an infinite loop.

The CPUs 20A and 20B in the present embodiment each monitor the other CPU and constantly mutually monitor whether or not the other CPU is in an abnormal state in an infinite loop.

In order to perform this mutual monitoring, the CPUs 20A and 20B periodically output preset confirmation signals to the other CPU at preset intervals such as, for example, 5 second intervals.

FIG. 1 shows a case where the CPU 20A outputs an 8-bit confirmation signal of 1101 1100 to the CPU 20B and the CPU 20B outputs an 8-bit confirmation signal of 1010 1001 to the CPU 20A.

Note that FIG. 1 shows a configuration in which 8-bit confirmation signals are mutually transmitted, but the confirmation signal is not limited to such a signal, and what kind of information should be used as the confirmation signal. You can do it. For example, when different identification numbers are assigned to each CPU, each CPU may output its own identification number as a confirmation signal.

Next, the hardware configurations of the CPUs 20A and 20B will be described with reference to FIG. Since the basic configurations of the CPUs 20A and 20B are the same, they are simply expressed as the CPU 20 when explaining the common configurations of the CPUs 20A and 20B.

As shown in FIG. 2, the CPU 20 includes a control unit 31, an instruction code storage unit 32, a program counter 33, an input unit 34, an output unit 35, and an internal memory 36. Further, the internal memory 36 stores log information 37, which is history information recording the current operating state of the CPU 20.

The CPU 20 is an arithmetic processing unit that sequentially executes a plurality of pre-stored instruction codes while storing information indicating an area in which an instruction code to be executed next is stored as a value of a program counter.

The control unit 31 performs various controls by sequentially reading and executing a plurality of instruction codes, that is, programs stored in the instruction code storage unit 32. Then, the program counter 33 stores information indicating an area in which the instruction code to be executed next is stored.

The input unit 34 inputs a signal from the outside of the CPU 20 based on the control by the control unit 31. The output unit 35 outputs a signal to the outside of the CPU 20 based on the control by the control unit 31.

The control unit 31 outputs a preset confirmation signal to the other CPU via the output unit 35. Further, the control unit 31 receives a confirmation signal transmitted from the other CPU to be monitored via the input unit 34.

The control unit 31 is configured so that the value of the program counter in the CPU to be monitored can be read out via the input unit 34.

Then, when the control unit 31 cannot receive the preset confirmation signal from the monitored CPU for a predetermined period or longer, the control unit 31 reads the value of the program counter from the monitored CPU via the input unit 34. .. For example, when the confirmation signal is set to be output at 5-second intervals, when the confirmation signal is not output from the monitored CPU for 10 seconds or more, the value of the program counter is output from the monitored CPU via the input unit 34. read out.

Then, when the read program counter value is periodically repeating the same change pattern, the control unit 31 executes a process for returning the monitored CPU to a normal state.

Specifically, the control unit 31 returns to a normal state by resetting the CPU to be monitored. Alternatively, the control unit 31 may restore the normal state by rewriting the value of the program counter of the CPU to be monitored to the address in which the instruction for executing the restoration process is stored.

The control unit 31 repeats the change pattern with the same program counter value when determining whether or not the program counter value read from the monitored CPU periodically repeats the same change pattern. When the cycle is shorter than the preset period, the process for returning the monitored CPU to the normal state may be executed.

Further, when the control unit 31 determines whether or not the change pattern of the program counter read from the monitored CPU periodically repeats the same change pattern, the control unit 31 repeats the change pattern of the same program counter value. When the fluctuation range during the program is narrower than the preset value, a process for returning the monitored CPU to a normal state may be executed.

Further, when the value of the program counter read from the CPU to be monitored becomes equal to or more than a preset value when the same change pattern is repeated, the control unit 31 normalizes the CPU to be monitored. The process for returning to the normal state may be executed.

Then, after returning the CPU that has fallen into the infinite loop state to the normal state, in order to clarify the cause of the fall into the infinite loop state, the control unit 31 sets the program counter before executing the return process. The log information 37 that records the operating state is acquired from the CPU that is determined to periodically repeat the change pattern having the same value.

Then, after acquiring the log information 37, the control unit 31 executes a process for returning the CPU that has fallen into the infinite loop state to the normal state.

Next, the operation of the information processing system of the present embodiment will be described in detail with reference to the drawings.

First, the operation of the CPU 20 of the present embodiment will be described with reference to the flowchart of FIG.

In the following description, as an example, as shown in FIG. 4, a case where the CPU 20B falls into an infinite loop and becomes an abnormal state will be described. FIG. 4 shows how the confirmation signal is not transmitted from the CPU 20B to the CPU 20A due to the CPU 20B falling into an infinite loop.

In step S101, the CPU 20A continuously receives the confirmation signal output from the CPU 20B, and confirms that the CPU 20B is in a normal state by receiving the confirmation signal at least once within a preset period. Continue to do.

Then, when the CPU 20A cannot receive the preset confirmation signal from the monitored CPU B for a period longer than the preset period in step S101, the operation mode is set to the check mode in step S102.

In this check mode, the CPU 20A reads the value of the program counter 33B from the CPU 20B as shown in FIG. In the following description, when the configuration of the CPU 20B is described, the characters B are added to the reference numerals shown in FIG.

Then, in step S104, the CPU 20A determines whether or not the value of the program counter read from the CPU 20B periodically repeats the same change pattern.

The CPU 20A observes a change in the value of the program counter for a sufficient period of time when determining whether or not the change pattern in which the value of the program counter is the same is periodically repeated.

FIG. 6 shows an example in which the value of the program counter periodically repeats the same change pattern.

With reference to the change pattern example shown in FIG. 6, it is shown that the same change pattern is repeated with the same period and the same fluctuation width. In order to detect the cycle of this change pattern, the cycle of the change pattern can be detected by measuring the period during which the same value appears.

When the CPU 20B falls into an infinite loop state, such the same change pattern will be repeated forever. Therefore, when the CPU 20A detects in step S104 that the same change pattern is periodically repeated a plurality of times in the value of such a program counter, the CPU 20B determines that the CPU 20B is in an infinite loop state.

Then, the CPU 20A acquires the log information 37B from the CPU 20B in step S105, and executes the reset process of the CPU 20B in step S106. FIG. 7 shows how the CPU 20A executes the reset process after acquiring the log information 37B from the CPU 20B.

In addition, in order for the CPU 20A to return the CPU 20B in the infinite loop state to the normal state, the infinite loop may be forcibly terminated by rewriting the value of the program counter instead of performing the reset process. ..

In the present embodiment, after first confirming that the confirmation signal is no longer output from the CPU to be monitored, it is determined whether or not the program value periodically repeats the same change pattern. The reason for doing this is that even in a normal state that is not in an infinite loop state, the value of the program counter may periodically transition in the same change pattern, so only the value of the program counter This is because there is a possibility of making an erroneous judgment if the judgment is made with.

That is, the CPU to be monitored enters an infinite loop state only after detecting both that the confirmation signal is not output for a preset time or longer and that the value of the program counter repeats the same change pattern periodically. By determining that the device has fallen, the possibility of the above-mentioned erroneous determination can be reduced.

Further, the process for determining whether or not a confirmation signal is output is compared with the process for determining whether or not the same change pattern of the program counter value is periodically repeated by the monitoring CPU. The processing load is small for. Therefore, normally, monitoring is performed only by the confirmation signal, and the value of the program counter is monitored only after the confirmation signal cannot be confirmed, so that the processing load for monitoring can be suppressed to a low level.

In this embodiment, the monitoring CPU confirms that the confirmation signal is no longer output from the monitored CPU, enters the check mode, reads the value of the program counter of the monitored CPU, and performs an infinite loop. Although it was determined whether or not it was in a state, the determination order may be changed.

That is, when the monitoring CPU reads the value of the program counter of the CPU to be monitored and determines that the same change pattern is periodically repeated in a normal state, the check mode is entered and the monitor is to be monitored. After confirming that the confirmation signal is no longer output from the CPU, it may be finally determined that the state is in an infinite loop.

[Modification example]
In the above embodiment, the configuration in which the two CPUs 20A and 20B mutually monitor each other has been described, but the present invention is not limited to this, and at least one CPU among the plurality of CPUs is the other CPU. The present invention can be similarly applied even in the case of a configuration in which monitoring is performed as a monitoring target.

Further, in an information processing system composed of three or more CPUs, the present invention can be applied to a case where each CPU monitors another CPU.

10 Information processing system 20, 20A, 20B CPU
31 Control unit 32 Instruction code storage unit 33 Program counter 34 Input unit 35 Output unit 36 Internal memory 37 Log information

Claims (9)

It has multiple arithmetic processing units
At least one of the plurality of arithmetic processing units
A receiving means for receiving a confirmation signal transmitted from the arithmetic processing unit to be monitored, and
A reading means for reading the value of the program counter in the arithmetic processing unit to be monitored, and
When the preset confirmation signal cannot be received from the arithmetic processing unit to be monitored for more than a preset period, the reading means reads the value of the program counter from the arithmetic processing unit to be monitored, and the program counter of the program counter is read. When the change pattern with the same value is periodically repeated, the execution means for executing the process for returning the monitored arithmetic processing unit to the normal state and
Information processing system equipped with. When the cycle in which the execution means repeats the same change pattern of the program counter value read from the monitored arithmetic processing unit is shorter than a preset period, the monitored arithmetic processing unit is put into a normal state. The information processing system according to claim 1, which executes a process for restoring. When the value of the program counter read from the arithmetic processing unit to be monitored by the execution means is narrower than the preset value when the value of the program counter repeats the same change pattern, the arithmetic processing unit to be monitored is used. The information processing system according to claim 1, wherein a process for returning to a normal state is executed. The execution means is the arithmetic processing unit to be monitored when the value of the program counter read from the arithmetic processing unit to be monitored becomes equal to or more than a preset value when the same change pattern is repeated. The information processing system according to claim 1, wherein a process for returning the CPU to a normal state is executed. The information processing system according to any one of claims 1 to 4, wherein the executing means returns to a normal state by resetting the arithmetic processing unit to be monitored. Any one of claims 1 to 4 in which the executing means rewrites the value of the program counter of the arithmetic processing unit to be monitored to the address in which the instruction for executing the process for returning is stored, thereby returning to the normal state. The information processing system described. Acquisition means for acquiring history information recording an operating state from an arithmetic processing unit determined to periodically repeat a change pattern having the same program counter value before the return process is executed by the execution means. The information processing system according to any one of claims 1 to 6, further comprising. The plurality of arithmetic processing units are arithmetic processing units that sequentially execute a plurality of pre-stored instructions while storing information indicating an area in which an instruction to be executed next is stored as a value of a program counter. The information processing system according to any one of Items 1 to 7. The plurality of arithmetic processing units are two arithmetic processing units, and each of the two arithmetic processing units performs mutual monitoring in which one arithmetic processing unit monitors the other arithmetic processing unit. The information processing system according to claim 1, wherein when one arithmetic processing unit goes into an abnormal state, the other arithmetic processing unit executes a process for returning to the normal state.

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