JP4451703B2 - Programmable logic device - Google Patents

Description

  The present invention relates to a programmable logic device, and more particularly to a programmable logic device that operates as a predetermined logic circuit in accordance with configuration information given from the outside.

  A programmable logic device is an integrated circuit that operates as a desired logic circuit by inputting configuration information representing information on the positions and wirings of elements constituting the circuit outside the manufacturing process. Usually, the configuration information is stored in an external storage medium (for example, a non-volatile memory), and the programmable logic device is set by supplying the configuration information from the external storage medium to the programmable logic device as necessary. Can be rewritten. By using a programmable logic device, a plurality of logic circuits can be realized by one programmable logic device, and a device including the logic circuit can be downsized. Programmable logic devices are used, for example, in communication base stations that perform communication by switching a plurality of communication methods.

The programmable logic device has a problem that when an external storage medium storing configuration information is duplicated, it is possible to duplicate a programmable logic device that performs the same operation. Therefore, configuration information is usually encrypted with an encryption key. The programmable logic device stores a decryption key for decrypting the encrypted configuration information. Thereby, unauthorized duplication of the configuration information and the programmable logic device can be prevented. As a method of storing the decryption key in the programmable logic device, for example, as described in Patent Document 1, a method of storing in an EEPROM (Electrically Erasable Programmable Read Only Memory) in the programmable logic device is known.
JP 2002-50956 A

  However, the conventional programmable logic device described in Patent Document 1 can read the decryption key by applying a probe or the like to the EEPROM, and is not sufficient as a countermeasure against unauthorized duplication of configuration information. . In addition, decoded configuration information is stored in a memory (hereinafter referred to as a configuration memory) that stores configuration information built in the programmable logic device. Therefore, there is also a problem that the configuration information can be illegally copied by directly reading the configuration information decoded from here.

  Therefore, an object of the present invention is to provide a programmable logic device in which it is difficult to read a decryption key and a configuration memory from the outside.

  A programmable logic device of the present invention that solves the above problems includes a storage circuit including a ferroelectric capacitor for storing a decryption key for decrypting encrypted configuration information, and a decryption key stored in the storage circuit. A decryption circuit for decrypting the encrypted configuration information, a configuration memory for storing the configuration information decrypted by the decryption circuit, and a predetermined logic according to the configuration information stored in the configuration memory. A reconfigurable circuit that operates as a circuit, a read voltage supply circuit that applies a read voltage to the ferroelectric capacitor, one end of the ferroelectric capacitor and a read voltage supply circuit, and a decryption key output from the storage circuit Cover the path of the signal containing information And a protection wiring.

  The programmable logic device of the present invention may include a current detection circuit that converts a current output from the storage circuit into a binary digital signal.

  Further, it is preferable that the protective wiring covers the wiring capable of reading the digital signal converted by the current detection circuit.

  Furthermore, it is preferable that the protective wiring covers the decoding circuit and the current detection circuit.

  The decryption circuit decrypts the new key using the decryption key stored in the storage circuit when the encrypted new key is given from the outside, and the decrypted new key is stored in the storage circuit. It preferably has a writing function.

  Alternatively, the programmable logic device of the present invention includes a storage circuit including a ferroelectric capacitor that stores configuration information, and a reconfigurable circuit that operates as a predetermined logic circuit according to the configuration information stored in the storage circuit. A read voltage supply circuit that applies a read voltage to the ferroelectric capacitor, and a protective wiring that is connected to one end of the ferroelectric capacitor and the read voltage supply circuit and covers a path of a signal including configuration information output from the storage circuit And may be provided.

  Moreover, it is preferable that the protective wiring covers the switch that controls the operation of the reconfigurable circuit.

  Alternatively, the programmable logic device of the present invention includes a storage circuit that stores a decryption key for decrypting the encrypted configuration information, and a configuration information encrypted using the decryption key stored in the storage circuit. A decoding circuit that decodes the configuration information, a configuration memory that stores configuration information decoded by the decoding circuit, and a reconfigurable circuit that operates as a predetermined logic circuit according to the configuration information stored in the configuration memory In addition, when a new encrypted key is given from the outside, the decryption circuit decrypts the new key using the decryption key stored in the storage circuit, and stores the decrypted new key in the storage circuit. You may have the function to write in.

  The programmable logic device of the present invention stores a decryption key for decrypting encrypted configuration information in a storage circuit including a ferroelectric capacitor, and also includes information on a decryption key output from the storage circuit. Covering the signal path with protective wiring makes it difficult to read the key from the outside.

  The programmable logic device of the present invention makes it more difficult to read the key from the outside by covering the wiring capable of reading the digital signal output from the current detection circuit with the protective wiring.

  The programmable logic device of the present invention further makes it difficult to read the key from the outside by covering the decryption circuit and the current detection circuit with the protective wiring.

  The programmable logic device of the present invention includes a storage circuit that stores configuration information, and reads the configuration information from the outside by covering a signal path including the configuration information output from the storage circuit with a protective wiring. Make it difficult.

(First embodiment)
The programmable logic device according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of a programmable logic device according to the present embodiment.

  A programmable logic device 1 shown in FIG. 1 includes a reconfigurable circuit 10, a ferroelectric memory 11, a decoding circuit 12, an address generation circuit 13, a current detection circuit 14, a configuration memory 15, a read voltage supply circuit 16, and a protective wiring 1020. Is provided. The programmable logic device 1 decrypts the encrypted configuration information stored in the nonvolatile memory 17 provided outside using the decryption key stored in the ferroelectric memory 11 in the decryption circuit 12. And operate according to the decoded configuration information. The programmable logic device 1 is characterized in that a circuit or wiring from which a decryption key can be read is covered with a protective wiring 1020.

  The ferroelectric memory 11 includes a ferroelectric capacitor and a transistor. The ferroelectric memory 11 stores a decryption key for decrypting the encrypted configuration information by accumulating charges in the ferroelectric capacitor. The decryption circuit 12 decrypts the encrypted configuration information stored in the nonvolatile memory 17 using the decryption key stored in the ferroelectric memory 11. The configuration memory 15 stores configuration information decoded by the decoding circuit 12. The reconfigurable circuit 10 operates as a predetermined logic circuit according to the configuration information stored in the configuration memory 15. The address generation circuit 13 generates a read address for output to the nonvolatile memory 17 and a write address for output to the configuration memory 15. The current detection circuit 14 converts the current output from the transistor included in the ferroelectric memory 11 into a binary digital signal, and outputs the converted digital signal to the decoding circuit 12. The read voltage supply circuit 16 applies a read voltage to the ferroelectric capacitor included in the ferroelectric memory 11.

  The protective wiring 1020 covers the wiring 1000 connecting the ferroelectric memory 11 and the current detection circuit 14, the wiring 100 connecting the current detection circuit 14 and the decoding circuit 12, the current detection circuit 14, and the decoding circuit 12. In FIG. 1, a part of the protective wiring 1020 is shown in order to show a circuit and wiring covered by the protective wiring 1020. Actually, the protective wiring 1020 covers a region indicated by a thick broken line. The protective wiring 1020 is, for example, an aluminum wiring. One end of the protective wiring 1020 is connected to the read voltage supply circuit 16. Further, the other end of the protective wiring 1020 is connected to the ferroelectric memory 11 (more specifically, one end of a ferroelectric capacitor included in the ferroelectric memory 11) via the junction 200.

  In the following, in order to simplify the description, a case where there is one ferroelectric memory 11, that is, a case where the decryption key is 1 bit will be described. However, an arbitrary number of ferroelectric memories 11 and current detection circuits 14 are described. Is provided in the programmable logic device 1, a decryption key having an arbitrary number of bits can be stored in the programmable logic device 1.

  FIG. 2 is a layout diagram showing a detailed configuration of the ferroelectric memory 11. A ferroelectric (not shown) is sandwiched between the electrode 1001 and the electrode 1002, thereby forming a ferroelectric capacitor. The charge supply terminal 1003 is a terminal to which a probe is applied when a charge is supplied to the ferroelectric capacitor from the outside. A wiring 1007 connects the junction 200 and the electrode 1001 of the ferroelectric capacitor. The ferroelectric capacitor and the transistor 1006 are connected through a junction 1004. The wiring 1000 connects the drain of the transistor 1006 and the current detection circuit 14. A wiring 1008 connects the source of the transistor 1006 and the ground. In FIG. 2, a rectangle with a diagonal line represents a contact.

  The ferroelectric memory 11 shown in FIG. 2 is shown in a circuit diagram as shown in FIG. The ferroelectric 1009 is inserted between the electrode 1001 and the electrode 1002. The electrode 1001, the electrode 1002, and the ferroelectric 1009 constitute a ferroelectric capacitor 1010.

  Hereinafter, a method for storing the decryption key and a method for reading the decryption key in the ferroelectric memory 11 will be described with reference to FIGS. The decryption key is stored by accumulating electric charges in the ferroelectric capacitor 1010 included in the ferroelectric memory 11. When supplying a charge to the ferroelectric capacitor 1010, a probe is directly applied to the charge supply terminal 1003 and the junction 200 from the outside. (See FIG. 3 (a)). When the electric charge is accumulated in the ferroelectric capacitor 1010, a potential difference corresponding to the amount of accumulated electric charge is generated between the electrodes of the ferroelectric capacitor 1010. When the readout voltage is applied to the ferroelectric capacitor 1010 from the readout voltage supply circuit 16, the readout voltage is applied to the gate 1005 of the transistor 1006, and a current corresponding to the potential difference between the electrodes of the ferroelectric capacitor 1010 is applied to the wiring 1000. Flowing. This current is converted into a digital signal in the current detection circuit 14 (see FIG. 1). This digital signal becomes a decryption key for decrypting the encrypted configuration information.

  As described above, the ferroelectric memory 11 stores the decryption key by accumulating charges in the ferroelectric capacitor 1010, and outputs the decryption key when a read voltage is applied to the ferroelectric capacitor 1010.

  The method for storing the decryption key in the ferroelectric memory 11 from the outside has been described above. In addition to this method, there is a method for storing the decryption key in the ferroelectric memory by controlling the internal circuit of the programmable logic device 1. is there. In this method, as illustrated in FIG. 3B, the transistor 1011 is connected between the electrode 1002 and the wiring 1008. When a predetermined voltage is applied to the gate 1012 of the transistor 1011, the ferroelectric capacitor 1010 and the ground are electrically connected, charges are supplied to the electrodes 1001 and 1002, and charges are accumulated in the ferroelectric capacitor 1010. This method is used when the key decrypted in the decryption circuit 12 is output from the decryption circuit 12 to the ferroelectric memory 11 and the decryption key stored in the ferroelectric memory 11 is rewritten.

  When the decryption key stored in the ferroelectric memory 11 is read from the outside, the encrypted configuration information stored in the nonvolatile memory can be decrypted. When the configuration information is decoded and read, the programmable logic device that operates according to the configuration information can be duplicated. Such a situation is not preferable for an LSI maker who creates a programmable logic device or configuration information. Therefore, it is essential for the LSI manufacturer to protect the decryption key stored in the programmable logic device. Therefore, the programmable logic device 1 according to the present embodiment has a structure for protecting the decryption key stored in the ferroelectric memory 11. Hereinafter, a method for protecting a decryption key in the programmable logic device according to the present embodiment will be described.

  The programmable logic device 1 according to the present embodiment protects the decryption key by covering the circuit and the wiring from which the decryption key can be read by the protective wiring 1020. Specifically, the protective wiring 1020 covers the wiring 1000 and the wiring 100 which are signal paths including information on the decryption key output from the ferroelectric memory 11. Further, the protective wiring 1020 covers the current detection circuit 14 and the decryption circuit 12 so that the key reading becomes more difficult.

  Since there are many variations in the method of covering the circuits and wirings with the protective wiring 1020, an example is shown in FIG. In the example shown in FIG. 4A, the protective wiring 1020 is constituted by a single wiring. One end of the protective wiring 1020 is connected to the read voltage supply circuit 16, and the other end is connected to one end of a ferroelectric capacitor 1010 included in the ferroelectric memory 11.

  The gap formed by the protective wiring 1020 shown in FIG. 4A is sufficiently small, and a probe for reading the decryption key cannot be inserted into this gap. Further, if a part of the protective wiring 1020 is removed to a size that allows the probe to be inserted, the protective wiring 1020 is a sufficiently thin wiring and thus is disconnected. When the protective wiring 1020 is disconnected, the read voltage supply circuit 16 cannot apply the read voltage to the ferroelectric capacitor 1010. The ferroelectric memory 11 cannot output a decryption key unless a read voltage is applied to the ferroelectric capacitor 1010. Therefore, if even a part of the protective wiring 1020 is removed, the decryption key cannot be read from the outside. As described above, as long as the protection wiring 1020 covers a circuit or wiring from which the decryption key can be read, as shown in the example of FIG. 4A, the decryption key cannot be read from the outside.

  FIG. 4B shows another example of the protective wiring 1020. In this example, the wiring 1000, the wiring 100, the current detection circuit 14, and the decoding circuit 12 are covered with plate-shaped wiring.

  As a method for reading out the decryption key from the outside, there is a method of measuring the potential difference between the electrodes of the ferroelectric capacitor 1010. However, when a voltmeter or the like is applied to the electrode of the ferroelectric capacitor 1010 and an attempt is made to measure the potential difference between the electrodes, the charge accumulated in the ferroelectric capacitor 1010 flows out to the voltmeter and the like, and the ferroelectric capacitor The potential difference between 1010 electrodes cannot be measured accurately. Therefore, even if this method is used, the key cannot be read from the outside.

  As described above, according to the programmable logic device 1 according to the present embodiment, the decryption key is stored in the ferroelectric memory, and the wiring 1000, the wiring 100, the current detection circuit 14, and the decryption circuit 12 are covered with the protective wiring 1020. Thus, it is possible to prevent key reading and configuration information duplication.

  Next, a method for distributing the programmable logic device 1 according to the present embodiment and configuration information for operating the programmable logic device 1 will be described. FIG. 5 is a diagram showing a method for distributing the programmable logic device 1 (abbreviated as PLD in the figure). Here, an LSI manufacturer that manufactures and sells the programmable logic device 1, a set manufacturer that manufactures and sells a device on which the programmable logic device 1 is mounted, and a user who purchases the device manufactured by the set manufacturer are considered. The LSI manufacturer stores the key A in the ferroelectric memory 11 included in the programmable logic device 1 in advance, and sells the programmable logic device 1 to the set manufacturer. Further, the LSI manufacturer sells the key B encrypted with the key A and the configuration information encrypted with the key B to the set manufacturer together with the programmable logic device 1. Thereby, the configuration information created by the LSI manufacturer is valid only for the programmable logic device 1 manufactured by the LSI manufacturer and storing the key A. As a result, the LSI manufacturer can obtain a price corresponding to the number of programmable logic devices 1 sold.

  Next, a configuration information installation method for the programmable logic device 1 according to the present embodiment will be described with reference to FIG. 6A to 6C are diagrams illustrating a procedure for installing configuration information in the programmable logic device 1 in the set maker. A key setting device 18 in the figure is a device for setting a decryption key for decrypting configuration information in the programmable logic device 1.

  When the key B encrypted with the key A is supplied from the key setting device 18 with the key A stored in the ferroelectric memory 11 (FIG. 6A), the decryption circuit 12 Using the key A stored in the memory 11, the encrypted key B is decrypted, and the obtained key B is written in the ferroelectric memory 11 (FIG. 6B). As a result, the decryption key stored in the ferroelectric memory 11 is rewritten from the key A to the key B. Thereafter, when the configuration information encrypted with the key B is given from the nonvolatile memory 17 (FIG. 6C), the programmable logic device 1 uses the key B stored in the ferroelectric memory 11. Thus, the given configuration information is decoded and operates as a predetermined logic circuit in accordance with the decoded configuration information.

  Next, a method for updating configuration information for the programmable logic device 1 according to the first embodiment of the present invention will be described. 6D to 6F are diagrams illustrating a procedure for installing new configuration information in the programmable logic device 1 in the set manufacturer. Here, in order to install new configuration information, it is assumed that the key C encrypted with the key B and the configuration information encrypted with the key C are distributed from the LSI manufacturer to the set manufacturer.

  In this case, the new configuration information is installed in the programmable logic device 1 in the same procedure as when the configuration information is first installed. That is, when the key C encrypted with the key B is supplied from the key setting device 18 with the key B stored in the ferroelectric memory 11 (FIG. 6D), the decryption circuit 12 Using the key B stored in the dielectric memory 11, the encrypted key C is decrypted, and the obtained key C is written into the ferroelectric memory 11 (FIG. 6 (e)). Thereafter, when configuration information encrypted with the key C is given from the nonvolatile memory 17 (FIG. 6F), the programmable logic device 1 uses the key C stored in the ferroelectric memory 11. Thus, the given configuration information is decoded and operates as a predetermined logic circuit in accordance with the decoded configuration information.

  As described above, the new configuration information is encrypted with the key C. For this reason, even if another manufacturer's set manufacturer or user copies new configuration information encrypted with the key C, as long as the information of the key C encrypted with the key B is secret, The updated configuration information cannot be used.

  Next, a description will be given of a case where configuration information is created independently by a set manufacturer. In this case, the set maker can also independently create a key for encrypting the configuration information. There are two ways to create this key. The first method is a method in which the LSI manufacturer encrypts the key generated by the set manufacturer as shown in FIG. That is, in this method, first, the set maker independently generates the key D (step S71). The LSI manufacturer receives the key D generated by the set manufacturer, and encrypts the key D using the key A managed by itself (step S72). The set manufacturer receives the programmable logic device 1 storing the key D encrypted with the key A and the key A from the LSI manufacturer, and the programmable logic device by a method (see FIG. 6) using the key setting device 18 described above. 1 stores the key D (step S73). Further, the set maker encrypts the configuration information created uniquely using the key D (step S74), and installs the encrypted configuration information in the programmable logic device 1 by the method described above (see FIG. 6). .

  The second method is a method in which the key generated by the set maker is directly stored in the programmable logic 1 as shown in FIG. That is, in this method, first, the set maker independently generates the key E (step S81). Further, the set manufacturer receives the programmable logic device 1 storing the key A from the LSI manufacturer, and directly applies the probe to the ferroelectric memory 11 in the programmable logic device 1 to store the key E in the programmable logic device 1. (Step S82). At this time, the key A is deleted. Further, similarly to the first method, the set maker encrypts the uniquely created configuration information using the key E (step S83), and installs the encrypted configuration information in the programmable logic device 1.

  The LSI manufacturer distributes the programmable logic device 1 according to the present embodiment by the method shown in FIG. 5, and the set manufacturer further sends configuration information to the programmable logic device 1 according to the procedure shown in FIGS. By installing, unauthorized duplication of the programmable logic device 1 and configuration information by a set manufacturer or user of another company can be prevented. Even when the configuration information is updated, the set manufacturer installs the new configuration information according to the procedure shown in FIGS. 6D to 6F, thereby preventing unauthorized duplication of the new configuration information. be able to. Further, even when configuration information is created by a set maker and installed in the programmable logic device 1, the set maker can be used by other set makers and users as long as the key information that is created is secret. Unauthorized duplication of configuration information can be prevented.

(Second Embodiment)
A programmable logic device according to the second embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a diagram showing the configuration of the programmable logic device according to the present embodiment.

  The programmable logic device 2 shown in FIG. 9 includes a reconfigurable circuit 10 and a configuration memory 20. The configuration memory 20 includes two configuration memory cells (hereinafter referred to as cells) 40 and 50 for storing configuration information, switches 4000 and 5000, a read voltage supply circuit 26, and a protective wiring 2020 (FIG. 9). In FIG. 8, the area covered by the protective wiring 2020 is indicated by a thick broken line. The cell 40 includes ferroelectric memories 21 and 31. The cell 50 is a cell having the same configuration as the cell 40 and includes ferroelectric memories 41 and 51. Switches 4000 and 5000 are connected to an input terminal (not shown) of a gate included in reconfigurable circuit 10. The protective wiring 2020 connects the read voltage supply circuit 26 and the ferroelectric memories 21, 31, 41, and 51 via the junctions 400, 401, 500, and 501. The ferroelectric memories 21 and 31 store configuration information related to on / off of the switch 4000. In addition, the ferroelectric memories 41 and 51 store configuration information related to on / off of the switch 5000.

  FIG. 10 is a circuit diagram of the cell 40 and the switch 4000. The ferroelectric memory 21 has the same configuration as the ferroelectric memory 11 included in the programmable logic device 1 according to the first embodiment of the present invention. That is, a ferroelectric 2009 is sandwiched between the electrode 2001 and the electrode 2002, and a ferroelectric capacitor 2010 is configured. Further, the ferroelectric capacitor 2010 is connected to the transistor 2004. The charge supply terminal 2003 is a terminal to which a probe is applied when a charge is supplied to the ferroelectric capacitor 2010 from the outside. A wiring 2007 connects the joint portion 400 and the electrode 2001. The terminal 2008 is connected to the ground.

  Further, the ferroelectric memory 31 has the same configuration as the ferroelectric memory 11 included in the programmable logic device 1 according to the first embodiment of the present invention. That is, the ferroelectric 3009 is sandwiched between the electrode 3001 and the electrode 3002, and the ferroelectric capacitor 3010 is configured. Further, the ferroelectric capacitor 3010 is connected to the transistor 3004. The charge supply terminal 3003 is a terminal to which a probe is applied when a charge is supplied to the ferroelectric capacitor 3010 from the outside. A wiring 3007 connects the bonding portion 401 and the electrode 3001.

  The switch 4000 is a switch that short-circuits (ON) or opens (OFF) the terminal 2051 and the terminal 3051. The terminal 4010 is connected to a current source provided outside the cell 40. The resistor 4020 is connected between the gate of the switch 4000 and the terminal 4010. A configuration mode signal is applied to terminals 2050 and 3050 from outside the cell 40. These two configuration mode signals are controlled so that at most one takes a value that turns on the transistor (2005 or 3005). As a result, one piece of configuration information is selected as configuration information for controlling the switch 4000 from the two pieces of configuration information stored in the two ferroelectric memories.

  Hereinafter, the operation of the cell 40 will be described with reference to FIG. It is assumed that a probe is applied to the junction 400 and the charge supply terminal 2003 from the outside, and charges are supplied to the ferroelectric capacitor 2010. As a result, the configuration information of the switch 4000 is stored in the ferroelectric memory 21 included in the cell 40. In this example, it is assumed that configuration information for turning on the switch 4000 is stored in the ferroelectric memory 21. In order to control the switch 4000 using the ferroelectric memory 21, when a read voltage is applied from the read voltage supply circuit 26 to the ferroelectric capacitor 2010 via the protective wiring 2020, the gate of the transistor 2004 is A read voltage is applied. Further, when a predetermined voltage is applied to the terminal 2050 by the configuration mode signal, an amount of current corresponding to the potential difference between both electrodes of the ferroelectric capacitor 2010 flows between the terminal 2008 and the terminal 4010. When a current flows between the terminal 2008 and the terminal 4010, a voltage is applied to the gate of the switch 4000. Therefore, the switch 4000 is turned on, and the terminal 2051 and the terminal 3051 are electrically connected.

  Switches 4000 and 5000 control the operation of the logic circuit in the reconfigurable circuit 10. When the information of these switches 4000 and 5000 is measured from the outside, the operation of the reconfigurable circuit 10 is read out. Therefore, the programmable logic device 2 according to the present embodiment includes the ferroelectric memories 21, 31, 41, and 51. It has a structure for protecting stored configuration information and switches 4000 and 5000. Hereinafter, a method for protecting configuration information in the programmable logic device 2 according to the present embodiment will be described.

  The programmable logic device 2 according to the present embodiment protects switch information by covering the switches 4000 and 5000 with the protective wiring 2020. Since there are many variations in the method of covering the switches 4000 and 5000 using the protective wiring 2020, an example is shown in FIG. In the example shown in FIG. 11A, the protective wiring 2020 is configured by a single wiring (for example, an aluminum wiring). One end of the protective wiring 2020 is connected to the read voltage supply circuit 26, and the other end is connected to one end of a ferroelectric capacitor included in the ferroelectric memories 21, 31, 41 and 51.

  The protective wiring 2020 shown in FIG. 11A has the same characteristics as the protective wiring 1020 included in the programmable logic device 1 according to the first embodiment of the present invention. Therefore, as long as the protective wiring 2020 is connected to the read voltage supply circuit and the junction as shown in FIG. 11A and covers the switches 4000 and 5000, the switch information cannot be read from the outside.

  As another example of the protective wiring 2020, as shown in FIG. 11B, a signal including configuration information output from the ferroelectric memories 21, 31, 41, and 51 covers the area covered by the protective wiring 2020. If it is enlarged so as to cover the entire path, it becomes more difficult to read the switch information.

  The protective wiring 2020 may be a plate-like wiring as in the protective wiring 1020 included in the programmable logic device according to the first embodiment of the present invention (see FIG. 12).

  Also in the programmable logic device 2 of this embodiment, an accurate potential difference between the electrodes of the ferroelectric capacitor included in the ferroelectric memory is obtained as in the programmable logic device 1 according to the first embodiment of the present invention. It cannot be measured with a probe from the outside. Therefore, even in the programmable logic device 2, information stored in the ferroelectric memory cannot be read out by the method of measuring the potential difference of the ferroelectric capacitor.

  As described above, the programmable logic device 2 according to the present embodiment stores the configuration information in the ferroelectric memory included in the configuration memory, and protects the switches 4000 and 5000 by the protective wiring 2020. Reading of the navigation information is prevented. Thereby, the LSI manufacturer and the set manufacturer can prevent unauthorized duplication of the configuration information.

  Since the programmable logic device of the present invention has a configuration in which it is difficult to read a decryption key and configuration information from the outside, the programmable logic device can be used for a device that needs to keep the operation of a built-in logic circuit secret.

The figure which shows the structure of the programmable logic device which concerns on the 1st Embodiment of this invention. 1 is a layout diagram of a ferroelectric memory provided in a programmable logic device according to a first embodiment of the present invention. 1 is a circuit diagram of a ferroelectric memory provided in a programmable logic device according to a first embodiment of the present invention. The figure which shows the example of the protective wiring with which the programmable logic device which concerns on the 1st Embodiment of this invention is equipped. The figure which shows the programmable logic device which concerns on the 1st Embodiment of this invention, and the distribution method of configuration information The figure which shows the installation method of the configuration information in the programmable logic device which concerns on the 1st Embodiment of this invention The figure which shows the 1st method which produces the configuration information uniquely installed in the programmable logic device which concerns on the 1st Embodiment of this invention in a set maker The figure which shows the 2nd method which produces the configuration information uniquely installed in the programmable logic device which concerns on the 1st Embodiment of this invention in a set maker The figure which shows the structure of the programmable logic device which concerns on the 2nd Embodiment of this invention. Circuit diagram of programmable logic device according to second embodiment of the present invention The figure which shows the example of the protective wiring with which the programmable logic device which concerns on the 2nd Embodiment of this invention is equipped. The figure which shows another example of the protective wiring with which the programmable logic device which concerns on the 2nd Embodiment of this invention is equipped.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Programmable logic device 10 Reconfigurable circuit 11, 21, 31, 41, 51 Ferroelectric memory 12 Decoding circuit 13 Address generation circuit 14 Current detection circuit 15, 20 Configuration memory 16, 26 Read-out voltage supply circuit 17 Nonvolatile Memory 18 Key setting device 40, 50 Cell 1020, 2020 Protection wiring 4000, 5000 Switch

Claims (8)

A programmable logic device that operates as a predetermined logic circuit according to encrypted configuration information given from the outside,
A storage circuit that includes a ferroelectric capacitor and stores a decryption key for decrypting the encrypted configuration information;
A decryption circuit for decrypting the encrypted configuration information using a decryption key stored in the storage circuit;
A configuration memory for storing configuration information decoded by the decoding circuit;
A reconfigurable circuit that operates as a predetermined logic circuit according to the configuration information stored in the configuration memory;
A read voltage supply circuit for applying a read voltage to the ferroelectric capacitor;
A programmable logic device comprising: a protective wiring that is connected to one end of the ferroelectric capacitor and the read voltage supply circuit and covers a path of a signal including information on the decryption key output from the storage circuit.   The programmable logic device according to claim 1, further comprising a current detection circuit that converts a current output from the storage circuit into a binary digital signal.   The programmable logic device according to claim 2, wherein the protective wiring further covers a wiring capable of reading the digital signal.   The programmable logic device according to claim 3, wherein the protective wiring further covers the decoding circuit and the current detection circuit.   The decryption circuit decrypts the new key using the decryption key stored in the storage circuit when the encrypted new key is given from the outside, and stores the decrypted new key in the storage The programmable logic device according to claim 1, wherein the programmable logic device is written to a circuit. A programmable logic device that operates as a predetermined logic circuit according to configuration information given from outside,
A storage circuit including a ferroelectric capacitor and storing the configuration information;
A reconfigurable circuit that operates as a predetermined logic circuit according to the configuration information stored in the storage circuit;
A read voltage supply circuit for applying a read voltage to the ferroelectric capacitor;
A programmable logic device comprising: a protective wiring connected to one end of the ferroelectric capacitor and the read voltage supply circuit and covering a path of a signal including the configuration information output from the storage circuit.   The programmable logic device according to claim 6, wherein the protective wiring further covers a switch that controls an operation of the reconfigurable circuit. A programmable logic device that operates as a predetermined logic circuit according to encrypted configuration information given from the outside,
A storage circuit for storing a decryption key for decrypting the encrypted configuration information;
A decryption circuit for decrypting the encrypted configuration information using a decryption key stored in the storage circuit;
A configuration memory for storing configuration information decoded by the decoding circuit;
A reconfigurable circuit that operates as a predetermined logic circuit according to the configuration information stored in the configuration memory;
The decryption circuit decrypts the new key using the decryption key stored in the storage circuit when the encrypted new key is given from the outside, and the decrypted new key is A programmable logic device characterized by writing to a storage circuit.

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