JP4448738B2 - Semiconductor device evaluation design apparatus, semiconductor device evaluation design method, semiconductor device evaluation design program, and recording medium - Google Patents

Description

  The present invention relates to an evaluation design apparatus for a semiconductor device for evaluating and designing a semiconductor device such as a semiconductor integrated circuit, an evaluation design method for a semiconductor device, an evaluation design program for a semiconductor device, and a recording medium.

  Conventionally, as miniaturization and high integration progress in the manufacturing process of a semiconductor device, deviation from design values such as element characteristics, wiring resistance, wiring capacitance, and the like has been regarded as a problem. Specifically, the circuit simulation accuracy deteriorates due to the difference between the design value and the finished size. As a technique for solving this problem, Patent Documents 1 to 3 below have been proposed.

  In the prior arts of these Patent Documents 1 to 3, a method that incorporates the proximity effect in exposure and etching (mostly a method similar to rule-based OPC) is used to predict the completion from design data, and circuit simulation is performed based on the prediction. It is to do.

  In addition, at the stage of further miniaturization in the manufacturing process of semiconductor devices, manufacturing variations that cannot be controlled or completely reproducible between patterns, chips, wafers, lots cannot be ignored, that is, There is a problem that even if an effort is made to reduce the manufacturing variation, the manufacturing variation cannot be ignored.

  For this reason, at the design stage of the semiconductor device, it is required to design the semiconductor device so that it operates even if there is some variation. For example, even if a circuit operation simulation is performed under the assumption that each characteristic value is the worst (for example, the slowest in terms of delay) within the range of variation, it is confirmed whether or not it operates without any problem. In addition, a Monte Carlo simulation gives random variations, and whether or not it still operates is confirmed by a circuit operation simulation.

Japanese Patent Laid-Open No. 10-171855 Japanese Patent Laid-Open No. 2001-22802 JP 2002-259485 A

  However, considering the actual manufacturing process, the assumption that all the elements are the slowest, and conversely, the assumption that they are completely random is not realistic. This point will be described with reference to the drawings. FIG. 10 is a graph plotting the variation in the size of the gate due to defocusing in the light exposure process. In the graph of FIG. 10, the dimensions of the gate whose design value indicated by the vertical axis CD is 80 [nm] are plotted against the pattern pitch.

  In FIG. 10, there is a pitch at which the size of the gate changes greatly with a focus shift, while there is a pitch at which the size hardly changes. That is, the dimensional variation caused by the focus shift depends on the pattern layout including the pitch. Also, the focus gradually changes within the chip, and the adjacent pattern at a submicron distance usually varies to the same extent.

  As described above, the variation occurring in the manufacturing process includes the influence of the curvature of the wafer, and thus has a close relationship with the peripheral pattern layout and pattern position coordinates. Therefore, there is a problem that it is not appropriate to give this uniform variation or completely random variation.

  The present invention eliminates the above-described problems caused by the prior art, and allows the semiconductor device evaluation and design to be performed realistically and with high accuracy, a semiconductor device evaluation and design method, a semiconductor device evaluation and design method, and a semiconductor device An object is to provide an evaluation design program and a recording medium.

  In order to solve the above-described problems and achieve the object, an evaluation design apparatus for a semiconductor device, an evaluation design method for a semiconductor device, an evaluation design program for a semiconductor device, and a recording medium according to the present invention store arbitrary layout data related to the semiconductor device. Input, extract arbitrary pattern data from the input layout data, generate information on the dimensional variation of the extracted pattern data, and enter the netlist of the semiconductor device from the input layout data And circuit simulation of the semiconductor device is executed based on the generated variation information and the extracted netlist.

  According to the present invention, it is possible to execute circuit simulation in consideration of variations in the dimensions of pattern data for which layout design has been performed.

Further, in the above invention, information related to the dimension of the extracted pattern data is calculated, information related to the distance between the extracted pattern data and the same kind of pattern data adjacent in parallel to the pattern data is calculated and calculated. Based on the information on the measured dimensions and the information on the calculated distance, information on the variation in the dimensions of the extracted pattern data may be generated.

  According to the present invention, a circuit simulation can be executed using a netlist that takes into account variations in pattern dimensions that may occur in the manufacturing process.

  Further, in the above-described invention, further, information regarding the density of the pattern data in the region including the extracted pattern data is calculated, and the size variation of the extracted pattern data is calculated based on the information regarding the calculated density. Information may be generated.

  According to the present invention, it is possible to execute a circuit simulation using a netlist that takes into account variations due to pattern integration that may occur in the manufacturing process.

  In the above invention, further, a correction amount related to a certain bias generated in the layout design process of the semiconductor device based on the information on the calculated dimension and the information on the calculated distance, and the manufacture of the semiconductor device Extracting a fluctuation amount representing a fluctuation of the correction amount with respect to a bias that occurs by chance, and calculating information on a variation in the size of the extracted pattern data based on the extracted correction amount and the fluctuation amount. It is good.

  According to the present invention, it is possible to generate a netlist that expresses a variation that can occur in an actual manufacturing process, which is more realistic than a uniform variation or a completely random variation.

  In the above invention, the variation information may be calculated based on the correction amount and a value obtained from a random function that randomly varies within a predetermined range based on the variation amount.

  According to the present invention, it is possible to generate a netlist that expresses the variation of the accidental error as a realistic variation that may occur in an actual manufacturing process.

  In the above invention, the random function may be a function that randomly varies based on a coordinate position on the wafer of the pattern data.

  According to the present invention, it is possible to generate a netlist that represents a realistic variation in consideration of the coordinate position on the wafer of the pattern data.

  In the above invention, the extracted netlist is corrected based on the generated variation information, and circuit simulation of the semiconductor device is executed based on the corrected netlist.

  According to the present invention, it is possible to generate a high-accuracy net list corrected by variation in the dimensions of pattern data for which layout design has been performed.

  Further, in the above invention, the pattern data representing the gate pattern is extracted from the pattern data included in the input layout data, and information regarding variations in the gate length of the pattern data representing the gate pattern is generated, and the gate data Information on the gate length included in the extracted netlist may be corrected based on the information on length variation.

  According to the present invention, the circuit simulation can be executed using the net list in which the variation of the gate length dimension of the layout designed gate electrode pattern data is corrected.

  In the above invention, the pattern data representing the wiring pattern is extracted from the pattern data included in the input layout data, and the wiring pattern is based on the information related to the wiring dimension of the pattern data representing the wiring pattern. Information on the wiring pattern variation is generated, and based on the information on the wiring dimension variation and the information on the wiring resistance of the wiring pattern included in the extracted netlist, a new information on the wiring pattern is generated. Information on the wiring resistance may be generated.

  According to the present invention, the wiring resistance value described in the netlist can be corrected by correcting the variation in the wiring dimension of the pattern data of the wiring pattern designed for layout.

  In the above invention, the pattern data representing the wiring pattern is extracted from the pattern data included in the input layout data, and the wiring pattern is based on the information related to the wiring dimension of the pattern data representing the wiring pattern. And generating new information on the wiring pattern based on the information on the wiring dimension variation and the information on the wiring capacity of the wiring pattern included in the extracted netlist. Information on the wiring capacity may be generated.

  According to the present invention, it is possible to correct the value of the wiring capacitance described in the netlist by correcting the variation in the wiring dimension of the pattern data of the wiring pattern designed for layout.

  According to the semiconductor device evaluation and design apparatus, the semiconductor device evaluation and design method, the semiconductor device evaluation and design program, and the recording medium according to the present invention, the semiconductor device evaluation and design can be performed realistically and with high accuracy. Play.

  Exemplary embodiments of a semiconductor device evaluation design apparatus, a semiconductor device evaluation design method, a semiconductor device evaluation design program, and a recording medium will be described below in detail with reference to the accompanying drawings. The semiconductor device evaluation and design apparatus and the semiconductor device evaluation and design method according to the following embodiment are realized by, for example, a CAD including a recording medium in which the semiconductor device evaluation and design program according to this embodiment is recorded. be able to.

(Embodiment)
(Hardware configuration of semiconductor device evaluation and design equipment)
First, a hardware configuration of a semiconductor device evaluation and design apparatus according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a semiconductor device evaluation design apparatus according to an embodiment of the present invention.

  In FIG. 1, a semiconductor device evaluation and design apparatus includes a CPU 101, a ROM 102, a RAM 103, an HDD (hard disk drive) 104, an HD (hard disk) 105, an FDD (flexible disk drive) 106, and a removable recording medium. As an example, an FD (flexible disk) 107, a display 108, an I / F (interface) 109, a keyboard 110, a mouse 111, a scanner 112, and a printer 113 are provided. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire semiconductor device evaluation and design apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106, or causes the evaluation design apparatus of the semiconductor device to read the data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into an evaluation design apparatus for a semiconductor device. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Functional configuration of semiconductor device evaluation and design equipment)
Next, a functional configuration of the semiconductor device evaluation and design apparatus according to the embodiment of the present invention will be described. FIG. 2 is a block diagram showing a functional configuration of the semiconductor device evaluation design apparatus according to the embodiment of the present invention.

  In FIG. 2, the semiconductor device evaluation design apparatus 200 includes a layout database 201. Here, the layout data stored in the layout database 201 will be described. FIG. 3 is an explanatory diagram showing an example of layout data stored in the layout database 201. This layout data shows a state displayed on the display 108 shown in FIG.

  In FIG. 3, the layout data 300 represents layout data 301a to 301c of a plurality of inverter circuits. The layout data 301a to 301c of each inverter circuit is constituted by layout data (310a, 320a), (310b, 320b), (310c, 320c) of two MOS transistors, respectively.

  One MOS transistor layout data 310a to 310c includes VDD terminal pattern data 311a to 311c, source electrode pattern data 312a to 312c, gate electrode pattern data 313a to 313c, and drain electrode pattern data 314a to 314c. And.

  The other MOS transistor pattern data 320a to 320c includes VSS terminal pattern data 321a to 321c, source electrode pattern data 322a to 322c, gate electrode pattern data 323a to 323c, and drain electrode pattern data 324a. -324c.

  The gate electrode pattern data (313a, 323a), (313b, 323b), (313c, 323c) are connected by wiring pattern data 331a-331c including input terminal data 330a-330c. The drain electrode pattern data (314a, 324a), (314b, 324b), (314c, 324c) are connected by wiring pattern data 333a-333c including output terminal data 332a-332c.

  Further, in the output terminal data 332a and 332b of the pattern data (301a, 301b) and (301b and 301c) of the adjacent inverter circuits, the wiring pattern data (333a, 331b) and (333b, 331c) are connected. . Further, the layout database 201 specifically realizes its function by a readable / writable recording medium such as the RAM 103, the HD 105, and the FD 107 shown in FIG.

  In FIG. 2, the semiconductor device evaluation design apparatus 200 includes a layout data input unit 203, a pattern data extraction unit 204, a variation information generation unit 205, and a net list generation unit 206.

  The layout data input unit 203 includes a layout data extraction unit 231 and a layout data reception unit 232. The layout data extraction unit 231 extracts the layout data 300 from the layout database 201. The layout data receiving unit 232 receives the layout data transmitted from the external server via the network 114. The layout data 300 is input by the layout data extracting unit 231 and the layout data receiving unit 232.

  The pattern data extraction unit 204 extracts arbitrary pattern data included in the layout data 300 input by the layout data input unit 203. The pattern data extraction unit 204 may be configured to sequentially extract all pattern data, or may be configured to sequentially extract only pattern data related to generation of variation information described later.

  The variation information generation unit 205 generates variation information regarding variation in the dimensions of the pattern data extracted by the pattern data extraction unit 204. The variation information generation unit 205 includes a dimension information calculation unit 251, a distance information calculation unit 252, a density information calculation unit 253, a variation parameter table 254, a variation parameter extraction unit 255, and a variation information calculation unit 256. ing.

  The dimension information calculation unit 251 extracts information (dimension information l) related to the dimension of the pattern data extracted by the pattern data extraction unit 204. For example, when the pattern data extracted by the pattern data extraction unit 204 is the gate electrode pattern data shown in FIG. 3, the gate length information lg can be extracted as the dimension information l. When the pattern data extracted by the pattern data extraction unit 204 is the wiring pattern data shown in FIG. 3, the wiring length information lw of the wiring pattern data can be extracted as the dimension information l.

  The distance information calculation unit 252 calculates information (distance information s) regarding the distance between the pattern data extracted by the pattern data extraction unit 204 and the same type of pattern data adjacent to the pattern data. For example, in the case of the pattern data of the gate electrode shown in FIG. 3 by the pattern data extraction unit 204, the pattern information of this gate electrode and the gates of other inverter circuits arranged adjacent to the pattern data as the distance information s. Distance information sg between the electrode pattern data is calculated.

  Further, in the case of the wiring pattern data shown in FIG. 3 by the pattern data extraction unit 204, as the distance information s, the wiring pattern data and the wiring pattern data of other inverter circuits arranged adjacent to the wiring pattern data Distance information sw is calculated. Specifically, the calculation process by the distance information calculation unit 252 can be calculated using the coordinate position of the pattern data on the wafer.

  The density information calculation unit 253 calculates information (density information a) related to the density of the pattern data in the area including the pattern data extracted by the pattern data extraction unit 204. An area including the pattern data is set in advance. For example, the region may include the entire MOS transistor including the pattern data extracted by the pattern data extraction unit 204, or may be the region including the entire inverter circuit including the pattern data extracted by the pattern data extraction unit 204. Good.

  For example, a region including the pattern data extracted by the pattern data extraction unit 204 is set as a region including the entire inverter circuit including the pattern data extracted by the pattern data extraction unit 204. When the pattern data extracted by the pattern data extraction unit 204 is the gate electrode pattern data shown in FIG. 3, the area area and the gate electrode pattern data area are calculated. Using the calculated area of the region and the area of the gate electrode pattern data, the density information a of the gate electrode pattern data in the region can be calculated.

  Next, the variation parameter table 254 will be described. FIG. 4 is an explanatory diagram illustrating an example of the variation parameter table 254. In FIG. 4, the variation parameter table 254 specifies variation parameters by a combination of the dimension information l and the distance information s. The specified variation parameter includes two types of values.

  One is a correction amount c related to a certain bias generated in the layout design process of the semiconductor device, and the other is a value σ related to a bias that occurs accidentally during the manufacture of the semiconductor device. This value σ is an amount representing the fluctuation range of the correction amount c (hereinafter referred to as a fluctuation amount σ). Specifically, the value on the left side in the table shown in FIG. 4 is the correction amount c, and the value on the right side is the variation amount σ. For example, when the dimension information 1 is l = 100 [nm] and the distance information s is s = 1300 [nm], the correction amount c is c = −1 [nm] and the variation amount σ is σ = 2 [nm]. ].

  Here, the correction amount c is, for example, a correction amount for correcting a systematic error generated by an OPC (Optical Proximity Correction) process which is one of the layout design processes of the semiconductor device. The OPC is a process of correcting the dimensional variation caused by the optical proximity effect so that the post-etching dimension becomes equal to the design dimension, and automatically correcting the layout data 300. However, in this OPC, the corrected minimum grid is determined. As a result, a correction residue is generated. The correction amount c is a correction amount in consideration of this correction residue, and represents an average deviation due to the OPC automatic correction process.

  On the other hand, the fluctuation amount σ is a value for correcting a coincidence error that occurs during manufacturing of a semiconductor device such as OPC. This variation σ can be expressed by a probability density function such as a Gaussian distribution, for example. FIG. 5 is a graph showing a Gaussian distribution. In FIG. 5, the horizontal axis indicates the error amount x, and the vertical axis indicates the existence probability P. The standard deviation σ of the Gaussian distribution coincides with the fluctuation amount σ.

  This variation parameter (correction amount c and variation amount σ) is used as a variation parameter for the gate length when the pattern data extracted by the pattern data extraction unit 204 is pattern data for the gate electrode, and is used by the pattern data extraction unit 204. When the extracted pattern data is wiring pattern data, it is used as a wiring length variation parameter.

  Further, the variation parameter table 254 can be provided for each density information a calculated by the density information calculation unit 253. For example, the density information a is 0 [%] ≦ a <10 [%], 10 [%] ≦ a <20 [%], 20 [%] ≦ a <30 [%], and so on. A variation parameter table 254 having different variation parameters for each density information a can be prepared. Further, the layout database 201 specifically realizes its function by a readable / writable recording medium such as the RAM 103, the HD 105, and the FD 107 shown in FIG.

  In FIG. 2, the variation parameter extraction unit 255 extracts variation parameters (correction amount c and variation amount σ) from the variation parameter table 254. For example, the dimension information l extracted by the dimension information calculation unit 251 is 1 = 100 [nm], the distance information s calculated by the distance information calculation unit 252 is s = 1300 [nm], and the density information calculation unit 253 When the calculated density information a is a = 7 [%], c = −1 [nm] as the correction amount c and σ = 2 [nm] as the variation amount σ are extracted from the variation parameter table 254.

The variation information calculation unit 256 calculates variation information based on the variation parameter extracted by the variation parameter extraction unit 255. Specifically, the variation information D can be calculated by the following equation (1).
D = c (s, l, a) + random [σ (s, l)] (1)

  In the above equation (1), c (s, l, a) is a correction amount c determined by distance information s (sg, sw), dimension information l (lg, lw), and density information a. . Further, σ (s, l) is a fluctuation amount σ determined by the distance information s (sg, sw) and the dimension information l (lg, lw). Furthermore, random [σ (s, l)] is a function that gives random variations.

  Specifically, the value of random [σ (s, l)] is a value that is randomly extracted from a Gaussian distribution in which the standard deviation is the variation amount σ. That is, the value of random [σ (s, l)] is the value on the horizontal axis of the Gaussian distribution shown in FIG. 5, and is randomly determined according to the probability density of the Gaussian distribution. In the Gaussian distribution shown in FIG. 5, random [σ (s, l)] = 0 has the highest probability of existence, and is therefore likely to be extracted.

As described above, by randomly changing the fluctuation amount σ according to the Gaussian distribution, it is possible to obtain a correction amount in consideration of an error caused by an actual manufacturing process. The variation information D can also be calculated by the following formula (2).
D = c (s, l, a) ± 3 × σ (s, l) (2)

  Since the above equation (2) has a smaller calculation amount than the above equation (1), the circuit scale of the semiconductor device is large, and it is used when there is no time for simulating various combinations of variations. The speed can be increased.

The variation information D can also be calculated by the following equation (3).
D = c (s, l, a) + σ (s, l) × f (x, y) (3)

Here, f (x, y) is a function that gradually changes depending on the position coordinates (x, y) on the wafer, and can be expressed by the following equation (4), for example.
f (x, y) = sin (jx + k) × sin (my + n) (4)

  In the above equation (4), j, k, m, and n are values given at random, and the upper limit value and the lower limit value of f (x, y) are set in advance. Since there are various types of variations that occur in the manufacturing process, when performing circuit simulation, by randomly giving the values of j, k, m, and n, errors caused by the position of pattern data on the wafer, for example, the wafer It is possible to obtain a correction amount that takes into account errors such as deflection and unevenness.

  In FIG. 2, the net list generation unit 206 includes a net list extraction unit 261 and a net list correction unit 262. The net list extraction unit 261 extracts a net list from the layout data 300 input by the layout data input unit 203. Specifically, the netlist is extracted from the layout data 300 by analyzing the layout data 300 with the layout tool.

  Here, an example of a specific extracted netlist is shown. FIG. 6 is an explanatory diagram showing an example of a net list extracted from the layout data 300. The net list 600 is a net list related to the inverter circuit represented by the layout data 301b shown in FIG.

  In the net list 600 shown in FIG. 6, the first line shows the circuit name and terminal information. That is, the inverter circuit having the circuit name “circuit 1” includes a power supply voltage terminal “VDD”, an output voltage terminal “VSS”, a signal input terminal “A”, and a signal output terminal “YB”. . Also, “M + 0” in the second row represents a MOS transistor.

  “6”, “A”, and “VDD” represent terminal information of “M + 0” that is a MOS transistor. Further, “pch” indicates that “M + 0”, which is a MOS transistor, is a p-channel. Further, w = 1000 nm represents the gate width of the MOS transistor “M + 0”, and lg = 120 nm represents the gate length of the MOS transistor “M + 0”. The description contents on the third line are in accordance with the description contents on the second line.

The fourth row indicates that the wiring resistance “R + 2” between the terminal “YB” and the terminal “6” is “35” [Ω]. The description content on the fifth line is in line with the description content on the fourth line. Further, the sixth line indicates that the wiring capacitance “C + 4” between the terminal “VDD” and the terminal “A” is “6.5e−17”, that is, 6.5 × 10 ⁻¹⁷ [F]. Appears. The description contents on the 7th to 15th lines are in accordance with the description contents on the 6th line.

  In FIG. 2, the net list correction unit 262 includes a semiconductor device net list 600 based on the variation information generated by the variation information generation unit 205 and the net list 600 extracted by the net list extraction unit 261. Correct the description of. For example, when correcting the gate length information of the gate electrode in the netlist 600, the variation information generated by the variation information generation unit 205 is added to the gate length information.

  Further, when the wiring resistance value of the wiring pattern in the netlist 600 is corrected, the wiring resistance value of the wiring pattern based on the variation information generated by the variation information generation unit 205 and the dimension information of the wiring pattern. Is calculated. Then, the wiring resistance value of the wiring pattern in the net list 600 is updated to the newly calculated wiring resistance value.

  Further, when correcting the wiring capacitance value between the wiring patterns in the netlist 600, the wiring between the wiring patterns based on the variation information generated by the variation information generating unit 205 and the dimension information of the wiring pattern. Calculate the capacitance value. Then, the wiring capacitance value between the wiring patterns in the netlist 600 is updated to the newly calculated wiring capacitance value.

  In addition, the circuit simulation execution unit 207 executes circuit simulation of the semiconductor device represented by the netlist 600 generated by the netlist generation unit 206. In this circuit simulation, for example, information on timing such as delay, setup, hold time, etc., in a small circuit unit that is a component of a circuit that is somewhat large, such as an inverter, flip-flop, etc. Find power consumption.

  The layout data verification unit 208 verifies the validity of the layout data 300 of the semiconductor device represented by the netlist 600 generated by the netlist generation unit 206. The validity is verified based on the simulation result described above. Specifically, using a simulation result by the circuit simulation execution unit 207 (information on timing such as delay, setup, and hold time described above, power consumption, etc.), in a circuit with a certain scale, whether or not timing failure occurs or desired It is verified by simulation whether it operates at a speed of 5 or power consumption is within the standard.

  The layout data correction unit 209 corrects the layout data 300 determined as invalid by the layout data verification unit 208. Specifically, when the desired specification is not satisfied based on the verification result by the layout data verification unit 208, the design of the small-scale circuit in which the problem has occurred is changed.

  The specific method of design change is to select a pitch and pattern width with a small variation compared to the current pitch and variation width (c + σ) in the pattern width, or to reposition the wiring pattern and increase the resistance. Examples of the method include lowering, expanding the space to reduce the capacity, and finely adjusting the gate length and gate width of the MOS transistor.

  The modified layout data 300 is stored in the layout database 201. Further, the layout data output unit 210 outputs the layout data 300 that is determined to be invalid by the layout data verification unit 208. The output layout data 300 can be used in a manufacturing process.

  The layout data input unit 203, the pattern data extraction unit 204, the dimension information calculation unit 251, the distance information calculation unit 252, the density information calculation unit 253, the variation parameter extraction unit 255, the variation information calculation unit 256, and the net list generation unit described above. Specifically, the circuit simulation execution unit 207, the layout data verification unit 208, the layout data correction unit 209, and the layout data output unit 210 are recorded in the ROM 102, the RAM 103, the HD 105, the FD 107, and the like shown in FIG. The function is realized by the CPU 101 executing the recorded program.

(Example of correction of gate length information)
Here, an example of correcting the gate length information will be described using the layout data 300 shown in FIG. FIG. 7 is an explanatory diagram showing a modification example of the pattern data of the gate electrode included in the layout data 300 shown in FIG. Here, the pattern data extracted by the pattern data extraction unit 204, that is, the pattern data to be corrected is referred to as the gate electrode pattern data 323b. The density information a is a = 7 [%].

  First, the dimension information calculation unit 251 extracts gate length information lg which is dimension information l of the gate electrode pattern data 323b. The distance information calculation unit 252 calculates distance information s between the gate electrode pattern data 323b and the gate electrode pattern data 323a and 323c adjacent to the pattern data 323b. Specifically, distance information sg1 between the right end side 702a of the gate electrode pattern data 323a and the left end side 701b of the gate electrode pattern data 323b is calculated. Similarly, distance information sg2 between the left end side 701c of the gate electrode pattern data 323c and the right end side 702b of the gate electrode pattern data 323b is calculated.

  Next, the variation parameter extraction unit 255 extracts the variation parameter of the gate electrode pattern data 323b for each edge. Specifically, for the left end side 701b, the variation parameter is extracted from the variation parameter table 254 shown in FIG. 4 using the gate length information lg and the distance information sg1. For example, when the gate length information lg is lg = 120 and the distance information sg1 is sg1 = 1800, the correction amount c is c = 0 and the variation amount σ is σ = 3.

  For the right end side 702b, the variation parameter is extracted from the variation parameter table 254 shown in FIG. 4 using the gate length information lg and the distance information sg2. For example, when the gate length information lg is lg = 120 and the distance information sg2 is sg2 = 1300, the correction amount c is c = −2 and the variation amount σ is σ = 4.

Then, the variation information calculation unit 256 calculates variation information for each edge. For example, if the variation information of the left end side 701b is calculated using the above equation (1), the variation information D1 of the left end side 701b is
D1 = c (sg1, lg, a) + random [σ (sg1, lg)]
= 0 + (-1)
= -1
The variation information D2 of the right end side 702b is
D2 = c (sg2, lg, a) + random [σ (sg2, lg)]
= -2 + (-2)
= -4
Suppose that Therefore, the variation information Dg in this case is a value obtained by adding the variation information D1 and D2 of each edge, that is,
Dg = D1 + D2 = (-1) + (-4) =-5
It becomes.

Then, the net list generation unit 206 extracts the net list 600 shown in FIG. In the net list 600, the description contents of the layout data 320b of the MOS transistor including the pattern data 323b of the gate electrode to be corrected are in the net list shown in FIG.
Since “M + 1 5 A VSS VSS nch w = 700.0 nm lg = 120 nm”, the netlist modification unit 262 adds the calculated variation information Dg (Dg (Dg) to the gate length information lg (lg = 120 nm) in this description. = -1) is added to obtain “lg = 119 nm”.

(Example of correction of wiring resistance)
Further, an example of correcting the wiring resistance value will be described using the layout data 300 shown in FIG. FIG. 8 is an explanatory diagram showing a modification example of the wiring resistance value of the wiring pattern represented by the layout data 300 shown in FIG. Here, the pattern data extracted by the pattern data extraction unit 204, that is, the pattern data to be corrected is referred to as wiring pattern pattern data 333b. The density information a is a = 7 [%].

  First, the dimension information calculation unit 251 extracts the wiring width information lw that is the dimension information 1 of the pattern data 333b of the wiring pattern. The distance information calculation unit 252 calculates distance information between the pattern data 333b of the wiring pattern and the pattern data 333a and 333c of the wiring pattern adjacent to the pattern data 333b. Specifically, the distance sw1 between the right end side 802a of the wiring pattern pattern data 333a and the left end side 801b of the wiring pattern pattern data 333b is calculated. Similarly, a distance sw2 between the left end side 801c of the wiring pattern pattern data 333c and the right end side 802b of the wiring pattern pattern data 333b is calculated.

  Next, the variation parameter extraction unit 255 extracts the variation parameter of the pattern data 333b of the wiring pattern for each end side. Specifically, for the left end side 801b, a variation parameter is extracted from the variation parameter table 254 shown in FIG. 4 using the wiring width information lw and the distance information sw1. For example, when the wiring width information lw is lw = 300 and the distance information sw1 is sw1 = 1800, the correction amount c is c = 0 and the variation amount σ is σ = 9.

  For the right end side 802b, the variation parameter is extracted from the variation parameter table 254 shown in FIG. 4 using the wiring width information lw and the distance information sw2. For example, when the wiring width information lw is lw = 300 and the distance information sw2 is sw2 = 1300, the correction amount c is c = -3 and the variation amount σ is σ = 6.

Then, the variation information calculation unit 256 calculates variation information for each edge. For example, if the variation information of the left end side 801b is calculated using the above equation (1), the variation information D3 of the left end side 801b is:
D3 = c (sw1, lw, a) + random [σ (sw1, lw)]
= 0 + 2
= 2
The variation information D4 of the right end side 802b is
D4 = c (sw2, lw, a) + random [σ (sw2, lw)]
= -3 + (-1)
= -4
Suppose that Therefore, the variation information Dw in this case is a value obtained by adding the variation information D3 and D4 of each edge, that is,
Dw = D3 + D4 = 2 + (-4) =-2
It becomes.

Further, the wiring resistance value is in inverse proportion to the cross-sectional area orthogonal to the wiring length direction in proportion to the wiring length of the wiring pattern extending along the signal flowing direction. Therefore, when the wiring resistance value after correction of the wiring pattern represented by the pattern data 333b of the wiring pattern is R, the wiring resistance value R is the original wiring resistance value r described in the net list and the wiring pattern value of the wiring pattern. It can be calculated by the following equation (5) using the wiring width information lw of the pattern data 333b and the variation information Dw.
R = r · lw / (lw + Dw) (5)

  Then, the net list generation unit 206 extracts the net list 600 shown in FIG. The wiring resistance value r of the wiring pattern represented by the wiring pattern pattern data 333b is detected from the extracted net list and updated to the calculated wiring resistance value R.

In the above example, the wiring resistance value R is corrected by using only the wiring width information lw. However, when the wiring pattern is adjacent to the wiring length direction, the variation parameter in the wiring length direction is used. The variation information calculated by this method can be taken into consideration. Since the value of the wiring resistance is proportional to the wiring length, here, the wiring length information is le, and the variation information obtained from the wiring length information le using any one of the above formulas (1) to (3) is De. Then, the above-described equation (5) becomes the following equation (6).
R = r · {lw / (lw + Dw)} · {(le + De) / le} (6)

(Example of correction of wiring capacitance value)
An example of correcting the wiring capacitance value will be described using the layout data 300 shown in FIG. The wiring capacitance value is generated between two patterns facing each other at an interval. For example, it occurs between pattern data 331b including input terminal data 330b and pattern data 331c including output terminal data 332b. In addition to the wiring width information lw, the distance information calculation unit 252 further calculates distance information sd between the pattern data 331b and the pattern data 331c.

The wiring capacitance value is proportional to the pattern area in the direction orthogonal to the interval direction between two patterns facing each other with an interval, and inversely proportional to the length of the interval. Therefore, in this case, the corrected wiring capacitance value generated between the pattern data 331b and the pattern data 333b is Q, and the distance information sd and the wiring are calculated using any one of the above formulas (1) to (3). Assuming that the variation information of one pattern obtained from the width information lw is Dd1, and the variation information of the other pattern is Dd2, the wiring capacitance value Q is expressed by the input terminal data 330b and output terminal data 332b described in the netlist 600. Between the line capacitance value q, distance information sd, and variation information Dd1 and Dd2.
Q = q · sd / (sd−Dd1−Dd2) (7)

In the above-described example, the wiring capacitance value Q is corrected using only the distance information sd. However, a pattern dimension in a direction orthogonal to the direction of the interval between two patterns facing each other at an interval can also be used. Since this pattern dimension is a parameter proportional to the value of the wiring capacitance, the dimension information is ls, and the variation information obtained from the dimension information ls using any one of the above formulas (1) to (3) is obtained. Assuming Ds, the above-described equation (7) becomes the following equation (8).
Q = q · {sd / (sd−Dd1−Dd2)} · {(ls + Ds) / ls} (8)

Also, the wiring capacitance value can be corrected when the height of the wiring is changed. The variation Dh of the height h can be expressed as a function of the pattern area and pattern width in the following formula (9).
Dh = c (a, W) + random [σ (a, W)] (9)
Accordingly, the wiring capacitance value Q in this case changes as shown in the following formula (10).
Q = q · (h + Dh) / h (10)

(Layout design process)
Next, a layout design processing procedure according to the embodiment of the present invention will be described. FIG. 9 is a flowchart showing a layout design processing procedure according to the embodiment of the present invention. In the flowchart of FIG. 9, the processing procedure from step S901 to step S909 is the above-described netlist generation processing procedure.

  In FIG. 9, first, arbitrary pattern data is extracted from the layout data 300 (step S901). When the extracted pattern data is the pattern data of the gate electrode (step S902: gate), gate length information is calculated from the pattern data (step S903). For example, if the extracted pattern data is the gate electrode pattern data 323b shown in FIG. 7, the gate length information lg is calculated.

  Further, distance information to the pattern data of another gate electrode adjacent in parallel with the pattern data of the gate electrode is calculated (step S904). When the extracted pattern data is the gate electrode pattern data 323b shown in FIG. 7, distance information sg1 and sg2 are calculated.

  Further, the density information a of the extracted pattern data is calculated (step S905). Then, using the gate length information lg, distance information sg1, sg2, and density information a, a variation parameter (correction amount c and variation amount σ) is extracted from the variation parameter table 254 (step S906).

  Next, variation information is calculated using any one of the equations (1) to (4) and the extracted variation parameters (correction amount c and variation amount σ) (step S907). For example, in the above example, the variation information D1 of the left end side 701b and the variation information D2 of the right end side 702b are calculated, and the variation information Dg is calculated from the variation information D1 and D2.

  Then, the net list 600 is corrected (step S908). Specifically, the description of the extracted pattern data is specified from the description content of the netlist 600, and the specified description is corrected using the calculated variation information. In the above-described example, the gate length information lg (lg = 120 nm) of the gate electrode pattern data 323b is specified, and the calculated variation information Dg is added to the specified gate length information lg. Thereby, gate length information can be corrected.

  On the other hand, when the extracted pattern data is the pattern data of the wiring pattern in step S902 (step S902: wiring), dimension information such as wiring length information and wiring width information of the wiring pattern is calculated (step S909). . For example, when the extracted pattern data is the pattern data 333b of the wiring pattern shown in FIG. 8, the wiring width information lw and the dimension information ls are calculated.

  Further, distance information from the pattern data of the wiring pattern to the pattern data of another wiring pattern adjacent in parallel to the pattern data is calculated (step S910). For example, when the extracted pattern data is the pattern data 333b of the wiring pattern shown in FIG. 7, distance information sw1, sw2, and sd are calculated.

  Further, the density information a of the extracted pattern data is calculated (step S911). Then, the variation parameters (correction amount c and variation amount σ) are extracted from the variation parameter table 254 using the dimension information, distance information, and density information a (step S912). In the above-described example, when the wiring resistance value is corrected, the variation parameters (correction amount c and variation amount σ) are extracted from the variation parameter table 254 using the wiring width information lw, the distance information sw1, sw2, and the density information a. . In the case of correcting the wiring capacitance value, the variation parameters (correction amount c and variation amount σ) are extracted from the variation parameter table 254 using the wiring width information lw, the distance information sd, and the density information a.

  Next, variation information is calculated using any one of the equations (1) to (4) and the extracted variation parameters (correction amount c and variation amount σ) (step S913). For example, in the above-described example, when the wiring resistance value is corrected, the variation information D3 of the left end side 801b and the variation information D4 of the right end side 802b are calculated, and the variation information Dw is calculated from the variation information D3 and D4. . Similarly, in the case of correcting the wiring capacitance value, the variation information Dd and Ds are calculated.

  Then, the wiring resistance value and the wiring capacitance value of the wiring pattern represented by the extracted pattern data are calculated (step S914). In the above example, the wiring resistance value R is calculated using the above equation (5) (or (6)). Further, the wiring capacitance value Q is calculated using the above equation (7) (or the above equation (8)).

  Thereafter, the net list is corrected (step S915). Specifically, the wiring resistance value and wiring capacitance value of the extracted pattern data are specified from the description content of the net list, and updated to the calculated wiring capacitance value and the calculated wiring capacitance value. In the above example, the wiring resistance value r and the wiring capacitance value q of the wiring pattern pattern data 333b are specified, and the calculated wiring resistance value R and wiring capacitance value Q are updated from the wiring resistance value r and wiring capacitance value q. To do. Thereby, the wiring resistance value and the wiring capacitance value described in the net list 600 can be corrected.

  Then, it is determined whether there is extracted pattern data (step S916). When there is unextracted pattern data (step S916: Yes), the process proceeds to step S901. On the other hand, when there is no unextracted pattern data (step S916: No), a circuit simulation is executed (step S917). The layout data is verified using the circuit simulation result.

  In this verification, if it is determined that the layout data is valid, that is, if the operation is OK (step S918: Yes), the layout data is output (step S919). On the other hand, when it is determined that the layout data is not valid, that is, when the operation is not OK (step S918: No), the layout data is corrected (step S920). Then, the process proceeds to step S901.

  As described above, according to the net list generating apparatus 202 according to the embodiment of the present invention, the dimensional information such as the gate length, the wiring width, and the wiring length of the pattern data included in the layout data 300, and the adjacent pattern data Is used to obtain a correction amount c indicating a constant error in dimension information of pattern data and a fluctuation amount σ indicating an indefinite error, and a random value of the fluctuation amount σ is calculated.

  Therefore, it is possible to represent a variation that can occur in an actual manufacturing process, which is more realistic than a uniform variation or a completely random variation. This can improve the accuracy of the netlist used for circuit simulation. In addition, the variation that occurs in the manufacturing process includes the influence of the curvature of the wafer, etc., but it is assumed that the pattern data is arranged in the curved portion of the wafer by using the above-described equation (3). Realistic variations can be expressed. Therefore, the accuracy of the netlist 600 used for circuit simulation can be improved in consideration of the surface state of the wafer.

  Further, the density information a calculated by the above-described density information calculation unit 253 is information calculated as a ratio of the pattern area indicated by an arbitrary reference area. The influence of the peripheral pattern density on the variation differs depending on the distance from the target pattern) to the peripheral pattern existing around the target pattern.

  For example, a peripheral pattern that exists in the vicinity of a target pattern is considered to be greatly affected by the pattern, and the effect is reduced as the distance from the target pattern increases. For this reason, if the density information a is defined by the following formula (11), the density information a can be expressed as an effective pattern density.

∬T (x, y) · g (x−x ₀ , y−y ₀ ) dxdy (11)
However, (x, y) is the position coordinate on the wafer, (x ₀ , y ₀ ) is the position coordinate where the pattern of interest exists, and T (x, y) is the position coordinate (x, y) if there is a pattern A function that is “1” or “0” if not, g (x, y) is a distance function that indicates the degree of influence of pattern density, and a function that is “1” when integrated over the entire region.

  Moreover, c and (sigma) mentioned above can be calculated | required by optics and an etching simulation. For example, OPC is applied to the pitch and width patterns described in the table. Thereafter, optical and etching simulations are performed under normal conditions to determine the finished dimensions. The difference between the finished dimension and the ideal value is set as a correction amount c. Next, the pattern dimensions when the etching conditions such as focus, exposure amount, time and pressure are shifted are obtained by optical and etching simulation. The difference between this pattern dimension and the normal pattern dimension is defined as a fluctuation amount σ.

  As described above, according to the net list generation device and the net list generation method according to the embodiment of the present invention, there is an effect that evaluation design of a semiconductor device can be performed realistically and with high accuracy.

  In the above-described embodiment, by using the variation information generated by the variation information generation unit 205, the net list is corrected by the net list correction unit, and the corrected net list is input to the circuit simulation execution unit 207. The circuit simulation is executed, but the variation information generated by the variation information generation unit 205 and the net list extracted by the net list extraction unit 261 are input to the circuit simulation execution unit 207, so that the circuit simulation is performed. A simulation may be executed. Also with this configuration, the same effects as those of the above-described embodiment can be achieved.

  The netlist generation method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer, a workstation, or a CAD. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Additional remark 1) The input means which receives the input of the arbitrary layout data regarding a semiconductor device,
Pattern data extraction means for extracting arbitrary pattern data from the layout data input by the input means;
Variation information generating means for generating information relating to variations in dimensions of pattern data extracted by the pattern data extracting means;
Net list extraction means for extracting a net list of the semiconductor device from the layout data input by the input means;
Circuit simulation executing means for executing circuit simulation of the semiconductor device based on the variation information generated by the variation information generating means and the net list extracted by the net list extracting means;
An apparatus for evaluating and designing a semiconductor device, comprising:

(Supplementary Note 2) The variation information generating means includes:
Dimension information calculating means for calculating information relating to the dimensions of the pattern data extracted by the pattern data extracting means;
Distance information calculation means for calculating information on the distance between the pattern data extracted by the pattern data extraction means and the same type of pattern data adjacent to the pattern data in parallel;
Based on the information on the dimensions calculated by the dimension information calculation means and the information on the distances calculated by the distance information calculation means, information on the dimension variation of the pattern data extracted by the pattern data extraction means is generated. The apparatus for evaluating and designing a semiconductor device according to appendix 1, wherein:

(Supplementary Note 3) The variation information generating means includes:
Density information calculation means for calculating information on the density of the pattern data in an area including the pattern data extracted by the pattern data extraction means;
The semiconductor device according to appendix 2, further comprising: generating information related to a variation in dimension of the pattern data extracted by the pattern data extracting unit based on the information related to the density calculated by the density information calculating unit. Evaluation design equipment.

(Supplementary Note 4) The variation information generating means includes:
Based on the information on the dimensions calculated by the dimension information calculation means and the information on the distances calculated by the distance information calculation means, a correction amount related to a certain bias generated in the layout design process of the semiconductor device, A correction amount / variation amount extraction means for extracting a fluctuation amount representing a fluctuation of the correction amount with respect to a bias that occurs by chance during manufacture of a semiconductor device;
Variation information calculating means for calculating information on the variation in the dimensions of the pattern data extracted by the pattern data extracting means based on the correction amount and the fluctuation amount extracted by the correction amount / variation amount extracting means;
The evaluation design apparatus for a semiconductor device according to appendix 2 or 3, characterized by comprising:

(Supplementary Note 5) The variation information calculating means includes:
6. The semiconductor device according to appendix 4, wherein the variation information is calculated based on the correction amount and a value obtained from a random function that randomly varies within a predetermined range based on the variation amount. Evaluation design generation device.

(Additional remark 6) The said random function is a function which changes at random based on the coordinate position on the wafer of the said pattern data, The evaluation design apparatus of the semiconductor device of Additional remark 5 characterized by the above-mentioned.

(Supplementary Note 7) A net list correction unit that corrects the net list extracted by the net list extraction unit based on the variation information generated by the variation information generation unit,
The circuit simulation execution means includes
7. The semiconductor device evaluation design apparatus according to claim 1, wherein a circuit simulation of the semiconductor device is executed based on the net list corrected by the net list correcting means.

(Supplementary note 8) The pattern data extracting means includes:
Extracting pattern data representing the gate pattern from the pattern data included in the layout data input by the input means,
The variation information generating means includes
Generating information about variations in gate length of pattern data representing a gate pattern extracted by the pattern data extraction unit;
The netlist correcting means includes
The information on the gate length included in the net list extracted by the net list extracting unit is corrected based on the information on the variation in gate length generated by the variation information generating unit. 2. An evaluation design apparatus for a semiconductor device according to 1.

(Supplementary note 9) The pattern data extracting means includes:
Extracting pattern data representing a wiring pattern from pattern data included in the layout data input by the input means,
The variation information generating means includes
Based on the information on the wiring dimension of the pattern data representing the wiring pattern extracted by the pattern data extracting means, generates information on the wiring dimension variation of the wiring pattern,
The netlist correcting means includes
The wiring based on the information on the wiring dimension variation generated by the variation information generating unit and the information on the wiring resistance of the wiring pattern included in the net list extracted by the net list extracting unit. The evaluation design apparatus for a semiconductor device according to appendix 7, wherein information on a new wiring resistance of the pattern is generated.

(Supplementary Note 10) The pattern data extracting means includes:
Extracting pattern data representing a wiring pattern from pattern data included in the layout data input by the input means,
The variation information generating means includes
Based on the information on the wiring dimension of the pattern data representing the wiring pattern extracted by the pattern data extracting means, generates information on the wiring dimension variation of the wiring pattern,
The netlist correcting means includes
The wiring based on the information on the wiring dimension variation generated by the variation information generating unit and the information on the wiring capacity of the wiring pattern included in the net list extracted by the net list extracting unit. The evaluation design apparatus for a semiconductor device according to appendix 7, wherein information on a new wiring capacity of the pattern is generated.

(Supplementary Note 11) Input means for receiving input of arbitrary layout data regarding the semiconductor device;
Pattern data extraction means for extracting arbitrary pattern data from the layout data input by the input means;
Variation information generating means for generating information relating to variations in dimensions of pattern data extracted by the pattern data extracting means;
Net list extraction means for extracting a net list of the semiconductor device from the layout data input by the input means;
Netlist correcting means for correcting the netlist extracted by the netlist extracting means based on the variation information generated by the variation information generating means;
An apparatus for evaluating and designing a semiconductor device, comprising:

(Additional remark 12) The input process which inputs the arbitrary layout data regarding a semiconductor device,
A pattern data extraction step for extracting arbitrary pattern data from the layout data input by the input step;
A variation information generation step for generating information on variation in the dimensions of the pattern data extracted by the pattern data extraction step;
A netlist extraction step of extracting a netlist of the semiconductor device from the layout data input by the input step;
A circuit simulation execution step of executing a circuit simulation of the semiconductor device based on the variation information generated by the variation information generation step and the netlist extracted by the netlist extraction step;
A method for evaluating and designing a semiconductor device, comprising:

(Additional remark 13) The input process which inputs the arbitrary layout data regarding a semiconductor device,
A pattern data extraction step for extracting arbitrary pattern data from the layout data input by the input step;
A variation information generation step for generating information on variation in the dimensions of the pattern data extracted by the pattern data extraction step;
A netlist extraction step of extracting a netlist of the semiconductor device from the layout data input by the input step;
Based on the variation information generated by the variation information generation step, a netlist correction step for correcting the netlist extracted by the netlist extraction step;
A method for evaluating and designing a semiconductor device, comprising:

(Additional remark 14) The input process which inputs the arbitrary layout data regarding a semiconductor device,
A pattern data extraction step for extracting arbitrary pattern data from the layout data input in the input step;
A variation information generating step for generating information on variations in the dimensions of the pattern data extracted by the pattern data extracting step;
A netlist extraction step for extracting a netlist of the semiconductor device from the layout data input by the input step;
A circuit simulation execution step of executing a circuit simulation of the semiconductor device based on the variation information generated by the variation information generation step and the netlist extracted by the netlist extraction step;
A computer-executable program for evaluating and designing a semiconductor device.

(Supplementary Note 15) An input process for inputting arbitrary layout data related to a semiconductor device;
A pattern data extraction step for extracting arbitrary pattern data from the layout data input in the input step;
A variation information generating step for generating information on variations in the dimensions of the pattern data extracted by the pattern data extracting step;
A netlist extraction step for extracting a netlist of the semiconductor device from the layout data input by the input step;
A netlist correction step for correcting the netlist extracted by the netlist extraction step based on the variation information generated by the variation information generation step;
A computer-executable program for evaluating and designing a semiconductor device.

(Supplementary Note 16) A computer-readable recording medium in which the layout design program according to Supplementary Note 14 or 15 is recorded.

  As described above, the semiconductor device evaluation and design apparatus, the semiconductor device evaluation and design method, the semiconductor device evaluation and design program, and the recording medium are useful for generating a netlist for use in semiconductor device layout design. In particular, it is suitable for generating a net list for circuit simulation.

It is a block diagram which shows the hardware constitutions of the evaluation design apparatus of the semiconductor device concerning embodiment of this invention. It is a block diagram which shows the functional structure of the evaluation design apparatus of the semiconductor device concerning embodiment of this invention. It is explanatory drawing which shows an example of the layout data memorize | stored in the layout database. It is explanatory drawing which shows an example of the variation parameter table. It is explanatory drawing which shows Gaussian distribution. It is explanatory drawing which shows an example of the net list extracted from the layout data. FIG. 4 is an explanatory diagram showing a modification example of pattern data of the gate electrode represented by the layout data shown in FIG. 3. FIG. 4 is an explanatory diagram illustrating a modification example of the wiring resistance value of the wiring pattern represented by the layout data illustrated in FIG. 3. It is a flowchart which shows the layout design processing procedure concerning embodiment of this invention. It is the graph which plotted the fluctuation | variation of the dimension of the gate by focus shift | offset | difference in a light exposure process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 200 Semiconductor device evaluation design apparatus 201 Layout database 203 Layout data input part 204 Pattern data extraction part 205 Variation information generation part 206 Net list generation part 207 Circuit simulation execution part 208 Layout data verification part 209 Layout data correction part 210 Layout data output part 251 Dimension information calculation unit 252 Distance information calculation unit 253 Density information calculation unit 254 Variation parameter table 255 Variation parameter extraction unit 256 Variation information calculation unit 300 Layout data 600 Netlist

Claims (6)

Input means for receiving input of arbitrary layout data relating to the semiconductor device;
Pattern data extraction means for extracting arbitrary pattern data from the layout data input by the input means;
Dimension information calculating means for calculating information relating to the dimensions of the pattern data extracted by the pattern data extracting means;
Distance information calculating means for calculating information on the distance between the pattern data extracted by the pattern data extracting means and the same kind of pattern data adjacent to the pattern data in parallel;
Based on the information on the dimensions calculated by the dimension information calculation means and the information on the distances calculated by the distance information calculation means, a correction amount related to a certain bias generated in the layout design process of the semiconductor device, A correction amount / variation amount extraction means for extracting a fluctuation amount representing a fluctuation of the correction amount with respect to a bias that occurs by chance during manufacture of a semiconductor device;
Variation information calculating means for calculating information on the variation in the dimension of the pattern data extracted by the pattern data extracting means based on the correction amount and the fluctuation amount extracted by the correction amount / variation amount extracting means;
Net list extraction means for extracting a net list of the semiconductor device from the layout data input by the input means;
Circuit simulation executing means for executing circuit simulation of the semiconductor device based on the variation information generated by the variation information calculating means and the net list extracted by the net list extracting means;
An apparatus for evaluating and designing a semiconductor device, comprising: Density information calculation means for calculating information on the density of the pattern data in an area including the pattern data extracted by the pattern data extraction means;
The variation information calculation means includes:
2. The semiconductor according to claim 1, further comprising: calculating information related to a variation in dimension of the pattern data extracted by the pattern data extracting unit based on information relating to the density calculated by the density information calculating unit. Equipment evaluation design equipment. The variation information calculation means includes:
The variation information is calculated based on the correction amount and a value obtained from a random function that randomly varies within a predetermined range based on the variation amount. Semiconductor device evaluation and design equipment. 4. The evaluation design apparatus for a semiconductor device according to claim 3, wherein the random function is a function that randomly varies based on a coordinate position on the wafer of the pattern data. A computer comprising input means, pattern data extraction means, dimension information calculation means, distance information calculation means, correction amount / variation amount extraction means, variation information calculation means, netlist extraction means, and circuit simulation execution means,
An input step of receiving input of arbitrary layout data related to the semiconductor device by the input means ;
A pattern data extracting step for extracting arbitrary pattern data from the layout data input in the input step by the pattern data extracting means ;
A dimension information calculating step of calculating information related to the dimension of the pattern data extracted by the pattern data extracting step by the dimension information calculating unit;
A distance information calculating step of calculating information on the distance between the pattern data extracted by the pattern data extracting step and the same type of pattern data adjacent in parallel to the pattern data by the distance information calculating unit;
Occurs in the layout design process of the semiconductor device based on the information on the dimension calculated by the dimension information calculation step and the information on the distance calculated by the distance information calculation step by the correction amount / variation amount extraction means. A correction amount / variation amount extraction step for extracting a correction amount relating to a certain bias, and a fluctuation amount representing a fluctuation of the correction amount relating to a bias that occurs during manufacturing of the semiconductor device;
Variation information for calculating, by the variation information calculation means, information on variation in the dimension of the pattern data extracted by the pattern data extraction step based on the correction amount and variation amount extracted by the correction amount / variation amount extraction step. A calculation process;
A netlist extraction step of extracting a netlist of the semiconductor device from the layout data input by the input step by the netlist extraction means ;
By the circuit simulation executing means, and the variation information generated by said variation information calculating step, on the basis of the netlist extracted by the netlist extraction step, and a circuit simulation execution step of executing a circuit simulation of the semiconductor device ,
Evaluation method of designing a semiconductor device, characterized by the execution. An input process for accepting input of arbitrary layout data relating to the semiconductor device;
A pattern data extraction step for extracting arbitrary pattern data from the layout data input in the input step;
A dimension information calculating step for calculating information on the dimension of the pattern data extracted by the pattern data extracting step;
A distance information calculation step for calculating information regarding the distance between the pattern data extracted by the pattern data extraction step and the same type of pattern data adjacent to the pattern data in parallel;
Based on the information on the dimensions calculated by the dimension information calculation step and the information on the distance calculated by the distance information calculation step, the correction amount regarding a certain bias generated in the layout design process of the semiconductor device, A correction amount / variation amount extraction step for extracting a variation amount representing a variation of the correction amount with respect to a bias that occurs by chance during manufacture of a semiconductor device;
A variation information calculation step for calculating information on variation in the dimensions of the pattern data extracted by the pattern data extraction step based on the correction amount and the variation amount extracted by the correction amount / variation amount extraction step;
A netlist extraction step for extracting a netlist of the semiconductor device from the layout data input by the input step;
A circuit simulation execution step of executing a circuit simulation of the semiconductor device based on the variation information generated by the variation information calculation step and the netlist extracted by the netlist extraction step;
A computer-executable program for evaluating and designing a semiconductor device.

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