JP4442406B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit in which, for example, a circuit that requires a synchronous reset and a circuit that operates by an asynchronous reset coexist, and particularly relates to a timing at which a reset signal is released.

  In recent system LSIs, many functional blocks are integrated, and as a result, the clock tends to become complicated.

  Against this background, the relationship between the timing of releasing hardware reset and the clock, and the timing of supplying the clock during the reset, conventionally, by creating a reset tree in the layout design and aligning the release timing, etc. Measures have been taken.

By the way, in the hardware reset of the system, the circuit may become unstable depending on the circuit configuration in which the timing at which the reset signal is released overlaps the edge of the clock.
In the logic simulation, since the propagation signal becomes indefinite, it is necessary to take some measures, but in an actual system, it is left as it is because it is an asynchronous signal.
And the more asynchronous multiple clock lines, the more difficult it is to design them so that they don't overlap.

On the other hand, some circuit blocks employ a synchronous reset, and there are some that need to continue to input a clock even during the reset.
By mixing these, it is necessary to accurately control the relationship between reset and clock.

  However, as described above, measures such as aligning the reset release timing have been conventionally performed in the layout design, but this method becomes difficult as the system scale increases.

  An object of the present invention is to provide a semiconductor integrated circuit capable of preventing the clock edge and the reset edge from overlapping.

To achieve the above object, the present invention is different as an asynchronous multiple of the external clock signal a plurality of internal circuits can be input to, a plurality of the time of reset is required to be synchronized reset by a common external clock signal synchronized with each other reset circuit, and starts a plurality of internal circuits including the common not necessary to input an external clock signal asynchronous reset circuits during reset, the oscillation with power supply, the elapsed time from the time the power is turned on Then, a phase synchronization circuit that generates a stable internal clock signal and outputs it to any of the plurality of internal circuits, a plurality of clock gate circuits connected to the input terminals of the clock signals of the plurality of internal circuits, external reset signal is input, have a reset control circuit for resetting the plurality of internal circuits, the reset control circuit, said When a unit reset signal is input, the clock signals to all of the plurality of internal circuits are blocked by the plurality of clock gate circuits, and a period in which the internal clock signal stabilizes after the clock signals are blocked A period in which all of the clock reset signals are released by the plurality of clock gate circuits, the plurality of synchronous reset circuits are initialized, and the period of the clock signals is released and then the plurality of synchronous reset circuits can be initialized. When the time elapses, the clock signals to all of the plurality of internal circuits are again shut off by the plurality of clock gate circuits, and the plurality of synchronous reset circuits and the asynchronous reset circuits are turned off during the second shut-off of the clock signal. All of the plurality of internal circuits including the same are reset at the same time, and the plurality of internal circuits are When the period is reset has elapsed, it releases any interruption by the plurality of clock gate circuit, to start the respective operations of the plurality of internal circuits.

According to the present invention, for example, after the power is turned on, when the control circuit receives a reset signal, the control circuit gives a sufficiently long reset to the first circuit that requires a synchronous reset that requires at least a clock.
The control circuit controls the clock to stop before and after the various clock edges and the reset release edge so that they do not overlap.

According to the present invention, it is possible to eliminate in principle the overlap of the clock edge and the reset edge, and there is an advantage that it is not necessary to align the reset skew.
The system can ensure the safety of reset release.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

  As shown in FIG. 1, the semiconductor integrated circuit 10 of the present embodiment is supplied with a plurality of clocks CK1 to CKn, a reset signal RST, and a control clock CLK.

  As shown in FIG. 1, the semiconductor integrated circuit 10 includes a PLL 11, selectors 12 to 14, gate circuits 15 to 17, a clock / reset control circuit 18, and a first circuit that requires a synchronous reset (hereinafter referred to as a synchronous reset circuit). 19 and 20, and a second circuit (hereinafter referred to as an asynchronous reset circuit) 21 that operates by asynchronous reset.

The PLL 11 receives the clock CK1, performs frequency division processing, etc., and outputs two clocks CK11 and CK12 having different frequencies synchronized with the reference clock to the selector.
The PLL 11 requires a predetermined time from the rising edge until the phase synchronization is stabilized.

  The selector 12 selects any one of the input clocks CK 1 and the output clocks CK 11 and CK 12 of the PLL 11 in accordance with a select signal from a control system (not shown) and outputs the selected clock to the gate circuit 15.

  The selector 13 selects any one of the output clock CK11, the input clocks CK2, and CK3 of the PLL 11 according to a select signal from a control system (not shown) and outputs the selected clock to the gate circuit 16.

  The selector 14 selects any one of the input clocks CK2 and CKn according to a select signal from a control system (not shown) and outputs the selected clock to the gate circuit 17.

  The gate circuit 15 supplies the clock selected by the selector 12 to the asynchronous reset circuit 21 only during a high level period when the clock supply control signal (clock enable signal) CKEN supplied by the clock / reset control circuit 18 is active, for example.

  The gate circuit 16 supplies the clock selected by the selector 12 to the synchronous reset circuit 19 only during a high level period when the clock supply control signal (clock enable signal) CKEN supplied by the clock / reset control circuit 18 is active, for example.

  The gate circuit 17 supplies the clock selected by the selector 12 to the synchronous reset circuit 20 only during a high level period when the clock supply control signal (clock enable signal) CKEN supplied by the clock / reset control circuit 18 is active, for example.

  The clock / reset control circuit 18 is supplied with the control clock CLK and the reset signal RST, waits for the PLL 11 to stabilize, gives a sufficiently long reset to a synchronous reset circuit that requires a synchronous reset that requires a clock, The clock enable signal CKEN is output to each gate circuit so that the clock is stopped before and after the clock edge and the reset release edge so as not to overlap each other, and the controlled reset signal CRST is output to the synchronous clock circuit and the asynchronous clock circuit.

FIG. 2 is a circuit diagram showing a configuration example of a main part of the clock / reset control circuit 18.
3A to 3F are timing charts for explaining the operation of each part of the clock / reset control circuit 18 of FIG.

  The clock / reset control circuit 18 in FIG. 2 includes counters 181 to 184 connected in cascade and a gate circuit 185.

  The counters 181 to 184 are supplied with a low level active reset signal RST and, for example, a control clock CLK of 27 MHz.

  The first-stage counter 181 is reset by receiving the reset signal RST at a low level, counts up the number of pulses of the control clock CLK, and a set value (128 × 1024) corresponding to a predetermined time until the count value is stabilized by the PLL 11 Then, as shown in FIG. 3A, for example, the high level and active count signal CNT1 is output to the enable terminal EN of the counter 182 of the next stage and the gate circuit 185.

  When the counter 182 receives the reset signal RST at a low level and is reset, and receives the high-level cowton signal CNT1 output from the counter 181 at the enable terminal EN, the counter 182 counts up the number of pulses of the control clock CLK, and the count value 3 becomes the set value (128), for example, a high level active count signal CNT2 is output to the enable terminal EN of the next-stage counter 183 and the gate circuit 185, as shown in FIG.

  When the counter 183 receives the reset signal RST at a low level and is reset, and receives the high-level cowton signal CNT2 output from the counter 182 at the enable terminal EN, the counter 183 counts up the number of pulses of the control clock CLK, and the count value 3 becomes the set value (128), for example, as shown in FIG. 3C, a high level active count signal CNT3 is output to the enable terminal EN of the counter 184 at the next stage and the gate circuit 185.

  When the counter 184 receives the reset signal RST at a low level and is reset, and receives the high-level cowton signal CNT3 output from the counter 183 at the enable terminal EN, the counter 184 counts up the number of pulses of the control clock CLK, and the count value When the value reaches the set value (128), as shown in FIG. 3D, for example, a high level active count signal CNT4 is output to the gate circuit 185.

When the gate circuit 185 receives the high-level count signal CNT1 from the counter 181, as shown in FIG. 3E, the gate circuit 185 generates a clock supply control signal (clock enable signal) CKEN for a predetermined period, specifically, the control clock CLK. For 128 pulses (a period equivalent to the count set value of the counter 182), the signal is set to the high level and output to the gate circuits 15-17.
That is, the gate circuit 185 outputs the high level clock supply control signal CKEN in response to the input of the high level count signal CNT1 by the counter 181 and responds to the input of the count signal CNT2 by the counter 182. Switch CKEN from high level to low level.
When the gate circuit 185 receives the high level count signal CNT3 from the counter 183 after switching the clock supply control signal CKEN to the low level in response to the high level count signal CNT2 from the counter 182, FIG. As shown in (F), a high level reset signal CRST is output to the synchronous reset circuits 19 and 20 and the asynchronous reset circuit 21.
When the gate circuit 185 outputs the reset signal CRST in response to the high level count signal CNT3 from the counter 183 and then receives the high level count signal CNT4 from the count 184, the gate circuit 185 is shown in FIGS. As described above, the clock supply control signal CKEN is set to a high level for a predetermined period, specifically, 128 pulses of the control clock CLK (a period equivalent to the count set value of the counter 182) and output to the gate circuits 15-17. To do.

Next, the operation according to the above configuration will be described with reference to FIGS.
4A shows the control clock CLK, FIG. 4B shows the reset signal RST, FIG. 4C shows the controlled reset signal CRST in the semiconductor integrated circuit 10, and FIG. 4D shows the control signal CLK. The clock supply control signal (clock enable signal) CKEN at the time of enable, FIG. 4E shows the clock supply control signal (clock enable signal) CKEN at the time of disable, and FIGS. CKn is shown respectively.

In the semiconductor integrated circuit 10, for example, after the power is turned on, until the PLL 11 starts oscillating and the phase-locked loop is stabilized, as shown in FIGS. 4 (F) to (I), all the various clocks CK1 to CKn Input to is blocked.
Then, as shown in FIGS. 4A and 4B, only the control clock CLK and the hardware reset signal RST are supplied to the clock / reset control circuit 18.

In the clock / reset control circuit 18, the counters 191 to 184 are reset in response to the reset signal RST.
First, in the first-stage counter 181, the number of pulses of the control clock CLK is counted up. When the count value reaches a set value (128 × 1024) corresponding to a predetermined time until the PLL 11 is stabilized, the counter 181 becomes active at a high level. Count signal CNT1 is output to the gate circuit 185 and the enable terminal EN of the counter 182 of the next stage.

In the gate circuit 185, in response to the high-level count signal CNT1 from the counter 181, the clock supply control signal (clock enable signal) CKEN is supplied for a predetermined period, specifically, 128 pulses of the control clock CLK (in the counter 182). It is set to the high level only for a period equivalent to the count set value and is output to the gate circuits 15-17.
That is, when the PLL 11 is stabilized, the clock / reset control circuit 18 outputs a high level clock supply control signal CKEN to the gate circuits 15 to 17, as shown in FIG. As shown in (I), all the clocks CK1 to CKn are supplied to the synchronous reset circuit 19 and the like for a certain period, and sufficient initialization is performed for the module (circuit) requiring synchronous reset.

In the counter 182 of the clock / reset control circuit 18, the enable terminal EN receives the high-level cowton signal CNT1 output from the counter 181 to count up the number of pulses of the control clock CLK and set the count value to the set value (128 ), The high level active count signal CNT2 is output to the gate circuit 185 and the enable terminal EN of the counter 183.
In the gate circuit 185, the clock supply control signal CKEN is switched from the high level to the low level in response to the input of the count signal CNT2 by the counter 182.
As a result, as shown in FIGS. 4F to 4I, the supply of the clocks CK1 to CKn to the synchronous reset circuit 19 and the like is stopped.

In the counter 183 of the clock / reset control circuit 18, the enable terminal EN receives the high-level cowton signal CNT 2 output from the counter 182, the number of pulses of the control clock CLK is counted up, and the count value is set to the set value (128 ), The high level active count signal CNT3 is output to the gate circuit 185 and the enable terminal EN of the counter 184.
In the gate circuit 185, the clock supply control signal CKEN is switched to the low level in response to the high level count signal CNT2 from the counter 182, and then the high level by the counter 183 after a predetermined time has passed (after a certain period of time). In response to the count signal CNT3, a high level reset signal CRST is output to the synchronous reset circuits 19 and 20 and the asynchronous reset circuit 21, as shown in FIG.
In other words, the supply of the reset signal is canceled a predetermined time after the supply of the clocks CK1 to CKn is stopped, and the synchronous reset circuit 19 and the asynchronous reset circuit 21 are reset.

In the counter 184 of the clock / reset control circuit 18, the high-level cowton signal CNT2 output from the counter 183 is received at the enable terminal EN, the number of pulses of the control clock CLK is counted up, and the count value is set to the set value (128 ), The high level active count signal CNT4 is output to the gate circuit 185.
The gate circuit 185 outputs the reset signal CRST in response to the high level count signal CNT3 from the counter 183, and after a predetermined time has passed (after a certain period of time), the high level count signal CNT4 from the count 184 is output. Then, as shown in FIG. 4D, the clock supply control signal CKEN is set to the high level for a predetermined period, specifically, for 128 pulses of the control clock CLK (a period equivalent to the count set value of the counter 182). It is set and output to the gate circuits 15-17.
That is, when the reset is completely cancelled, the supply of the clock CK1 and the like is resumed after a certain period of time.

  The semiconductor integrated circuit 10 is controlled so that the operation of the system is started after the above operation is completely completed.

As described above, according to the present embodiment, the PLL 11 waits for stability, gives a sufficiently long reset to a synchronous reset circuit that requires a synchronous reset that requires a clock, and releases various clock edges and resets. The clock enable signal CKEN is output from each gate circuit 15 to 7 so as to stop the clock before and after the edges of the clocks, and the clock / reset control circuit 21 outputs the reset signal CRST to the synchronous clock circuit and the asynchronous clock circuit. Therefore, it is possible in principle to eliminate the overlap of the clock edge and the reset edge, and there is an advantage that it is not necessary to align the reset skew.
As a result, the system can ensure the safety of reset release.

  The above-described embodiment is an example, and the count value of the counter is set according to the system. The circuit configuration is not limited to the above-described embodiment, and various modes are possible.

1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. It is a circuit diagram which shows the structural example of the principal part of the clock / reset control circuit in this embodiment. 3 is a timing chart for explaining the operation of each part of the clock / reset control circuit 18 of FIG. 5 is a timing chart for explaining a clock / reset control operation of the semiconductor integrated circuit according to the present embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit, 11 ... PLL, 12-14 ... Selector, 15-17 ... Gate circuit, 18 ... Clock / reset control circuit, 181-184 ... Counter, 185 ... Gate circuit, 19, 20 ... Synchronous reset circuit, 21: Asynchronous reset circuit.

Claims (1)

As a plurality of internal circuits that can input a plurality of different asynchronous external clock signals , a plurality of synchronous reset circuits that need to be synchronously reset by a common external clock signal at the time of resetting, and the common at the time of resetting a plurality of internal circuits including the external clock signal asynchronous reset circuitry is not necessary to enter,
A phase synchronization circuit that starts oscillation upon power-on, generates a stable internal clock signal when time elapses from when the power is turned on, and outputs it to any of the plurality of internal circuits;
A plurality of clock gate circuits connected to clock signal input terminals of each of the plurality of internal circuits;
External reset signal is input, have a reset control circuit for resetting the plurality of internal circuits,
The reset control circuit includes:
When the external reset signal is input, the clock signals to all the plurality of internal circuits are cut off by the plurality of clock gate circuits,
When a period during which the internal clock signal is stabilized after the clock signal is shut off, all the clock signal blocking by the plurality of clock gate circuits is released, and the plurality of synchronous reset circuits are initialized,
When a period in which the plurality of synchronous reset circuits can be initialized has elapsed after releasing the blocking of the clock signal, the clock signals to all the plurality of internal circuits are again blocked by the plurality of clock gate circuits,
During the second interruption of the clock signal, simultaneously reset all the plurality of internal circuits including the plurality of synchronous reset circuits and the asynchronous reset circuit;
A semiconductor integrated circuit that releases all of the interruptions by the plurality of clock gate circuits and starts the operations of the plurality of internal circuits when a period during which the plurality of internal circuits are reset by the reset has elapsed .

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