JP4442382B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device.

More specifically , the present invention relates to a solid-state imaging device such as a CCD solid-state imaging device or an amplification type solid-state imaging device.

  Taking an n-type semiconductor substrate as an example, the imaging region of the CCD solid-state imaging device is formed with a p-type well region on the n-type semiconductor substrate, and an n-type photoelectric conversion portion, ie, a light receiving portion, on the surface of the well region. A portion is formed, and a plurality of light receiving portions are arranged in a matrix.

In such a CCD solid-state imaging device, the allowable amount of signal charge e accumulated in the light receiving portion by the incidence of light, the so-called charge amount handled by the light receiving portion, is a p-type well as shown in the potential distribution diagram of FIG. is determined by the height of the potential barrier phi _a of the configured overflow barrier OFB in the region. That is, when the signal charges e accumulated in the light receiving section exceeds the amount of charges, is swept to the n-type substrate that the exceeding amount charge constitutes an overflow drain OFD beyond the potential barrier phi _a of the overflow barrier .
A CCD solid-state imaging device having such a vertical overflow structure is also disclosed in Patent Document 1, for example.

Handling charge amount of the light receiving portion, i.e. the height of the potential barrier phi _a of the overflow barrier OFB is controlled bias voltage applied to the substrate serving as the overflow drain, i.e., a so-called substrate voltage V _sub. However, this structure, because of manufacturing variations of the device, necessary variation as shown height of the potential barrier phi _a of the overflow barrier OFB is by broken lines is large and sets the substrate voltage V _sub V _sub 'different for each device There is.

  Further, in the CCD solid-state imaging device, as shown in FIG. 22, a floating diffusion region FD for charge-voltage conversion is provided at the subsequent stage of the horizontal transfer register 1 via the horizontal output gate portion HOG, and further the floating diffusion region. A reset gate portion 2 and a reset drain region 3 are provided for resetting the signal charges transferred to the FD for each pixel.

In the horizontal transfer register 1, for example, a plurality of transfer electrodes 6 [6A, 6B] are formed on a n-type transfer channel region 5 formed on the surface of a p-type well region 2 via a gate insulating film, and are connected to each other. Two adjacent transfer electrodes 6A and 6B are taken as one set, and every other set of transfer electrodes 6 [6A, 6B] and every other transfer electrode 6 [6A, 6B], respectively. Two-phase horizontal drive pulses φH ₁ and φH ₂ are applied. For example, a p-type region 7 is formed by ion implantation in the transfer channel region 5 below each second transfer electrode 6B, and the storage unit using the first transfer electrode 6A as a storage electrode and the second transfer electrode 6B are connected to each other. A transfer portion having a transfer portion serving as a transfer electrode is formed.

The horizontal output gate portion HOG is formed by forming a gate electrode 8 through a gate insulating film, and a ground potential is applied to the gate electrode 8. The floating diffusion region FD is formed of, for example, an n-type semiconductor region and is connected to the charge detection circuit 9. t ₁ is an output terminal. The reset drain region 3 is formed of, for example, an n-type semiconductor region, and a reset voltage V _RD , for example, a power supply voltage V _DD is applied to the reset drain region 3.
The reset gate portion 2 is formed by forming a gate electrode 10 through a gate insulating film, and a reset pulse _φRG is applied to the gate electrode.

In recent CCD solid-driving circuit for applying driving pulses .phi.H ₁ to the horizontal transfer register 1, a drive circuit for applying a .phi.H _2, the reset pulse phi _RG is now incorporated in the timing generator In order to reduce power consumption, the pulse amplitude is lowered.

In such a case, since the operating point of the reset pulse φ _RG is determined by the power supply voltage V _DD which is the reset voltage V _RD , potential variation under the reset gate portion 2 shown in FIG. . It is necessary to set the DC bias value of the reset pulse phi _RG to a desired value as a countermeasure, for example, every device. The setting of the DC bias value of the reset pulse phi _RG is conventionally not only set or done in an external circuit (a so-called bias circuit), digitally in the phase-cut manner even in the self-contained.

  An amplification type solid-state image sensor is known as a solid-state image sensor. In this amplification type solid-state imaging device, holes (signal charges) obtained by photoelectric conversion are accumulated in a p-type well region of an n-channel MOS transistor (pixel transistor), and potential fluctuations in the p-type well region (that is, A change in channel current based on a change in potential of the back gate is output as a pixel signal. Here, an n-type well region is formed on a p-type substrate, and a p-type well region in which the above-described charges are accumulated is formed in the n-type well region. Also in this amplified solid-state imaging device, it is necessary to set the substrate voltage.

  On the other hand, an ultraviolet erasable ROM is known as a device that uses a SiN film as a gate insulating film and stores potential-controlled memory. In this ROM, as shown in FIG. 24, an n-type source region 12 and a drain region 13 are formed on the surface of a p-type region 11, and a silicon oxide film 14 and a silicon nitride film 15 are formed between both regions 12 and 13. For example, a polycrystalline silicon gate electrode 17 is formed through the gate insulating film 16, and electrons and holes are accumulated in the silicon nitride film 15 to produce a memory effect. However, this ROM is only digital on / off setting, and when the SiN and the gate electrode are in contact with each other, the injected electrons e are likely to leak to the gate, which is not analog DC bias control.

JP 54-95116 A

  The CCD solid-state imaging device is a product that uses the potential of a so-called MIS device, but its potential control is difficult and manufacturing variation is large. Conventionally, this potential variation is avoided by controlling the bias value applied from the outside. In contrast, the present inventor has conceived that the variation in potential is measured and selectively adjusted forcibly. The ROM described above is known as an MIS element whose operating point is changed later. However, this is an on / off digital operation, and the potential cannot be adjusted in an analog manner.

In view of the above points, there is provided a solid-state imaging device that enables potential adjustments, external adjustment-free, such as board voltage setting using the novel MIS device.

A solid-state imaging device according to the present invention includes a plurality of pixels having a signal charge storage region portion formed of a semiconductor region of a first conductivity type, means for receiving a scanning pulse voltage and outputting a signal obtained from the pixels,
A second conductivity type semiconductor region serving as an overflow control gate adjacent to the bottom of the signal charge storage region; and a first conductivity type semiconductor substrate serving as an overflow drain adjacent to the second conductivity type semiconductor region. Discharging means for discharging unnecessary signals of pixels;
A bias circuit for generating a voltage for controlling the discharging operation of the discharging means,
The bias circuit includes a load and a MISFET connected in series between a first potential and a second potential, and a bias voltage is obtained from a contact point between the load and the MISFET, and is applied to a gate insulating film of the MISFET. The charge for adjusting the threshold value is injected, the voltage applied to the semiconductor substrate of the discharge means is set by the charge injection, and the unnecessary signal of the pixel is discharged to the semiconductor substrate side .

The solid-state imaging device according to the present invention has a multi-layer structure in which the gate insulating film of the MISFET is sequentially stacked on the oxide film, the nitride film, and the oxide film in the above-described solid-state imaging device.

According to the solid-state imaging device of the present invention, the voltage applied to the semiconductor substrate in the discharging means for discharging the unnecessary signal of the pixel is the load connected in series between the bias circuit, that is, the first potential and the second potential. And a bias circuit in which a bias voltage is obtained from the contact point between the load and the MISFET and a charge for adjusting the threshold voltage is injected into the gate insulating film of the MISFET. Voltage can be set, and voltage control in the discharging means or potential control of the overflow barrier can be appropriately performed.

Thus, by generating a voltage to be applied to the semiconductor substrate of the discharge means for discharging the pixel signal by the bias circuit, a desired voltage can be applied and an appropriate discharge operation can be performed. For example, it is possible to make no external adjustment of the substrate voltage setting of a CCD solid-state image pickup device , an amplification type solid-state image pickup device or the like . In addition, by incorporating the bias circuit in the chip of the solid-state imaging device, it is possible to partially reduce the protective element.

In the solid-state imaging device, the gate insulating film of the MISFET has a multilayer structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked, so that charges accumulated in the nitride film can be retained. .

  Embodiments of the present invention will be described below with reference to the drawings.

First, an example of an element having a metal (electrode) -insulator-semiconductor structure according to the present invention, a so-called MIS element will be described. In the MIS element of this example, the potential under the gate or the threshold voltage V is controlled by controlling the accumulation amount of charges such as electrons and holes in the gate insulating film, in particular, the nitride film among them. It is configured such that _th can be set in an analog manner.

FIG. 1 shows an example of a MIS element according to the present invention as a MISFET (insulated gate field effect transistor). The MISFET 21 of this example includes a source region 23 of a second conductivity type (p type or n type) on the main surface of a semiconductor region (semiconductor well, semiconductor substrate, etc.) 22 of a first conductivity type (for example, n type or p type) and A drain region 24 is formed, and an oxide film such as a silicon oxide film (SiO ₂ ) 26, a nitride film such as a silicon nitride film (SiN) 27, and the like is formed on the main surface corresponding to the space between the source region 23 and the drain region 24 of the semiconductor region 22. A gate insulating film 25 having a three-layer structure in which an oxide film such as a silicon oxide film (SiO ₂ ) 28 is laminated in this order is formed, and a gate electrode 30 made of, for example, polycrystalline silicon is formed on the gate insulating film 25 on the source region. The source electrode 31 and the drain electrode 32 are formed on the drain region 24 and the drain region 24, respectively.

In MISFET21 of this so-called MONOS (metal oxide nitride oxide semiconductor) structure, if accumulated electrons into the silicon nitride film 27 of the gate insulating film 25, equivalent to adding the offset of constant negative potential to the gate voltage V _G For example, in the case of the n-channel type, the potential under the gate moves in the so-called enhancement direction (the direction in which the potential becomes shallow), and in the case of the p-channel type, the depletion (in the direction in which the potential becomes deep) is moved. If accumulated holes in opposite to the silicon nitride film 27 of the gate insulating film 25, it becomes equivalent to adding the offset of the constant positive potential to the gate voltage V _G, if for example n-channel type, under a gate potential Moves in the so-called depletion direction, and in the p-channel type, it moves in the enhancement direction.

For example, when the n-channel MISFET 21N having the MONOS structure is used as shown in FIG. 2, a high voltage is applied between the gate electrode 30 and the channel region immediately below the gate electrode 30, and as an example, the source voltage V _S and the drain voltage V _D When the gate electrode 30 is given a positive (+) high gate voltage (voltage higher than the normal drive voltage) V _G for a certain period of time, A certain amount of electrons e are injected into the silicon nitride film 27 from the n ⁺ layer constituting the source region 23 and the drain region 24. The injection amount of the electrons e depends on the voltage V _G applied to the gate electrode 30 and the application time, and a desired amount of electrons e can be injected by controlling the application voltage and application time. That is, the potential moves in the direction of enhancement, and a desired potential or threshold voltage V _th is obtained.
Conversely, when a gate voltage V _G having a high − (negative) is applied to the gate electrode 30 of the n-channel MISFET 21N, if there is a p-type hole supply source in the vicinity of the gate, the hole h is in the silicon nitride film 27. The potential moves in the direction of depletion.

Further, for example, as shown in FIG. 3, in the case of a p-channel MISFET 21P having a MONOS structure, a high voltage is similarly applied between the gate electrode 30 and its channel region, and as an example, a source voltage V _S and a drain voltage V Both _D are set to 0V (however, a predetermined positive voltage is applied to the n-type semiconductor region 22), and a negative (−) high gate voltage V _G (a voltage higher than a normal driving voltage) is applied to the gate electrode 30. Then, holes h are similarly injected into the silicon nitride film 27 of the gate insulating film 25 from the p ⁺ layer constituting the source region 23 and the drain region 24, the potential moves in the direction of enhancement, and the desired potential or A threshold voltage V _th is obtained.
In the p-channel MISFET 21P, conversely, when a gate voltage V _G having a high + (positive) is applied to the gate electrode 30, if there is an n-type electron supply source in the vicinity of the gate, the electron e is a silicon nitride film. The potential is moved in the direction of depletion.

  The charges of electrons and holes once injected into the silicon nitride film 27 are sandwiched between the silicon oxide films 26 and 28 above and below the silicon nitride film 27, are difficult to escape, and exceed the barrier at a normal driving voltage. Instead, it is permanently held in the silicon nitride film 27.

According to the MISFET 21 having such a configuration, the channel potential or the threshold voltage V _th can be set in an analog manner by controlling the amount of charge injected into the silicon nitride film 27 of the gate insulating film 25. The MISFET 21 can be an analog MISFET and used for an analog circuit or the like.

  The MONOS structure MIS element capable of analogly setting the potential or threshold voltage described above can be applied to an analog memory element, a bias circuit for obtaining an output bias having a desired value, and the like.

Further, the MIS element having the above-described MONOS structure can be applied to a reset gate unit in a solid-state imaging device or a transfer unit of a CCD transfer register.
Furthermore, the present invention can be applied to the setting of the substrate voltage and the reset gate bias in the solid-state imaging device.

  4 to 6 show an embodiment of a CCD solid-state imaging device according to the present invention. In this example, in particular, the potential of the reset gate portion is controlled by using the MIS element, that is, the MONOS structure.

  This figure shows a case where the present invention is applied to an interline transfer type CCD solid-state imaging device. This CCD solid-state imaging device has a so-called vertical overflow structure in which saturated charges are swept away in the substrate direction, that is, in the vertical direction.

  The CCD solid-state imaging device 41 includes a plurality of light receiving portions 42 serving as pixels arranged in a matrix, an image pickup region 44 in which a vertical transfer register 43 having a CCD structure is provided on one side of each light receiving portion row, and each vertical transfer. A horizontal transfer register 45 having a CCD structure to which the final stage of the register 43 is connected, and an output circuit connected to the output side of the horizontal transfer register 45, that is, a charge detection circuit 46, are provided.

  In the imaging region 44, as shown in FIG. 5, n that constitutes the light receiving portion 42 in the second conductivity type, that is, the p-type first well region 49 on the silicon semiconductor substrate 48 of the first conductivity type, for example, n type. Type impurity diffusion region 50, n type transfer channel region 51 constituting vertical transfer register 43, and p type channel region 52 are formed, and p type positive charge accumulation is performed on n type impurity diffusion region 50. In the region 53, a second p-type well region 54 is formed immediately below the n-type transfer channel region 51, respectively.

Here, a light receiving portion (photoelectric conversion portion) 42 is constituted by a photodiode PD formed by a pn junction between the n-type impurity diffusion region 50 and the p-type well region 49. A silicon oxide film (SiO ₂ ) 56, a silicon nitride film (Si ₃ N ₄ ) 57, and a silicon oxide film (SiO ₂ ) are formed over the transfer channel region 51, the channel stop region 52, and the read gate portion 47 that constitute the vertical transfer register 43. ) 58 are sequentially stacked, and a three-layered gate insulating film 59 is formed. On the gate insulating film 59, a plurality of transfer electrodes 61 made of, for example, the first and second layers of polycrystalline silicon are arranged in the transfer direction. The vertical transfer register 43 is formed by the transfer channel region 51, the gate insulating film 59, and the transfer electrode 61.

The vertical transfer register 43 is driven by, for example, four-phase vertical drive pulses φV ₁ , φV ₂ , φV _3, and φV ₄ .

On the other hand, as shown in FIG. 6, the horizontal transfer register 45 has a silicon oxide film (SiO ₂ ) 56, a silicon nitride film (Si ₃ N ₄ ) 57, and silicon similar to the above on the n-type transfer channel region 51. A first transfer electrode 65A made of a first polycrystalline silicon film and a second polycrystalline silicon film made of a second layer are interposed through a gate insulating film 59 having a three-layer structure made of an oxide film (SiO ₂ ) 58. The plurality of transfer electrodes 65B are alternately arranged along the transfer direction.

In the horizontal transfer register 45, two adjacent transfer electrodes 65A and 65B connected to each other are taken as one set, and every other set of transfer electrodes 65 [65A, 65B] and every other set of transfer electrodes are transferred. Two-phase horizontal drive pulses φH ₁ and φH ₂ are applied to the electrodes 65 [65A, 65B], respectively. In the transfer channel region 51 below each second transfer electrode 65B, a second conductivity type, that is, a p-type semiconductor region 66 is formed by, for example, ion implantation of impurities, whereby the first transfer electrode 65A is used as a storage electrode. And a transfer unit having a transfer unit using the second transfer electrode 65B as a transfer electrode.
In the gate insulating film 59, charge injection from the polycrystalline silicon electrode to the silicon nitride film 57 is blocked by the silicon oxide film 58 during normal operation, and potential fluctuation does not occur.

After the final transfer portion of the horizontal transfer register 45, a horizontal output gate portion HOG is formed by forming a gate electrode 67 made of, for example, a second-layer polycrystalline silicon film via a gate insulating film 59. A fixed output gate voltage, for example, a ground potential (GND) is applied to the horizontal output gate unit HOG. A charge detection device 80 is formed at the subsequent stage of the horizontal output gate portion HOG. The charge detection device 80 includes a floating diffusion region FD composed of an n-type semiconductor region for accumulating signal charges adjacent to the horizontal output gate portion HOG, and a floating diffusion region FD adjacent to the floating diffusion region FD. An output circuit (detection circuit) that is connected to the reset gate portion 82, the reset drain region 81, and the floating diffusion region FD for detecting the signal charges accumulated in the floating diffusion region FD. 46. t ₂ is the output terminal.
The reset drain region 81 is formed of an n-type semiconductor layer, and a reset voltage V _RD (for example, a power supply voltage V _DD ) is applied to the reset drain region 81. A reset pulse φ _RG is applied to the reset gate unit 82.

Thus, in the present embodiment, in particular, the reset gate portion 82 is formed on the p-type well 49 at the same time as the silicon oxide film (SiO ₂ ) 56 formed simultaneously with the gate insulating film 59 of the horizontal transfer registers 43 and 45. A gate electrode 85 made of, for example, a polycrystalline silicon film is formed through a gate insulating film 84 having a three-layer structure in which a silicon nitride film (Si ₃ N ₄ ) 57 and a silicon oxide film (SiO ₂ ) 58 are sequentially stacked. Constitute. That is, the reset gate unit 82 is configured as the MIS element having the MONOS structure described above. Here, a MIS element having a MONOS structure, that is, a MISFET is configured by the reset gate portion, the floating diffusion region, and the reset drain region.

In the CCD solid-state imaging device 41, signal charges photoelectrically converted in accordance with the amount of light received by each light receiving unit 42 are read to the vertical transfer register 43, transferred in the vertical transfer register 43, and transferred to the horizontal transfer register 45. The The signal charges transferred to the horizontal transfer register 45, each pixel are transferred to the floating diffusion region FD, are read out as CCD output from the charge-voltage converter has been the terminal t ₂ through the output circuit 46.

After the signal charge of one pixel is read out, the reset pulse φ _RG is applied to the reset gate portion 82, whereby the signal charge in the floating diffusion region FD is swept away to the reset drain region 81 through the reset gate portion 82. The potential of the floating diffusion region FD is reset to the potential of the reset drain region 81.

Therefore, in the CCD solid-state imaging device 41 of the present embodiment, as shown by the potential distribution 89 before adjustment in FIG. 7, when the potential φ _m below the reset gate portion 82 becomes deep due to manufacturing variations, Adjust potential as follows.

That is, the potential φ _m (= φ _m1 ) under the reset gate portion 82 is detected, and this potential φ _m1 is compared with the reference value φ _m2 (that is, the potential value to be set).

Then, an amount of charge that compensates for the deviation from the reference value φ _m2 is injected into the silicon nitride film 57 of the gate insulating film 84. That is, the reset voltage V _RD of the reset drain region 81 is set to 0 V, and a required + (positive) high voltage V _RD set according to the amount of deviation is applied to the gate electrode 85 of the reset gate portion 82 for a required time. An amount of electrons to compensate for the deviation from the reference value φ _m2 is injected into the silicon nitride film 57 of the gate insulating film 84 and accumulated.

  In practice, while observing the waveform of the image output, the amount of charge is injected until the waveform is appropriate.

Due to the electrons accumulated in the silicon nitride film 57, the potential under the reset gate portion 82 becomes shallower in the direction of enhancement and accordingly shallower than the potential distribution 90 after adjustment from the potential φ _m1 immediately after manufacture (before adjustment). It can be moved in the direction and can be adjusted to the normal potential φ _m2 .

  Here, since the terminal of the reset drain and the terminal of the reset gate portion are terminals led to the outside, it is necessary to avoid the above-described potential fluctuation due to static electricity. Usually, a protective element (for example, a diode or a transistor) is added to these external terminals so that a high voltage is not applied. The potential cannot be adjusted with this protective element added.

  Therefore, only when the potential is adjusted, the protective element is separated or the breakdown voltage is increased to stop the operation of the protective element, thereby enabling the potential adjustment. After the potential adjustment, the protection element is operated again by connecting the protection element or the like so that the adjustment value does not deviate thereafter.

As a specific example, as shown in FIG. 7, on the same semiconductor wafer, together with the image sensor body, for example, a pair of diodes PD connected in series is connected. One end is connected to the power supply voltage V _DD and the other end is grounded. Then, a protection element 86 is formed so that the connection midpoint of both diodes PD is connected to the external lead-out terminal 87. In the wafer state, the external lead-out terminal 87 connected to the gate electrode 85 of the reset gate portion 82 is formed. The protection element 86 is placed in a separated state. The potential φ _m below the reset gate portion 82 is adjusted at the time of inspection in the wafer state, and the external lead-out terminal 87 and the protective element 86 are connected by wire bonding 88 at the time of assembly. As a result, even if static electricity is applied to the external lead-out terminal 85 after shipment, static electricity is not applied to the reset gate portion 82 by the protective element 86, and failure after shipment can be prevented.

According to the CCD solid-state imaging device 41 shown in FIGS. 4 to 7, a reset gate portion 82 having a so-called MONOS structure having a gate insulating film 84 composed of a silicon oxide film 56, a silicon nitride film 57, and a silicon oxide film 58. The potential φ _m below the reset gate portion 82 can be adjusted in an analog manner by injecting and accumulating a desired amount of charge into the silicon nitride film 57 of the gate insulating film 84 in an analog manner.
Therefore, after completion of the conventional CCD solid-state imaging device, potential adjustment after completion is possible compared to adjustment of potential by an external circuit or the like, and the reset pulse φ _{RG has} a lower amplitude for lower power consumption. Can be achieved.

On the other hand, in the CCD solid-state imaging device, the substrate voltage _Vsub is set because the substrate structure has a pn junction and is not an MIS transistor structure, and thus a direct adjustment method like the reset gate unit 82 described above cannot be adopted. .

  In such a case, an adjustment circuit, that is, a bias circuit for adjustment is separately added, the MIS element having the MONOS structure described above is used for this bias circuit, and the output bias value from the bias circuit is adjusted by adjusting the channel potential of the MIS element. This output bias may be applied to the substrate 48 of the CCD solid-state imaging device.

In the above example, the potential φ _m below the reset gate portion 82 is directly adjusted, but can be indirectly adjusted. The variation of the potential φ _m can be considered the same as the variation of the DC bias V _RG applied to the gate electrode 85. Therefore, if the DC bias V _RG applied to the gate electrode 85 of the reset gate portion 82 is controlled by the above bias circuit. It will be good.

FIG. 8A shows an example of such a bias circuit. The bias circuit 91 is a source follower circuit including a driving MIS transistor 92 and a load resistor 93.
As the driving MIS transistor 92, a MISFET having the MONOS structure shown in FIG. 1, for example, an n-channel MISFET 21N is used.

The drain of the driving MIS transistor 92 is connected to the power supply terminal 96 to which the power supply voltage V _DD is applied, the other end of the load resistor 93 is connected to the ground (GND), and the output terminal t ₃ is derived from the source side.
The gate of the driving MIS transistor 92 is connected to the drain (power supply) via the resistor R ₁ so that the specific gate bias is applied.

8B, the gate of the driving MISFET transistor 92 ′ is connected to the ground (GND) via the resistor R ₁ ′ so that the specific gate bias is applied.
8A and 8B have the same configuration except that the connections of the resistors R ₁ and R ₁ ′ are different. Therefore, in FIG. 8B, the same reference numerals are given to the portions corresponding to FIG.

Normally, in an on-chip circuit, the gate may be directly connected to a power source or GND without a resistor. However, when a high voltage is applied, the drain is set to 0 V and a high voltage is applied to the gate terminal 95 as described later. Therefore, the resistor R ₁ is required so that the MIS transistor 92 is not destroyed even when this high voltage is applied. The resistor R ₁ is only required to withstand a high voltage, and a resistor made of polycrystalline silicon, a diffused resistor, a MIS resistor, or the like can be used.

In the bias circuit 91, the initial output (potential) of the driving MIS transistor 92 is set so that the gate voltage V _G ≈the source voltage V _S (that is, the threshold voltage V _th is 0 V), and the bias is set. In the circuit 91 ′, the initial output of the driving MIS transistor 92 ′ is set to such an extent that the power supply voltage (V _DD ) is obtained when the gate voltage V _G = 0V (V _th ≈−V _DD ), and V _DD = V _sub (or V _RG ) = 0V (that is, the power supply terminals 96 and 96 ′ and the output terminals t ₃ and t ₃ ′ are 0 V), a high voltage is applied to the gate terminals 95 and 95 ′, and the driving MIS transistors 92 and 92 Charges are injected into the silicon nitride film 27 of the gate insulating film, and the area under the gate is adjusted to a desired potential.

The output bias voltage applied to the output terminal t ₃ ′ of the bias circuit 91 ′ is applied to the substrate as the substrate voltage V _sub of the CCD solid-state imaging device.

As a result, for example, the value of the substrate voltage V _sub can be varied from the power supply voltage V _DD to a voltage of 0 V. That is, if the driving MIS transistor 92 'is in a depletion state of V _th = −V _DD , the output becomes the power supply voltage V _DD , and then the output decreases as the potential is adjusted in the enhancement direction, so that the driving is completely performed. If the MIS transistor 92 'is turned off, the output is in the vicinity of 0V and can be varied in the range of V _{DD to} 0V.

The output bias voltage applied to the output terminal t ₃ of the bias circuit 91 is applied to the reset gate electrode as the DC bias V _RG of the reset gate portion of the CCD solid-state imaging device.
As a result, for example, the value of the DC bias V _RG of the reset gate section can be varied from the power supply voltage V _DD to a voltage of 0V. That is, if the driving MIS transistor 92 is in a depletion ON state, the output becomes the power supply voltage V _DD , and then the output decreases as the potential is adjusted in the enhancement direction, and the driving MIS transistor 92 is completely When turned off, the output becomes 0 V, and can be varied in the range of V _{DD to} 0 V.

  In addition to the resistors, for example, constant current sources 97 and 97 ′ may be used as the loads 93 and 93 ′ constituting the source follower circuit. The constant current source has better linearity of input / output characteristics.

If such adjustment circuits, that is, bias circuits 91 and 91 'are built in the chip of the CCD solid-state imaging device, the gate terminals 95 and 95' of the driving MIS transistor 92 whose potential is to be adjusted do not need to be led to the outside. If the potentials under the gates of the driving MIS transistors 92 and 92 'are adjusted at the time of inspection, it is not necessary to add protective elements to the gate terminals 95 and 96' during or after assembly.
However, a protection element is required for the power supply terminals 96 and 96 '.

In the bias circuit 91 ′, the input gate is grounded, so that even if the power supply voltage fluctuates, the output hardly fluctuates, which is suitable for the V _sub bias circuit.

In the above-described bias circuit 91, when the power supply voltage V _DD varies, the output bias varies substantially in the same manner. When this bias circuit 91 is used to supply the substrate potential V _sub , when the power supply voltage V _DD fluctuates, the substrate voltage V _sub fluctuates, whereby the height of the overflow barrier fluctuates, and the charge handled in the light receiving section. There is a fear that the amount changes greatly.

On the other hand, when this bias circuit 91 is used for adjusting the DC bias V _RG of the reset gate unit 82, the drive of the bias circuit 91 is performed when the power supply voltage V _DD that becomes the reset drain voltage V _RD fluctuates. also varies the gate voltage V _G of the use MIS transistor 92, the output bias value in the same change amount as the variation of V _DD, thus will be the DC bias value of the reset gate is fluctuated, an advantage reversed.
In other words, the power source followability is improved, and the source follower type bias circuit 91 is optimal as a bias circuit for applying a DC bias for potential adjustment to the reset gate portion.

  FIG. 9 shows an embodiment in which the bias circuit 91 is applied to potential adjustment (that is, DC bias adjustment) of the reset gate portion 82 of the CCD solid-state imaging device. In the figure, portions corresponding to those in FIGS. 4 to 6 are denoted by the same reference numerals, and redundant description is omitted.

In the CCD solid-state imaging device 101 of the present embodiment, as shown in FIG. 9, the source follower-type bias circuit 91 is built in the chip 97 constituting the CCD solid-state imaging device, and the drain side of the driving MIS transistor 92 is provided. Is connected to the power supply terminal 96 connected to the reset drain region 81. A power supply voltage V _{DD serving} as a reset drain voltage V _RD is applied to the reset drain region 81 through the power supply terminal 96.

Further, the source side of the driving MIS transistor 92 is connected to the gate electrode 85 of the reset gate portion 82 and is connected to the reset pulse generating means 100 via the external capacitor 99 outside the chip 97. 198 is an external terminal.
In the reset gate portion 82, the gate insulating film does not need to have a special configuration because it is not necessary to inject charges therein, and is a gate insulating film having the above three-layer structure or another configuration. be able to.

In the embodiment of FIG. 9, the potential φ _m below the reset gate portion 82 is measured during wafer inspection, and if it deviates from the reference value φ _m2 , the gate insulating film of the driving MIS transistor 92 in the bias circuit 91 is formed. An amount of electric charge that compensates for the deviation is injected by the above-described method, and the channel potential of the driving MIS transistor is adjusted, whereby an output bias voltage having a desired value is obtained from the bias circuit 91, and the DC bias V is applied to the reset gate portion. _Applied as _RG . As a result, the potential φ _m below the reset gate portion 82 is adjusted.

A reset pulse φ _RG in which the high frequency component of the reset pulse from the reset pulse generating means 100 is weighted to the DC bias V _RG is applied to the reset gate electrode 85.
After the potential φ _m is adjusted, the driving MIS transistor 92 is enhanced. Therefore, when the load current i is minimized, the bias circuit 91 is viewed from the terminal t ₃ and the low clamp using the Zener diode ZD is equivalently used. The circuit 98 is obtained (see FIG. 10). FIG. 11 is a VI characteristic diagram of this equivalent circuit. If the driving MIS transistor 92 is depleted, it does not function as a diode but has resistance characteristics, so that it becomes an average value clamp circuit, and the reset gate voltage fluctuates due to fluctuations in the amplitude and duty ratio of the reset pulse. Insufficient saturation signal amount of the floating diffusion FD and reset failure occur. However, in the case of the low clamp circuit 98, the low level voltage of the reset gate pulse is constant even if the pulse amplitude and the duty ratio vary, and the saturation signal amount is not insufficient.

Therefore, according to this CCD solid-state imaging device 101, the power supply if the voltage V _DD is them varies, so also varies the potential of the reset gate portion 82 in the same variation with this, the reset gate portion 82 under the change in the power supply voltage V _DD And the potential difference between the reset drain region 81 does not fluctuate.

In the bias circuit 91 of the above example, when the amount of potential shift is large, V _G >> V _S , the potential difference between the gate and the source becomes large, and the breakdown voltage in the actual operation state becomes a problem. In the bias circuit 91 ′, V _G << V _D at the initial stage, the potential difference between the gate and the drain is large, and the breakdown voltage is also a problem. For example, the substrate voltage _Vsub has a large variation, a variation of several volts, and the adjustment range is close to 10V.

An example of this solution is shown in FIG. In the bias circuit 102 according to this example, a large number of driving MIS transistors 92 having the above-described MONOS structure are connected in series (in this example, three stages), and a load resistor 93 is connected to the source side of the driving MIS transistor at the final stage. Configure the source follower system. t ₃ is the output terminal. A resistor R ₁ is connected between the gate and drain of the driving MIS transistor 92 in each stage, and each gate terminal 95 [95A, 95B, 95C] is provided.

At the time of adjustment, the drain side of the driving MIS transistor 92 at each stage, V _DD, and the terminal t ₃ are grounded as indicated by a broken line, and a desired high voltage is applied to each gate terminal 95 [95A, 95B, 95C]. Thus, the channel potential of each driving MIS transistor 92 is adjusted.

  According to the bias circuit 102 having such a configuration, the potential shift amount of the driving MIS transistor 92 per stage can be reduced, that is, the adjustment range can be reduced, and the total potential shift amount and accordingly the adjustment range can be increased. It is possible to avoid the deterioration of the breakdown voltage between the gate, the source and the drain of the driving MIS transistor 92 in the actual operation state.

In other words, if all the driving MIS transistors are in a depletion-on state, the first output from the output terminal t ₃ is the power supply voltage V _DD , and the potential in the enhancement direction (in which the potential becomes shallower). As the adjustment is made, the output decreases. When each driving MIS transistor 92 is completely turned off, the output becomes 0V. Therefore, a wide range of adjustment from V _{DD to} 0 V is possible, and the breakdown voltage problem of the driving MIS transistor is solved.

The one-stage bias circuit 91 of the driving MIS transistor 92 shown in FIG. 8 is suitable for adjustment to a place such as a reset gate portion where variation in potential is originally small and the shift amount is small.
A bias circuit 102 in which the driving MIS transistors 92 shown in FIG. 12 are connected in multiple stages is suitable for adjustment to a place where the variation is large, such as the substrate voltage V _sub . However, the problem of power fluctuation cannot be avoided.

  FIG. 13 shows another example of the bias circuit. This example is a bias circuit that can be adjusted over a wide range. In particular, the amplification type is configured to obtain a large output change with a small shift amount.

The bias circuit 105 of this example has a driving MIS transistor 106 and a load resistor 107, and the drain D of the driving MIS transistor 106 is connected via the load resistor 107 to a power supply terminal 109 to which a power supply voltage V _DD is applied. , The source S is grounded, and an inverter circuit in which the gate G is input and the output terminal t ₄ is led out to the drain D side is constituted.
As the driving MIS transistor 106, the MISFET having the MONOS structure shown in FIG. 1, for example, an n-channel MISFET 21N is used.
A resistor 122 similar to R ₁ shown in FIG. 8 is connected between the gate and source of the driving MIS transistor 106.

In this inverter type bias circuit 105, the driving MIS transistor 106 is turned on in the initial state, and then the driving MIS transistor 106 is enhanced by utilizing the potential shift with respect to the driving MIS transistor 106 according to the above example. If the control is performed until the output terminal t _{4 is} completely turned off, the output bias from the output terminal t ₄ changes from 0 V to the range of the power supply voltage V _DD . Therefore, since this bias circuit 105 is an inverter system, a large adjustment range can be obtained with a small potential shift amount.
However, the bias circuit 105 is still affected by power supply fluctuations.

  FIG. 14 shows another example of an inverter-type bias circuit that is not affected by power supply fluctuations.

The bias circuit 110 of the present example has the above-described inverter-type bias circuit, that is, the driving MIS transistor 106 and the load resistor 107, and the drain D of the driving MIS transistor 106 becomes the power supply voltage V _DD via the load resistor 107. In addition to the configuration in which the source S is grounded, the gate G is used as an input, and the output terminal t ₄ is derived on the drain D side, a normal applied voltage is further applied to the gate G as a resistor R _a from the power supply voltage V _DD. And _Rb are applied by resistance division, and the division ratio is made equal to the gain of the inverter. As the driving MIS transistor 106, the MISFET having the MONOS structure shown in FIG. 1, for example, an n-channel MISFET 21N is used.

Even if the source of the inverter is not directly GND, it may be grounded through the feedback resistor R as shown in the frame 111 of FIGS. 13 and 14, and it is desirable to put it in accordance with the required gain. If the gain is lowered appropriately, the potential φ _m can be easily adjusted. Further, the feedback resistance may be any of a resistance due to polycrystalline silicon, an MIS resistance, and a diffusion resistance.
The load resistor 107 may be a constant current source equivalent to that of the source follower, and the resistors 122, R _a , and R _b may be any of a resistor made of polycrystalline silicon, a MIS resistor, and a diffused resistor at a high voltage. It only has to be able to bear.

According to this bias circuit 110, when the power supply voltage V _DD varies, the gate bias applied to the gate (gate bias at point a) varies by (1 / gain) of the power supply. Since the fluctuation of the gate bias is amplified and inverted on the output side, the fluctuation of the power applied to the drain side is absorbed and becomes zero.

In this bias circuit 110, if the transistor 106 is turned on by the gate bias applied to the gate of the driving MIS transistor 106, the output becomes 0V in the initial stage, and from there, it goes to the enhancement direction by electron injection. The output can be changed up to the power supply voltage V _DD .

In this way, a large change in output can be obtained with a small shift amount, and there is no influence of power supply fluctuations. Therefore, the bias circuit 110 is an adjustment circuit that is optimal for setting the substrate voltage _Vsub of the CCD solid-state imaging device.

15 to 17 show still another example of the bias circuit.
A bias circuit 125 in FIG. 15 connects a source follower circuit including a driving MIS transistor 126 and a load resistor 127 to the output of the inverter bias circuit in FIG. 14, and an output terminal t ₅ is connected from the source side of the MIS transistor 126. This is derived so as to lower the output impedance.

The bias circuit 130 of FIG. 16 connects an emitter follower circuit composed of a driving bipolar transistor 131 and a load resistor 132 to the output of the inverter bias circuit of FIG. 14, and derives an output terminal t ₆ from the emitter side of the bipolar transistor 131. It is configured as follows. According to the bias circuit 130, the output impedance can be lowered, and at the same time, for example, the withstand voltage when applying a shutter pulse in the solid-state imaging device can be improved.

The bias circuit 140 of FIG. 17 further connects an emitter follower circuit comprising a driving bipolar transistor 131 and a load resistor 132 shown in FIG. 16 to the output of the bias circuit of FIG. t ₇ is derived. Also in this bias circuit, an emitter follower circuit is added to the final output stage, so that the output impedance can be lowered and the breakdown voltage at the time of applying the shutter pulse can be improved.

Here, a specific process when performing the above-described potential shift of the MIS element will be described.
For example, a case where a potential shift is performed by an n-channel MIS element will be described.
As described above with reference to FIG. 2, by setting both or one of the source region 23 and the drain region 24 to 0V, the channel surface is filled with electrons e, and the channel potential is set to 0V. When a (+) positive high voltage V _G is applied to the gate electrode in this state, a strong electric field is applied to the gate insulating film 25, and electrons e on the silicon surface exceed the barrier of the silicon oxide film 26 and enter the silicon nitride film 27. enter. That is, the total amount of electrons e entering the silicon nitride film 27 is determined by the electric field and time applied to the silicon oxide film 26. The voltage needs to be applied in an amount proportional to the thickness d ₁ of the gate insulating film 25.
Therefore, to obtain a desired potential, the applied voltage or the application time is controlled.
Since the potential value≈the output voltage of the source follower (or inverter) circuit, a pulse voltage is applied to the gate, the output value is read, judged, and repeated.

  There are two methods for adjusting the potential of the MIS element in the MONOS structure: pulse amplitude modulation and pulse width modulation. FIG. 18 shows a case where a pulse amplitude modulation method is used. Similarly to FIG. 8 described above, a MIS element having a MONOS structure is used as a driving MIS transistor 92 to form a source follower circuit including the driving MIS transistor 92 and a load resistor 93.

First, in step [I] in FIG. 18, the output voltage _Vout of the source follower circuit is detected.
Next, in step [II], this output voltage V _out is compared with a reference value (desired voltage value), and if it matches (ie, V _out ≦ reference value), it is set to a desired potential. Stop the process.
If the output voltage V _out does not match the reference value (ie, V _out > reference value) in the comparison process of step [II] (ie, V _out > reference value), the drain side power supply terminal 96 is set to 0 V in the next step [III], and the reference value and output applying a phi _VG high voltage (pulse voltage ie fixed pulse width modulating the amplitude) which is proportional to the difference between voltage V _out to the gate of the drive MIS transistor 92, to inject a predetermined amount of electrons in the gate insulating film .
Next, returning to step [I], the output voltage _Vout of the source follower circuit is detected again, and in step [II], the output voltage _Vout is compared with the reference value. This process is repeated until they match.

FIG. 19 shows a case where a pulse width modulation method is used.
As in FIG. 18, a MIS element having a MONOS structure is used as a driving MIS transistor 92 to form a source follower circuit with a load resistor 93.
First, in step [I], the output voltage _Vout of the source follower circuit is detected.
Next, in step [II], this output voltage V _out is compared with a reference value (desired voltage value), and if it matches (ie, V _out ≦ reference value state), it is set to a desired potential. Stop the adjustment process.
If the output voltage V _out does not match the reference value (ie, V _out > reference value) in the comparison process of step [II] (ie, V _out > reference value), the drain-side power supply terminal 96 is set to 0 V and the gate has a high voltage. _Is applied for a time proportional to the difference between the reference value and the output voltage V _out , that is, a pulse voltage φ _VG whose pulse width is adjusted at a constant voltage (amplitude), and a predetermined amount of electrons is injected into the gate insulating film.
Then, returning to step [I], the output voltage V _out of the source follower circuit is detected again, and in step [II], the output voltage V _out is compared with a reference value. Repeat this process until they match.

In this way, the potential of the MIS element having the MONOS structure can be set to a desired value.
When an inverter circuit is used, a desired potential can be set by detecting the output voltage and repeating the same process.

Although the above example is applied to an interline transfer type CCD solid-state image sensor, it is needless to say that the present invention can also be applied to a frame interline transfer type CCD solid-state image sensor.

  In the above example, the bias circuit is applied to the setting of the substrate voltage and reset gate bias of the CCD solid-state imaging device. However, in the amplification type solid-state imaging device, the control circuit applied to the substrate may be set by the bias circuit. it can.

  In the amplification type solid-state imaging device, holes (signal charges) obtained by photoelectric conversion are accumulated in a p-type potential well of an n-channel MOS transistor, and potential fluctuations in this p-type potential well (so-called back gate potential change). The change in channel current due to is output as a pixel signal.

  FIG. 20 shows a semiconductor structure of a unit pixel of the amplification type solid-state imaging device. In this figure, 120 is a p-type substrate, 121 is an n-type well region, and 122 is a p-type well region for accumulating holes (signal charges) 123 obtained by photoelectric conversion. An n-type source region 124 and a drain region 125 are formed in the p-type well region 123, and a gate electrode 126 is formed between the regions 124 and 125 via a gate insulating film. A plurality of unit pixels are arranged in a matrix. Although not shown, for example, the gate of the unit pixel is connected to a vertical selection line from a vertical scanning circuit, and the source is connected to a signal line. A load MOS transistor is connected to one end of the signal line, and the other end of the signal line is connected to a horizontal signal line via a sample hold circuit and a switching MOS transistor for sampling and holding a pixel signal, and a gate of each switching MOS transistor. Are connected to the horizontal scanning circuit. The drain of each unit pixel is connected to a power source, and a switching MOS transistor at the time of reset is connected between the power source and the signal line.

  The holes accumulated in the p-type well region 122 of the unit pixel control the channel region at the time of reading, thereby changing the potential of the source terminal in the source follower circuit composed of the unit pixel and the load MS transistor. The potential change is output as a pixel signal to the horizontal signal line through the sample and hold circuit.

In this amplification type solid-state imaging device, as indicated by a solid line in the potential diagram of FIG. 21, a substrate voltage V _sub (for example, 0 V) is applied to the substrate terminal Sub at the time of pixel reading. On reset (or when the electronic shutter), with the same gate voltage as the time of reading the for example the gate as indicated by the broken line is applied, the substrate terminal S _ub to a desired substrate voltage V _sub R (e.g. -6V to-10V Degree) is applied. Holes (signal charges) 123 are discharged to the substrate 120. The bias circuit 91, 102, 105 or 110 described above can also be used for setting the substrate voltage V _sub R at the time of reset (or at the time of electronic shutter).

  The present invention can also be applied to a method for correcting variations in threshold voltage between MIS elements of a semiconductor integrated circuit composed of a plurality of MIS elements. In this example, each MIS element has a so-called MONOS structure having a three-layer gate insulating film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order. Then, the channel potential of each MIS element is detected, and the channel potential is compared with a reference value. Then, the source and drain are set to 0 V, a high voltage is applied to the gate, and an amount of charge that compensates for the difference between the channel potential and the reference value is applied to the silicon nitride film of the gate insulating film by the same charge injection method as described above. Inject and accumulate. As a result, variations in the threshold voltage of each MIS element can be corrected.

  The present invention can be applied to a method for adjusting the channel potential of a MIS element. Also in this example, the MIS element is configured in a MONOS structure having a three-layer gate insulating film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order. Then, the channel potential of the MIS element is compared with a reference value, and an amount of charge that compensates for the deviation from the reference value is injected into the silicon nitride film of the gate insulating film of the MIS element by the same method as described above. Thereby, the channel potential of the MIS element can be adjusted.

  As another embodiment, the present invention can be applied to a charge transfer device having a CCD structure applied to a solid-state imaging device or the like. The charge transfer device of this example includes a charge transfer unit in which a plurality of transfer electrodes are arranged in a transfer direction on a semiconductor substrate via a gate insulating film, and a stray capacitance that stores charges transferred from the charge transfer unit. A so-called floating diffusion region composed of a semiconductor region of one conductivity type, and a reset transistor for resetting the potential of the stray capacitance to a predetermined potential. The reset transistor is configured by forming a reset gate portion having a MIS structure between a so-called reset drain region formed of one conductive type semiconductor region to which a predetermined potential is applied and a stray capacitance. A bias voltage supplied to the reset transistor, that is, the gate electrode (control electrode) of the reset gate portion is obtained by the bias circuit 91, 102, 105 or 110 described above.

The MIS element according to the present invention is a generic term for a CCD structure, a CCD transfer register, a MISFET, and the like.
For example, the gate insulating film of the CCD transfer register may have a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charges may be accumulated in the silicon nitride film to set the channel potential below the transfer unit.

  As described above, according to the embodiment of the present invention, the potential of the MIS element or the value of the gate via can be set finely in an analog manner. Therefore, for example, in the case of a CCD solid-state image pickup device, the reset gate portion of the CCD solid-state image pickup device and the substrate voltage are not adjusted, the reset pulse is reduced in amplitude, and the power consumption is reduced. Is planned.

In addition, when a bias circuit is used, it is advantageous in terms of protection elements, such as partly omitting protection elements.
Further, the source follower type bias circuit is suitable for a bias circuit that obtains the DC bias V _RG of the reset gate portion of the CCD solid-state image sensor, and the inverter type bias circuit is suitable for a bias circuit that obtains the substrate voltage of the solid-state image sensor. .

It is a block diagram which shows embodiment of the MIS element which concerns on this invention. It is explanatory drawing of the potential shift operation | movement in the case of the n channel MIS element which concerns on this invention. It is explanatory drawing of the potential shift operation | movement in the case of the p channel MIS element which concerns on this invention. It is a schematic block diagram which shows one Embodiment of the CCD solid-state image sensor which concerns on this invention. It is sectional drawing on the AA line of FIG. It is sectional drawing on the BB line of FIG. It is explanatory drawing including the potential distribution with which it uses for description of the potential adjustment in a reset gate part. A is a circuit diagram showing an example of a source follower type bias circuit according to the present invention. B is a circuit diagram showing another example of a source follower type bias circuit according to the present invention. FIG. It is a block diagram of the principal part of the CCD solid-state image sensor based on this invention using the bias circuit of FIG. It is circuit explanatory drawing with which description of this invention is provided. It is a VI characteristic figure in the equivalent circuit of FIG. It is a circuit diagram which shows an example of the bias circuit of the multistage structure concerning this invention. 1 is a circuit diagram showing an example of an inverter type bias circuit according to the present invention. FIG. It is a circuit diagram which shows the other example of the bias circuit of the inverter system based on this invention. It is a circuit diagram which shows the other example of the bias circuit based on this invention. It is a circuit diagram which shows the other example of the bias circuit based on this invention. It is a circuit diagram which shows the other example of the bias circuit based on this invention. 3 is a flowchart illustrating an example of a method for performing a potential shift of a MIS element according to the present invention. It is a flowchart which shows the other example of the method of performing the potential shift of the MIS element which concerns on this invention. It is sectional drawing which shows the example of the pixel MOS transistor of an amplification type solid-state image sensor. It is a potential distribution diagram at the time of reading and resetting of the amplification type solid-state imaging device. It is a block diagram of the principal part used for description of the conventional CCD solid-state image sensor. A is a potential diagram in the substrate direction including light reception for explaining a conventional CCD solid-state imaging device. B is a potential diagram after adjustment. It is sectional drawing of the conventional ultraviolet erasable ROM.

Explanation of symbols

21 MIS element 22 First conductivity type region 23 Second conductivity type source region 24 Second conductivity type drain region 25 Gate insulating film 26 Silicon oxide film 27 Silicon nitride film 28 Silicon oxide film 30 Gate electrode 41 CCD solid-state imaging device 42 43 Vertical transfer register 44 Imaging area 45 Horizontal transfer register 46 Output circuit (charge detection circuit)
56 Silicon oxide film 57 Silicon nitride film 58 Silicon oxide films 59 and 84 Gate insulating film 67 Horizontal output gate portion FD Floating diffusion region 82 Reset gate portion 81 Reset drain region 86 Protection elements 91 and 102 Source follower type bias circuit 92 Drive MIS transistor 93 Load resistor 96 Power supply terminal 95 Gate terminal 97 Chip 105, 110 Inverter type bias circuit

Claims (2)

A plurality of pixels having a signal charge storage region portion made of a first conductivity type semiconductor region ;
It means for outputting a signal obtained from the pixel receives a scan pulse voltage,
A second conductivity type semiconductor region serving as an overflow control gate adjacent to the bottom of the signal charge storage region; a first conductivity type semiconductor substrate serving as an overflow drain adjacent to the second conductivity type semiconductor region; and discharging means for discharging the unnecessary signal of the pixel consists of,
A bias circuit for generating a voltage for controlling the discharging operation of the discharging means,
The bias circuit includes a load and a MISFET connected in series between a first potential and a second potential,
A bias voltage is obtained from the contact point between the load and the MISFET,
A charge for adjusting the threshold is injected into the gate insulating film of the MISFET,
A solid-state imaging device, wherein a voltage applied to the semiconductor substrate of the discharging means is set by the charge injection , and unnecessary signals of the pixels are discharged to the semiconductor substrate side . The gate insulating film of the MISFET is an oxide film, nitride film, a solid-state imaging device according to claim 1, characterized in that it has a multi-layer structure laminated in the order of oxide film.

Images