JP4441186B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a DRAM, and more particularly to an eDRAM (embedded DRAM) device in which a DRAM and a high-speed CMIS logic circuit are mixed.
[0002]
[Prior art]
In recent years, with the progress of the IT industry, there is an increasing demand for semiconductor LSIs to have a function of processing a large amount of data such as image processing data at high speed. For this reason, DRAM-embedded logic LSIs (eDRAM devices) that can ensure a wide bus width for data transfer are promising.
[0003]
In order for DRAM-embedded logic LSIs to be widely used in the future, in order not to degrade the performance of logic transistors, many new technologies have been developed and process improvements have been made, such as shortening the heat treatment time when forming a capacitor cell capacitor film. It is essential. One of the biggest problems is that in a DRAM memory cell, the distance between the substrate and the first metal wiring is increased in order to form a stack capacitance above the MIS transistor, making it difficult to open a deep small contact hole. It is to become.
[0004]
Therefore, conventionally, in order to avoid such a problem, for example, a structure as disclosed in Patent Document 1 is adopted. FIG. 7 is a cross-sectional view showing an example of the structure of a semiconductor device which is a conventional eDRAM mixed logic device disclosed in Patent Document 1. In FIG. In FIG. 7, memory cell transistors and capacitors, which are NMISFETs, are arranged in the cell array region, and PMISFETs and NMISFETs are arranged in the core / peripheral circuit region, which is a logic circuit region.
[0005]
As shown in FIG. 7, an element isolation region 1002 surrounding an active region is provided in a part of the semiconductor substrate 1001, and first and second interlayer insulating films 1051 and 1052 are provided above the semiconductor substrate 1001. ing.
[0006]
In the cell array region of the semiconductor device, an N-type source region 1012, an N-type drain region 1012 (impurity diffusion region), a source region 1025 (impurity diffusion region), a gate oxide film 1004, a gate electrode 1005, an on-gate protective film 1010, etc. A memory cell transistor 1061 is disposed. Note that the gate electrode 1005 has a polysilicon portion 1006 and a silicide portion 1008.
[0007]
In the cell array region, a storage node contact 1026 made of polysilicon that penetrates the first and second interlayer insulating films 1051 and 1052 and contacts the source region 1012 of the memory cell transistor 1061 is provided. A stacked capacitor 1062 including a cylindrical storage electrode 11030, a capacitive insulating film 1036, and a plate electrode 1040 is provided above 1026. Also, a bit line contact plug 1020 made of polysilicon that contacts the drain region 1014 of the memory cell transistor 1061 through the first interlayer insulating film 1051 and a bit line contact plug 1020 through the second interlayer insulating film 1052. A bit line / metal plug 1030 made of W or the like is provided.
[0008]
On the other hand, in the core / peripheral circuit region, a PMISFET 1065 having a P-type source / drain region 1016 (impurity diffusion region), a gate oxide film 1004, a gate electrode 1005, etc., and an N-type source / drain region 1018 (impurity diffusion region), An NMISFET 1066 having a gate oxide film 1004, a gate electrode 1005, and the like is disposed. The gate electrode 1005 has a polysilicon part 1006 and a silicide part 1008.
[0009]
A contact plug 1022 made of polysilicon is provided so as to penetrate the first interlayer insulating film 1051 and come into contact with the source / drain regions 1016 and 1018. Although not shown, when the third and fourth interlayer insulating films are provided on the second interlayer insulating film 1052, the contact plug 1022 penetrates the fourth interlayer insulating film and the third interlayer insulating film. A metal plug in contact with the metal and a metal wiring are formed.
[0010]
In the semiconductor device configured as described above, a contact plug made of polysilicon doped with impurities is used immediately above the impurity diffusion region and the gate electrode in the cell array region and the core / peripheral circuit region, and between the contact plug and the wiring. Are connected by a low-resistance metal plug. In such a structure, since the base of each metal plug is raised by the contact plug made of polysilicon, the depth of the metal plug 1030 connecting the metal wiring and each element can be reduced. As a result, the contact member between the wiring and the base can be formed without increasing the parasitic resistance.
[0011]
[Patent Document 1]
JP-A-11-214660
[0012]
[Problems to be solved by the invention]
However, in recent eDRAM devices, one of the most important issues is to reduce the area occupied by the memory cell array region Rmemo. In order to reduce the memory cell array region Rmemo, it is most effective to reduce the area occupied by the capacitor. For that purpose, it is most effective to form the capacitor insulating film of the capacitor with a dielectric having a high relative dielectric constant. is there. However, perovskite, which is widely used as a high dielectric material, has a remarkable deterioration in characteristics due to oxygen vacancies, so it is necessary to suppress diffusion and desorption of oxygen from the capacitor insulating film of the capacitor.
[0013]
Thus, it is conceivable to use a barrier conductive film, particularly a conductive film made of metal nitride (TiN, TaN, WN, etc.) as a plug. However, in general, a barrier conductive film, particularly a conductive film made of metal nitride (TiN, TaN, WN, etc.) has a high barrier function for suppressing diffusion of oxygen, hydrogen, and various metal atoms. Since the electrical resistance is larger than that of the conductive film, if the contact plug is composed only of a conductive film having a high barrier function, the parasitic resistance of the contact plug increases, which may hinder the operation performance of the transistor, particularly the logic transistor. There is. Therefore, as disclosed in Patent Document 1, the logic circuit region and the memory cell array region have to be individually subjected to a lithography process to form individual plugs.
[0014]
As described above, in general, when two or more types of plugs that require different characteristics are present in a semiconductor device, in the conventional semiconductor device, a lithography process is performed separately to form each type of plug. It was unavoidable.
[0015]
An object of the present invention is to satisfy different characteristics required for each plug in a semiconductor device having a plurality of types of contact plugs, while simplifying the process of forming contact holes and plugs.
[0016]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a substrate, first and second impurity diffusion layers provided on the substrate, an insulating film covering the substrate, and the first impurity diffusion layer penetrating the insulating film. On the bottom and side surfaces of the first contact plug made of the first conductor film filling the first contact hole that reaches and the second contact hole that penetrates the insulating film and reaches the second impurity diffusion layer And a second contact plug having a wall portion made of the first conductor film deposited on the central portion and a center portion made of the second conductor film deposited on the wall portion.
[0017]
Thus, by selecting materials for the first conductor film and the second conductor film, two types of contact plugs having different characteristics can be obtained without increasing the number of lithography processes. For example, the first conductor film is made of a material having a high barrier property, and the second conductor film is made of a material having a small electric resistance, whereby a fine first contact plug having a high barrier property; A second contact plug having a small parasitic resistance and capable of increasing the operation speed of the transistor can be obtained.
[0018]
It is preferable that the first contact plug and the second contact plug have a common height.
[0019]
At least a part of the first conductor film can function as a wiring.
[0020]
A memory cell transistor having a gate electrode, a source region and a drain region as the first impurity diffusion layer, a storage node contact plug connected to the source region of the memory cell transistor, and connected to the storage node contact plug A memory cell capacitor, a bit line contact plug connected to the drain region of the memory cell transistor, and a bit line connected to the bit line contact plug, the first contact plug Since the storage node contact plug is used, the area occupied by the DRAM memory cell can be reduced, and a semiconductor device including a DRAM having a reduced memory cell array region can be obtained.
[0021]
In that case, since the second contact plug is the bit line contact plug, the operation speed of the memory cell transistor can be kept high.
[0022]
Above the second contact plug, the second conductor film has a portion that extends on the insulating film together with the first conductor film and functions as a bit line of a DRAM memory. There is no need to separately provide a conductor film for formation, and the manufacturing cost can be reduced.
[0023]
In that case, above the second contact plug, the second conductor film has a portion that extends on the insulating film together with the first conductor film and functions as a bit line of the DRAM memory. As a result, it is possible to obtain a wiring with lower electrical resistance while reducing the manufacturing cost.
[0024]
A logic MIS transistor having a gate electrode and a source / drain region as the second impurity diffusion layer; a source / drain contact plug connected to the source / drain region of the logic transistor; And a wiring connected to the source / drain contact plug, the second contact plug is at least one of the storage node contact plug and the source / drain contact plug. Thus, it is possible to ensure a high operation speed of the logic transistor.
[0025]
The diameter of the first contact plug is preferably smaller than the diameter of the second contact plug, and the diameter of the first contact hole is ½ or less of the thickness of the second conductor film. Is preferred.
[0026]
By forming a sidewall made of an insulating material different from the insulating film on the side surface of the first contact hole, a plug diameter having a diameter equal to or smaller than the minimum design rule can be provided.
[0027]
Since the first conductor film includes a refractory metal nitride film, a first contact plug having a high barrier property can be obtained. In particular, a high dielectric constant dielectric is applied to a capacitor of a DRAM memory cell. When a body membrane is disposed, a remarkable effect can be exhibited.
[0028]
Since the first conductor film further includes a refractory metal film as a base film for the refractory metal nitride film, adhesion between the refractory metal nitride film and the base can be improved.
[0029]
The first conductor film is preferably any one film selected from a TiN film, a TaN film, a Ti / TiN film, and a Ti / TaN film.
[0030]
Since the second conductor film is a refractory metal film, a second contact plug having relatively low electrical resistance and stable characteristics can be obtained.
[0031]
The method of manufacturing a semiconductor device according to the present invention includes a step (a) of depositing an insulating film on a substrate having first and second impurity diffusion layers, and the first impurity diffusion layer penetrating the insulating film. Forming a first contact hole reaching the first contact hole and a second contact hole having a larger diameter than the first contact hole penetrating the insulating film and reaching the second impurity diffusion layer (b) And a step of depositing a first conductor film that fills the first contact hole, covers the bottom and side surfaces of the second contact hole of the second contact hole, and extends on the insulating film ( c) and a step (d) of depositing a second conductor film filling the second contact hole on the first conductor film, and the first conductor filling the first contact hole A first contact plug made of a film and the second contact hole; A wall portion made of the first conductive film deposited on the surface and the side surface, thereby forming a second contact plug having a central portion which is deposited on the wall portion.
[0032]
By selecting the materials for the first conductor film and the second conductor film by this method, the first and second contact holes having different diameters can be used to increase the characteristics without increasing the lithography process. Two different types of contact plugs can be obtained. For example, the first conductor film is made of a material having a high barrier property, and the second conductor film is made of a material having a small electric resistance, whereby a fine first contact plug having a high barrier property; A second contact plug having a small parasitic resistance and capable of increasing the operation speed of the transistor can be obtained.
[0033]
After the step (d), CMP or etchback is performed to remove a portion of the second conductor film located on the insulating film and to position the first conductor film on the insulating film. A step (e) of leaving at least a part of the portion to be formed, and a step (f) of patterning the first conductor film to form a wiring connected to the first contact plug, Since a process of separately depositing a conductor film for wiring is not required, the manufacturing cost can be reduced by simplifying the process.
[0034]
A step of performing CMP or etchback after the step (d) to planarize the upper surface and leave at least a part of the portion of the first and second conductor films located on the insulating film (e And the step (f) of patterning the first and second conductive films to form a wiring connected to the first contact plug, thereby reducing the manufacturing cost. A low resistance wiring can be obtained.
[0035]
When a memory cell transistor having a gate electrode and a source region and a drain region which are the first impurity diffusion layers is formed on the substrate before the step (a), the step (d) As the first contact hole, a storage node contact hole that penetrates the insulating film and reaches the source region of the memory cell transistor can be formed.
[0036]
In that case, in the step (d), a bit line contact hole that penetrates the insulating film and reaches the drain region of the memory cell transistor can be formed as the second contact hole.
[0037]
In the case where a logic MIS transistor having a gate electrode and a source / drain region as the second impurity diffusion layer is formed on the substrate before the step (a), the step ( In d), as the second contact hole, a source / drain contact hole that penetrates the insulating film and reaches the source / drain region of the logic transistor can be formed.
[0038]
The step (b) includes forming a first resist film having first and second openings above the regions where the first and second contact holes are to be formed on the insulating film. A step (b1), a sub-step (b2) for forming a resist sidewall made of a second resist film on the side surfaces of the first and second openings of the first resist film, and the first resist With the sub-process (b3) for etching the insulating film using the film and the resist sidewall as a mask, the diameter of the first contact hole can be made smaller than the minimum design rule. .
[0039]
The step (b) includes a sub-step (b1) for opening first and second initial contact holes having a diameter larger than the first and second contact holes in the insulating film, and the first step of the insulating film. 1 and a sub-process (b2) for forming a side wall made of a second insulating film covering the side surface of the second initial contact hole. Smaller than that.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1A to FIG. 2D are process cross-sectional views illustrating a method of manufacturing a CUB (Capacitor Under Bit-line) type DRAM mixed logic semiconductor device according to the first embodiment of the present invention. In the semiconductor device shown in FIGS. 1A to 2D, the memory cell array region Rmemo is a region where the memory cell transistor 153 and the capacitor 154 are arranged, and the logic circuit region Rlogc is the PMISFET 151 and the NMISFET 152 (CMIS). Is an area where
[0041]
In the step shown in FIG. 1A, an element isolation region (STI) 102 surrounding an active region in which each MISFET is disposed, a P well region 103 in which an NMISFET 152 of a logic circuit is disposed, on a P-type semiconductor substrate 101. The N well region 105 in which the PMISFET 151 of the logic circuit is disposed and the P well region 104 in which the memory cell transistor 153 and the capacitor 154 are disposed are formed by being separated from the semiconductor substrate 101 by the N type buried region 106. Thereafter, after implanting impurity ions (channel implantation) for controlling the threshold voltage of each MISFET, a silicon oxide film 107 having a thickness of 7.5 nm is formed by thermal oxidation. Further, after forming a photoresist film 108 covering the memory cell array region Rmemo on the silicon oxide film 107, etching is performed using the photoresist film 108 as a mask, and the silicon oxide film 107 is positioned in the logic circuit region Rlogc. Remove the part.
[0042]
Next, in the step shown in FIG. 1B, after the photoresist film 108 is removed, thermal oxidation is performed again to form a silicon oxide film 109x having a thickness of 3 nm in the logic circuit region Rlogc. At this time, a thick silicon oxide film 110x (10.5 nm) is formed in the memory cell array region Rmemo by two thermal oxidations. Next, a polysilicon film 111 is deposited on the silicon oxide films 109x and 110x, and phosphorus (P) is implanted only into a portion of the polysilicon film located in the NMISFET formation region to form an N-type polysilicon film 112. . Note that boron is implanted into a portion of the polysilicon film located in the PMISFET formation region in a later process in order to suppress boron penetration into the semiconductor substrate 101.
[0043]
Next, in the step shown in FIG. 1C, the polysilicon films 111 and 112 and the silicon oxide films 109x and 110x are patterned by etching using a photoresist film (not shown) covering the gate electrode formation region as a mask. Then, an N-type gate electrode 113, a gate electrode wiring 114, a P-type gate electrode 115, a thin gate insulating film 109, and a thick gate insulating film 110 are formed. Thereafter, ion implantation of P-type impurities and ion implantation of N-type impurities are performed using individually formed photoresist films (not shown), and the N-type extension diffusion layer of the NMISFET 152 is formed in the logic circuit region Rmemo. 116 and a P-type extension diffusion layer 117 of the PMISFET 151. In the memory cell array region Rmemo, an N-type source region 118 (LDD region) and an N-type drain region 119 (LDD region) of the memory cell transistor 153 are formed. And form.
[0044]
Next, in the step shown in FIG. 1D, sidewalls covering the side surfaces of the gate electrodes 113 and 115 and the gate electrode wiring 114 are formed, and then ion implantation of high-concentration P-type impurities and high-concentration N-type are performed. Impurity ion implantation is performed using a separately formed photoresist film (not shown). In the logic circuit region Rmemo, the N-type source / drain region 120 of the NMISFET 152 and the P-type source / drain region of the PMISFET 151 are used. 121 and a P-type gate electrode 122 are formed. However, ion implantation of high concentration impurities is not performed in the memory cell array region Rmemo.
[0045]
Next, in the step shown in FIG. 1E, using the well-known salicide technique, the gate electrodes 113 and 122, the gate electrode wiring 114, the source / drain regions 120 and 121, the source region 118, A cobalt silicide film 123 is formed above the drain region 119. Thereafter, after depositing a first interlayer insulating film 124 covering the PMISFET 151, the NMISFET 152, and the memory cell transistor 153, a contact hole penetrating the first interlayer insulating film 124 is formed. At this time, the source / drain contact hole 125 reaching the source / drain regions 120 and 121 in the logic circuit region Rlogc, the on-wiring contact hole 126 reaching the gate electrode wiring 114, and the drain region 119 of the memory cell transistor 153 The reaching bit line contact hole 128 has a relatively large diameter (for example, a diameter of 140 nm). On the other hand, the storage node contact hole 127 reaching the source region 118 of the memory cell transistor 153 has a relatively small diameter (for example, a diameter of 80 nm).
[0046]
Next, in the step shown in FIG. 1F, a Ti film and a TiN film are respectively formed in the contact holes 125, 126, 127, and 128 and on the first interlayer insulating film 124 by using a sputtering method and a CVD method. The Ti / TiN film 129 which is the first conductor film is deposited in order. At this time, the total thickness of the Ti / Ti film 129 is set so that the storage node contact hole 127 is filled with the Ti / TiN film 129 while the other contact holes 125, 126, and 128 are not filled with the Ti / TiN film 129. decide. In this embodiment, since the diameters of the contact holes 125, 126, and 128 are 140 nm and the storage node contact hole 127 is 80 nm, the total thickness of the Ti / TiN film 129 may be 40 nm. Therefore, the Ti / Ti film 129 is formed so as to form a wall portion extending along the bottom and side surfaces of the contact holes 125, 126, and 128. Next, a W film 130 as a second conductor film is deposited in each contact hole 125, 126, 128 and on the first interlayer insulating film 124 by using the CVD method. At this time, since the storage node contact hole 127 is already filled with the Ti / TiN film 129, the W film 130 is not deposited in the storage node contact hole 127. On the other hand, the other contact holes 125, 126, and 128 are filled with the Ti / TiN film 129 constituting the wall portion and the W film 130 constituting the center portion. As a result, a large-diameter source / drain contact plug 131 made of a Ti / TiN / W film, a gate contact plug 132, a bit line contact plug 134, and a small-diameter storage node contact plug 133 made of a Ti / TiN film are formed. The
[0047]
That is, when depositing one or more conductor films common to the storage node contact hole and the contact hole of the logic circuit formation region Rlogc, the storage node contact hole is embedded by the one or more conductor films. Since the contact holes other than the storage node contact holes are not filled with the one or more conductor films, the basic configuration of the present invention can be obtained.
[0048]
Next, in the step shown in FIG. 2A, a portion of the W film 130 and the Ti / TiN film 129 located on the first interlayer insulating film 124 is removed by CMP.
[0049]
Next, in the step shown in FIG. 2B, after depositing a second interlayer insulating film 135 made of a silicon oxide film on the first interlayer insulating film 124 and each plug, the second interlayer insulating film is formed by dry etching. A storage electrode groove 136 penetrating 135 is formed. Here, a part of the storage electrode groove 136 is in contact with the upper surface of the storage node contact plug 133. Thereafter, a Ru film is deposited on the storage electrode trench 136 and the second interlayer insulating film 135 using a CVD method, and then the second interlayer insulating film 135 of the Ru film is formed using an etch back method or a CMP method. The storage electrode 137 is formed in the storage electrode groove 136 by removing the portion located above.
[0050]
Next, in the step shown in FIG. 2C, after a BST film is deposited on the second interlayer insulating film 135 and the storage electrode 137, the BST film is oxidized using oxygen plasma, and further the RTA is performed. Processing is performed to crystallize the BST film. Next, after depositing a TiN film serving as a plate electrode on the BST film, patterning of the TiN film and the BST film is performed using a photoresist film (not shown) as a mask, so that the plate electrode 139 and the capacitor insulating film 138 are formed. Form. Thereby, a stack type capacitor is formed. In place of BST film, Ta ₂ O _Five Other high dielectric constant films may be used.
[0051]
Next, in the step shown in FIG. 2D, a third interlayer insulating film 140 made of a silicon oxide film is deposited on the stacked capacitor and the second interlayer insulating film 135, and then the third interlayer insulating film is formed by dry etching. After opening contact holes reaching the source / drain contact plug 131, the gate contact plug 132 and the bit line contact plug through the insulating film 140, a Ti film is formed in each contact hole and on the third interlayer insulating film 140. A TiN film and a W film are deposited. Thereafter, a portion of the Ti film, TiN film, and W film located on the third interlayer insulating film 140 is removed by planarization using CMP, and the Ti film, TiN film, and W film are formed in each contact hole. Then, the wiring plug 141 and the bit line plug 142 are formed. Next, after depositing a metal film such as an aluminum alloy film on the third interlayer insulating film 140 and the plugs 141, 142, the metal film is patterned to form a metal wiring 143 on the third interlayer insulating film 140. Form. A portion of the metal wiring 143 connected to the drain region 119 of the memory cell transistor 153 functions as a bit line.
[0052]
Thereafter, according to the circuit structure of the semiconductor device, one or more interlayer insulating films that are higher than the third interlayer insulating film 140, one or more wirings that are higher than the third interlayer insulating film 140, and the uppermost passivation are used. A film, a shield wall, and the like are formed, but illustration and description of the process are omitted.
[0053]
In the method of manufacturing the semiconductor device of this embodiment, the storage node contact hole 127 is opened with a small diameter by etching using a common etching mask in the step shown in FIG. , 128 are opened with a large diameter, and in the step shown in FIG. 1 (f), the small-diameter storage node contact hole 127 is filled with the first conductor film (Ti / TiN film in this embodiment), while the large-diameter storage node contact hole 127 is filled. In the contact holes 125, 126, and 128, a first conductor film serving as a wall is deposited while securing a space, and then a second conductor film (serving as a center in the space in each contact hole 125, 126, 128 ( In this embodiment, a W film) is embedded. By adopting such a manufacturing method, the following effects can be exhibited.
[0054]
In general, a barrier conductive film, particularly a conductive film made of metal nitride (TiN, TaN, WN, etc.) has a high barrier function to suppress diffusion of oxygen, hydrogen, and various metal atoms, but a conductor made of a single metal material. Compared with membrane, electrical resistance is large. Therefore, if the contact plug is composed only of a conductor film having a high barrier function, the parasitic resistance of the contact plug increases, which may hinder the operation performance of the transistor, particularly the logic transistor.
[0055]
On the other hand, in the case of a storage node contact plug of a memory cell, the size of the parasitic resistance does not matter so much, but as described above, in the eDRAM device, the capacitance of the capacitor is reduced in order to reduce the occupied area of the memory cell array region Rmemo. There is a demand for the insulating film to be composed of a dielectric film (high dielectric constant film) having a high relative dielectric constant. However, when a high dielectric constant film is used, the barrier performance of the storage node contact plug is a very important characteristic, and the entire storage node contact plug is formed of a barrier conductive film, which reduces the memory cell region Rmemo. Therefore, it can be said that it is preferable. Further, although the storage node contact plug is made of a barrier conductive film such as a TiN film, a TaN film, or a WN film, the electrical resistance of the storage node contact plug may increase, but as described above, In the case of the storage node contact plug, even if the parasitic resistance increases, there is almost no problem.
[0056]
In this case, if the source / drain contact plugs of the transistors in the logic circuit region Rlogc are configured only by the barrier conductive film, an increase in parasitic resistance becomes a problem as described above. However, as in the present embodiment, By simply depositing a barrier conductive film in the contact hole, since the source / drain contact plug is mainly composed of a W film, low resistance can be maintained. Since the TiN film, which is a barrier conductive film in the source / drain contact plug in the logic circuit region Rlogc, functions as a barrier film that suppresses the reaction between the W film and silicon or dopant of the semiconductor substrate, the logic circuit region Rlogc The performance of the transistor can be kept high.
[0057]
In that case, the storage node contact hole and the contact hole in the logic circuit region Rlogc can be simultaneously formed by etching using a common resist film as a mask, and it is not necessary to provide a separate resist film in the subsequent plug formation process. The lithography process is not increased and the process can be simplified.
[0058]
In particular, in the case of a stacked DRAM memory cell having a CUB structure, a barrier property of a storage node contact plug is required because a capacitive insulating film made of a high dielectric constant film is in contact with a storage no-contact. That is, when the DRAM memory cell size is further reduced and a high dielectric constant film such as BST is used, in order to prevent oxygen from diffusing from the high dielectric constant film and oxidizing the metal in the contact portion, diffusion of TiN or the like is prevented. A barrier film is required for the storage electrode connecting portion. Therefore, when the present invention is applied to a semiconductor device (eDRAM device) including a DRAM using a high dielectric constant film as a capacitor insulating film, a remarkable effect can be exhibited.
[0059]
In the present embodiment, the example in which the storage node contact plug in the memory cell array region Rmemo of the eDRAM device has a small diameter and the source / drain contact plug in the logic circuit region Rlogc has a large diameter has been described. It is not limited to the embodiment. In the case of a semiconductor device having a plurality of contact plugs, one contact plug is embedded with a first conductor film, while the other contact plug is embedded with a first conductor film and a second conductor film, thereby This is because each contact plug can have desired characteristics by utilizing the characteristics of the first conductor film and the characteristics of the second conductor film while simplifying the process by the reduction.
[0060]
In particular, in a semiconductor device having a plurality of contact plugs, the first conductor film is a barrier conductor film, while the second conductor film is a low-resistance conductor film, and the contact plugs that require barrier properties are A contact plug that is buried with the first conductor film and requires a lower resistance than the barrier property is buried with the first and second conductor films, thereby simplifying the process and requiring two types of plugs. Can satisfy the characteristics.
[0061]
(Second Embodiment)
3A to 4D are process cross-sectional views illustrating a method of manufacturing a CUB (Capacitor Under Bit-line) type DRAM mixed logic semiconductor device according to the second embodiment of the present invention. In the semiconductor device shown in FIGS. 3A to 4D, the memory cell array region Rmemo is a region where the memory cell transistor 253 and the capacitor 254 are arranged, and the logic circuit region Rlogc is the PMISFET 251 and the NMISFET 252 (CMIS). Is an area where
[0062]
3A, an element isolation region (STI) 202 surrounding an active region in which each MISFET is arranged and a P well region 203 in which an NMISFET 252 of a logic circuit is arranged on a P-type semiconductor substrate 201. Then, an N well region 205 in which the PMISFET 251 of the logic circuit is disposed, and a P well region 204 in which the memory cell transistor 253 and the capacitor 254 are disposed are formed by being separated from the semiconductor substrate 201 by the N type buried region 206. Thereafter, after implanting impurity ions (channel implantation) for controlling the threshold voltage of each MISFET, a silicon oxide film 207 having a thickness of 7.5 nm is formed by thermal oxidation. Further, after forming a photoresist film 208 covering the memory cell array region Rmemo on the silicon oxide film 207, etching is performed using the photoresist film 208 as a mask, and the silicon oxide film 207 is located in the logic circuit region Rlogc. Remove the part.
[0063]
Next, in the step shown in FIG. 3B, after the photoresist film 208 is removed, thermal oxidation is performed again to form a silicon oxide film 209x having a thickness of 3 nm in the logic circuit region Rlogc. At this time, a thick silicon oxide film 210x (10.5 nm) is formed in the memory cell array region Rmemo by two thermal oxidations. Next, a polysilicon film 211 is deposited on the silicon oxide films 209x and 210x, and phosphorus (P) is implanted only into a portion of the polysilicon film located in the NMISFET formation region to form an N-type polysilicon film 212. . Note that boron is implanted into a portion of the polysilicon film located in the PMISFET formation region in a later step in order to prevent boron from penetrating into the semiconductor substrate 201.
[0064]
Next, in the step shown in FIG. 3C, the polysilicon films 211 and 212 and the silicon oxide films 209x and 210x are patterned by etching using a photoresist film (not shown) covering the gate electrode formation region as a mask. Then, an N-type gate electrode 213, a gate electrode wiring 214, a P-type gate electrode 215, a thin gate insulating film 209, and a thick gate insulating film 210 are formed. Thereafter, ion implantation of P-type impurities and ion implantation of N-type impurities are performed using individually formed photoresist films (not shown), and the N-type extension diffusion layer of the NMISFET 252 is formed in the logic circuit region Rmemo. 216 and the P-type extension diffusion layer 217 of the PMISFET 251 are formed. In the memory cell array region Rmemo, the N-type source region 218 (LDD region) and the N-type drain region 219 (LDD region) of the memory cell transistor 253 are formed. And form.
[0065]
Next, in the step shown in FIG. 3D, after forming sidewalls covering the side surfaces of the gate electrodes 213 and 215 and the gate electrode wiring 214, ion implantation of high-concentration P-type impurities and high-concentration N-type are performed. Impurity ion implantation is performed using individually formed photoresist films (not shown). In the logic circuit region Rmemo, the N-type source / drain region 220 of the NMISFET 252 and the P-type source / drain region of the PMISFET 251 221 and a P-type gate electrode 222 are formed. However, ion implantation of high concentration impurities is not performed in the memory cell array region Rmemo.
[0066]
Next, in the step shown in FIG. 3E, using the well-known salicide technique, each gate electrode 213, 222, gate electrode wiring 214, each source / drain region 220, 221, source region 218, A cobalt silicide film 223 is formed on the drain region 219. Thereafter, after depositing a first interlayer insulating film 224 that covers the PMISFET 251, the NMISFET 252, and the memory cell transistor 253, a contact hole penetrating the first interlayer insulating film 224 is formed. At this time, the source / drain contact hole 225 reaching the source / drain regions 220 and 221 in the logic circuit region Rlogc, the on-wiring contact hole 226 reaching the gate electrode wiring 214, and the drain region 219 of the memory cell transistor 253 are formed. The reaching bit line contact hole 228 has a relatively large diameter (for example, a diameter of 140 nm). On the other hand, the storage node contact hole 227 reaching the source region 218 of the memory cell transistor 253 has a relatively small diameter (for example, a diameter of 80 nm).
[0067]
Next, in the step shown in FIG. 3F, a Ti film and a TiN film are respectively formed in the contact holes 225, 226, 227, 228 and on the first interlayer insulating film 224 by using a sputtering method and a CVD method. The Ti / TiN film 229, which is the first conductor film, is sequentially deposited. At this time, the total thickness of the Ti / Ti film 229 is set so that the storage node contact hole 227 is filled with the Ti / TiN film 229 while the other contact holes 225, 226 and 228 are not filled with the Ti / TiN film 229. decide. In this embodiment, since the diameters of the contact holes 225, 226, and 228 are 140 nm and the storage node contact hole 227 is 80 nm, the total thickness of the Ti / TiN film 229 may be 40 nm. Therefore, the Ti / Ti film 229 is formed so as to extend along the bottom and side surfaces of the contact holes 225, 226, and 228. Next, a W film 230 as a second conductor film is deposited in each contact hole 225, 226, 228 and on the first interlayer insulating film 224 by using the CVD method. At this time, since the storage node contact hole 227 is already filled with the Ti / TiN film 229, the W film 230 is not deposited in the storage node contact hole 227. On the other hand, the other contact holes 225, 226 and 228 are filled with the W film 230 and the Ti / TiN film 229.
[0068]
That is, when depositing one or more conductor films common to the storage node contact hole and the contact hole of the logic circuit formation region Rlogc, the storage node contact hole is embedded by the one or more conductor films. Since the contact holes other than the storage node contact holes are not filled with the one or more conductor films, the basic configuration of the present invention can be obtained.
[0069]
Next, in the step shown in FIG. 4A, a portion of the W film 230 located on the first interlayer insulating film 224 is removed by using the CMP method using the TiN film as a stopper.
[0070]
Next, in the step shown in FIG. 4B, a nitride film is deposited on the Ti / TiN film 229, and then the nitride film and the Ti / TiN film 229 are selected by etching using the photoresist film 261 as a mask. To remove. As a result, the protective nitride film 260, the large-diameter source / drain contact plug 231 made of the Ti / TiN / W film, the gate contact plug 232 and the bit line contact plug 234, and the small-diameter storage node contact made of the Ti / TiN film. A plug 233 and a bit line BL made of a Ti / TiN film extending on the first interlayer insulating film 224 are formed.
[0071]
Next, in the step shown in FIG. 4C, after a nitride film is deposited on the substrate, etch back is performed to cover the protruding portion of the bit line contact plug 234 and the side surface of the protective nitride film 260. Form.
[0072]
Thereafter, a second interlayer insulating film 235 made of a silicon oxide film is deposited on the first interlayer insulating film 224 and each plug, and then a storage electrode groove 236 penetrating the second interlayer insulating film 235 is formed by dry etching. . Here, a part of the on-wiring contact hole 226 is in contact with the upper surface of the storage node contact plug 233. Thereafter, a Ru film is deposited on the storage electrode trench 236 and the second interlayer insulating film 235 by using a CVD method, and then the second interlayer insulating film 235 of the Ru film is formed by using an etch back method or a CMP method. The storage electrode 237 is formed in the storage electrode groove 236 by removing the portion located above.
[0073]
Next, in the step shown in FIG. 4D, after depositing a BST film on the second interlayer insulating film 235 and the storage electrode 237, the BST film is oxidized using oxygen plasma, and then the RTA is further performed. Processing is performed to crystallize the BST film. Next, after depositing a TiN film serving as a plate electrode on the BST film, patterning of the TiN film and the BST film is performed using a photoresist film (not shown) as a mask, so that the plate electrode 239 and the capacitor insulating film 238 are formed. Form. Thereby, a stack type capacitor is formed. In place of BST film, Ta ₂ O _Five Other high dielectric constant films may be used.
[0074]
After that, a third interlayer insulating film 240 made of a silicon oxide film is deposited on the stack type capacitor and the second interlayer insulating film 235, and then the source / drain contact is penetrated through the third interlayer insulating film 240 by dry etching. After opening the contact holes reaching the plug 231, the gate contact plug 232, and the bit line contact plug 234, a Ti film, a TiN film, and a W film are deposited in each contact hole and on the third interlayer insulating film 240. Thereafter, a portion of the Ti film, TiN film, and W film located on the third interlayer insulating film 240 is removed by planarization using CMP, and the Ti film, TiN film, and W film are formed in each contact hole. Then, a wiring plug 241 and a bit line plug (not shown) are formed. Next, after depositing a metal film such as an aluminum alloy film on the third interlayer insulating film 240 and each plug 241, the metal film is patterned to form a metal wiring 243 on the third interlayer insulating film 240. .
[0075]
Thereafter, according to the circuit structure of the semiconductor device, one or more interlayer insulating films that are higher than the third interlayer insulating film 240, one or more wirings that are higher than the third interlayer insulating film 240, and the uppermost passivation are used. A film, a shield wall, and the like are formed, but illustration and description of the process are omitted.
[0076]
Also in the method of manufacturing the semiconductor device of this embodiment, as in the method of manufacturing the semiconductor device of the first embodiment, the storage node contact is performed by etching using a common etching mask in the step shown in FIG. After the hole 227 is opened with a small diameter and the other contact holes 225, 226, 228 are opened with a large diameter, the storage node contact hole 227 with a small diameter is formed in the first conductor film (the main film) in the step shown in FIG. In the embodiment, the first conductive film is deposited while securing a space in the large-diameter contact holes 225, 226, and 228, and then the spaces in the contact holes 225, 226, and 228 are filled. The second conductor film (W film in the present embodiment) is embedded in the structure. By adopting such a manufacturing method, it is possible to simplify the process without causing an increase in the lithography process by the same operation as that of the first embodiment.
[0077]
In particular, in the case of a stacked DRAM memory cell having a CUB structure, a barrier property of a storage node contact plug is required because a capacitive insulating film made of a high dielectric constant film is in contact with a storage no-contact. That is, when the DRAM memory cell size is further reduced and a high dielectric constant film such as BST is used, in order to prevent oxygen from diffusing from the high dielectric constant film and oxidizing the metal in the contact portion, diffusion of TiN or the like is prevented. A barrier film is required for the storage electrode connecting portion. Therefore, when the present invention is applied to a semiconductor device provided with a DRAM using a high dielectric constant film as a capacitor insulating film, significant effects can be exhibited.
[0078]
In this embodiment, as shown in FIG. 4A, at least a part of the portion located on the first interlayer insulating film 224 in the Ti / TiN film 229 that is the first conductor film is not removed. In addition, since the bit line BL is formed later using the Ti / TiN film 229, a process of separately forming a conductor film for the bit line becomes unnecessary, and the manufacturing cost is reduced by simplifying the process. Can be achieved. It is also possible to form local wiring using the Ti / TiN film 229.
[0079]
In the present embodiment, the example in which the storage node contact plug in the memory cell array region Rmemo of the eDRAM device has a small diameter and the source / drain contact plug in the logic circuit region Rlogc has a large diameter has been described. It is not limited to the embodiment. In the case of a semiconductor device having a plurality of contact plugs, one contact plug is embedded with a first conductor film, while the other contact plug is embedded with a first conductor film and a second conductor film, thereby This is because each contact plug can have desired characteristics by utilizing the characteristics of the first conductor film and the characteristics of the second conductor film while simplifying the process by the reduction.
[0080]
In particular, in a semiconductor device having a plurality of contact plugs, the first conductor film is a barrier conductor film, while the second conductor film is a low-resistance conductor film, and the contact plugs that require barrier properties are A contact plug that is buried with the first conductor film and requires a lower resistance than the barrier property is buried with the first and second conductor films, thereby simplifying the process and requiring two types of plugs. Can satisfy the characteristics. The first conductor film can be used as a part of the bit line as in this embodiment, or can be used as a part of the local wiring.
[0081]
(Third embodiment)
FIG. 5A to FIG. 6D are process cross-sectional views illustrating a method of manufacturing a CUB (Capacitor Under Bit-line) type DRAM mixed logic semiconductor device according to the third embodiment of the present invention. In the semiconductor device shown in FIGS. 5A to 6D, the memory cell array region Rmemo is a region where the memory cell transistor 353 and the capacitor 354 are arranged, and the logic circuit region Rlogc is a PMISFET 351 and an NMISFET 352 (CMIS). Is an area where
[0082]
5A, on the P-type semiconductor substrate 301, an element isolation region (STI) 302 surrounding an active region where each MISFET is arranged, a P well region 303 where an NMISFET 352 of a logic circuit is arranged, The N well region 305 where the PMISFET 351 of the logic circuit is disposed and the P well region 304 where the memory cell transistor 353 and the capacitor 354 are disposed are formed by being separated from the semiconductor substrate 301 by the N type buried region 306. Thereafter, after implanting impurity ions (channel implantation) for controlling the threshold voltage of each MISFET, a silicon oxide film 307 having a thickness of 7.5 nm is formed by thermal oxidation. Further, after forming a photoresist film 308 covering the memory cell array region Rmemo on the silicon oxide film 307, etching is performed using the photoresist film 308 as a mask, and the silicon oxide film 307 is located in the logic circuit region Rlogc. Remove the part.
[0083]
Next, in the step shown in FIG. 5B, after removing the photoresist film 308, thermal oxidation is performed again to form a silicon oxide film 309x having a thickness of 3 nm in the logic circuit region Rlogc. At this time, a thick silicon oxide film 310x (10.5 nm) is formed in the memory cell array region Rmemo by two thermal oxidations. Next, a polysilicon film 311 is deposited on the silicon oxide films 309x and 310x, and phosphorus (P) is implanted only into a portion of the polysilicon film located in the NMISFET formation region to form an N-type polysilicon film 312. . Note that boron is implanted into a portion of the polysilicon film located in the PMISFET formation region in a later step in order to suppress boron penetration into the semiconductor substrate 301 and the like.
[0084]
Next, in the step shown in FIG. 5C, the polysilicon films 311 and 312 and the silicon oxide films 309x and 310x are patterned by etching using a photoresist film (not shown) covering the gate electrode formation region as a mask. Then, an N-type gate electrode 313, a gate electrode wiring 314, a P-type gate electrode 315, a thin gate insulating film 309, and a thick gate insulating film 310 are formed. Thereafter, ion implantation of P-type impurities and ion implantation of N-type impurities are performed using individually formed photoresist films (not shown), and the N-type extension diffusion layer of the NMISFET 352 is formed in the logic circuit region Rmemo. 316 and a P-type extension diffusion layer 317 of the PMISFET 351. In the memory cell array region Rmemo, an N-type source region 318 (LDD region) and an N-type drain region 319 (LDD region) of the memory cell transistor 353 are formed. And form.
[0085]
Next, in the step shown in FIG. 5D, after forming sidewalls covering the side surfaces of the gate electrodes 313 and 315 and the gate electrode wiring 314, ion implantation of high-concentration P-type impurities and high-concentration N-type are performed. Impurity ion implantation is performed using a separately formed photoresist film (not shown). In the logic circuit region Rmemo, the N-type source / drain region 320 of the NMISFET 352 and the P-type source / drain region of the PMISFET 351 321 and a P-type gate electrode 322 are formed. However, ion implantation of high concentration impurities is not performed in the memory cell array region Rmemo.
[0086]
Next, in the step shown in FIG. 5E, each of the gate electrodes 313, 322, the gate electrode wiring 314, the source / drain regions 320, 321, the source region 318, A cobalt silicide film 323 is formed above the drain region 319. Thereafter, after depositing a first interlayer insulating film 324 covering the PMISFET 351, the NMISFET 352, and the memory cell transistor 353, a contact hole penetrating the first interlayer insulating film 324 is formed. At this time, the contact hole 325 reaching the source / drain regions 320 and 321 of the logic circuit region Rlogc, the on-wiring contact hole 326 reaching the gate electrode wiring 314, and the bit reaching the drain region 319 of the memory cell transistor 353 The line contact hole 328 has a relatively large diameter (for example, a diameter of 140 nm). On the other hand, the storage node contact hole 327 reaching the source region 318 of the memory cell transistor 353 has a relatively small diameter (for example, a diameter of 80 nm).
[0087]
Next, in the step shown in FIG. 5F, a Ti film and a TiN film are respectively formed in the contact holes 325, 326, 327, and 328 and on the first interlayer insulating film 324 by using a sputtering method and a CVD method. A Ti / TiN film 329 that is a first conductor film is deposited in order. At this time, the total thickness of the Ti / Ti film 329 is set so that the storage node contact hole 327 is filled with the Ti / TiN film 329 while the other contact holes 325, 326 and 328 are not filled with the Ti / TiN film 329. decide. In this embodiment, since the diameters of the contact holes 325, 326, and 328 are 140 nm and the storage node contact hole 327 is 80 nm, the total thickness of the Ti / TiN film 329 may be 40 nm. Therefore, the Ti / Ti film 329 is formed so as to form a wall portion extending along the bottom and side surfaces of the contact holes 325, 326, and 328. Next, a W film 330 as a second conductor film is deposited in each contact hole 325, 326, 328 and on the first interlayer insulating film 324 by using the CVD method. At this time, since the storage node contact hole 327 is already filled with the Ti / TiN film 329, the W film 330 is not deposited in the storage node contact hole 327. On the other hand, the other contact holes 325, 326, and 328 are filled with the Ti / TiN film 329 constituting the wall portion and the W film 330 constituting the center portion.
[0088]
That is, when depositing one or more conductor films common to the storage node contact hole and the contact hole of the logic circuit formation region Rlogc, the storage node contact hole is embedded by the one or more conductor films. Since the contact holes other than the storage node contact holes are not filled with the one or more conductor films, the basic configuration of the present invention can be obtained.
[0089]
Next, in the step shown in FIG. 6A, after a nitride film is deposited on the W film 330, the nitride film, the W film 330, and the Ti / TiN film 329 are etched by using the photoresist film 361 as a mask. Is selectively removed. Thus, the protective nitride film 360, the large-diameter source / drain contact plug 331 made of Ti / TiN / W film, the gate contact plug 332 and the bit line contact plug 334, and the small-diameter storage node contact made of Ti / TiN film. A plug 333 and a bit line BL made of a Ti / TiN film and a W film extending on the first interlayer insulating film 224 are formed. That is, unlike the first embodiment, at least a part of the portion of the Ti / TiN film 329 and the W film 330 that are the first and second conductor films located on the first interlayer insulating film 324 is removed. The bit line BL is formed without being left behind. This is a feature of this embodiment.
[0090]
Next, in the step shown in FIG. 6B, after a nitride film is deposited on the substrate, etch back is performed to cover the protruding portion of the bit line contact plug 334 and the side surface of the protective nitride film 360. Form.
[0091]
Thereafter, a second interlayer insulating film 335 made of a silicon oxide film is deposited on the first interlayer insulating film 324 and each plug, and then a storage electrode trench 336 penetrating the second interlayer insulating film 335 is formed by dry etching. . Here, a part of the on-wiring contact hole 326 is in contact with the upper surface of the storage node contact plug 333. Thereafter, a Ru film is deposited on the storage electrode trench 336 and the second interlayer insulating film 335 using a CVD method, and then the second interlayer insulating film 335 of the Ru film is formed using an etch back method or a CMP method. The storage electrode 337 is formed in the storage electrode groove 336 by removing the portion located above.
[0092]
Next, in the step shown in FIG. 6D, after a BST film is deposited on the second interlayer insulating film 335 and the storage electrode 337, the BST film is oxidized using oxygen plasma, and further the RTA is performed. Processing is performed to crystallize the BST film. Next, a TiN film to be a plate electrode is deposited on the BST film, and then the TiN film and the BST film are patterned using a photoresist film (not shown) as a mask, so that the plate electrode 339 and the capacitor insulating film 338 are formed. Form. Thereby, a stack type capacitor is formed. In place of BST film, Ta ₂ O _Five Other high dielectric constant films may be used.
[0093]
Thereafter, a third interlayer insulating film 340 made of a silicon oxide film is deposited on the stack type capacitor and the second interlayer insulating film 335, and then, through dry etching, the third interlayer insulating film 340 is penetrated and the source / drain contact is made. After opening the contact holes reaching the plug 331, the gate contact plug 332, and the bit line contact plug 334, a Ti film, a TiN film, and a W film are deposited in each contact hole and on the third interlayer insulating film 340. Thereafter, a portion of the Ti film, TiN film, and W film located on the third interlayer insulating film 340 is removed by planarization using CMP, and the Ti film, TiN film, and W film are formed in each contact hole. Then, a wiring plug 341 and a bit line plug (not shown) are formed. Next, after depositing a metal film such as an aluminum alloy film on the third interlayer insulating film 340 and each plug 341, the metal film is patterned to form a metal wiring 343 on the third interlayer insulating film 340. .
[0094]
Thereafter, according to the circuit structure of the semiconductor device, one or more interlayer insulating films that are higher than the third interlayer insulating film 340, one or more wirings that are higher than the third interlayer insulating film 340, and the uppermost passivation are used. A film, a shield wall, and the like are formed, but illustration and description of the process are omitted.
[0095]
Also in the method of manufacturing the semiconductor device of the present embodiment, as in the method of manufacturing the semiconductor device of the first embodiment, the storage node contact is performed by etching using a common etching mask in the step shown in FIG. After opening the hole 327 with a small diameter and opening the other contact holes 325, 326, and 328 with a large diameter, the storage node contact hole 327 with a small diameter is formed in the first conductor film (main film) in the step shown in FIG. In the embodiment, the first conductive film is deposited while securing a space in the large-diameter contact holes 325, 326, and 328, and then the spaces in the contact holes 325, 326, and 328 are filled. The second conductor film (W film in the present embodiment) is embedded in the structure. By adopting such a manufacturing method, it is possible to simplify the process without causing an increase in the lithography process by the same action as that of the first embodiment.
[0096]
In particular, in the case of a stacked DRAM memory cell having a CUB structure, a barrier property of a storage node contact plug is required because a capacitive insulating film made of a high dielectric constant film is in contact with a storage no-contact. That is, when the DRAM memory cell size is further reduced and a high dielectric constant film such as BST is used, in order to prevent oxygen from diffusing from the high dielectric constant film and oxidizing the metal in the contact portion, diffusion of TiN or the like is prevented. A barrier film is required for the storage electrode connecting portion. Therefore, when the present invention is applied to a semiconductor device provided with a DRAM using a high dielectric constant film as a capacitor insulating film, significant effects can be exhibited.
[0097]
In the present embodiment, as shown in FIG. 6A, portions of the Ti / TiN film 329 and the W film 330, which are the first and second conductor films, located on the first interlayer insulating film 324. Since the bit line BL is formed without removing at least a part thereof, a step of separately forming a conductor film for the bit line becomes unnecessary, and the manufacturing cost can be reduced by simplifying the step. .
[0098]
In the present embodiment, the example in which the storage node contact plug in the memory cell array region Rmemo of the eDRAM device has a small diameter and the source / drain contact plug in the logic circuit region Rlogc has a large diameter has been described. It is not limited to the embodiment. In the case of a semiconductor device having a plurality of contact plugs, one contact plug is embedded with a first conductor film, while the other contact plug is embedded with a first conductor film and a second conductor film, thereby This is because each contact plug can have desired characteristics by utilizing the characteristics of the first conductor film and the characteristics of the second conductor film while simplifying the process by the reduction.
[0099]
In particular, in a semiconductor device having a plurality of contact plugs, the first conductor film is a barrier conductor film, while the second conductor film is a low-resistance conductor film, and the contact plugs that require barrier properties are A contact plug that is buried with the first conductor film and requires a lower resistance than the barrier property is buried with the first and second conductor films, thereby simplifying the process and requiring two types of plugs. Can satisfy the characteristics. The first conductor film can be used as a part of the bit line as in this embodiment, or can be used as a part of the local wiring.
[0100]
(Other embodiments)
As the first conductor film, a metal nitride film which is a metal film or a metal nitride film is preferably used in order to provide low resistance, and particularly in order to provide a barrier property, a refractory metal (W, It is preferable to use a refractory metal nitride film which is a nitride film of Ti, Ta, Zr, Ni, Co, V, Mn and the like. As the refractory metal nitride film, a TiN film or a TaN film is preferred in practice in consideration of ease of production and chemical stability.
[0101]
In the case of using the refractory metal nitride film, it is preferable that the first conductor film is composed of the refractory metal film and the refractory metal nitride film as in each of the above embodiments in order to improve the adhesion with the base. . In that case, considering the ease of manufacture, it can be said that a Ti / TiN film and a Ta / TaN film are practically preferable.
[0102]
As the second conductor film, a refractory metal film having a low resistance and migration resistance is preferable, and a W film, a Ti film, and the like are preferable in practice in consideration of ease of manufacture.
[0103]
In the step of forming the first and second contact holes in each of the above embodiments, the first and second contact holes are formed before the steps shown in FIGS. 1 (e), 3 (e), and 5 (e), respectively. First and second initial contact holes having a diameter larger than that of the contact hole are formed, and an insulating film having a high etching selectivity with respect to the first interlayer insulating film (the diameter of the first contact hole) is formed thereabove. In this case, the insulating film may be anisotropically etched to form sidewalls covering the side surfaces of the first and second initial contact holes. Thereby, the diameter of the first contact hole can be made smaller than the minimum design rule.
[0104]
Further, in the step of forming the first and second contact holes in each of the above-described embodiments, the first and first contact holes are formed before the steps shown in FIGS. 1E, 3E, and 5E, respectively. After forming a resist film having first and second openings larger in diameter than the two contact holes, and depositing a second resist film thereon, the second resist film is anisotropically formed. In the steps shown in FIGS. 1 (e), 3 (e) and 5 (e), a resist film and a resist side are formed. The first interlayer insulating film may be etched using the wall as an etching mask. Thereby, the diameter of the first contact hole can be made smaller than the minimum design rule.
[0105]
【The invention's effect】
According to the present invention, two types of contact plugs can be formed without increasing the number of lithography processes, and an eDRAM device equipped with a high-permittivity DRAM having a small occupied area and a logic transistor that operates at high speed. It is possible to provide a high-performance semiconductor device such as the above and a manufacturing method thereof.
[Brief description of the drawings]
FIGS. 1A to 1F are cross-sectional views showing the first half of a manufacturing process of an eDRAM device according to a first embodiment.
FIGS. 2A to 2D are cross-sectional views showing the latter half of the manufacturing process of the eDRAM device according to the first embodiment. FIGS.
FIGS. 3A to 3F are cross-sectional views showing the first half of an eDRAM device manufacturing process according to a second embodiment. FIGS.
FIGS. 4A to 4D are cross-sectional views showing the latter half of the manufacturing process of the eDRAM device according to the second embodiment. FIGS.
FIGS. 5A to 5F are cross-sectional views showing the first half of an eDRAM device manufacturing process according to a third embodiment;
FIGS. 6A to 6D are cross-sectional views showing the latter half of the manufacturing process of the eDRAM device according to the third embodiment. FIGS.
FIG. 7 is a cross-sectional view showing the structure of a conventional SDRAM device.
[Explanation of symbols]
101 Semiconductor substrate
102 element isolation region
103 P-well region
104 P-well region
105 N-well region
106 N-type buried region
107 Silicon oxide film
108 Photoresist film
109 Gate insulation film
109x silicon oxide film
110 Gate insulation film
110x silicon oxide film
111 Polysilicon film
112 N-type polysilicon film
113 N-type gate electrode
114 Gate electrode wiring
115 Gate electrode
116 Extension diffusion layer
117 Extension diffusion layer
118 Source region
119 drain region
120 N-type source / drain regions
121 P-type source / drain regions
122 P-type gate electrode
123 Cobalt silicide film
124 first interlayer insulating film
125 Source / drain contact hole
126 Contact hole on wiring
127 Storage node contact hole
128 bit line contact hole
129 Ti / TiN film (first conductor film)
130 W film (second conductor film)
131 Source / drain contact plug
132 Gate electrode wiring contact plug
133 Storage node contact plug
134 Bit line contact plug
135 Second interlayer insulating film
136 Storage electrode groove
137 Storage electrode
138 Capacitance insulation film
139 Plate electrode
140 Third interlayer insulating film
141 Wiring plug
142 bit line plug
143 Metal wiring
151 PMISFET
152 NMISFET
153 Memory cell transistor
154 capacitors
201 Semiconductor substrate
202 Element isolation region
203 P-well region
204 P-well region
205 N-well region
206 N-type buried region
207 Silicon oxide film
208 Photoresist film
209 Gate insulation film
209x silicon oxide film
210 Gate insulation film
210x silicon oxide film
211 Polysilicon film
212 N-type polysilicon film
213 N-type gate electrode
214 N-type gate electrode wiring
215 Gate electrode
216 Extension diffusion layer
217 Extension diffusion layer
218 Source region
219 drain region
220 N-type source / drain regions
221 P-type source / drain region
222 P-type gate electrode
223 Cobalt silicide film
224 First interlayer insulating film
225 Source / drain contact hole
226 Contact hole on wiring
227 Storage node contact hole
228 Bit line contact hole
229 Ti / TiN film
230 W film
231 Source / drain contact plug
232 Gate electrode wiring contact plug
233 Storage node contact plug
234 Bit line contact plug
235 Second interlayer insulating film
236 Storage electrode groove
237 storage electrode
238 capacitive insulating film
239 Plate electrode
240 Third interlayer insulating film
241 Wiring plug
243 metal wiring
251 PMISFET
252 NMISFET
253 Memory cell transistor
254 capacitors
260 Protective nitride film
261 photoresist film
262 Nitride film sidewall
301 Semiconductor substrate
302 Element isolation region (STi)
303 P-well region
304 P-well region
305 N well region
306 N-type buried region
307 Silicon oxide film
308 Photoresist film
309 Gate insulation film
309x silicon oxide film
310 Gate insulating film
310x silicon oxide film
311 Polysilicon film
312 N-type polysilicon film
313 N-type gate electrode
314 N-type gate electrode wiring
315 Gate electrode
316 Extension diffusion layer
317 Extension diffusion layer
318 source region
319 drain region
320 N-type source / drain regions
321 P-type source / drain region
322 P-type gate electrode
323 Cobalt silicide film
324 First interlayer insulating film
325 Source / drain contact hole
326 Contact hole on wiring
327 Storage node contact hole
328 Bit line contact hole
329 Ti / TiN film
330 W membrane
331 Source / drain contact plug
332 Gate electrode wiring contact plug
333 storage node contact plug
334 Bit line contact plug
335 Second interlayer insulating film
336 Storage electrode groove
337 Storage electrode
338 capacitive insulating film
339 Plate electrode
340 Third interlayer insulating film
341 Wiring plug
343 Metal wiring
351 PMISFET
352 NMISFET
353 Memory Cell Transistor
354 capacitors
360 Protective nitride film
361 Photoresist film
362 Nitride film sidewall

Claims (8)

Depositing an insulating film on the substrate having the first and second impurity diffusion layers;
A storage node contact hole that passes through the insulating film and reaches the first impurity diffusion layer, and a storage node contact hole that passes through the insulating film and reaches the second impurity diffusion layer. Forming a bit line contact hole (b);
Depositing a first conductor film filling the storage node contact hole and covering the bottom and side surfaces of the bit line contact hole and having a refractory metal nitride film extending on the insulating film;
Depositing a second conductor film having a refractory metal film filling the bit line contact hole on the first conductor film;
A storage node contact plug made of a first conductor film filling the storage node contact hole; a wall part made of the first conductor film deposited on the bottom and side surfaces of the bit line contact hole; A method of manufacturing a semiconductor device, comprising: forming a bit line contact plug having a central portion made of a second conductor film deposited thereon. In the manufacturing method of the semiconductor device according to claim 1 ,
After the step (d), the method further includes a step (e) of performing CMP or etchback to remove a portion of the first and second conductor films located on the insulating film. Method. In the manufacturing method of the semiconductor device according to claim 1 ,
After the step (d), CMP or etchback is performed to remove a portion of the second conductor film located on the insulating film, and on the insulating film of the first conductor film. Leaving at least a portion of the located portion (e);
And a step (f) of patterning the first conductor film to form a bit line connected to the bit line contact plug. In the manufacturing method of the semiconductor device according to claim 1 ,
After the step (d), the method further includes a step (f) of patterning the first and second conductive films to form a bit line connected to the bit line contact plug. . In the manufacturing method of the semiconductor device according to any one of claims 1 to 4 ,
Before the step (a), a method of manufacturing a semiconductor device, wherein a memory cell transistor having a gate electrode and a source region and a drain region which are the first and second impurity diffusion layers is formed on the substrate. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5 ,
Before the step (a), the On the substrate, a gate electrode, a source-drain region and the MIS transistor logic having is formed a third impurity diffusion layer of及beauty,
In the step (d), a source / drain contact hole that penetrates the insulating film and reaches the third impurity diffusion layer is formed. In the manufacturing method of the semiconductor device according to any one of claims 1 to 6 ,
The step (b)
A sub-process (b1) for forming a first resist film having first and second openings on the insulating film above the region where the storage node contact hole and the bit line contact hole are to be formed; ,
A sub-step (b2) of forming a resist sidewall made of a second resist film on the side surfaces of the first and second openings of the first resist film;
The first resist film and the resist side walls as a mask, a method of manufacturing a semiconductor device which is characterized that you have a sub-step (b3) performing the etching of the insulating film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 6 ,
The step (b)
A sub-step (b1) of opening first and second initial contact holes having a diameter larger than that of the storage node contact hole and the bit line contact hole in the insulating film;
And a sub-process (b2) for forming a sidewall made of a second insulating film covering a side surface of the first and second initial contact holes of the insulating film.

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