JP4440670B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a memory element, and more particularly to a nonvolatile semiconductor memory device having a memory element having a MONOS (metal-oxide film-nitride film-oxide film-semiconductor) structure.

A memory element capable of electrically rewriting data is generally called an EEPROM, and is suitable for storing data necessary for the specification and operation of an electronic device.
As the main types of EEPROM, there are a memory element having a MONOS structure, a memory element having a MNOS (metal-nitride film-oxide film-semiconductor) structure, and a memory element having a floating gate structure.

  By the way, the data necessary for the specifications and operation of the electronic device may be already known at the start of manufacturing the memory element. In that case, the memory element mounted on the semiconductor device may be a mask ROM instead of an EEPROM.

However, a product ROM program that does not need to be corrected or fixed data may be stored in a mask ROM. However, a memory element that is assumed to be overwritten or written / erased can only be composed of an EEPROM. Absent.
In addition, just before mounting a semiconductor device including a memory element on an electronic device, it may be necessary to add or rewrite data in order to correct manufacturing variations or suddenly change specifications. EEPROM is widely used.

  In the EEPROM, it is necessary to prepare a positive power source for writing and a negative power source for erasing regardless of the type of data to be written. In a semiconductor device provided with an EEPROM, it is necessary to write and erase data that requires man-hours and time in the manufacturing process, which is a great burden when mass-producing semiconductor devices.

  Among the above, as a method for improving the problem of having to prepare a positive power source for writing and a negative power source for erasing, several proposals are being seen (see, for example, Patent Document 1).

  The prior art shown in Patent Document 1 will be described. FIG. 8 is a simplified diagram showing the structure of a memory element having a MONOS structure, which is the main type of EEPROM, and is a diagram rewritten without departing from the gist thereof.

In FIG. 8, 10 is a memory element having a MONOS structure, 11 is a p-type semiconductor substrate, 12a is an n ⁺ diffusion layer as a source, 12b is an n ⁺ diffusion layer as a drain, 13 is a depletion layer, 14c is a gate insulating film, Reference numeral 15 is a control gate, 21 is a drain terminal, 22 is a gate terminal, 23 is a source terminal, 141 is a tunnel oxide film, 142 is a memory nitride film, and 143c is a top oxide film.
The gate insulating film 14c includes a tunnel oxide film 141, a memory nitride film 142, and a top oxide film 143c.

  FIG. 8 shows a case where a positive power source is connected to the drain terminal 21, the gate terminal 22 is set to the ground potential, and the source terminal 23 is opened (open). In such a potential relationship, the depletion layer 13 spreads from the drain-side pn junction surface toward the source-side pn junction surface.

The memory element having the MONOS structure having such a configuration writes (stores) data by accumulating charges in the memory nitride film 142 of the gate insulating film 14c. Control of the threshold voltage (control of the charge accumulation amount) during the write and erase operations is performed by changing the voltage applied to the control gate 15, the n ⁺ diffusion layer 12a and the n ⁺ diffusion layer 12b.

  For example, when writing, by applying a positive voltage of about 10 V from the gate terminal 22 to the control gate 15, electrons near the surface of the p-type semiconductor substrate 11 pass through the tunnel oxide film 141 and are accumulated in the memory nitride film 142. The

At the time of erasing, a positive voltage of about 10 V is applied from the drain terminal 21 to the n ⁺ diffusion layer 12b, the control gate 15 is set to the ground potential via the gate terminal 22, and the source terminal 23 is electrically opened. The n ⁺ diffusion layer 12a is also electrically open.
By applying a positive potential to the drain terminal 21, as shown in FIG. 8, the depletion layer 13 extends into the channel, and the channel potential under the gate terminal 22 increases. Therefore, negative charges held in the memory nitride film 142 of the gate insulating film 14c are extracted to the depletion layer 13, and as a result, data is erased.

The prior art disclosed in Patent Document 1 provides an erasing method by applying a positive voltage, thereby eliminating the need for preparing a negative power source for erasing.
As a result, when the power supply for writing and erasing is provided inside the semiconductor device, the booster circuit can be easily designed, and when the power supply for writing and erasing is prepared outside the semiconductor device, therefore. The equipment is no longer needed.

Japanese Patent No. 3402014 (Section 2-3, Fig. 1)

  The prior art disclosed in Patent Document 1 has a problem that man-hours and time are required at the time of writing and erasing, which are the largest loads in mass production of nonvolatile semiconductor memory devices.

  The problem to be solved by the present invention is that, even though general-purpose data is almost fixed, the time required for writing is the same as when data is rewritten for unexpected reasons or for various reasons. It is a point that has to spend time.

  In a state where the memory element is just manufactured, the data storage state is a so-called indeterminate state. For this reason, in writing data, it is necessary to selectively write to a desired bit while erasing all bits at once and avoiding bits that maintain the erased state. That is, a major problem is that the writing time and the man-hour increase as the number of bits increases.

  In order to solve the above problems, the present invention adopts the following configuration.

The structure of the non-volatile semiconductor memory device of the present invention has a gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order on a semiconductor substrate, and a memory according to the voltage applied to the gate electrode. In a nonvolatile semiconductor memory device having a memory element that writes data by accumulating charges in a nitride film and erases data by releasing charges,
The top oxide film is composed of a thin first top oxide film and a thick second top oxide film,
A first memory element having a first top oxide film desired to be written and a second memory having a second top oxide film desired to be erased are formed on a semiconductor substrate so as to correspond to data. Having an element,
By applying the same negative voltage to the first memory element and the second memory element at the same time , it is possible to selectively write or erase each bit in one step .
Further, the structure of the nonvolatile semiconductor memory device of the present invention has a gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order on a semiconductor substrate, and according to the voltage applied to the gate electrode. In a nonvolatile semiconductor memory device having a memory element that writes data by discharging charges to the memory nitride film and erases data by accumulating charges,
The top oxide film includes a thin first top oxide film and a thick second top oxide film.
Consists of
A first memory element having a first top oxide film desired to be erased and a second top oxide film desired to be written is formed on the semiconductor substrate so as to correspond to data. Having an element,
By applying the same negative voltage to the first memory element and the second memory element at the same time, it is possible to selectively write or erase each bit in one step.

A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a first oxide film forming step for forming a tunnel oxide film on a conductor substrate, and a nitride film forming step for forming a memory nitride film on the tunnel oxide film. A second oxide film forming step of forming a dummy oxide film on the memory nitride film;
A removal step of leaving the desired part of the dummy oxide film and removing the other part to expose the memory nitride film;
The surface of the memory nitride film and the surface of the dummy oxide film are oxidized to form a first top oxide film with a thin oxide film thickness and a second top oxide film with a thick oxide film film on the memory nitride film. An oxide film forming step,
Forming a first memory element having a first top oxide film and a second memory element having a second top oxide film corresponding to data ;
Applying the same negative voltage to the first memory element and the second memory element at the same time, setting the first memory element in a write state and setting the second memory element in an erase state in one step;
It is characterized by having.
The method for manufacturing a nonvolatile semiconductor memory device according to the present invention also includes a first oxide film forming step for forming a tunnel oxide film on a conductor substrate, and a nitride film for forming a memory nitride film on the tunnel oxide film. A forming step; a second oxide film forming step of forming a dummy oxide film on the memory nitride film;
A removal step of leaving the desired part of the dummy oxide film and removing the other part to expose the memory nitride film;
The surface of the memory nitride film and the surface of the dummy oxide film are oxidized to form a first top oxide film with a thin oxide film thickness and a second top oxide film with a thick oxide film film on the memory nitride film. An oxide film forming step,
Forming a first memory element having a first top oxide film and a second memory element having a second top oxide film corresponding to data;
Applying the same negative voltage to the first memory element and the second memory element at the same time, bringing the first memory element into the erased state and the second memory element into the written state in one step;
It is characterized by having.

  The present invention applies the same voltage to all the bits of the memory element at once, so that the first memory element with the thin top oxide film and the top can be selectively written and erased for each bit in one step. The main feature is that the second memory element having a thick oxide film is mixed in one semiconductor device.

In the nonvolatile semiconductor memory device of the present invention, a first memory element having a thin top oxide film and a second memory element having a thick top oxide film are provided on a semiconductor substrate, and the entire memory including these memory elements is provided. By applying the same voltage to the bits all at once, writing and erasing can be selectively performed for each bit in one step.
Therefore, there is an advantage that time and man-hours can be reduced because the conventional voltage application (writing after erasing) is performed only once.
In addition, since the same voltage is applied to all the bits at once, there is an advantage that even if the number of bits increases, the writing time and the man-hour do not change.
The first memory element having a thin top oxide film and the second memory element having a thick top oxide film can perform information writing and erasing without any difference from a normal memory element in a single memory element. That is, in the nonvolatile semiconductor memory device of the present invention, the time for writing data to the memory element and the reduction of the man-hour are realized without losing the feature of the EEPROM that it can be rewritten.

[Description of structure: Fig. 1]
FIG. 1 is a simplified diagram showing the structure of the nonvolatile semiconductor memory device of the present invention. FIG. 1 shows a total of 2 bits, that is, 1 bit of a memory element for which a write state is desired with general-purpose data and 1 bit of a memory element for which an erase state is desired.
Bias conditions applied to each terminal of the memory element indicate conditions at the time of writing and erasing.

In FIG. 1, 10 is a MONOS type memory element, 11 is a p-type semiconductor substrate, 12a and 12c are n ⁺ diffusion layers as sources, 12b is an n ⁺ diffusion layer as a drain, 14a and 14b are gate insulating films, 15 Denotes a control gate, and 20 denotes a power source capable of generating both positive and negative voltages (hereinafter referred to as positive and negative power sources).

Here, the n ⁺ diffusion layers 12 a, 12 b and 12 c are formed in the surface layer portion of the p-type semiconductor substrate 11 at a predetermined interval.
n ⁺ on the semiconductor substrate 11 of the region sandwiched between the diffusion layer 12a and 12b is a gate insulating film 14a in the state to bridge the n ⁺ diffusion layer 12a and 12b. on the n ⁺ diffusion layer 12b and 12c and the region of the semiconductor substrate 11 sandwiched between form a gate insulating film 14b in a state of bridging the n ⁺ diffusion layer 12b and 12c.
A control gate 15 is provided on the gate insulating films 14a and 14b.

The gate insulating film 14a includes a tunnel oxide film 141 that is closest to the semiconductor substrate 11, a memory nitride film 142 that is an intermediate silicon nitride film, and a top oxide film 143a that is provided as the uppermost layer. Similarly, the gate insulating film 14b includes a tunnel oxide film 141, a memory nitride film 142, and a top oxide film 143b.
The first top oxide film with a thin top oxide film is defined as a top oxide film 143a, and the second top oxide film with a thick top oxide film is defined as a top oxide film 143b. The memory element having the top oxide film 143a is referred to as a first memory element, and the memory element having the top oxide film 143b is referred to as a second memory element.
The top oxide film 143b shown in FIG. 1 is described as being several times thicker than the top oxide film 143a. However, the top oxide film thickness of the first memory element and the second memory element is described. Can be freely selected in relation to the power supply voltage used and the peripheral circuit.

The positive / negative power source 20 is connected to the control gate 15. The p-type semiconductor substrate 11 and the n ⁺ diffusion layers 12a, 12b and 12c are set to the ground potential.

The basic structure of the nonvolatile semiconductor memory device of the present invention is no different from the conventional example when attention is paid to one bit of a specific memory element.
However, when all bits are compared, the first memory element having the thin top oxide film 143a as a constituent element and the second memory element having the thick top oxide film 143b as a constituent element are mixed in one semiconductor device. It is characterized by that.
By adopting such a configuration, by applying the same voltage to all bits at once, writing and erasing can be selectively performed for each bit in one step.

[Description of Manufacturing Method: FIGS. 1 to 6]
Next, a method for manufacturing a semiconductor device having a memory element according to the present invention will be described with reference to FIGS.

  2 to 6, 10, 11, 12a to 12c, 15, 141, 142, 143a and 143b are the same as those in FIG. Reference numerals 16a and 16b are photoresists, and 144 is a dummy oxide film.

First, as shown in FIG. 2, a tunnel oxide film 141 is formed on the surface of the p-type semiconductor substrate 11 by using a first oxide film forming step. In the first oxide film forming step, a known oxidation method is used. For example, it is formed by thermal oxidation in an atmosphere in which oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.
Next, the memory nitride film 142 is formed using a nitride film forming step. In this step, for example, it is formed by a CVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as a reaction gas.
Next, a dummy oxide film 144 is formed in an upper layer portion of the memory nitride film 142 by a second oxide film formation step. This step is formed, for example, by thermal oxidation in a steam atmosphere using an oxidation diffusion furnace.

Next, the removal process will be described. First, a photoresist 16a is formed on the dummy oxide film 144 using a known photolithography technique.
Here, the region where the photoresist 16a is formed is in the same range as the region where the top oxide film 143b shown in FIG. 1 is formed. That is, this is a region where the top oxide film is desired to be thickened.
Next, after the dummy oxide film 144 is dry-etched using the photoresist 16a as a mask, the photoresist 16a is removed by wet etching. By this step, the dummy oxide film 144 remains in a desired region on the memory nitride film 142 as shown in FIG.

Next, the third oxide film forming step will be described. The upper layer portion of the memory nitride film 142 is thermally oxidized including the region where the dummy oxide film 144 is formed. In this step, for example, it is formed by thermal oxidation in a steam atmosphere using an oxidation diffusion furnace. By this process, an oxide film is again formed on the memory nitride film 142, and is formed integrally with the dummy oxide film 144 that has already been formed.
As shown in FIG. 4, the region a where the dummy oxide film 144 is thin has the same value as the top oxide film 143a, which is the first top oxide film shown in FIG. 1, and the dummy oxide film 144 is thick. The region b has the same value as the top oxide film 143b which is the second top oxide film shown in FIG.

Next, a process for forming a gate insulating film will be described. This will be described with reference to FIG. A photoresist 16b is formed on the dummy oxide film 144 using a known photolithography technique.
Using the photoresist 16b formed on the dummy oxide film 144 as a mask, the dummy oxide film 144, the memory nitride film 142, and the tunnel oxide film 141 are sequentially dry etched.
By this dry etching, as shown in FIG. 5, regions of a thin gate insulating film and a thick gate insulating film of the dummy oxide film 144 can be formed. Later, the photoresist 16b is removed by wet etching.
Here, among the regions left after the dry etching of the dummy oxide film 144, a thin region is defined as a top oxide film 143a, and a thick region is defined as a top oxide film 143b.

A process of forming the gate electrode and the source / drain will be described. As shown in FIG. 6, a polysilicon film (not shown) for forming the control gate 15 is formed using the CVD method. In this step, for example, monosilane (SiH ₄ ) is used as a reaction gas.
Thereafter, a photoresist (not shown) is formed, dry-etched using this as a mask, and then removed by wet etching. Thereby, the control gate 15 can be formed on the gate insulating films 14a and 14b, and the gate electrode is completed.
Next, the basic element structure of the memory element is completed by forming three n ⁺ diffusion layers 12a, 12b and 12c to be a source and a drain by a known ion implantation method.

  Thereafter, using a known technique, an interlayer insulating film (not shown), various wirings, and the like are formed, and a semiconductor device having the first memory element and the second memory element of the present invention is completed.

[Description of voltage application conditions: FIGS. 1 and 7]
Hereinafter, voltage application conditions of a semiconductor device having a memory element of the present invention will be described with reference to FIGS.

  FIG. 7 is a diagram schematically showing changes in the threshold voltage Vt when the voltage Vp is applied to the control gate 15 of FIG.

In FIG. 7, the horizontal axis indicates the voltage Vp applied to the control gate 15 at the time of data writing and erasing. At the intersection with the vertical axis, Vp is 0 V, and the right side represents the minus direction.
The vertical axis represents the threshold voltage Vt when reading data. The upper side represents the plus direction (written state) and the lower side represents the minus direction (erased state) at the intersection with the horizontal axis.
Va represents the case of the first memory element having the thin top oxide film 143a shown in FIG. 1 as a constituent element, and Vb represents the case of the second memory element having the thick top oxide film 143b shown in FIG. 1 as a constituent element.

  As shown in FIG. 7, as the voltage Vp applied to the control gate 15 is gradually shifted from 0V in the minus direction (right side), the threshold voltage Vt also changes in the minus direction, and the erase state is entered.

Here, as the voltage Vp applied to the control gate 15 is further shifted in the negative direction (right side), the threshold voltage Vt approaches the horizontal axis (between the written state and the erased state), and finally. Changes in the positive direction and enters a writing state.
Here, the value of Vp (horizontal axis) at the point where the threshold voltage Vt switches from the erased state to the written state is Vpa for Va and Vpb for Vb.

  Although the negative voltage is applied to the control gate 15 as described above, the threshold voltage Vt is in the positive direction, that is, the negative charge is accumulated in the memory nitride film 142 of FIG. It ’s like that.

  That is, in FIG. 1, when the negative voltage applied to the control gate 15 increases, electrons in the control gate 15 pass through the top oxide films 143a and 143b and enter the memory nitride film 142. When the amount of electrons that have entered the memory nitride film 142 exceeds the amount of electrons that pass through the tunnel oxide film 141 and is extracted to the p-type semiconductor substrate 11, negative charge is accumulated in the memory nitride film 142. It is.

  In the above description, the threshold voltage Vt switches from the erased state to the written state, that is, the values of Vpa and Vpb depend on the thickness of the top oxide film 143a for Vpa and the thickness of the top oxide film 143b for Vpb. .

  Accordingly, in the case of the first memory element having the thin top oxide film 143a as a constituent element in FIG. 1, the voltage applied to the control gate 15 is set to a value between Vpa and Vpb shown in FIG. In the case of the second memory element having the thick top oxide film 143b as a constituent element, an erased state can be created.

  In manufacturing the semiconductor device having the memory element of the present invention, the top oxide film 143a shown in FIG. 1 is formed in the memory element which desires the write state, corresponding to the most frequently used general-purpose data, and the erase state is desired. A top oxide film 143b shown in FIG.

As described above, by selectively using the top oxide films 143a and 143b, writing and erasing can be performed for each bit selectively in one step only by applying the same voltage to all the bits at once.
Therefore, the conventional voltage application (writing after erasing) is performed only once, and the time and man-hours can be reduced.
Even if the number of bits increases, the writing time and man-hours do not increase.

  By the way, immediately before mounting a semiconductor device having a memory element on an electronic device, it may be necessary to add or rewrite data in order to correct manufacturing variations or suddenly change specifications. Also in the present invention, it is possible to freely add or rewrite data to a specific bit by using a known voltage application method.

When data is added or rewritten, writing is performed by applying a positive voltage to the control gate 15 shown in FIG. 1, and erasing is performed by applying a negative voltage.
There is no restriction on the positive voltage at that time. Regarding the negative voltage, a value between 0 V and Vpa shown in FIG. 7 may be used.

  As described above, according to the present invention, it is possible to reduce the time and man-hour for writing data to the memory element without losing the feature of the EEPROM that can be rewritten.

  The semiconductor device having the memory element of the present invention can shorten the manufacturing process that conventionally requires writing after erasure and two man-hours. Therefore, it can be applied to mass-produced semiconductor devices.

It is a simplified diagram showing the basic structure of the present invention. It is a simplified diagram explaining the manufacturing process of this invention. It is a simplified diagram explaining the manufacturing process of this invention. It is a simplified diagram explaining the manufacturing process of this invention. It is a simplified diagram explaining the manufacturing process of this invention. It is a simplified diagram explaining the manufacturing process of this invention. It is a figure which shows typically the relationship between the voltage Vp applied to the control gate of this invention, and the threshold voltage Vt. It is a simplified diagram illustrating a conventional memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 MONOS type memory element 11 p-type semiconductor substrate 12a n ⁺ diffusion layer 12b n ⁺ diffusion layer 12c n ⁺ diffusion layer 13 depletion layer 14a gate insulating film 14b gate insulating film 14c gate insulating film 15 control gate 16a photoresist 16b photoresist 20 Positive power source 21 Drain terminal 22 Gate terminal 23 Source terminal 141 Tunnel oxide film 142 Memory nitride film 143a Top oxide film 143b Top oxide film 143c Top oxide film 144 Dummy oxide film

Claims (4)

A gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order on a semiconductor substrate, and charges are stored in the memory nitride film according to the voltage applied to the gate electrode. In a nonvolatile semiconductor memory device having a memory element that performs writing and erasing data by releasing electric charge,
The top oxide film is composed of a thin first top oxide film and a thick second top oxide film,
A first memory element having the first top oxide film desired to be written and having a second top oxide film desired to be erased is formed on the semiconductor substrate so as to correspond to data . Two memory elements,
By applying the same negative voltage simultaneously to the first memory element and the second memory element, the write state or the erase state can be selectively set for each bit in one step. Semiconductor memory device. A gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order on a semiconductor substrate, and data is discharged by discharging charges to the memory nitride film in accordance with the voltage applied to the gate electrode. In a nonvolatile semiconductor memory device having a memory element that performs writing and erasing data by accumulating charges,
The top oxide film is composed of a thin first top oxide film and a thick second top oxide film,
A first memory element having the first top oxide film desired to be erased and a second top oxide film desired to be written is formed on the semiconductor substrate so as to correspond to data. Two memory elements,
The nonvolatile state, wherein the same negative voltage is simultaneously applied to the first memory element and the second memory element, so that the write state or the erase state can be selectively made bit by bit in one step. Semiconductor memory device. A first oxide film forming step of forming a tunnel oxide film on the semiconductor substrate; a nitride film forming step of forming a memory nitride film on the tunnel oxide film; and a dummy oxide film on the memory nitride film A second oxide film forming step of forming a film;
A removal step of leaving the desired part of the dummy oxide film and removing the other part to expose the memory nitride film;
The surface of the memory nitride film and the surface of the dummy oxide film are oxidized to form a first top oxide film with a thin oxide film thickness and a second top oxide film with a thick oxide film film on the memory nitride film. A third oxide film forming step,
Forming a first memory element having the first top oxide film and a second memory element having the second top oxide film corresponding to data ;
Applying the same negative voltage to the first memory element and the second memory element at the same time, setting the first memory element in a writing state and setting the second memory element in an erasing state in one step; When,
A method of manufacturing a nonvolatile semiconductor memory device, comprising: A first oxide film forming step of forming a tunnel oxide film on the semiconductor substrate; a nitride film forming step of forming a memory nitride film on the tunnel oxide film; and a dummy oxide film on the memory nitride film A second oxide film forming step of forming a film;
A removal step of leaving the desired part of the dummy oxide film and removing the other part to expose the memory nitride film;
The surface of the memory nitride film and the surface of the dummy oxide film are oxidized to form a first top oxide film with a thin oxide film thickness and a second top oxide film with a thick oxide film film on the memory nitride film. A third oxide film forming step,
Forming a first memory element having the first top oxide film and a second memory element having the second top oxide film corresponding to data;
Applying the same negative voltage to the first memory element and the second memory element at the same time, bringing the first memory element into an erasure state and making the second memory element into a writing state in one step; When,
A method of manufacturing a nonvolatile semiconductor memory device, comprising:

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