JP4435615B2 - Program, test pattern creation method and apparatus - Google Patents

Description

The present invention relates to a program, a storage medium, a pattern creation method, a program, a storage medium, and an apparatus for automatically generating a test pattern used for a dynamic function test of an integrated circuit, and more particularly to an operation for detecting a delay fault by applying a system clock. The present invention relates to a program, a storage medium, a pattern creation method, a program, a storage medium, and a device that improve the failure detection rate of a functional function test and reduce processing time.

  In recent years, with the increase in circuit speed and miniaturization, the influence of delay faults mixed in due to variations in LSI manufacturing processes has increased, and these delay faults are detected only by the conventional low-speed static function test (SFT). Therefore, sufficient test quality cannot be guaranteed for the operation in the state where the LSI is actually incorporated in the system.

  For this reason, the system clock is supplied as a feed clock, changed from the send FF to the net and propagated, and similarly received by the system clock as the clock, and the change is captured by the receive FF, and received from the send FF. A dynamic function test (DFT) that detects a delay fault in a path between FFs has been proposed.

Such an automatic test pattern generation method (ATPG: Automatic Test Pattern Generation) for automatically generating a test pattern for a conventional dynamic function test is based on detection of a transition fault assumed on the net or a specific feed FF. The transfer operation of the route between the receiving FF and the receiving FF is targeted. In this case, the method for activating the fault propagation path is based on the restriction to increase the resolution for the detection of the target transition fault or the measurement of the specific path, that is, the restriction to suppress the occurrence of the hazard. In many cases, a method of activating only a propagation path of a transition fault to be detected or a specific path for performing a transfer operation is used.
JP 2002-131399 A JP 2001-042012 A JP-A-8-101258

  However, in such an automatic test pattern generation using the conventional single path activation method, the input clock other than the activated path is input to all the multi-input gates existing on the activated path. It is necessary to align the state with the non-control value before and after, and when an inevitable change propagates to the gate input trying to set the non-control value both before and after the feed clock due to re-convergence of the path to be activated, etc. The test will always fail.

  For this reason, it becomes difficult to obtain a sufficient detection rate for a specific path for performing a transition fault or transfer operation targeted for automatic test pattern generation.

  In automatic test pattern generation using the single path activation method, there is no change before and after the feed clock at the gate input other than the activated path, so the transition fault or transfer operation detected by this test pattern is not detected. The specific path to be performed is limited to only the specific path that performs the transition fault or transfer operation on the activated path, and the number of generated tests increases when trying to obtain the highest possible fault detection rate There is a problem to do.

  Also, considering the operation of the LSI incorporated in the actual system, the situation where only a single path is activated in the transfer path from the sending FF to the receiving FF is considered a peculiar case. There is a problem that the operation of the test pattern created by the method is likely to deviate from the operation of the LSI incorporated in the actual system.

The present invention relates to a program, a storage medium, a pattern generation method, and an apparatus for improving the detection rate of delay faults in a dynamic function test that applies a system clock, reducing the number of generated tests, and reducing the processing time. The purpose is to provide.

  FIG. 1 is a diagram illustrating the principle of the present invention. The present invention includes a circuit data reading unit 12 for reading circuit data, a path cut countermeasure unit 14 for selecting a path cut point from a target circuit and fixing a state, and automatic test pattern generation. A pattern creation method including an automatic test pattern generation step for generating test data for detecting a delay fault in a circuit for which a path cut has been completed by a section (ATPG section) 16 is targeted.

(Acceptance of don't care X as a propagation path activation state)
In the present invention as such a pattern creation method, as an automatic test pattern generation step,
A narrowing step for specifying, as a processing target circuit, a region including the feed FF group corresponding to the failure assumption point, the receiving FF, and the preparation FF group one stage before the feed FF group by the narrowing processing unit,
A failure excitation step in which a failure excitation unit assigns a failure excitation state of a receiving time and a receiving time in an inverted relationship from 0 to 1 for a rising failure and 1 to 0 for a falling failure to a failure assumption point;
A path activation step in which a failure propagation state setting unit assigns a state of a sending time and a receiving time to activate a propagation path of a failure to the remaining preparation FFs and sending FFs, and
The automatic test pattern generation control unit sends the system clock to the sending FF as a sending clock, changes the sending FF to the net and propagates it, receives the system clock to the FF as the receiving clock, and catches the net change To propagate a state for detecting a delay fault to the path between the sending FF and the receiving FF, and to generate a test pattern upon successful propagation,
In addition,
The path activation step allows the assignment of don't care X as a state that activates the propagation path of the failure,
The fault propagation step is characterized by activating a fault propagation path by transitioning from a don't care X to a non-control value after a net change. Here, the don't care X is a logical value that constitutes a test pattern that does not affect the failure detection rate even if it is replaced with the opposite value.

  As described above, according to the present invention, as a condition for activating a path through which a delay fault is propagated, a non-control value having no change, for example, an AND gate assigned a non-control value 1 is used. When an unavoidable change is propagated to a net that gives an activation condition by assigning a state to perform fault excitation by allowing an activation condition that becomes a non-control value at the receiving time after the change from the don't care X at the sending time Even so, the test pattern can be generated.

  Further, even when the failure propagation path itself converges and an inevitable change propagates to a plurality of paths, a test pattern can be generated. In addition, by accepting a change in the non-control value from the don't care X in the activation condition, the state assignments of 0 and 1 at the sending time are combined into X, the number of state assignments is reduced, and the contradiction is caused by the reduction of the assigned state. The possibility of occurring is reduced.

(Fault excitation by compaction)
In the pattern creation method of the present invention, after the failure propagation step is completed,
A compaction failure excitation step that receives the don't care X of the path activation step and changes the state to the opposite value of the time state and assigns the failure excitation state;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A compaction fault propagation step for propagating a state for detecting a delay fault to the path between FFs and generating a test pattern with successful propagation;
It is provided with.

  After failure propagation is successfully completed at the first failure propagation step performed in this way, the first failure propagation is performed by failure excitation in which the don't care X is changed to a state opposite to the time state and the failure excitation state is assigned. The path given the activation condition can be used as a fault propagation path, and this process is repeated for all selectable remaining undetected hypothetical faults, improving the efficiency of pattern compaction and reducing the number of generated test patterns. .

(Determination of failure excitation impossible)
The failure excitation step implies an uncontrol value u indicating that failure excitation is not possible with respect to a failure value with respect to an output at a reception time of the feeding FF when clock-off is assigned to the feeding FF at the feeding time; It is characterized in that the assignment of the uncontrol value u itself is determined to be impossible for fault excitation and is excluded from the target of the delay fault.

  Thus, since the uncontrol value u is implied in the failure value at the failure assumption point of the feed clock off, the failure excitation assignment itself is determined to be contradictory (cannot be excited), and wasteful targets are reduced. .

(Determination of undetectable failure)
When failure propagation fails in the failure propagation step, among the failures assumed in the net from the failure assumption failure net to the fan-out free area branch input, the failure relationship is equal to the failure failure and the failure value Are extracted and excluded as undetectable faults.

  When automatic test pattern generation for a certain failure fails in this way, a failure that satisfies the same inversion relationship as the failed failure and that satisfies the same failure value as the gate control value is determined as an undetectable failure and excluded from the target. Accelerate automatic test pattern generation.

(Pass cut measures)
In the pass cut step, at the gate input that drives the pass cut point, the gate control value is given at the sending time and receiving time to fix the state, or the gate is not controlled at all the gate inputs at the sending time and receiving time By assigning a value, the state of the path cut point is assigned and fixed as an invariant state 0 to 0 or 1 to 1.

  Here, fixing the state by assigning the gate control value is the same as the path cut countermeasure for a normal loop path if the path to be cut is a loop configuration, but if the path is not a loop configuration, the path cut countermeasure is applied to the normal loop path. Different paths to be cut can be controlled. In addition to this, in the delay fault test, the present invention pays attention to the fact that the path cut point should be the same non-control value between the sending time and the receiving time. A non-control value of the gate is assigned to the to fix the state of the pass cut point. As a result, in addition to the normal loop circuit, an nτ path state that does not require transfer completion in one cycle (1τ) existing in the transfer between FFs is fixed at the sending time and the receiving time, and the path is cut.

  In the path cut step, for the invariant states 0 to 0 or 1 to 1 to be assigned to the path cut points, the number of detected faults is measured by the automatic test pattern generation step, and an invariant state for selecting an invariant state with a small number of fault undetectable numbers is selected. A selection step. By selecting an invariant state that minimizes the number of faults that cannot be detected in this way, the fault detection rate is not lowered.

  Further, in the pass cut step, when there is a change in the pin input position of the control value at the sending time and the receiving time at a plurality of input pins of the driver side gate with respect to the pass cutting point, at least the control value is given at the receiving time. A hazard free step of generating a hazard free invariant state for the path cut point by adding and assigning a control value to a single input pin at the sending time is provided.

(Narrowing trace stop method)
The narrowing step marks the narrowing range as a pre-processing of the failure excitation step by two-step backtrace from the failure assumption point to the sending FF group via the receiving FF and from the sending FF group to the preparation FF group. If neither the net sending time nor the receiving time stay is the don't care X, the back trace after this net is stopped.

  When narrowing is performed in the dynamic function test of the present invention, in order to generate a change in the feed clock, in addition to performing backward tracing in the range from the receiving FF to the sending FF, preparation from the sending FF to the preceding stage is performed. It is necessary to perform backward tracing up to FF. In this case, if the fanout spreads between the FFs are uniformly equal, the trace range from the feed FF to the preparation FF on average is wider than the trace range from the receive FF to the feed FF. Therefore, it takes time to perform the trace processing for performing narrow wing.

  Therefore, if the state of the sending time and the receiving time of the net is not the don't care X in the backtrace, the backtrace after the net is stopped and the mark processing for implication propagation is reduced.

(Pair failure target)
If the automatic test pattern generation step fails to detect a delay fault for either the rising delay fault or the falling delay fault of the same net, the narrowing range mark marked in the backtrace of the narrowing step The test pattern generation is executed with the other delay fault that has not been detected as a target by diverting it without being removed. In this way, the processing amount is halved as a single narrowing process for the pair failure which is two failures.

(program)
The present invention provides a program for executing an integrated circuit test. That is, the program of the present invention is stored in a computer.
A reading step for reading circuit data;
A path cut step for selecting a path cut point from the target circuit and fixing the state by the path cut countermeasure unit,
An automatic test pattern generation step for generating test data for detecting a delay fault in a circuit for which a path cut has been completed;
The automatic test pattern generation step includes:
A narrowing step for identifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit;
A failure excitation step for assigning to the failure assumption point a failure excitation state of 0 to 1 for a rising failure and 1 to 0 for a falling failure;
A path activation step for allocating a state of a sending time and a receiving time to activate the propagation path of the failure to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A fault propagation step for propagating a state for detecting a delay fault to the path between the FFs and generating a test pattern with successful propagation;
In addition,
The path activation step allows the assignment of don't care X as a state that activates the propagation path of the failure,
The fault propagation step is characterized by activating a fault propagation path by transitioning from a don't care X to a non-control value after a net change.

(Storage medium)
The present invention provides a computer-readable storage medium storing a program for integrated circuit testing. That is, the storage medium of the present invention is stored in a computer.
A reading step for reading circuit data;
A path cut step for selecting a path cut point from the target circuit and fixing the state by the path cut countermeasure unit,
An automatic test pattern generation step for generating test data for detecting a delay fault in a circuit for which a path cut has been completed;
And execute
The automatic test pattern generation step
A narrowing step for identifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit;
A failure excitation step for assigning to the failure assumption point a failure excitation state of 0 to 1 for a rising failure and 1 to 0 for a falling failure;
A path activation step for assigning a state of a sending time and a receiving time to activate the propagation path of the failure to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is received and supplied to the FF as a receiving clock to catch the net change, thereby receiving the receiving FF from the sending FF. A fault propagation step for propagating a state for detecting a delay fault to the path between and generating a test pattern with successful propagation;
In addition,
The path activation step allows the assignment of don't care X as a state that activates the propagation path of the failure,
The fault propagation step is characterized in that a program for activating the fault propagation path by changing from the don't care X to the non-control value after the change of the net is characterized.

(apparatus)
The present invention provides an integrated circuit test apparatus. That is, the integrated circuit test apparatus of the present invention targets a circuit data reading unit that reads circuit data, a path cut countermeasure unit that selects a path cut point from a target circuit and fixes a state, and a circuit that has been subjected to a path cut. And an automatic test pattern processing unit that generates test data for detecting delay faults in the integrated circuit test apparatus, wherein the automatic test pattern generation unit includes:
A narrowing step for identifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit, and a failure assumption point from 0 at a rising failure. 1. A failure excitation unit that assigns a failure excitation state between a sending time and a receiving time that have an inversion relationship of 1 to 0 due to a falling failure; a sending time that activates a propagation path of a failure to the remaining preparation FFs and sending FFs; A failure propagation state setting unit that assigns the state of the reception time, a system clock is sent to the FF as a supply clock, changed from the transmission FF to the net and propagated, and a system clock is received and supplied to the FF as a reception clock By capturing the net change, the state for detecting the delay fault is propagated to the path between the sending FF and the receiving FF, and the propagation is successful. An automatic test pattern generation control unit that generates a fault pattern, and the failure propagation state setting unit permits allocation of don't care X as a state for activating the failure propagation path. Then, after the change of the net, the transition from the don't care X to the non-control value is performed to activate the failure propagation path.

The details of the storage medium and the apparatus are basically the same as those of the pattern creation method and program.

  According to the present invention, as a state for activating a failure propagation path for a dynamic function test, the allocation of don't care X at the sending time is allowed, and after the change of the net, the transition from the don't care X to the non-control value is performed. Since the failure propagation path is activated, automatic test pattern generation processing can be performed even when inevitable changes propagate to the net to which activation conditions are assigned by assigning the state that performs failure excitation. The rate can be greatly improved.

  Also, by accepting the change in the non-control value of the receiving time from the don't care X of the sending time in the activation condition, the number of state allocations at the sending time decreases, and the contradiction may occur due to the decrease of the allocated states As a result, the number of test patterns to be generated can be reduced and the processing speed can be increased.

  Also, by implying uncontrol u to the failure value at the receiving time of the sending FF to which the clock-off is assigned, it is determined that the failure excitation assignment itself is impossible in failure observation, thereby reducing useless targets. As a result, the automatic test pattern generation can be speeded up.

  In addition, when automatic test pattern generation for a certain failure fails, a failure satisfying the same inversion relationship as the failed failure and the condition satisfying the same failure value as the gate control value is determined as an undetectable failure and excluded from the target. Thus, automatic test pattern generation can be accelerated.

  As the invariant state assigned to the pass cut point of the dynamic function test, either 0 to 0 or 1 to 1 is set as the state from the sending time to the receiving time. By selecting the state, the path cut of the nτ path that does not complete the transfer in one cycle other than the loop circuit is surely performed, and the failure detection rate is not lowered due to the setting of the invariant state.

  In addition, when the gate control value setting for multiple gates of the gate input driving the pass cut point is changed to the control value of another input gate at the receiving time, the control value is further controlled at the feed time for one input pin. By assigning and adding, it is possible to generate a hazard-free invariant state in which no hazard propagates to the path cut point.

  Also, in narrowing that is performed as pre-processing for failure excitation, the back trace is stopped on the net that is not a don't care X by back trace, thereby reducing the mark processing for narrowing and, consequently, speeding up automatic test pattern generation. You can plan.

In addition, for the pair failure of the rising delay failure and the falling delay failure, if the automatic test pattern generation of one of the delay failures fails, the undetected remaining in the pair failure is not performed without unmarking the narrowing range. By diverting the narrowing range to this delay fault, the processing amount can be halved so that only one narrowing process is required for the pair fault.

<Contents>
1. 1. Dynamic function test and automatic test pattern generation 2. Don't care X tolerance 3. Determination of failure excitation impossible 4. Determination of undetectable failure Pass cut measures Narrowing process

(1. Dynamic function test and automatic test pattern generation)
FIG. 2 is a block diagram of a functional configuration of the integrated circuit test apparatus according to the present invention. 2, the integrated circuit test apparatus of the present invention includes an overall control unit 10, a circuit data reading unit 12, an automatic test pattern generation unit (hereinafter referred to as “ATPG unit”) 16, a path cut countermeasure unit 14, a failure simulation unit 18, and The circuit data writing unit 20 is configured.

  The circuit data reading unit 12 reads circuit data from a net list created by automatic circuit setting in response to a reading request from the overall control unit 10. The path cut countermeasure unit 14 receives a path cut countermeasure request from the overall control unit 10, selects a path cut point from the target circuit read by the data reading unit 12, and fixes the state.

  The ATPG unit 16 generates test data for defining a delay fault for a circuit that has undergone path cut. The test pattern created by the ATPG unit is given to the failure simulation unit 18, and based on the simulation execution request from the overall control unit 10, a simulation using the test pattern is executed to obtain an execution time and a diagnosis rate. The circuit data writing unit 20 writes the processed circuit data according to the test pattern and ends the processing.

  The ATPG unit 16 automatically generates a dynamic functional test (DFT) test pattern. In the dynamic function test, a system clock is supplied as a sending clock and propagated from the sending FF to the net, and similarly, the system clock is received as a clock and supplied to the receiving FF. Stop delay faults in the path between.

  The integrated circuit test apparatus of the present invention shown in FIG. 2 is realized by, for example, hardware resources of a computer as shown in FIG. In the computer shown in FIG. 3, a RAM 301, a hard disk controller (software) 304, a floppy disk driver (software) 310, a CD-ROM driver (software) 314, a mouse controller 318, a keyboard controller 322, and a display controller 326 are connected to the bus 301 of the CPU 300. The communication board 330 is connected.

  The hard disk controller 304 is connected to the hard disk drive 306 and loaded with a program for executing the integrated circuit test processing of the present invention. When the computer is started, a necessary program is called from the hard disk drive 306 and expanded on the RAM 302. To execute.

  A floppy disk drive (hardware) 312 is connected to the floppy disk driver 310, and reading / writing with respect to the floppy disk (R) 312 can be performed. A CD drive (hardware) 316 is connected to the CD-ROM driver 314, and data and programs stored in the CD can be read.

  The mouse controller 318 transmits an input operation of the mouse 320 to the CPU 300. The keyboard controller 322 transmits the input operation of the keyboard 324 to the CPU 300. The display controller 326 performs display on the display unit 328. The communication board 330 uses a communication line 332 including radio, and communicates with other computers via a network such as the Internet.

FIG. 4 is a flowchart showing an overall processing procedure in the integrated circuit test apparatus of FIG. The overall processing procedure is as follows.

Step S1: Read circuit data from the net list.
Step S2: Perform a path cut.
Step S3: Test data is generated by automatic test pattern generation processing.
Step S4: A failure simulation is executed with the generated test data.
Step S5: The execution result is analyzed, and if the end condition is satisfied, the process proceeds to Step S6, and if not, the process returns to Step S3.
Step S6: The circuit data is written and the process is terminated.

  FIG. 5 is a block diagram of the ATPG unit 16 in FIG. The ATPG unit 16 includes an ATPG overall control unit 21, a 1st / 2nd failure selection unit 22, and an ATPG core unit 24.

FIG. 6 is a flowchart of automatic test pattern generation processing by the ATPG unit 16 of FIG. 5, and processing is performed according to the following procedure.

Step S1: An undetected failure is arbitrarily selected as a 1st failure from the failure set.
Step S2: For the 1st failure selected in Step S1, a test for detecting the 1st failure is generated by the ATPG core unit.
Step S3: If the test generation to the 1st failure is successful by the ATPG core part of Step S2, the process proceeds to pattern compaction after Step S4, and if it fails, the test failure is returned to the return value.
Step S4: In the current net state (the net state for detecting the 1st fault or for detecting the 2nd fault selected before that), the fault that is not detected from the fault set is arbitrarily selected as the 2nd fault. select.
Step S5: A test for detecting a 2nd failure is generated by the ATPG core unit for the 2nd failure selected in Step S4.
Step S6: If there is an undetectable fault that can be selected in the fault set, the process returns to step S4, and if not, the test generation is returned to the return value.

  FIG. 7 is a block diagram of the ATPG core unit 24 provided in the ATPG unit 16 of FIG. The ATPG core unit 24 includes an ATPG core overall control unit 26, a narrowing mark processing unit 28, a failure excitation unit 30, an implication operation unit 32, a condition solution state setting unit 34, and a failure propagation state setting unit 36.

  The narrowing processing unit 28 performs marking to identify a region including the feed FF portion corresponding to the failure excitation unit 30, the receiving FF, and the preparatory feed FF portion one step before the feed FF as a processing target circuit. This narrowing process is performed based on a narrowing range setting request from the ATPG core overall control unit 26, and the marked narrowing range is output to the implication operation unit 32.

  When the automatic test pattern generation for a certain fault assumption point is successful, the ATPG core overall control unit 26 outputs a narrowing range release request, and in response to this, the narrowing mark processing unit 28 receives the processed narrowing range. Release the mark.

  In response to a failure excitation request from the ATPG core overall control unit 26, the failure excitation unit 30 rises to a failure assumption point that is a processing target, a normal value is 0 to 1 and a failure value is 0 to 0, a falling failure. Then, a failure excitation state is assigned at a sending time and a receiving time when the normal value is 1 to 0 and the failure value is 1 to 01.

  The failure propagation state setting unit 36 assigns a state of sending time and receiving time for accelerating the failure propagation path to the preparation FF and the sending FF. The implication operation unit 32 receives an implication operation request from the ATPG core overall control unit 26, and determines and notifies the implication success failure whether or not the state of the sending time and the reception time allocated for fault propagation matches the implication. .

  The condition solution state setting unit 34 notifies the presence / absence of the failure propagation state, and sets the condition solution state upon receiving the notification of the presence / absence of the condition solution state from the ATPG core overall control unit 26 corresponding thereto.

  With the functions of the implication operation unit 32 and the condition solving state setting unit 34, the system clock is sent to the FF as a send clock, and the net is changed from the feed FF to the net and propagated, and the system clock is received as the received clock at the FF. Automatic test pattern generation control processing is performed in which a state for detecting a delay fault is propagated to the path between the sending FF and the receiving FF by detecting the net change by supplying and generating a test pattern upon successful propagation become.

  In the present invention, the ATPG core unit 24 is characterized in that the failure propagation state setting unit 36 activates the failure propagation path and allows the don't care X to be allocated. As a result, the fault propagation process according to the present invention can activate the fault propagation path by controlling the don't care X in the activation state to a non-control value after the change of the net by the feed clock. The route is allowed to change in the state at the sending time and the receiving time.

FIG. 8 is a flowchart showing a processing procedure by the ATPG core unit 24 of FIG. 7, and is as follows.

Step S1: Mark a net connection related to a failure given to the ATPG core as a narrowing range.
Step S2: It is determined whether or not the given fault can be excited in the current net state. If excitation is possible, the process proceeds to Step S3. If not possible, the test failure is returned to the return value, and the process proceeds to Step S12.
Step S3: An initial net state for fault excitation is set as an implication start state.
Step S4: An implication operation is performed based on the given implication start state.
Step S5: If a contradiction occurs in the implication operation in step S4, the process proceeds to step S11, and if not, the process proceeds to step S6.
Step S6: If an unresolved gate condition exists in the implication operation of Step S5, the process proceeds to Step S7, and if not, the process proceeds to Step S8.
Step S7: A state for resolving an unresolved gate is set as an implication start state, and the process returns to step S4.
Step S8: If it can be observed that the failure has reached the observation point, the test success is returned to the return value, and the process proceeds to step S12. If the observation is impossible, the process proceeds to step S9.
Step S9: If there is a gate that has reached a fault that can still propagate, the process proceeds to step S10, and if not, the process proceeds to step S11.
Step S10: The fault propagation state which is a gate condition for propagating the fault is set as an implication start state, and the process returns to step S4.
Step S11: Return the implication operation and if the next implication start state can be selected (backtracking), the process returns to Step S7 and Step S10 next to Step S6 and Step S9, respectively, after moving the process to Step S11. If backtracking is not possible, a test failure is returned to the return value, and the process proceeds to step S12.
Step S12: Unmark the narrowing range marked in step S1, and if there is a return value of the test success, imply the net state implied in step S4 again. Implications.

On the premise of the automatic pattern generation processing of the present invention based on such a dynamic function test, the following is the feature of the present invention: the acceptance of don't care X as an activation state, determination of failure excitation impossible, determination of undetectable location, path Each of the cutting measures and the narrowing process will be described in detail below.

(2. Acceptance of Don't Care X)
In the dynamic function test targeted by the automatic test pattern generation processing according to the present invention, a system clock is supplied as a feed clock, a change is made from the feed FF to the net, and the change is received by the feed clock and captured by the FF. Specifies the transfer between the sending FF and receiving FF.

  FIG. 9 is a schematic explanatory diagram of a dynamic function test that allows don't care X as an activation condition. In FIG. 9, in the dynamic function test, a feed clock SCK is supplied as a system clock to the sending FFs 48 and 50 to change the net where the NAND gate 52 exists, and a receiving clock RCK is supplied to the receiving FF 54 to change the net. For example, the failure state of the failure assumption point 56 selected for one input of the NAND gate 52 is propagated and tested. The participant who is the target of automatic test pattern generation at this time is a delay fault that works to delay changes on the net.

  Also, in the dynamic function test, the set state values of the feed FFs 48 and 50 and the preparation FFs 40 and 42 one stage before giving the activation condition change by the application of the feed clock SCK. Trace the area up to the preparation FF 40 to determine the state.

  As an automatic test pattern generation for performing such a dynamic function test, the failure state at the failure assumption point 56 on the sending FF 48 side of the NAND gate 52 is propagated and observed by the receiving FF 54, so that a failure occurs on the sending FF 50 side of the gate 52. An activation state for activating the fault propagation 58 at the assumption point 56 is set, and in the present invention, the don't care X is permitted as the state of the feed clock in the activation state.

  Here, a delay fault in the dynamic function test of the present invention will be described. FIG. 10 is an explanatory diagram of the failure excitation state of the rising failure (also referred to as 0 delay failure) among the delay failures in the dynamic function test of the present invention. FIG. 10A shows an AND gate 60 as an example, and when a failure assumption point 62 is selected as the output net, the states at normal time and delay failure at the failure assumption point 62 are shown in FIGS. 10B and 10C. become that way.

  10B, the state of the failure assumption point 62 is 0 at the sending time t1, and the state is 1 at the receiving time t2. On the other hand, in the delay fault of FIG. 10C, the state 0 at the sending time t1 does not become 1 at the receiving time t2, but remains in the state 0, which causes a delay fault.

  The fault excitation state for the dynamic function test of the fault assumption point 62 can be expressed as shown in FIG. That is, the normal value and failure value at the sending time are displayed as (0/0) on the numerator side, and the normal value and failure value at the receiving time are displayed as (1/0) on the denominator side.

  From this notation, the sending time state is normally 0 and the receiving time state is 1 and has risen normally, while the sending time state is 0 and the receiving time state is delayed. It turns out that it is 0 as before. Such a failure excitation state of the rising failure in FIG. 10 is similarly displayed for the failure assumption point 56 in FIG.

  FIG. 11 is an explanatory diagram of a failure excitation state of a falling failure (also referred to as 1 delay failure) in the dynamic function test of the present invention. FIG. 11A shows a case where the failure assumption point 62 of the output net of the AND gate 60 is selected. The states at the normal time and the abnormal time at the time of sending and receiving are shown in FIGS. )become that way.

  In the normal state of FIG. 11B, the state is 1 at the sending time t1, and the state is 0 at the receiving time t2. On the other hand, in the case of the delay failure in FIG. 11C, the state is state 1 at the sending time t1, the state 1 is changed to the previous state due to the delay failure at the receiving time t2, and the state is 0 thereafter.

  The failure excitation state of the failure assumption point 62 in this falling failure is expressed as shown in FIG. This notation is the same as in the case of FIG. 10 (D). For normal values, the sending time state is 1 and the receiving time state is 0, which causes a falling change. Thus, the state becomes 1 of the receiving time, and a delay failure occurs without causing a fall.

  FIG. 12 is an explanatory diagram of activation states assigned to activate the fault propagation path according to the present invention. FIGS. 12A and 12B are non-controlling values of the gate that are fixedly set in the conventional static function test (SFT) without having the concept of the sending time and the receiving time. (D) and the activation state in the same dynamic function test as in FIG. 11 (D).

  That is, FIG. 12A represents the non-control value 0 of the OR gate as an activation state of the dynamic function test, and the normal value and the failure value are in the state 0 at the sending time and the receiving time. FIG. 12B shows the activation state of the non-control value 1 of the AND gate, and the normal value and the failure value are all in the state 1 of the sending time and the receiving time.

  FIGS. 12C and 12D show activation states by don't care X newly permitted according to the present invention. FIG. 12C shows an activation state of the OR gate. The normal value and the failure value at the sending time are the don't care X, and the normal value and the failure value at the reception time that require activation are both in the state 0. It has become.

  FIG. 12D shows the AND gate activation state, in which both the normal value and failure value state of the sending time are don't care X, and both the normal value and failure value of the receiving time are non-control values. It is 1.

  12 (E) and 12 (F) are states in which the don't care X is set to state 1 or 0 in the activation state of FIGS. 12 (C) and 12 (D) in which the state of the sending time is set to don't care X. As is clear from FIGS. 12E and 12F, the activation state in the dynamic function test of the present invention allows a change in state between the sending time and the receiving time.

  The activation state of FIG. 12D is set as the activation state at the input of the NAND gate 52 on the side of the feed FF 50 in order to propagate the failure excitation state of the failure assumption point 56 by the failure propagation unit 58 in FIG. Yes.

  FIG. 13 is an explanatory diagram of failure propagation by the activation state of the don't care X of the present invention. FIG. 13A shows a failure propagation state when the non-control value of the gate is fixedly set as a conventional activation condition for the AND gates 64 and 66.

  That is, when the failure state is propagated for the AND gates 64 and 66 as indicated by the failure propagation path 68, the non-control value state 1 is fixedly set to the input pin on the opposite side of the AND gates 64 and 66, and the failure propagation is performed. The path 68 is activated.

  On the other hand, in the present invention, as shown in FIG. 13B, the don't care X at the sending time is allowed as the activation state, and the failure propagation path 68 is activated with the non-control value 1 at the receiving time. .

By setting the activation state that allows the don't care X at the sending time, it is possible to generate a test pattern that cannot be realized by setting the activation state fixed to the conventional gate control value as shown in FIG. FIG. 14A shows a state where a failure excitation state of a rising failure is assigned to the failure assumption point 70 and the failure is propagated to the gates 76 and 78 via appropriate logic 72 and 74.

  When the activation state of the conventional single path by such path activation, i.e., all the states of the appropriate logic 74 side are fixed to the non-control value, the gate 78 for setting the non-control value before and after the feed clock. If an inevitable change propagates to the input pin, automatic test pattern generation will fail.

  However, in the present invention, even if an inevitable change before and after the feed clock is propagated to the gate 78 by the appropriate logic 74, the activation state of the gate 78 is the don't care for the normal value and the fault value for the feed time. Automatic test pattern generation is possible by assigning the state of X, and automatic test pattern generation that has failed in the activation state fixed to the conventional non-control value can be succeeded in the present invention. The failure detection rate can be improved.

  FIG. 14B shows a case where the failure propagation path itself converges by the appropriate logic 82 of the net following the failure assumption point 80, and an unavoidable change is propagated to a plurality of paths composed of the gates 84 and 86.

  In this case, since the activation state of the gate 88 is inevitably changed before and after the sending clock, the conventional automatic test pattern generation fixed to the non-control value has failed. Even in the case where an unknown path propagates to the path for setting the activation state due to the convergence of the fault propagation path itself, in the present invention, the normal value of the sending time and the fault value of the don't care X Since this is allowed, automatic test generation by failure propagation in FIG. 14B will also succeed, and the failure detection rate can be improved.

  FIG. 15 is an explanatory diagram of a process in which the failure propagation path when the activation condition due to the change from the don't care X to the non-control value 1 according to the present invention is recognized and the path given the activation condition after the successful test is the failure propagation path. It is.

  FIG. 15A shows a state in automatic test pattern generation for a dynamic function test of a net in which two AND gates 96 and 98 are provided between the sending FFs 90, 92 and 94 and the receiving FF 100.

  In this case, the failure assumption point 101 is selected as the output of the AND gate 96, the failure excitation state 102 of the rising failure is set here, and the test is performed by state assignment and implication operation for receiving the failure excitation state 102 and propagating it to the FF 100. Represents a successful state.

  As is clear from the allocation state of the failure state and the activation state when the automatic test pattern generation in FIG. 15A is successful, the state of the don't care X is permitted at the sending time for the activation state. With respect to the don't care X, it is necessary to assign the activation state in the processing equivalent to the conventional static function test for each of the state 1 and the state 0, but in the present invention, by using the state of the don't care X As a result, the number of allocation states is reduced, and the occurrence of contradictions due to the reduction of allocation states is reduced. As a result, the failure detection rate can be improved.

  Further, as shown in FIG. 15A, if the failure propagation in the failure excitation state 102 for the failure assumption point 101 is successful and the test pattern is generated, the activation is performed to propagate the failure excitation state 102 in the failure assumption point 101. By changing the don't care X of the sending time in the activation state 104 of the net 109 for performing the activation to the state 0, as shown in FIG. Pattern generation processing can be executed.

  Here, the automatic test pattern generation in FIG. 15A is performed by performing the 1st failure selection in steps S1 and S2 of the ATPG process in FIG. 6 and the ATPG core unit process, and when ATPG success is determined in step S3, FIG. Steps S4 and S5, which are ATPG core processing by selecting the 2nd fault in the pattern compaction, which is the processing of).

  The processing procedure of test pattern generation by 2nd fault selection using the path 105 given the activation condition in the first fault selection of FIG. 15B as the fault propagation path is as follows.

(Procedure 1: Removal of the effects of the 1st failure)
The influence of the failure point existing in the paths of the nets 105 and 107 in FIG. 15A is removed, and the state of normal value = failure value is obtained. Note that the state of the net 107 in FIG. 15B shows the state after the implication operation in step 3 to be described later, so that the state of the normal value and the failure value at the receiving time are different. The state is adjusted to normal value = failure value by procedure 1.

(Procedure 2: 2nd fault excitation)
In the net 109 of FIG. 15B, a state of “0/0” is assigned to the sending time state “X / X” of the state 104 of FIG. By assigning the fault excitation state 106 having a change of “0 → 1”, a rising delay fault (0 delay fault) is excited at the fault assumption point 111.

(Procedure 3: Implication operation)
The fault excitation state 106 excited in the net 109 is propagated to the net 109, the net 107, and the receiving FF 100.

  In FIGS. 15A and 15B, the capture state (D input of the feed FF) is shown as a receiving time state, assuming that the feed clock SCK enters all the feed FFs 90, 92, and 94. ing.

  Next, a specific example of the automatic test pattern generation processing for the dynamic function test of the present invention by the ATGP core processing of FIG. 8 will be described with reference to FIGS.

  FIG. 16 is an explanatory diagram of a specific example in the case where the narrowing marking process is completed in step S1, the excitation is determined in step S2, and the fault excitation is performed in step S3 in the ATGP core process of FIG. is there.

In FIG. 16, there is a net of AND gate G1, inverters N1 and N2, and NAND gates G2 to G6 between sending FFs 108 and 110 and receiving FF 113 , and failure assumption point 115 is selected as the output of AND gate G1. Take the case as an example. In the following description, G1 to G6 are simply referred to as gates. In this target circuit, feed FFs are provided for the inputs of the inverter N1 and the gate G3 and the input pins of the gate G4 and the inverter N2, respectively, but this is omitted.

  In the fault excitation of FIG. 16, the fault excitation state 112 is assigned to the selected fault assumption point 115. The failure excitation state 112 excites a rising failure in which the normal value rises to state 0 at the sending time and state 1 at the receiving time, and the failure value becomes state 0 at the sending time and state 0 at the receiving time.

  Subsequently, as shown in FIG. 17, the process proceeds to step S4 in FIG. 8 to perform an implication operation. This implication operation assigns the same states 114 and 116 as the failure excitation state to the input pins of the gates G3 and G4 in front of the failure assumption point 115 and assigns the states 118 and 120 to the output pins.

In addition, the states 122 and 126 are assigned to the input pins of the gate G1 located behind the failure assumption point 115 , whereby the same states 124 and 128 are assigned to the input pins of the gates G2 and G5, respectively.

  In FIG. 18, after performing the implication operation as shown in FIG. 17 in step S4 of FIG. 8, it is determined that there is no contradiction in step S5, the condition to be solved is determined in step S6, and the process proceeds to step S7 to resolve the condition It is explanatory drawing when the setting of a state is performed and it returns to step S4 and implication operation is performed subsequently.

  That is, in FIG. 18, the conditions to be solved for the states 122 and 126 of the two input pins of the gate G1 in FIG. 17 are checked. In this case, there is no condition to be solved for the states of the lower input pins. At 132, the condition solving state 130 is performed and the state 133 is assigned.

  When this condition solving state setting is completed, the states 134, 136, and 138 are assigned by performing the implication operation in step S4 for the input pin and the output pin of the gate G2.

  Subsequently, in step S5 in FIG. 8, it is determined that there is no contradiction, and in step S6, there is no condition to be solved. Therefore, in step S8, the failure observation is performed and the FF 112 is performed. It is determined whether or not there is a fault that can be propagated. In this case, since there is a fault that can be propagated, the fault propagation state is set in step S10, and then the implication operation is performed by returning to step S4.

  FIG. 19 is a specific example of the setting of the fault propagation state in step S10 and the subsequent implication operation in step S4. First, among the gates G3 and G4 as a fault that can be propagated, in this case, the frontier selection 140 is performed on the gate G3, and the state 142 of the input pin above the gate G3 for propagating the fault state from the fault assumption point 111 is set. To do.

  With the setting of this state 142, the failure state 144 is propagated to the output pin of the gate G3. Further, the implication operation of step S4 accompanying the setting of the fault propagation state 142 assigns the state 146 of the input gate of the inverter N1 and the state 148 of the output pin, and further determines the state 150 of the output pin of the gate G2, and at the same time inputs the gate G6. Pin state 152 is assigned.

  Subsequently, through steps S5, S6, S8, and S9 in FIG. 8, the setting of the fault propagation state in step S10 and the implication operation in step S4 are performed. The fault propagation state setting and the implication operation associated with the second process are as shown in the specific example of FIG.

  As the second propagationable failure, the gate G4 is set as the frontier selection 154 and the same state assignment operation as in FIG. 9 may be performed. In this example, the failure assumption point 115 of the output pins of the gate G6 and the gate G1 is used. From the viewpoint of symmetry, the failure propagation state 156 of the gate G6 can be set immediately exceptionally.

  In the core operation for this fault propagation state 156, the output pin state 158 of the gate G5, the input pin state 160 from the inverter N2, the input pin state 162 of the inverter N2, the input state 164 of the input pin of the gate G4, and the gate G4 Output pin states 166 can be assigned all at once.

  By setting the fault propagation state and the implication operation, the input pins other than the input pin from the gate G3 to which the fault state is input are assigned to the state in which the fault can be propagated, and the output of the gate G6 is output. A fault state 170 propagates to the pin.

  For this reason, in FIG. 8, failure observation becomes possible when the process proceeds to S8 via steps S5, S6, and S7, and the process proceeds to step S12 to perform a narrowing mark removal process. In step S13, the FF clock-off uncontrol is performed. An implication operation of the state of u (which will be clarified in later explanation) is performed, and the process of automatic test pattern generation ends when the test is successful.

  The ATGP core part process of FIG. 8 shown in FIGS. 16 to 20 is an ATGP core part process by the first failure selection of steps S1 to S2 in FIG. 6. When it is determined in step S3 that the ATGP is successful. In steps S4 and S5, ATPG core processing by 2nd failure selection for pattern compaction is performed.

  In this case, according to the present invention, as shown in FIG. 21, the state 172 giving the activation condition of the gate G1 in FIG. Compaction failure excitation is performed in which the failure state 172-1 that has been changed to the inverse value 0 of the state 1 at the reception time of the don't care X is assigned.

  The fault propagation and implication operation associated with the compaction fault excitation is performed according to the same procedure as in the case of FIG.

In this way, by assigning the compaction failure excitation state 172-1, a condition for giving an activation condition in successful test pattern generation can be a failure propagation path, thereby improving the processing efficiency of the pattern compaction test pattern generation processing. The total number of generated test patterns can be increased. this

(3. Determination of failure excitation)
In the dynamic function test using the system clock in the present invention, as shown in FIG. 9, the state change from the feed FFs 48 and 50 is the preparation FFs 40 and 42 set before the feed clock is applied. And the state of the input pins of the feed FFs 48 and 50 captured by the applied feed clock SCK. Therefore, in order to excite a transition fault such as a rising fault or a falling fault, it is essential that a system clock be applied to at least one feed FF that drives the net of the fault assumption point 56 where a transition fault is assumed. It becomes.

  At this time, in the automatic test pattern generation by the dynamic function test that performs gate management equivalent to the static function test as in the past, the implication operation of the gate in the FF is turned off, for example, in the feed clock of the feed FF 48 at the feed time. Even when assigned, the implications derived from this clock-off are limited to the hold state of the output of the feed FF 48 at the receiving time.

  However, if the output state of the FF at the sending time and receiving time when the clock-off is assigned is both don't care X, the output of the receiving FF 54 at the receiving time only implies X to X. No state updates are made.

  In other words, even if the transition state of the net controlled only by the output of the feed FF cannot be fault-excited, it is impossible to excite the transition fault in automatic test pattern generation equivalent to the static function test. Can not know immediately.

  Therefore, in automatic test pattern generation in which only implication processing equivalent to that of the conventional static function test is performed, after the state allocation for excitation is actually performed, when the processing reaches the FF whose clock is off, There is a problem of spending time on processing that should be useless because it detects a contradiction for the first time and determines that it is unsuccessful.

  Therefore, in the gate implication of the dynamic function test of the present invention, as shown in FIG. 22A, if the sending clock FF 174 is assigned to the sending FF 174 at the sending time, the receiving time corresponding to the sending FF 174 is set. The implication of impressing u as the failure value state at the reception time for the output pin of the reception FF 176 is implied.

  That is, for the sending FF 174 received on the clock-off side in FIG. 22A, state allocation is performed with the failure value state at the receiving time as the uncontrolled u as the output state of the sending FF 174, and this is propagated.

FIG. 22B shows the state of implication processing in the conventional static function test. In this case, the state of the output of the sending FF 174 becomes the same don't care X for the sending time and the receiving time due to clock-off, and this is the gate. Propagate with activation condition for 176.

  Based on the state assignment of the conventional clock-off feed FF 174 as described above, when the failure excitation state 182 is assigned to the failure assumption point 180 as shown in FIG. 22C, and the failure propagated in the receiving FF is confirmed, Performs an implication operation for the back. In this implication operation, the state 186 is assigned as the state of the output pin of the feed FF 174 corresponding to the failure excitation state 182 of the failure assumption point 180.

  However, in this case, since the sending FF 174 is in the clock-off state, the output state should be in the state 1 at both the sending time and the receiving time as in the state 188, and contradicts the state 188. At this time, it is determined that the failure excitation by the failure excitation state 182 of the failure assumption point 180 cannot be excited.

For this reason, a lot of processing time is required to determine whether failure excitation is not possible in the output state of the clock-off feed FF by the implication operation of the static function test as shown in FIGS. On the other hand, in the present invention, as shown in FIG. 22A, by assigning and propagating the state of the uncontrol u as the failure value at the reception time of the output of the feed FF 174, the signal is observed in the receiver FF. If the failure value at the reception time of the state is uncontrolled u, the failure excitation for the failure assumption point in the failure propagation path from the clock-off feed FF is excluded from the target. This eliminates the need for automatic test pattern generation for useless targets, and can speed up automatic test pattern generation processing as a whole.

(4. Determination of undetectable failure)
In the present invention, when dealing with a transition fault subject to dynamic function testing, the possibility and the possibility of an excited fault are defined as the relationship between states at least at two times, the sending time and the receiving time. It is impossible to use the equivalent fault concept equivalent to the stuck-at fault handled in the static function test.

  For example, each 0 stuck-at fault assumed for an input pin and an output pin in an AND gate is an equivalent fault because it has the same condition that the states of all the input pins and the output pins are set to 1 with respect to fault propagation.

  However, in the case of a transition fault targeted by the present invention, for example, in an AND gate having two inputs, net A and net B, a zero transition fault assumed for net A, that is, the state of net A starts from 0. When considering the detection of a fault that is excited as 0 to 0 when changing to 1, the essential condition for this AND gate is that the change in normal value from the sending time of the net A to the receiving time is 0 to 1, and the fault value In the case of the net B, the normal value from the sending time to the receiving time is from X to 1, and the failure value is also from X to 1.

  Similarly, when considering the detection of a zero transition fault assumed in the net B, the change in the normal value of the sending time from the reception time of the net A is from X to 1, and the change in the fault value is also from X to 1. For B, the change in normal value from the sending time to the receiving time is from 0 to 1, and the change in failure value is from 0 to 0. For this reason, since the essential conditions in the state before the change, that is, the sending time are different, the zero transition faults assumed for the net A and the net B are not equivalent faults.

  For this reason, in the transition faults targeted by the dynamic function test of the present invention, an equivalent fault equivalent to a known stuck-at fault cannot be obtained. Only when a failure has to be targeted, or a transition fault for which automatic test pattern generation has failed has no fan-out and is assumed to be an input / output pin of a gate such as a 1-input 1-output inverter or buffer, Only the exclusion process of excluding from the target as a failure that cannot be detected can be performed.

For this reason, the automatic test pattern generation in the dynamic function test of the present invention takes much processing time as compared with the case based on the static function test. Therefore, in the present invention, as shown in FIG. 23, for example, when the automatic test pattern for failure excitation at the failure assumption point 196 fails, the branch 185 in the fan-out free area 192 is selected from the net where the failure assumption point 196 is selected. Among the failure assumption points 200, 204, and 206 in the nets up to 1,185-2, with the failed failure assumption point 196,
(Condition 1) The inversion relationship is equal to the failed failure, and (Condition 2) the failure value is equal to the normal value of the gate,
A mark F0 is given as a non-detectable fault that satisfies the above condition, and the marked non-detectable fault is excluded from the target for automatic test pattern generation.

  Note that the fan-out free area 192 for determining an undetectable failure means an area where the circuit converges and does not diverge at the failure assumption point 196 where the automatic test pattern has failed.

  FIG. 24 is an explanatory diagram of condition 1 and condition 2 for determining an undetectable failure. FIG. 24 shows the failure excitation of the failure assumption point 212 at the input of the gate 210 with respect to the state of the failure assumption point 208 that failed as the condition 1 when the automatic test pattern due to the failure excitation of the failure assumption point 208 at the output of the gate 210 fails. Since the states have the same inversion relationship, Condition 1 is satisfied.

  In addition, since the failure value 0 at the reception time of the failure assumption point 212 is equal to the normal value 0 of the AND gate 210, the condition 2 is satisfied. Therefore, the failure assumption point 212 is given a mark F0 indicating a failure as an undetectable failure.

  FIG. 25 is an explanatory diagram of a determination condition for an undetectable failure in the AND gate 216 having two inputs including the net A and the net B.

  FIG. 25A shows a case where a failure assumption point 215 is selected for the output pin of the AND gate 216 in the fan-out free area 214 and a failure excitation state is assigned. In this case, automatic test pattern generation is performed in the net A and net B. The state setting for succeeding is either the state of FIG. 25 (A) or the state of FIG. 25 (B).

  For this reason, the automatic test pattern generation in the assignment of the excitation fault state of the fault assumption point 215 of the output pin of the AND gate 216 fails because the state assignment of any of the input gates in FIGS. 25A and 25B fails. Or there is no activation path from the stem 217 to the fan-out destination.

  Here, the state of the input that failed to be assigned is a fault in which the fault value at the receiving time is equal to the normal value 0 of the AND gate 216 among the fault states assumed in the fault assumption points 219-1 and 219-2 of the nets A and B. Since the inversion relationship is the same as the failure excitation state of the failed failure assumption point 215 in the excitation state, the failure assumptions 219-2 and 219-2 of the nets A and B are also not detected in the failure satisfying the conditions 1 and 2. Is possible.

When automatic test pattern generation for a certain failure excitation state fails, a failure assumption point satisfying conditions 1 and 2 is determined for the branch to stem in the fan-out free area 214 to indicate an undetectable failure. By adding the mark F0 and excluding the assumed fault point where the mark F0 is performed from the target of the automatic test pattern, the processing speed is increased so as not to generate a useless automatic test pattern.

(5. Path cut measures)
FIG. 26 is a block diagram of the path cut countermeasure unit 14 in the integrated circuit test apparatus of FIG. The path cut countermeasure unit 14 includes a path cut countermeasure overall control unit 218, a path cut point selection unit 220, an invariant state setting ATPG unit 222, and an undetectable failure number measurement unit 224.

  With such a configuration, the path cut countermeasure unit 14 gives the gate control value at the feed time and the receive time to fix the gate at the gate input for driving the pass cut point or fixes the gate at the feed time and the receive time. By assigning a non-control value to the gate, the state of the pass cut point is assigned and fixed from the receiving time state 0 to the sending time 0 which becomes an invariant state, or from the sending time 1 to the receiving time 1 .

  The reason for requiring such a path cut countermeasure is as follows. Conventionally, a loop circuit is known as a path that requires a path cut, and many path cut methods relating to the loop circuit have been proposed.

On the other hand, as a path that needs to be cut in a dynamic function test, there is an nτ path 226 shown in FIG. 27 that does not guarantee transfer in one system cycle (1τ) in addition to a loop circuit. The nτ path 226 is a path that is effective only at the time of system startup or debugging such as setting by the operation status register.

  In addition, the nτ path 226 that requires a path cut in the dynamic function test does not constitute a loop, and is not a fixed path cut but needs to be cut according to the timing requirements of the sending time and the receiving time.

  In addition, the path cut applied in the static function test has a sufficient timing for cutting the target path with respect to the clock application, so there is no need to consider the hazard that the disturbance changes through the net. is there. On the other hand, in the dynamic function test, the sending clock and the receiving clock are applied at high speed, so if a hazard occurs in the path to be cut, there is a risk that the clock will cause the integrated circuit to malfunction during the test due to this hazard. Therefore, it is necessary to cut the path in consideration of hazard suppression.

  Further, as a path cut for a route such as the nτ path 226 of FIG. 26 that does not guarantee the transfer of the system clock unique to the dynamic function test, for example, the path cut is performed in the same manner as the conventional loop path cut. When the operation is performed, it is regarded as a loop even though it is not actually a loop, and the loop path itself is not controllable, so that a multi-input gate among the gates constituting the path regarded as a loop is regarded as a loop. Set the gate control value to the non-side input.

  At this time, propagation of the fixed state given to the path cut 230 and the control point 231 from the control point 231 for setting the state for fixing the nτ path 226 to be cut and the gate 242 connected to the path cut point 230 is performed. It is inevitable that a failure that cannot be detected due to the above will occur.

  However, in the conventional path cut for the loop circuit, the state of the path cut point 230 can only be fixed by the control value of the gate 242. Therefore, the selection of the cut point and the cut point are fixed in the dynamic function test. For this reason, there is a problem that a non-optimal selection is made.

  In addition, in static function test path cuts, there is a margin between the timing at which the state is fixed at the cut point and the timing of clock application, so when performing a path cut with the gate control value fixed at the path cut point It is not necessary to consider the hazard that occurs in the target path.

  However, in the dynamic function test, there is a possibility that a control value is given so that the path is cut independently at the sending time and the receiving time. Depending on the timing at which the control value reaches the cut point, a hazard may occur in the path cut target path.

  Therefore, in the present invention, one of the two path cut methods shown in FIGS. 28A and 28B is selected. FIG. 28A shows the same method as the path cut for the loop circuit. At the input pin of the AND gate 246 that drives the path cut point 245, a control value 0 is assigned at the sending time and the receiving time to change the state. The state of the path cut point 245 is fixed, and an invariant state from the state 0 of the sending time to the state 0 of the receiving time is assigned and fixed.

  FIG. 28B shows a path cut countermeasure newly added according to the present invention. As a countermeasure against this path cut, in the gate input of the AND gate 248 that drives the path cut point 245, the non-control value 1 of the AND gate 248 is given to all gate inputs at the sending time and the receiving time, and the path cut point 245 The state is assigned and fixed from 1 of the sending time to 1 of the receiving time.

  The path cut countermeasure in FIG. 28B is performed by paying attention to the condition that the state of the path cut point only needs to be the same between the sending time and the receiving time in the dynamic function test. Yes.

  By the way, as a path cut countermeasure of the present invention, assigning an invariant state to a path cut point of a certain path means that an undetectable fault occurs because the degree of freedom in selecting a state for automatic test pattern generation is reduced. To do. At this time, there are two selections for the invariant state for a certain path cut point: between 0 to 0 and between 1 and 1 between the sending time and the receiving time.

  Therefore, in the present invention, an invariant state of 0 to 0 or 1 to 1 is selected so as to minimize the occurrence of an undetectable failure as a fixed state at the path cut point.

  Specifically, when assigning the invariant state to the selected path cut point, the invariant state setting ATPG unit 222 in FIG. 25 is used for each of the invariant states from 0 to 0 and the invariant state from 1 to 1. A hyperplane that increases the number of undetectable faults in a discrete space based on 0 to 0 and 1 to 1 as shown in FIG.

  In the hyperplane obtained from the measurement of the number of undetectable faults, an invariant state in which the number of undetectable faults decreases so as to go down the slope of the hyperplane, for example, in the case of FIG. 29, an invariant state of 0 to 0 is selected. By assigning them to the path cut points, the number of undetectable faults is minimized, and the failure detection rate is prevented from decreasing.

FIG. 30 is a flowchart of the path cut countermeasure process shown in FIG. 29, and includes the following processing procedure.

Step S1: One path cut point is arbitrarily selected from a set of path cut points specified by the user.
Step S2: For the path cut point selected in step S1, both 0 and 1 are tried as invariant states to be given to the path cut point.
Step S3: A net state satisfying the invariant state at the cut point set in Step S2 is obtained by automatic test pattern generation processing.
Step S4: The number of faults measured as undetectable in the net state obtained by the automatic test pattern generation processing in step S3 is stored as the number of undetectable faults [invariant state].
Step S5: Compare the number of undetectable faults [0] and the number of undetectable faults [1] for both of the invariant states (0, 1) set at the path cut points obtained by the operations in steps S2 to S4. The state in which the number of undetectable faults is reduced is adopted as an invariant state to be set at the path cut point selected in step S1.
Step S6: If there is a path cut point that has not been processed in steps S1 to S5 in the set of path cut points specified by the user, the process returns to step S1.

  FIG. 31 is an explanatory diagram of the hazard-free operation performed when the allocation of the invariant state of the path cut point is successful. FIG. 31A shows the AND at the sending time and the receiving time for the input pin 254-1 among the three input pins 254-1 to 254-3 of the AND gate 254 by the path cut countermeasure of FIG. By assigning the control value 0 of the gate 254 and fixing the state, the invariant state from the sending time state 0 to the receiving time state 0 is successfully assigned at the path cut point 258.

  However, in this case, in the AND gate 254 on the driver side, the control value 0 of the input pin 254-1 is changed to the control value 0 of the input pin 254-3 at the reception time. For this reason, the failure assumption point 258 is statically 0 to 0, but a hazard may occur in other inputs that are don't cares X.

Therefore, in the present invention, as shown in FIG. 31 (B), when the invariant state is successfully allocated at the path cut point 258, the back trace is performed. When there is a transfer to the receiving time, the input pin 254-3 that gives the control value 0 at the receiving time can also be assigned to the control value 0 by not assigning the donation care X at the sending time, so that the hazard is free from the pass cut point 258. Create an immutable state.

(6. Narrowing process)
In the narrowing mark processing unit 28 provided in the ATPG core unit 24 of FIG. 7, as preprocessing of failure excitation by the failure excitation unit 30, as shown in FIG. 32, the receiving FF group 266 is received from the failure assumption point 268. The narrowing range mark by the back traces 270 and 272 up to the feed FF group 264 and the narrowing range mark by the back trace 274 from the feed FF group 264 to the preparation FF group 262 are performed.

  At this time, if the fanout spread between the FFs is uniform, the trace range from the feed FF group 264 to the preparation FF group 262 is generally compared to the trace range from the receive FF group 266 to the feed FF group 264. On average, it has a square area, and it takes time to perform tracing for narrowing.

  FIG. 33 shows a backtrace that marks implication propagation with a narrowing operation for a certain target failure. As the net state in this backtrace, the state of the input pin 276-1 of the AND gate 276 is assigned a state other than the don't care X for both the sending time and the receiving time.

  Therefore, the net state of the input pin 276-1 is not changed by any fault excitation and fault propagation implication operations that are subsequently performed on the target fault. Accordingly, the trace is stopped with the input pins 276-1 having states other than the don't care X excluded from implication propagation.

  The net state of the sending time and receiving time for stopping the narrowing back trace is determined in this way when a fixed value of the net state such as the test mode is set or in the pattern compaction. This is a case where the state assignment by the successful automatic pattern generation for the target failure is completed.

  Therefore, in the narrowing processing of the present invention, the implication propagation range for performing trace stop in narrowing by pattern compaction, that is, the mark processing in the narrowing range is reduced, and automatic test pattern generation is accelerated. Can do.

  On the other hand, the narrowing process in the present invention performs net marking as preprocessing prior to failure excitation and failure propagation operation for a certain failure target, and marks after completion of automatic test pattern generation by failure excitation and propagation operation to the target failure. The net range to be traced does not depend on the failure value of the target.

  However, in a normal dynamic function test, the target failure includes the pair of the rising delay failure shown in FIG. 10 and the falling delay failure shown in FIG.

  Therefore, in the present invention, when the automatic pattern generation for one of the pair failures including the rising failure and the falling failure fails, the narrowing range is not unmarked if the other of the pair failures is not detected. In addition, the narrowing range that has already been set is diverted, and the rest of undetected pair faults are used as the next target to perform automatic test pattern generation by fault excitation and propagation operations.

  FIG. 34 is a flowchart of ATPG processing targeting a pair failure, and steps S1 to S6 are the same as the processing of FIG. In addition to this, when pair failure is targeted, if ATPG fails for one of the pair failures in step S3, it is determined whether or not another pair failure is not detected in step S7, and is not detected. In this case, the process proceeds to step S8, the narrowing range is used, an undetected pair failure is set as a target, and the ATPG process from step S1 is performed.

  In addition, the present invention provides a program for integrated circuit test processing realized by the flowchart shown in each embodiment, and also provides a computer-readable storage medium storing the program. Storage media in this case include portable storage media such as CD-ROMs, floppy disks, DVD disks, magneto-optical disks, and IC cards, storage devices such as hard disk HDDs provided inside and outside the computer system, and lines. Including a database for storing programs via the network, other computer systems, the database, and a transmission medium on a line.

  In addition, this invention is not limited to said embodiment, The appropriate deformation | transformation which does not impair the objective and advantage is included. The present invention is not limited by the numerical values shown in the above embodiments.

Here, the features of the present invention are collectively listed as follows.
(Appendix)

(Appendix 1)
On the computer,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF group, and the preparation FF group one stage before the feeding FF group,
A fault excitation step for assigning states representing the circuit states of fault excitation at the sending time and the receiving time;
A path activation step for allocating a state representing a circuit operation state for activating the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation step for generating a test pattern
And execute
Further, as the path activation step, when a state representing a circuit operation state for activating a failure propagation path after the change of the net is a state in which a transition from a don't care value X to a non-control value is performed,
A program for executing a step of activating a propagation path of a failure by allowing the don't care value X. (1)

(Appendix 2)
In the program according to attachment 1, after the failure propagation step is completed,
A compaction failure excitation step of assigning the state changed to the inverted value of the state representing the circuit operating state at the time of receiving the don't care value X of the path activation step;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagating a state representing a circuit operating state for detecting a delay fault in a path between FFs,
A compaction fault propagation step for generating a test pattern composed of an input value for the sending FF group and an output value of the receiving FF group, which is an expected value for the input value, when the state propagation is successful; ,
A program characterized by having executed. (2)

(Appendix 3)
On the computer,
When assigning a state representing the circuit operation state of the fault excitation to the fault assumption point of the circuit that creates a test pattern for detecting a delay fault,
When the clock-off is assigned to the feed FF at the feed time, the uncontrol value u is implied as a value indicating that fault excitation is impossible with respect to the fault value corresponding to the output at the reception time of the feed FF,
When an uncontrol value u is assigned to the fault assumption point, the step of excluding the fault assumption point from the target of the delay fault is executed by determining that fault excitation is impossible. program. (3)

(Appendix 4)
On the computer,
When failure propagation of a circuit that creates a test pattern for detecting a delay fault fails,
Of the faults assumed in the net from the fault assumption point on the net where the fault that failed in the fault propagation is assumed to the branch input of the fan-out free area where there is no circuit having a branch output,
By extracting a fault in which the inversion relationship between the failed fault and the fault value is equal and the fault value is equal to the control value of the gate,
A program for executing a step of excluding a fault assumed in the net as an undetectable fault. (4)

(Appendix 5)
On the computer,
In the gate input that drives the path cut point of the circuit that creates the test pattern for detecting the delay fault,
By fixing the gate control values at the sending time and receiving time, the state representing the circuit operation state is fixed, or
Or by assigning uncontrolled values of the gate to all gate inputs at the sending time and receiving time,
A program for executing a step of fixing by assigning an invariant state having a change of 0 to 0 or 1 to 1 as a state representing the same-path operation state at the path cut point. (5)

(Appendix 6)
In the program described in Appendix 5,
To a plurality of input pins in the driver side gate that drives the path cut point, between the sending time and the receiving time,
When there is a transfer with a change in the pin input position of the control value, by additionally assigning a control value at the feed time to at least one input pin to which the control value is given at the receiving time,
A program for executing a step of generating an invariant state that does not cause a hazard for the path cut point. (6)

(Appendix 7)
On the computer,
The back trace from the failure assumption point of the circuit for creating the test pattern for detecting the delay fault to the sending FF group via the receiving FF group, and the back trace from the sending FF group to the preparation FF group Mark the narrowing range by performing backtrace,
A program for executing a step of performing a narrowing to stop execution of the back trace from the net when both the states representing the circuit operation state at the net sending time and the receiving time are not the don't care value X. (7)

(Appendix 8)
In the program described in Appendix 7,
When one of the rising delay fault and falling delay fault of the same net fails to detect the delay fault,
By diverting the mark as it is without erasing the mark in the narrowing range marked in the narrowing backtrace,
A program for causing a test pattern generation to be executed with the other delay fault that has not been detected as a target. (8)

(Appendix 9)
On the computer,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF group, and the preparation FF group one stage before the feeding FF group,
A fault excitation step for assigning states representing the circuit states of fault excitation at the sending time and the receiving time;
A path activation step for allocating a state representing a circuit operation state for activating the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation step for generating a test pattern
And execute
Further, as the path activation step, when a state representing a circuit operation state for activating a failure propagation path after the change of the net is a state in which a transition from a don't care value X to a non-control value is performed,
A computer-readable storage medium storing a program for executing a step of activating a failure propagation path by allowing the don't care value X.

(Appendix 10)
In the storage medium according to appendix 9, after the failure propagation step is completed,
A compaction failure excitation step of assigning the state changed to the inverted value of the state representing the circuit operating state at the time of receiving the don't care value X of the path activation step;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagating a state representing a circuit operating state for detecting a delay fault in a path between FFs,
A compaction fault propagation step for generating a test pattern composed of an input value for the sending FF group and an output value of the receiving FF group, which is an expected value for the input value, when the state propagation is successful; ,
A computer-readable storage medium storing a program for executing the program.

(Appendix 11)
On the computer,
When assigning a state representing the circuit operation state of the fault excitation to the fault assumption point of the circuit that creates a test pattern for detecting a delay fault,
When the clock-off is assigned to the feed FF at the feed time, the uncontrol value u is implied as a value indicating that fault excitation is impossible with respect to the fault value corresponding to the output at the reception time of the feed FF,
When an uncontrol value u is assigned to the fault assumption point, a computer storing a program for executing a step of excluding the fault assumption point from the target of the delay fault by determining that fault excitation is impossible A readable storage medium.

(Appendix 12)
On the computer,
When failure propagation of a circuit that creates a test pattern for detecting a delay fault fails,
Of the faults assumed in the net from the fault assumption point on the net where the fault that failed in the fault propagation is assumed to the branch input of the fan-out free area where there is no circuit having a branch output,
By extracting a fault in which the inversion relationship between the failed fault and the fault value is equal and the fault value is equal to the control value of the gate,
A computer-readable storage medium storing a program for executing a step of excluding a fault assumed in the net as an undetectable fault.

(Appendix 13)
On the computer,
In the gate input that drives the path cut point of the circuit that creates the test pattern for detecting the delay fault,
By fixing the gate control values at the sending time and receiving time, the state representing the circuit operation state is fixed, or
Or by assigning uncontrolled values of the gate to all gate inputs at the sending time and receiving time,
A computer-readable storage medium storing a program for executing a step of fixing by assigning an invariant state having a change of 0 to 0 or 1 to 1 as a state representing the same-path operation state at the path cut point .

(Appendix 14)
In the storage medium described in appendix 13,
To a plurality of input pins in the driver side gate that drives the path cut point, between the sending time and the receiving time,
When there is a transfer with a change in the pin input position of the control value, by additionally assigning a control value at the feed time to at least one input pin to which the control value is given at the receiving time,
A storage medium that executes a step of generating an invariant state that does not cause a hazard with respect to the path cut point.

(Appendix 15)
On the computer,
The back trace from the failure assumption point of the circuit for creating the test pattern for detecting the delay fault to the sending FF group via the receiving FF group, and the back trace from the sending FF group to the preparation FF group Mark the narrowing range by performing backtrace,
When the state representing the circuit operating state at the sending time and receiving time of the net is not the don't care value X, the computer can read the program for executing the narrowing step for stopping the execution of the back trace from the net. Storage medium.

(Appendix 16)
In the storage medium described in appendix 15,
When one of the rising delay fault and falling delay fault of the same net fails to detect the delay fault,
By diverting the mark as it is without erasing the mark in the narrowing range marked in the narrowing backtrace,
A storage medium that causes test pattern generation to be executed with the other delay fault that has not been detected as a target.

(Appendix 17)
In a pattern creation method for creating a test pattern for detecting a delay fault in a circuit,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF group, and the preparation FF group one stage before the feeding FF group,
A fault excitation step for assigning a state representing a circuit operation state of fault excitation at a sending time and a receiving time;
A path activation step for allocating a state representing a circuit operation state for activating the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation step for generating a test pattern
And execute
Further, as the path activation step, when a state representing a circuit operation state for activating a failure propagation path after the change of the net is a state in which a transition from a don't care value X to a non-control value is performed,
A test pattern generation method, comprising: activating a failure propagation path by allowing the don't care value X. (9)

(Appendix 18)
In the test pattern creation method according to appendix 17, after the failure propagation step ends,
A compaction failure excitation step of assigning the state changed to the inverted value of the state representing the circuit operating state at the time of receiving the don't care value X of the path activation step;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagating a state representing a circuit operating state for detecting a delay fault in a path between FFs,
A compaction fault propagation step for generating a test pattern composed of an input value for the sending FF group and an output value of the receiving FF group, which is an expected value for the input value, when the state propagation is successful; ,
A test pattern creation method characterized by executing

(Appendix 19)
When assigning a state representing the circuit operation state of the fault excitation to the fault assumption point of the circuit that creates a test pattern for detecting a delay fault,
When the clock-off is assigned to the feed FF at the feed time, the uncontrol value u is implied as a value indicating that fault excitation is impossible with respect to the fault value corresponding to the output at the reception time of the feed FF,
When an uncontrol value u is assigned to the fault assumption point, the step of excluding the fault assumption point from the target of the delay fault is executed by determining that fault excitation is impossible. Test pattern creation method.

(Appendix 20)
When failure propagation of a circuit that creates a test pattern for detecting a delay fault fails,
Of the faults assumed in the net from the fault assumption point on the net where the fault that failed in the fault propagation is assumed to the branch input of the fan-out free area where there is no circuit having a branch output,
By extracting a fault in which the inversion relationship between the failed fault and the fault value is equal and the fault value is equal to the control value of the gate,
A test pattern creation method, comprising: performing a step of excluding a fault assumed in the net as an undetectable fault.

(Appendix 21)
In the gate input that drives the path cut point of the circuit that creates the test pattern for detecting the delay fault,
By fixing the gate control values at the sending time and receiving time, the state representing the circuit operation state is fixed, or
Or by assigning uncontrolled values of the gate to all gate inputs at the sending time and receiving time,
A test pattern generation method, comprising: performing a step of fixing by assigning an invariant state having a change of 0 to 0 or 1 to 1 as a state representing the same-path operation state at the path cut point.

(Appendix 22)
In the test pattern creation method according to appendix 21,
To a plurality of input pins in the driver side gate that drives the path cut point, between the sending time and the receiving time,
When there is a transfer with a change in the pin input position of the control value, by additionally assigning a control value at the feed time to at least one input pin to which the control value is given at the receiving time,
A test pattern generation method, comprising: generating an invariant state that does not cause a hazard for the path cut point.

(Appendix 23)
The back trace from the failure assumption point of the circuit for creating the test pattern for detecting the delay fault to the sending FF group via the receiving FF group, and the back trace from the sending FF group to the preparation FF group Mark the narrowing range by performing backtrace,
When the state representing the circuit operation state at the sending time and receiving time of the net is not the don't care value X, a narrowing step for stopping execution of the back trace from the net is executed. Method.

(Appendix 24)
In the test pattern creation method according to attachment 23,
When one of the rising delay fault and falling delay fault of the same net fails to detect the delay fault,
By diverting the mark as it is without erasing the mark in the narrowing range marked in the narrowing backtrace,
A test pattern generation method, characterized in that test pattern generation is executed with the other delay fault that has not been detected as a target.

(Appendix 25)
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF, and the preparation FF group one stage before the feeding FF group,
A fault excitation unit for assigning a state representing a circuit operation state of fault excitation at a sending time and a receiving time;
A path activating unit that assigns a state representing a circuit operation state that activates the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation unit that generates a test pattern
With
Further, when the state representing the circuit operation state for activating the propagation path of the failure after the change of the net is a state in which the state is changed from the don't care value X to the non-control value,
A pattern creating apparatus that activates a propagation path of a failure by allowing the don't care value X. (10)

(Appendix 26)
In the pattern creation device according to attachment 25, after the processing of the fault propagation unit is finished,
A compaction failure excitation unit that assigns the state changed to the inverted value of the state representing the circuit operating state at the time of receiving the don't care value X of the path activating unit;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagating a state representing a circuit operating state for detecting a delay fault in a path between FFs,
When the propagation of the state is successful, a compaction fault propagation unit that generates a test pattern composed of an input value for the sending FF group and an output value of the receiving FF group that is an expected value for the input value; ,
A pattern creating apparatus characterized by causing

(Appendix 27)
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
When assigning a state representing the circuit operation state of the fault excitation to the fault assumption point of the circuit that creates a test pattern for detecting a delay fault,
When the clock-off is assigned to the feed FF at the feed time, the uncontrol value u is implied as a value indicating that fault excitation is impossible with respect to the fault value corresponding to the output at the reception time of the feed FF,
When an uncontrol value u is assigned to the failure assumption point, a failure excitation unit is provided that excludes the failure assumption point from a delay failure target by determining that failure excitation is impossible. A pattern creation device.

(Appendix 28)
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
When failure propagation of a circuit that creates a test pattern for detecting a delay fault fails,
Of the faults assumed in the net from the fault assumption point on the net where the fault that failed in the fault propagation is assumed to the branch input of the fan-out free area where there is no circuit having a branch output,
By extracting a fault in which the inversion relationship between the failed fault and the fault value is equal and the fault value is equal to the control value of the gate,
A pattern creating apparatus comprising a fault propagation unit for excluding faults assumed in the net as undetectable faults.

(Appendix 29)
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
In the gate input that drives the path cut point of the circuit that creates the test pattern for detecting the delay fault,
By fixing the gate control values at the sending time and receiving time, the state representing the circuit operation state is fixed, or
Or by assigning uncontrolled values of the gate to all gate inputs at the sending time and receiving time,
A pattern generation comprising a path cut processing unit for fixing by assigning an invariant state having a change of 0 to 0 or 1 to 1 as a state representing the same-path operation state at the path cut point apparatus.

(Appendix 30)
In the pattern creation device according to attachment 29,
To a plurality of input pins in the driver side gate that drives the path cut point, between the sending time and the receiving time,
When there is a transfer with a change in the pin input position of the control value, by additionally assigning a control value at the feed time to at least one input pin to which the control value is given at the receiving time,
A pattern generating apparatus that executes a step of generating an invariant state that does not cause a hazard with respect to the path cut point.

(Appendix 31)
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
The back trace from the failure assumption point of the circuit for creating the test pattern for detecting the delay fault to the sending FF group via the receiving FF group, and the back trace from the sending FF group to the preparation FF group Mark the narrowing range by performing backtrace,
A narrowing processing unit is provided that performs narrowing to stop the execution of the backtrace from the net when the state representing the circuit operation state at the sending time and the receiving time of the net is not the don't care value X. Pattern creation device.

(Appendix 32)
In the pattern creation device according to attachment 31,
When one of the rising delay fault and falling delay fault of the same net fails to detect the delay fault,
By diverting the mark as it is without erasing the mark in the narrowing range marked in the narrowing backtrace,
A pattern generation apparatus comprising a pattern generation unit that executes test pattern generation with the other delay fault that has not been detected as a target.

(Appendix 33)
A reading step of reading circuit data by the circuit data reading unit;
A path cut step for selecting a path cut point from the target circuit and fixing the state by the path cut countermeasure unit,
An automatic test pattern generation step for generating test data for detecting a delay fault for a circuit for which a path cut has been completed by an automatic test pattern generation unit;
In the pattern creation method comprising
The automatic test pattern generation step includes:
A narrowing step for specifying, as a processing target circuit, a region including the feed FF group corresponding to the failure assumption point, the receiving FF, and the preparation FF group one stage before the feed FF group by the narrowing processing unit,
A failure excitation step for assigning, by the failure excitation unit, a failure excitation state of a sending time and a receiving time in an inverted relationship from 0 to 1 for a rising failure and 1 to 0 for a falling failure, to the failure assumption point;
A path activation step of allocating a state of sending time and receiving time for activating the propagation path of the fault to the remaining preparation FFs and sending FFs by the fault propagation state setting unit;
The automatic test pattern generation control unit supplies a system clock to the sending FF as a sending clock, changes the sending FF to the net and propagates it, and supplies the system clock to the receiving FF as a receiving clock to change the net. A fault propagation step of propagating a state for detecting a delay fault to a path between the sending FF and the receiving FF by generating a test pattern with successful propagation;
In addition,
The path activation step allows assignment of don't care X as a state that activates a propagation path of a failure,
The fault propagation step is a pattern generation method characterized by activating a fault propagation path by transitioning from a don't care X to a non-control value after a net change.

(Appendix 34)
34. The pattern creation method according to claim 33, wherein the don't care X is a logical value that constitutes a test pattern that does not affect the failure detection rate even if the don't care X is replaced with an opposite value.

(Appendix 35)
In the pattern creation method according to attachment 33, after the failure propagation step is completed,
A compaction failure excitation step that receives the don't care X of the path activation step and changes the state to the opposite value to the time state and assigns a failure excitation state;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A compaction fault propagation step for propagating a state for detecting a delay fault to the path between the FFs and generating a test pattern with successful propagation;
A pattern creating method characterized by comprising:

(Appendix 36)
The pattern creation method according to attachment 33, wherein in the failure excitation step, when the clock FF is assigned to the feed FF at the feed time, the fault excitation cannot be performed for the fault value with respect to the output at the reception time of the feed FF. The pattern creation method is characterized in that it is implied by an uncontrol value u indicating that the assignment of the uncontrol value u itself is determined to be impossible for fault excitation and is excluded from the target of the delay fault.

(Appendix 37)
In the pattern creation method according to attachment 33, if failure propagation fails in the failure propagation step, failure among the assumed failures in the net from the assumed failure failure to the branch-out of the fan-out free area A pattern generation method characterized by extracting faults that have the same inversion relationship as the fault and the fault value equal to the control value of the gate and exclude it as an undetectable fault.

(Appendix 38)
The pattern creation method according to attachment 33, wherein the pass cut step fixes a state by assigning a gate control value at a feed time and a receive time at a gate input for driving the pass cut point, or a feed time and a receive time. A pattern generation method characterized by assigning a non-control value of a gate to all gate inputs at a time and fixing the state of the path cut point by assigning invariant states 0 to 0 or 1 to 1.

(Appendix 39)
In the pattern creation method according to attachment 38, in the path cut step, the inability states 0 to 0 or 1 to 1 assigned to the path cut point are measured by the automatic test pattern generation step to detect the number of faults that cannot be detected, and the fault cannot be detected. A pattern generation method comprising an invariant state selection step of selecting an invariant state having a small number.

(Appendix 40)
The pattern creation method according to attachment 38, wherein the pass cut step receives a change when a pin input position of a control value changes at a feed time and a receive time at a plurality of input pins of a driver side gate with respect to the pass cut point. Having a hazard-free step of generating a hazard-free invariant state for the path cut point by adding and assigning a control value at the feed time to at least one input pin to which the control value is given at the time Characteristic pattern creation method.

(Appendix 41)
In the pattern creation method according to attachment 33, the narrowing step includes, as pre-processing of the failure excitation step, from the failure assumption point to the sending FF group via the receiving FF and from the sending FF group to the preparation FF group. The narrowing range is marked by a two-step backtrace, and if the stay of the net sending time and receiving time is both don't care X, a narrowing step for stopping the backtrace after the net is provided. How to create a pattern.

(Appendix 42)
42. The pattern creation method according to appendix 41, wherein the automatic test pattern generation step includes a step in which the narrowing step is backed up when a delay fault is detected for either one of a rising delay fault and a falling delay fault of the same net. A pattern creation method, wherein a test pattern is generated by using the other undetected delay fault as a target by diverting the narrowing range marked in the trace without removing the mark.

(Appendix 43)
On the computer,
A reading step for reading circuit data;
A path cut step for selecting a path cut point from the target circuit and fixing the state by the path cut countermeasure unit,
An automatic test pattern generation step for generating test data for detecting a delay fault in a circuit for which a path cut has been completed;
In a program that executes
The automatic test pattern generation step includes:
A narrowing step for identifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit;
A failure excitation step of assigning, to the failure assumption point, a failure excitation state of a sending time and a receiving time in an inverted relationship of 0 to 1 for a rising failure and 1 to 0 for a falling failure;
A path activation step for assigning a state of a sending time and a receiving time to activate the propagation path of the failure to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A fault propagation step for propagating a state for detecting a delay fault to the path between the FFs and generating a test pattern with successful propagation;
In addition,
The path activation step allows assignment of don't care X as a state that activates a propagation path of a failure,
The fault propagation step is a program characterized by activating a fault propagation path by making a transition from a don't care X to a non-control value after a net change.

(Appendix 44)
44. The program according to claim 43, wherein the don't care X is a logical value constituting a test pattern that does not affect the failure detection rate even if the don't care X is replaced with an opposite value.

(Appendix 45)
In the program according to attachment 43, after the failure propagation step is completed,
A compaction failure excitation step that receives the don't care X of the path activation step and changes the state to the opposite value to the time state and assigns a failure excitation state;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A compaction fault propagation step for propagating a state for detecting a delay fault to the path between FFs and generating a test pattern with successful propagation;
A program characterized by comprising:

(Appendix 46)
In the program according to attachment 43, the failure excitation step indicates that failure excitation is not possible with respect to a failure value with respect to an output at a reception time of the feed FF when clock-off is assigned to the feed FF at a feed time. A program implied by an uncontrol value, wherein the assignment of the uncontrol value itself is determined to be impossible for fault excitation, and is excluded from the target of a delay fault.

(Appendix 47)
In the program according to attachment 43, when failure propagation fails in the failure propagation step, the failure which is failed among the failures assumed in the net from the net where the failed failure is assumed to the branch input of the fan-out free area A program having the same inversion relationship and a fault value equal to the gate control value is extracted and excluded as an undetectable fault.

(Appendix 48)
In the program according to attachment 43, in the pass cut step, at the gate input for driving the pass cut point, a gate control value is given at a sending time and a receiving time to fix a state, or at a sending time and a receiving time, A program characterized in that a gate non-control value is assigned to all gate inputs, and the state of the path cut point is fixed by assigning invariant states 0 to 0 or 1 to 1.

(Appendix 49)
In the program according to attachment 48, in the path cut step, the number of detected failure failures is measured by the automatic test pattern generation step for the invariant states 0 to 0 or 1 to 1 assigned to the path cut points. A program comprising an invariant state selection step for selecting a few invariant states.

(Appendix 50)
In the program according to attachment 48, when the path cut step includes a transfer in which a pin input position of a control value changes between a feed time and a receive time for a plurality of input pins of a driver side gate with respect to a pass cut point, A hazard-free step is provided that generates a hazard-free invariant state for a path cut point by adding and assigning a control value at a feed time to at least one input pin to which a control value is given. Program to do.

(Appendix 51)
In the program according to attachment 33, the narrowing step is a pre-process of the failure excitation step, which is a two-stage process from a failure assumption point to a sending FF group via a receiving FF and a sending FF group to a preparation FF group. A narrowing step for marking a narrowing range by backtrace of the network and stopping the backtrace after the net if both the net sending time and the receiving time stay are not don't care X .

(Appendix 52)
The program according to appendix 51, wherein the automatic test pattern generation step includes a backtrace of the narrowing step when the detection of a delay fault for either one of the rising delay fault and the falling delay fault of the same net fails. A program characterized by executing a test pattern using the other delay fault that has not been detected as a target without diverting the marked narrowing range without performing the mark removal.

(Appendix 53)
On the computer,
A reading step for reading circuit data;
A path cut step for selecting a path cut point from the target circuit and fixing the state by the path cut countermeasure unit,
An automatic test pattern generation step for generating test data for detecting a delay fault in a circuit for which a path cut has been completed;
And execute
The automatic test pattern generation step includes:
A narrowing step for specifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit;
A failure excitation step of assigning, to the failure assumption point, a failure excitation state of 0 to 1 for a rising failure and 1 to 0 for a falling failure, and a failure excitation state at a receiving time;
A path activation step for assigning a state of a sending time and a receiving time to activate the propagation path of the failure to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. A fault propagation step for propagating a state for detecting a delay fault to the path between the FFs and generating a test pattern with successful propagation;
In addition,
The path activation step allows assignment of don't care X as a state that activates a propagation path of a failure,
A computer-readable storage medium characterized in that the failure propagation step stores a program for activating a failure propagation path by transitioning from a don't care X to a non-control value after a change of a net.

(Appendix 54)
A circuit data reading unit for reading circuit data;
A path cut countermeasure unit that selects a path cut point from the target circuit and fixes the state;
An automatic test pattern processing unit that generates test data for detecting a delay fault for a circuit that has undergone a path cut;
In an integrated circuit test apparatus comprising:
The automatic test pattern generation unit
A narrowing step for identifying a region including a feed FF group corresponding to a failure assumption point, a receiving FF, and a preparation FF group one stage before the feed FF group as a processing target circuit;
A failure exciter that assigns the failure excitation state of 0 to 1 for a rising failure and 1 to 0 for a falling failure and a failure excitation state at a receiving time to the failure assumption point;
A failure propagation state setting unit for assigning states of a sending time and a receiving time to activate the propagation path of the failure to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. An automatic test pattern generation control unit that propagates a state for detecting a delay fault to a path between FFs, and generates a test pattern upon successful propagation;
In addition,
The failure propagation state setting unit allows assignment of don't care X as a state for activating a failure propagation path,
The automatic test pattern generation control unit makes a transition from a don't care X to a non-control value after a net change and activates a propagation path of a failure.

Principle explanatory diagram of the present invention Block diagram of functional configuration of integrated circuit test apparatus according to the present invention 2 is an explanatory diagram of a computer hardware environment in which the apparatus of FIG. 2 is realized. Flowchart of integrated circuit test processing according to the present invention. Block diagram of the automatic test pattern generator in FIG. Flowchart of automatic test pattern generation process of FIG. Block diagram of the automatic test pattern generation core unit of FIG. Flow chart of automatic test pattern generation core processing of FIG. Explanatory drawing of a dynamic function test according to the present invention that allows activation by don't care X Explanatory drawing of the failure excitation state of the rising failure in the dynamic function test of the present invention Explanatory drawing of the fault excitation state of the downstream fault in the dynamic function test of the present invention Explanatory diagram of activation states assigned in the present invention Explanatory drawing of failure propagation by activation that allows don't care X of the present invention Explanatory drawing of the failure propagation path which enables test pattern generation | occurrence | production by the activation which permitted the don't care X of this invention Explanatory drawing of the process which makes a failure propagation path the path | route which gave the activation condition after the failure propagation and test success when the activation condition by the change from the don't care X to the non-control value 1 is recognized by this invention Specific example of failure excitation in step S3 of FIG. Specific example of the implication operation in step S4 of FIG. A specific example when the implication operation in step S4 is performed after setting the condition solving state in step S7 in FIG. A specific example when the implication operation of step S4 is performed through the fault propagation state setting in step S10 of FIG. FIG. 8 is a specific explanatory diagram when failure propagation can be observed and test pattern generation is successful. Explanatory drawing of the state reset to the control value 0 of the don't care X at the time of shifting to 2nd failure selection of step S4 of FIG. Explanatory drawing of determination processing of failure excitation impossible at clock-off of feed FF Explanatory drawing of failure impossible determination process based on failure that failed automatic test pattern generation Explanatory drawing of the judgment conditions in FIG. Explanatory drawing when automatic test pattern generation fails for a rise failure taking an AND gate as an example Block diagram of the path cut countermeasure part of FIG. Explanatory diagram of path cut countermeasures according to the present invention for nτ paths Explanatory diagram of two path cut countermeasures according to the present invention Explanatory drawing of the hyperplane with the number of undetectable faults in the discrete space used for selection from the invariant states 1 to 1 and 0 set as the path cut point Flowchart of path cut countermeasure processing according to FIG. Explanatory diagram of hazard-free by successful assignment of invariant state at pass cut point Explanatory drawing of narrowing trace stop processing in the present invention Illustration of narrowing trace stop condition Flow chart of automatic test pattern generation process using narrowing per pair failure target

Explanation of symbols

10: Overall control unit 12: Circuit data reading unit 14: Path cut countermeasure unit 16: Automatic test pattern generation unit (ATPG unit)
18: Failure simulation section

20: Circuit data writing unit 21: Automatic test pattern generation overall control unit (ATGP overall control unit)
22: 1st / 2nd failure selection unit 24: automatic test pattern generation core unit (ATGP core unit)
26: ATPG core overall control unit 28: narrowing mark processing unit 30: failure excitation unit 32: implication operation unit 34: condition solution state setting unit 36: failure propagation state setting unit 40, 42: preparation FF
44, 46, 76, 78, 84, 86, 88: Gate 48, 50, 90, 92, 94, 108, 110: Feed FF
52: NAND gate 54, 100: receiving FF
56, 62, 70, 80, 101, 180, 196, 208, 212: Fault assumption 58: Fault propagation 60, 64, 66, 96, 98: AND gate 102, 106, 182: Fault excitation state 218: Path cut Overall countermeasure control unit 220: Path cut point selection unit 222: Invariant state setting ATPG unit 224: Undetectable failure number measurement unit 226: nτ path 228: 1τ path

Claims (8)

On the computer,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF group, and the preparation FF group one stage before the feeding FF group,
A fault excitation step for assigning states representing the circuit states of fault excitation at the sending time and the receiving time;
A path activation step for allocating a state representing a circuit operation state for activating the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation step for generating a test pattern
And execute
Furthermore, as the path activation step, when the state is a transition from X to non-control value of the net,
A program for executing a step of activating a propagation path of a failure by allowing the don't care value X with respect to a sending time .
The program according to claim 1, wherein after the fault propagation step is completed,
A compaction failure excitation step of assigning the state changed to the inverted value of the state representing the circuit operating state at the time of receiving the don't care value X of the path activation step;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagating a state representing a circuit operating state for detecting a delay fault in a path between FFs,
A compaction fault propagation step for generating a test pattern composed of an input value for the sending FF group and an output value of the receiving FF group, which is an expected value for the input value, when the state propagation is successful; ,
A program characterized by having executed.
On the computer,
When failure propagation of a circuit that creates a test pattern for detecting a delay fault fails,
Of the faults assumed in the net from the fault assumption point on the net where the fault that failed in the fault propagation is assumed to the branch input of the fan-out free area where there is no circuit having a branch output,
By extracting a fault in which the inversion relationship between the failed fault and the fault value is equal and the fault value is equal to the control value of the gate,
A program for executing a step of excluding a fault assumed in the net as an undetectable fault.
On the computer,
In the gate input that drives the path cut point of the circuit that creates the test pattern for detecting the delay fault,
The path at the path cut point is a path in which transfer in one system cycle is not completed, and is an nτ path that does not constitute a loop.
By fixing the control value of the gate at the sending time and receiving time, the state representing the circuit operation state is fixed, or
Or, by giving a non-control value of the gate to all gate inputs at the sending time and receiving time,
A program for executing a step of fixing by assigning an invariant state having a change of 0 to 0 or 1 to 1 as a state representing the same-path operation state at the path cut point.
The program according to claim 4 , wherein
To a plurality of input pins in the driver side gate that drives the path cut point, between the sending time and the receiving time,
When there is a transfer with a change in the pin input position of the control value, by additionally assigning a control value at the feed time to at least one input pin to which the control value is given at the receiving time,
A program for executing a step of generating an invariant state that does not cause a hazard for the path cut point.
On the computer,
The back trace from the failure assumption point of the circuit for creating the test pattern for detecting the delay fault to the sending FF group via the receiving FF group, and the back trace from the sending FF group to the preparation FF group Mark the narrowing range by performing backtrace,
When the state representing the circuit operation state at the sending time and the receiving time of the net is not the don't care value X, the step of performing the narrowing to stop the execution of the back trace from the net is executed,
When one of the rising delay fault and falling delay fault of the same net fails to detect the delay fault,
By diverting the mark as it is without erasing the mark in the narrowing range marked in the narrowing backtrace,
Program characterized Rukoto to execute the test pattern generation and the other delay fault the delay fault is undetected as a target.
In a pattern creation method for creating a test pattern for detecting a delay fault in a circuit,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF group, and the preparation FF group one stage before the feeding FF group,
A fault excitation step for assigning a state representing a circuit operation state of fault excitation at a sending time and a receiving time;
A path activation step for allocating a state representing a circuit operation state for activating the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation step for generating a test pattern
And execute
Further, as the path activation step, when a state representing a circuit operation state for activating a failure propagation path after the change of the net is a state in which a transition from a don't care value X to a non-control value is performed,
A test pattern creation method, comprising: activating a failure propagation path by allowing the don't care value X with respect to a sending time .
In a pattern creation device for creating a test pattern for detecting a delay fault in a circuit,
The failure assumption point of the processing target circuit including the feeding FF group, the receiving FF, and the preparation FF group one stage before the feeding FF group,
A fault excitation unit for assigning a state representing a circuit operation state of fault excitation at a sending time and a receiving time;
A path activating unit that assigns a state representing a circuit operation state that activates the propagation path of the failure at a sending time and a receiving time to the remaining preparation FFs and sending FFs;
A system clock is supplied to the sending FF as a sending clock and changed from the sending FF to the net to be propagated, and a system clock is supplied to the receiving FF as a receiving clock to catch the net change. Propagate a state representing the circuit operating state for detecting a delay fault to the path between FFs,
When propagation of a state representing a circuit operating state for detecting the delay fault is successful, an input value for the sending FF group and a set of output values of the receiving FF group that are expected values for the input value A fault propagation unit that generates a test pattern
With
Further, when the state representing the circuit operation state for activating the propagation path of the failure after the change of the net is a state in which the state is changed from the don't care value X to the non-control value,
A pattern creation device that activates a propagation path of a failure by allowing the don't care value X with respect to a sending time .

Images