JP4433399B2 - Semiconductor device manufacturing method and three-dimensional semiconductor device - Google Patents

Semiconductor device manufacturing method and three-dimensional semiconductor device Download PDF

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JP4433399B2
JP4433399B2 JP2004353873A JP2004353873A JP4433399B2 JP 4433399 B2 JP4433399 B2 JP 4433399B2 JP 2004353873 A JP2004353873 A JP 2004353873A JP 2004353873 A JP2004353873 A JP 2004353873A JP 4433399 B2 JP4433399 B2 JP 4433399B2
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wiring board
semiconductor element
semiconductor
multilayer printed
double
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JP2006165236A (en
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浩之 平井
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東芝ディーエムエス株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、生産性に優れた半導体装置の製造方法及びその半導体装置を複数積層した三次元半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device excellent in productivity and a three-dimensional semiconductor device in which a plurality of semiconductor devices are stacked.

携帯電話やＰＤＡ等のモバイル用通信機器やノートパソコン等の電子機器の小型化、高機能化に伴い、これらを構成する電子部品の高密度実装対応が不可欠になっている。電子部品の高密度化は、従来より電子部品の小型化による部品端子のファインピッチ化や実装基板の配線パターンの微細化によって対応してきたが、半導体ベアチップや半導体パッケージ部品を三次元に積み重ねて実装効率を向上させた三次元モジュール構造が提案されている（例えば、特許文献１参照。）。   As mobile communication devices such as mobile phones and PDAs and electronic devices such as notebook computers become smaller and more functional, it is indispensable to support high-density mounting of electronic components constituting these devices. Higher density of electronic components has been supported by finer pitch of component terminals and miniaturization of wiring pattern of mounting board by miniaturization of electronic components, but it is mounted by stacking semiconductor bare chips and semiconductor package components in three dimensions. A three-dimensional module structure with improved efficiency has been proposed (see, for example, Patent Document 1).

特許文献１の従来技術では、半導体チップを搭載した複数の半導体パッケージを積層する際、半導体パッケージの接続ランド部に接合されるはんだボールによって一体化する構造である。このため、半導体チップ等の厚みが厚くなるにつれて、一体化するはんだバンプの径を大きくしなければならない。はんだバンプの径が大きくすることは、その分、実装面積が小さくなることから、その小さくなった実装面積では半導体チップ等を搭載することができなくなる。このため、半導体装置の外形を大きくして実装面積を確保しなければならない問題がある。   The conventional technology of Patent Document 1 has a structure in which a plurality of semiconductor packages having semiconductor chips mounted thereon are integrated by solder balls joined to connection land portions of the semiconductor package. For this reason, as the thickness of the semiconductor chip or the like increases, the diameter of the solder bump to be integrated must be increased. When the diameter of the solder bump is increased, the mounting area is reduced correspondingly, and therefore it becomes impossible to mount a semiconductor chip or the like with the reduced mounting area. For this reason, there exists a problem which must ensure the mounting area by enlarging the external shape of a semiconductor device.

また、基板に実装された半導体チップにワイヤボンディングを施し、更に、周辺の受動部品を構成するチップ部品と一緒に樹脂封止する場合には、その大きさに応じた金型を用いて樹脂封止しなければならず、金型作成に余計なコストが掛かる問題があった。
特開２００３−１８８３４２号公報（頁６、図１、図７） In addition, when wire bonding is performed on a semiconductor chip mounted on a substrate and further resin sealing is performed together with chip components constituting peripheral passive components, resin sealing is performed using a mold corresponding to the size. There was a problem that it took an extra cost to make the mold.
JP 2003-188342 A (page 6, FIG. 1, FIG. 7)

従来から、実装効率を向上させた三次元モジュール構造が提案されているが、半導体チップやチップ部品の厚みが厚くなるにつれて、一体化するはんだバンプの径を大きくしなければならないことから、実装面積を確保するために半導体装置の外形を大きくしなければならない問題があった。また、基板に実装された半導体チップやチップ部品を一緒に樹脂封止する場合には、その大きさに応じた金型を用いて樹脂封止しなければならず、金型作成に余計なコストが掛かる問題があった。   Conventionally, a three-dimensional module structure with improved mounting efficiency has been proposed, but as the thickness of the semiconductor bumps and chip components increases, the diameter of the integrated solder bumps must be increased. There is a problem that the outer shape of the semiconductor device has to be enlarged in order to ensure the above. In addition, when resin-sealing semiconductor chips and chip components mounted on a substrate together, they must be resin-sealed using a metal mold according to the size, which is an extra cost for mold production. There was a problem that took.

本発明は、上記問題点を解決するためになされたもので、多層プリント配線板の上にキャビティ付きの両面配線板を搭載して小型化を保ち、かつ生産性の良い半導体装置の製造方法及びその製造方法で得た半導体装置を積層した三次元半導体装置を提供することを目的とする。   The present invention has been made in order to solve the above-described problems. A method of manufacturing a semiconductor device that has a double-sided wiring board with a cavity mounted on a multilayer printed wiring board, maintains miniaturization, and has high productivity. An object is to provide a three-dimensional semiconductor device in which semiconductor devices obtained by the manufacturing method are stacked.

上記目的を達成するために、半導体装置の製造方法は、多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、前記多層プリント配線板の前記複数箇所の半導体素子取り付け部および両面配線板取り付け部に接続用フィルムを貼り付ける工程と、前記半導体素子取り付け部に第１半導体素子を仮置きし、前記第１半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面配線板を前記両面配線板取り付け部に仮貼り付けする工程と、前記第１半導体素子および前記両面配線板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、前記第１半導体素子の上に第２半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程とを有することを特徴とする。 In order to achieve the above object, a method for manufacturing a semiconductor device includes creating a plurality of semiconductor devices in which semiconductor elements and passive components are combined at least on one side of a multilayer printed wiring board, and separating the semiconductor devices into individual pieces. A method of manufacturing a semiconductor device, comprising: connecting the passive component to the plurality of locations of the multilayer printed wiring board; and attaching the semiconductor element mounting portions and double-sided wiring board mounting portions at the plurality of locations of the multilayer printed wiring board. A step of attaching a connection film; and a double-sided wiring board in which a first semiconductor element is temporarily placed on the semiconductor element mounting portion, and cavity portions are formed at a plurality of locations corresponding to the first semiconductor element and the passive component. the multilayer purine said the step of attaching temporarily attached to the double-sided wiring board mounting portion, collectively pressurizing and heating to the first semiconductor element and the double-sided wiring board A step of connecting to the wiring board; a second semiconductor element is mounted on the first semiconductor element to constitute the semiconductor element; and a wire is provided between the semiconductor element and the connection terminal portion on the multilayer printed wiring board. A step of resin-sealing the cavity portion after bonding connection; and a step of dividing into individual pieces after forming a solder bump for connection for each of the semiconductor devices sealed with the resin. .

また、半導体装置の製造方法は、多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、前記多層プリント配線板の前記複数箇所内の両面配線板取り付け部に接続用フィルムを貼り付ける工程と、前記複数箇所内の半導体素子取り付け部に金属製パンプ付きの第１半導体素子を仮置きし、前記第１半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面配線板を前記両面配線板取り付け部に仮貼り付けする工程と、前記第１半導体素子および前記両面配線板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、前記第１半導体素子の上に第２半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程とを有することを特徴とする。 Also, a method for manufacturing a semiconductor device is a method of manufacturing a semiconductor device by creating a plurality of semiconductor devices in which semiconductor elements and passive components are combined at a plurality of locations on at least one side of a multilayer printed wiring board, and dividing the semiconductor devices into individual pieces. The step of connecting the passive component to the plurality of locations of the multilayer printed wiring board, the step of attaching a connection film to the double-sided wiring board mounting portion in the plurality of locations of the multilayer printed wiring board, A double-sided wiring board in which a first semiconductor element with a metal bump is temporarily placed on a semiconductor element mounting portion in a plurality of locations, and a cavity portion is formed in a plurality of locations corresponding to the first semiconductor element and the passive component a step of attaching temporarily attached to the double-sided wiring board mounting portion, connected to the multilayer printed wiring board and collectively pressurizing and heating the first semiconductor element and the double-sided wiring board And a step of mounting a second semiconductor element on the first semiconductor element to constitute the semiconductor element, and wire bonding connection between the semiconductor element and a connection terminal portion on the multilayer printed wiring board. And a step of resin-sealing the cavity portion and a step of separating each of the semiconductor devices that are resin-sealed after forming solder bumps for connection.

本発明の半導体装置の製造方法によれば、半導体素子やチップ部品の厚みが厚くなってもキャビティ部が形成された両面配線板によって対処することができ、半導体装置の外形を大きくする必要がない。しかも、半導体素子および両面配線板を一括して加圧・加熱して多層プリント配線板に接続することができるため、生産性に優れている。また、基板上に実装された半導体素子やチップ部品を樹脂封止するための特別な金型も必要としない等の効果を有する。 According to the method for manufacturing a semiconductor device of the present invention, even if the thickness of a semiconductor element or chip part is increased, it can be dealt with by the double-sided wiring board in which the cavity portion is formed, and it is not necessary to increase the outer shape of the semiconductor device. . Moreover, since the semiconductor element and the double-sided wiring board can be collectively pressed and heated and connected to the multilayer printed wiring board, the productivity is excellent. In addition, there is an effect that a special die for resin-sealing a semiconductor element or chip component mounted on the substrate is not required.

以下、図面を参照して本発明の実施形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１（ａ）〜（ｇ）は、本発明の第１の実施形態に係る半導体装置の製造方法の各工程を示した図である。   FIGS. 1A to 1G are views showing respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

本発明は、多層プリント配線板の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であり、まず、表面と裏面および内層に所定のプリント配線が施された多層プリント配線板１０が用意される（図１（ａ））。ただし、図１では、一部の半導体装置だけを図示するものである。   The present invention is a method of manufacturing a semiconductor device by creating a plurality of semiconductor devices in which semiconductor elements and passive components are combined at a plurality of locations on a multilayer printed wiring board, and separating them into pieces. And the multilayer printed wiring board 10 by which predetermined printed wiring was given to the inner layer is prepared (FIG. 1 (a)). However, FIG. 1 shows only some semiconductor devices.

次に、多層プリント配線板１０の所定の配線位置に受動部品であるチップ部品１１をセットして、はんだ印刷・リフロー法にて接続固定する（図１（ｂ））。   Next, the chip component 11 which is a passive component is set at a predetermined wiring position of the multilayer printed wiring board 10 and is connected and fixed by a solder printing / reflow method (FIG. 1B).

次に、両面配線板用の取り付け部１２、および半導体素子の取り付け部１３に接続用フィルム１４を貼り付ける（図１（ｃ））。なお、両面配線板用の取り付け部１２の多層プリント配線板１０にはスルホール（図示せず）が形成されており、多層プリント配線板１０の表面と裏面および内層との間が電気接続可能に構成されている。   Next, the connection film 14 is affixed to the mounting portion 12 for the double-sided wiring board and the mounting portion 13 for the semiconductor element (FIG. 1C). A through hole (not shown) is formed in the multilayer printed wiring board 10 of the mounting portion 12 for the double-sided wiring board, and the front surface, the back surface, and the inner layer of the multilayer printed wiring board 10 can be electrically connected. Has been.

次に、下面にバンプが形成されている第１の半導体素子１５ａ（フリップチップ）を半導体素子の取り付け部１３の接続用フィルム１４上に位置合わせをして仮置きし、更に、半導体素子１５やチップ部品１１を収めるキャビティ部１６が形成された両面配線板１７を接続用フィルム１４上に仮貼り付けする（図１（ｄ））。この両面配線板１７は多層プリント配線板１０と同じ大きさであって、キャビティ部１６は半導体素子１５やチップ部品１１を囲う空洞である。なお、半導体装置１５は、第１の半導体装置１５ａと第２の半導体装置１５ｂによって構成されるものである。   Next, the first semiconductor element 15a (flip chip) having a bump formed on the lower surface is positioned and temporarily placed on the connection film 14 of the mounting portion 13 of the semiconductor element. A double-sided wiring board 17 on which a cavity 16 for accommodating the chip component 11 is formed is temporarily pasted on the connection film 14 (FIG. 1D). The double-sided wiring board 17 is the same size as the multilayer printed wiring board 10, and the cavity portion 16 is a cavity surrounding the semiconductor element 15 and the chip component 11. The semiconductor device 15 includes a first semiconductor device 15a and a second semiconductor device 15b.

また、両面配線板１７の両面配線板用の取り付け部１２に対向する両面に配線１７ａ、１７ｂが施されており、また、配線１７ａと１７ｂの間にはスルホール（図示せず）が形成されている。これにより、多層プリント配線板１０と両面配線板１７とが電気接続可能に構成されている。この両面配線板１７の高さを決める際には、半導体素子１５やチップ部品１１を収納するための高さを有するキャビティ部１６のものを選択すれば良く、これにより半導体素子１５やチップ部品１１の高さ変更にも容易に対処することが出来る。   Further, wirings 17a and 17b are provided on both sides of the double-sided wiring board 17 facing the mounting part 12 for the double-sided wiring board, and a through hole (not shown) is formed between the wirings 17a and 17b. Yes. Thereby, the multilayer printed wiring board 10 and the double-sided wiring board 17 are comprised so that electrical connection is possible. When the height of the double-sided wiring board 17 is determined, the cavity part 16 having a height for accommodating the semiconductor element 15 and the chip part 11 may be selected, whereby the semiconductor element 15 and the chip part 11 are selected. It is possible to easily cope with changes in height.

そして、図１（ｄ）で仮置きした第１の半導体素子１５ａと仮貼り付けした両面配線板１７に対し等方性プレスにより一括して加圧・加熱処理を施し、多層プリント配線板１０への接続を行う（図１（ｅ））。   Then, the first semiconductor element 15a temporarily placed in FIG. 1D and the double-sided wiring board 17 temporarily attached are subjected to pressure and heat treatment collectively by an isotropic press to obtain the multilayer printed wiring board 10. Are connected (FIG. 1 (e)).

次に、第１の半導体素子１５ａの上に第２の半導体素子１５ｂをマウントし、更に、第２の半導体素子１５ｂの端子と多層プリント配線板１０の接続端子部との間がワイヤボンディングによって配線接続される。また、キャビティ部１６内に収められた半導体素子１５とチップ部品１１をエポキシ樹脂１８などで樹脂封止し、多層プリント配線板１０の底面の配線部１９にはんだバンプ２０を施す（図１（ｆ））。   Next, the second semiconductor element 15b is mounted on the first semiconductor element 15a, and wiring between the terminal of the second semiconductor element 15b and the connection terminal portion of the multilayer printed wiring board 10 is performed by wire bonding. Connected. Further, the semiconductor element 15 and the chip component 11 housed in the cavity portion 16 are sealed with an epoxy resin 18 or the like, and solder bumps 20 are applied to the wiring portion 19 on the bottom surface of the multilayer printed wiring board 10 (FIG. )).

最後に、所定のサイズの半導体装置を形成するために、ダイサーやルーターなどと呼ばれる切削機で１つずつの個片に切断して半導体装置を製造する（図１（ｇ））。   Finally, in order to form a semiconductor device of a predetermined size, the semiconductor device is manufactured by cutting into individual pieces with a cutting machine called a dicer or a router (FIG. 1G).

図２は、図１（ａ）〜（ｇ）の工程で製造した半導体装置３０を３段積層してマスタ基板上に接続した三次元半導体装置の構成を示す図である。各半導体装置３０ａ〜３０ｃの間は、はんだバンプ２０を介して電気接続されている。   FIG. 2 is a diagram showing a configuration of a three-dimensional semiconductor device in which three stages of semiconductor devices 30 manufactured in the steps of FIGS. 1A to 1G are stacked and connected on a master substrate. The semiconductor devices 30a to 30c are electrically connected via solder bumps 20.

図３（ａ）〜（ｇ）は、本発明の第２の実施形態に係る半導体装置の製造方法の各工程を示した図である。この第２の実施形態では、半導体素子１５を多層プリント配線板１０に実装する方法が第１の実施形態と異なっている。   FIGS. 3A to 3G are views showing respective steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the second embodiment, the method of mounting the semiconductor element 15 on the multilayer printed wiring board 10 is different from that of the first embodiment.

即ち、第１の実施形態では、半導体素子１５を接続用フィルム１４を介して接続する構造であったが、この第２の実施形態でははんだバンプ５０によって接続する構造となっている。したがって、図１（ｃ）に対応する図３（ｃ）では、半導体素子１５が搭載される接続部１３ａには接続用フィルムが貼り付けされていない点が異なっている。そして、図３（ｄ）では、所定の位置にセットした金属製パンプ付きの第１の半導体素子１５ａと仮貼り付けした両面配線板１７に対し等方性プレスにより一括して加圧・加熱処理を施し、多層プリント配線板１０への接続を行う。その他の工程は、図１の対応する各工程と同様なので、その説明は省略する。   That is, in the first embodiment, the semiconductor element 15 is connected via the connection film 14. In the second embodiment, the semiconductor element 15 is connected by the solder bump 50. Therefore, FIG. 3C corresponding to FIG. 1C is different in that no connection film is attached to the connection portion 13a on which the semiconductor element 15 is mounted. In FIG. 3 (d), the first semiconductor element 15a with a metal pump set at a predetermined position and the double-sided wiring board 17 temporarily attached are collectively pressed and heated by an isotropic press. Then, connection to the multilayer printed wiring board 10 is performed. The other steps are the same as the corresponding steps in FIG.

図４は、本発明の第３の実施形態に係る半導体装置の製造方法によって得られた半導体装置６０を２段積層した３次元半導体装置の構成を示す図である。   FIG. 4 is a diagram showing a configuration of a three-dimensional semiconductor device in which semiconductor devices 60 obtained by the semiconductor device manufacturing method according to the third embodiment of the present invention are stacked in two stages.

即ち、この第３の実施形態では、各多層プリント配線板６１の両面に半導体素子１５やチップ部品１１を搭載し、その両面にキャビティ付の両面配線板６２ａ、６２ｂ、６３ａ、６３ｂを接続した構成である。なお、この時の両面配線板６２ａ、６２ｂ、６３ａ、６３ｂおよび半導体素子１５は一括して加圧・加熱が施されて多層プリント配線板１０に接続する方法が採用されている。 That is, in the third embodiment, the semiconductor element 15 and the chip component 11 are mounted on both surfaces of each multilayer printed wiring board 61, and double-sided wiring boards 62a, 62b, 63a, 63b with cavities are connected to both surfaces. It is. At this time, the double-sided wiring boards 62a, 62b, 63a, 63b and the semiconductor element 15 are collectively pressed and heated and connected to the multilayer printed wiring board 10.

本発明の半導体装置の製造方法によれば、半導体素子やチップ部品の厚みが厚くなってもキャビティ部が形成された両面配線板によって対処することができ、半導体装置の外形を大きくする必要がない。しかも、半導体素子および両面配線板を一括して加圧・加熱して多層プリント配線板に接続することができるため、生産性に優れている。また、チップ部品ははんだ印刷法によって接続実装できるので生産性に優れている。更に、基板上に実装された半導体素子やチップ部品を樹脂封止するための特別な金型も必要としない等の効果を有する。 According to the method for manufacturing a semiconductor device of the present invention, even if the thickness of a semiconductor element or chip part is increased, it can be dealt with by the double-sided wiring board in which the cavity portion is formed, and it is not necessary to increase the outer shape of the semiconductor device. . Moreover, since the semiconductor element and the double-sided wiring board can be collectively pressed and heated and connected to the multilayer printed wiring board, the productivity is excellent. Further, since chip parts can be connected and mounted by a solder printing method, they are excellent in productivity. Furthermore, there is an effect that a special mold for resin-sealing a semiconductor element or chip component mounted on the substrate is not required.

本発明の第１の実施形態に係る半導体装置の製造方法の各工程を示した図。The figure which showed each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 第１の実施形態の製造工程で製造した半導体装置を３段積層してマスタ基板上に接続した三次元半導体装置の構成を示す図。The figure which shows the structure of the three-dimensional semiconductor device which laminated | stacked three steps of semiconductor devices manufactured at the manufacturing process of 1st Embodiment, and connected on the master substrate. 本発明の第２の実施形態に係る半導体装置の製造方法の各工程を示した図。The figure which showed each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造方法によって得られた３次元半導体装置の構成を示す図。The figure which shows the structure of the three-dimensional semiconductor device obtained by the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１０‥多層プリント配線板
１１‥チップ部品（受動部品）
１３‥半導体素子の取り付け部
１４‥両面配線板の取り付け部
１５（１５ａ、１５ｂ）‥半導体素子
１６‥キャビティ部
１７‥両面配線板
１８‥エポキシ樹脂
１９‥接続部
２０、５０‥はんだバンプ
10. Multilayer printed circuit board 11. Chip component (passive component)
DESCRIPTION OF SYMBOLS 13 ... Semiconductor element attachment part 14 ... Double-sided wiring board attachment part 15 (15a, 15b) ... Semiconductor element 16 ... Cavity part 17 ... Double-sided wiring board 18 ... Epoxy resin 19 ... Connection part 20, 50 ... Solder bump

Claims (4)

多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、
前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、
前記多層プリント配線板の前記複数箇所の半導体素子取り付け部および両面配線板取り付け部に接続用フィルムを貼り付ける工程と、
前記半導体素子取り付け部に第１半導体素子を仮置きし、前記第１半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面配線板を前記両面配線板取り付け部に仮貼り付けする工程と、
前記第１半導体素子および前記両面配線板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、
前記第１半導体素子の上に第２半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、
前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device by creating a plurality of semiconductor devices by combining semiconductor elements and passive components at a plurality of locations on at least one side of a multilayer printed wiring board,
Connecting the passive component to the plurality of locations of the multilayer printed wiring board;
A step of attaching a connecting film to the semiconductor element mounting portion and the double-sided wiring board mounting portion of the multilayer printed wiring board;
A first semiconductor element is temporarily placed on the semiconductor element mounting portion, and a double-sided wiring board having cavities formed at a plurality of locations corresponding to the first semiconductor element and the passive component is temporarily attached to the double-sided wiring board mounting portion. A process of attaching,
Connecting the first semiconductor element and the double-sided wiring board to the multilayer printed wiring board by collectively pressing and heating;
The second semiconductor element is mounted on the first semiconductor element to constitute the semiconductor element, and the cavity portion is formed by wire bonding connection between the semiconductor element and the connection terminal portion on the multilayer printed wiring board. A step of resin-sealing,
A method of manufacturing a semiconductor device, comprising: forming a solder bump for connection for each of the resin-sealed semiconductor devices; 請求項１の製造方法によって製造され、前記多層プリント配線板の両面に前記半導体素子、前記受動部品、および前記キャビティ部が形成された前記両面配線板が接続された半導体装置が複数積層されて構成される三次元半導体装置。 A semiconductor device manufactured by the manufacturing method according to claim 1 , wherein a plurality of semiconductor devices in which the semiconductor element, the passive component, and the double-sided wiring board in which the cavity portion is formed are connected to both surfaces of the multilayer printed wiring board are stacked. Three-dimensional semiconductor device. 多層プリント配線板の少なくとも片面の複数箇所に半導体素子と受動部品とを組み合わせた複数の半導体装置を作成して、これを個片化して半導体装置を製造する方法であって、
前記多層プリント配線板の前記複数箇所に前記受動部品を接続する工程と、
前記多層プリント配線板の前記複数箇所内の両面配線板取り付け部に接続用フィルムを貼り付ける工程と、
前記複数箇所内の半導体素子取り付け部に金属製パンプ付きの第１半導体素子を仮置きし、前記第１半導体素子および前記受動部品に対応して複数箇所にキャビティ部が形成された両面配線板を前記両面配線板取り付け部に仮貼り付けする工程と、
前記第１半導体素子および前記両面配線板を一括して加圧・加熱して前記多層プリント配線板に接続する工程と、
前記第１半導体素子の上に第２半導体素子をマウントして前記半導体素子を構成し、前記半導体素子と前記多層プリント配線板上の接続端子部との間をワイヤボンディング接続した後に、前記キャビティ部を樹脂封止する工程と、
前記樹脂封止された前記半導体装置毎に接続用はんだバンプを形成した後に、前記個片化する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device by creating a plurality of semiconductor devices by combining semiconductor elements and passive components at a plurality of locations on at least one side of a multilayer printed wiring board,
Connecting the passive component to the plurality of locations of the multilayer printed wiring board;
A step of attaching a connection film to a double-sided wiring board mounting portion in the plurality of locations of the multilayer printed wiring board;
A double-sided wiring board in which a first semiconductor element with a metal bump is temporarily placed on the semiconductor element mounting portion in the plurality of locations, and cavity portions are formed at a plurality of locations corresponding to the first semiconductor element and the passive component. Temporarily pasting the double-sided wiring board mounting portion;
Connecting the first semiconductor element and the double-sided wiring board to the multilayer printed wiring board by collectively pressing and heating;
The second semiconductor element is mounted on the first semiconductor element to constitute the semiconductor element, and the cavity portion is formed by wire bonding connection between the semiconductor element and the connection terminal portion on the multilayer printed wiring board. A step of resin-sealing,
A method of manufacturing a semiconductor device, comprising: forming a solder bump for connection for each of the resin-sealed semiconductor devices; 請求項３の製造方法によって製造され、前記多層プリント配線板の両面に前記半導体素子、前記受動部品、および前記キャビティ部が形成された前記両面配線板が接続された半導体装置が複数積層されて構成される三次元半導体装置。 A semiconductor device manufactured by the manufacturing method according to claim 3 , wherein a plurality of semiconductor devices in which the semiconductor element, the passive component, and the double-sided wiring board in which the cavity portion is formed are connected to both surfaces of the multilayer printed wiring board are stacked. Three-dimensional semiconductor device.
JP2004353873A 2004-12-07 2004-12-07 Semiconductor device manufacturing method and three-dimensional semiconductor device Expired - Fee Related JP4433399B2 (en)

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