JP4429342B2 - Power saving driving method for mobile phone - Google Patents

Description

  The present invention relates to a power-saving driving method for a display device, and more particularly to a power-saving driving method for a display device that can be applied particularly effectively to a mobile phone equipped with a TFT-LCD (Thin Film Transistor Liquid Crystal Display). .

  In the mobile phone field, new multifunctional models are emerging one after another. While multi-functionalization is a request of the times, increasing the time that can be continuously used without charging continues to be required as a basic request. Therefore, various power saving measures have been proposed, and some have been implemented.

A mobile phone not only consumes power during a call, but also consumes power in a standby state. Looking at the portion of the cellular phone that consumes power, it can be divided into a control unit (CPU) that controls the entire cellular phone, a wireless communication unit that performs transmission and reception, and a display unit.
For example, in a foldable mobile phone in which the display unit is hidden when folded, the display unit is not driven when the mobile phone is in a folded state and is in a standby state to save power. Since the display unit cannot be seen in the folded state, the power saving measure of not driving the display unit is extremely effective and realistic.

However, ordinary mobile phones that do not hide the display require display such as time display and battery level display even when no operation is on standby, and most mobile phones on the market display time display. And the remaining battery level display.
Under such a request, in a mobile phone having an STN type liquid crystal display unit, in the no-operation standby state, only the time display and the remaining battery level display part are selectively driven without driving the entire liquid crystal display unit. It has been proposed to display.

On the other hand, the display part of a mobile phone is expected to shift from STN type liquid crystal display to TFT-LCD, coupled with demands for colorization, high definition, and moving image display. It is expected that the demand for power saving will be further strengthened because the power consumption is expected to increase with the increase in color, high definition and the adoption of TFT-LCD. However, since the TFT-LCD has a completely different driving technique from the STN type liquid crystal display, the above power saving measures for the STN type liquid crystal display unit cannot be applied to the TFT-LCD. For this reason, in order to save power of the TFT-LCD, it is currently possible to apply only a method that does not drive the entire display unit as disclosed in Japanese Patent Laid-Open No. 10-65598. However, with this method, it is not possible to respond to a request for display such as time display or battery remaining amount display in the no-operation standby state.
Japanese Patent Laid-Open No. 10-65598

  Accordingly, the present invention provides a TFT-LCD display device capable of reducing the power consumption of the TFT-LCD while enabling a necessary display in a non-operation waiting state in a mobile phone or the like equipped with the TFT-LCD. It is intended to provide a power saving driving method.

  According to the present invention, in a mobile phone having a liquid crystal display unit that is driven in a detailed display mode for displaying at all gradation levels, at least in a no-operation standby state, less power compared to the detailed display mode. There is provided a power-saving driving method for a mobile phone, characterized in that it is driven in a simple display mode in which the entire liquid crystal display unit is displayed by consumption.

  In the simple display mode, the entire liquid crystal display unit can be driven by reducing the number of gradations, or the entire liquid crystal display unit can be driven by reducing the liquid crystal driving voltage.

  As described above, in a mobile phone or the like, necessary display such as time display and remaining battery level must be performed even in a no-operation standby state. On the other hand, since the necessary amount of information is small, it is considered that there is room for adopting a simple display. Currently, in the operation state, for example, the display is performed with gradations of 8 gradations or more. However, the display such as the time display and the remaining battery level does not require clear or detailed display with gradations of 8 gradations or more.

Specifically, the time display, the remaining battery level, and the like can be sufficiently read even if the entire liquid crystal display unit is displayed with two gradations. Even in the case of colorization, eight colors can be displayed with two gradations of RGB. On the other hand, if the number of gradations is left as it is, the liquid crystal drive voltage is lowered, the difference between the gradation levels is reduced and the entire liquid crystal display unit is driven, the brightness is lowered and the contrast is lowered. A display such as the remaining battery level is sufficiently legible.
By reducing the number of gradations of the liquid crystal display in this way, power consumption of the operational amplifier constituting the analog buffer of the liquid crystal display device can be reduced, and power saving can be realized. In addition, by reducing the liquid crystal driving voltage of the liquid crystal display device, the amount of charge / discharge generated each time the displayed gradation level changes can be reduced, and power saving can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a first mode of a power saving driving method for a cellular phone according to the present invention. When the power of a mobile phone that is turned off is turned on, the mobile phone enters a no-operation standby state under the control of the monitoring unit (control unit) 11 in the mobile phone. In this state, the liquid crystal display of the mobile phone is driven in the simple display mode under the control of the monitoring unit (control unit) 11 in the mobile phone.
When a key of the mobile phone is operated, a call is made, or communication is performed, the mobile phone is placed in an operation state, a call state, or a communication state under the control of the monitoring unit (control unit) 11 in the mobile phone. When the mobile phone is placed in a state other than the no-operation standby state, the liquid crystal display is displayed in a detailed display mode for displaying at all gradation levels under the control of the monitoring unit (control unit) 11. When the key operation is finished or the call or communication is finished, the timer in the mobile phone is operated, and when a predetermined time elapses, the mobile phone is in a non-operation standby state under the control of the monitoring unit (control unit) 11. The liquid crystal display of the mobile phone is displayed in the simple display mode.

When the liquid crystal display of the mobile phone is in the detailed display mode, the TFT-LCD driving circuit drives the liquid crystal with an analog voltage corresponding to all gradation levels so that the display is performed at all gradation levels. It also includes the case where the liquid crystal is driven with a smaller number of analog voltages than the whole gradation level by frame rate control or the like.
On the other hand, when the liquid crystal display of the mobile phone is in the simple display mode, the TFT-LCD driving circuit drives the liquid crystal with two power supply voltages (for example, 5 V and 0 V) used in the driving stage, for example. Alternatively, when the liquid crystal display of the mobile phone is in the simple display mode, the TFT-LCD drive circuit drives the liquid crystal with a drive power supply voltage lower than the drive power supply voltage in the detailed display mode. For example, if the drive power supply voltage in the detailed display mode is 5V, which is the power supply voltage, the low drive power supply voltage can be 3V.

FIG. 2 is a diagram illustrating a second mode of the power-saving driving method for a mobile phone according to the present invention. This second mode is a modification of the first mode, and the monitoring unit (control unit) 11 in the mobile phone displays, for example, only character information and icons even in a state other than the no-operation standby state. The text mode and the image mode for displaying image information and the like can be discriminated. In the no-operation standby state, the liquid crystal display of the mobile phone is displayed in the simple display mode as in the first mode.
In the second aspect, even in a state other than the no-operation standby state, the monitor (control unit) 11 in the mobile phone places the liquid crystal display of the mobile phone in the simple display mode in the text mode, and details in the image mode. Put in display mode.

For example, when only character information is displayed, the contrast between the characters and the background is clear, so that even if displayed in the simple display mode, there is no problem in reading. On the other hand, the icon display on the menu screen is also designed and colored so that it is easy to see without using a lot of colors, so even if it is displayed in the simple display mode, there is no problem in reading. Here, such a display that does not necessarily require hundreds of colors or more of multicolor display is referred to as a text mode. In the text mode, even if displayed in the simple display mode, there is no problem in reading.
The determination of the text mode and the image mode by the monitoring unit (control unit) 11 is relatively easy to perform in association with a software tool for displaying an image. For example, in the text mode tool selection screen, when a tool that displays an image is activated, it can be easily realized by switching to the image mode so that all gradations can be displayed and returning to the text mode when the tool ends. Can do.

FIG. 3 is a diagram illustrating a third mode of the power-saving driving method for a mobile phone according to the present invention. The third aspect is a modification of the first aspect, and the basic operation is exactly the same, so the description of the basic operation is omitted.
In the third aspect, in a state other than the no-operation standby state, the mobile phone display unit is not seen, such as when the earphone sensor detects that the mobile phone is touching the ear during a call. When it is detected, the mobile phone's liquid crystal display is placed in the simple display mode. Thereby, further power saving can be achieved.

FIG. 4 is a block diagram of a data line driving circuit of a liquid crystal display device provided in a mobile phone in an embodiment in which the number of gradations is reduced and the entire liquid crystal display unit is driven in the simple display mode.
As shown in FIG. 4, the data line driving circuit includes a frame memory 18, a data latch 22, a D / A converter 24, a gradation voltage generation circuit 26, and an output circuit 28. In FIG. 4, the digital data corresponding to the display is written into the frame memory 18 according to the address, the digital data corresponding to each scanning line is sequentially read out from the frame memory 18 and sent to the data latch 22, and the D / D The gradation voltage corresponding to the digital data is selected by the A converter 24, amplified by the output circuit 28, and output to the data line. As shown in FIG. 4, in the data line driving circuit provided with the frame memory 18, when the same display is continuously performed, the same data as the previous frame can be read from the frame memory 18. Can be stopped, and power consumption accompanying data transfer can be reduced. The polarity inversion signal is a signal synchronized with AC driving for preventing deterioration of the liquid crystal, and is supplied to the gradation voltage generation circuit 26 and the output circuit 28. The gradation voltage generation circuit 26 can invert the gradation level in accordance with the polarity inversion signal and supply an analog voltage corresponding to the polarity to the D / A converter 24 for the same data. In FIG. 4, a characteristic configuration according to the present invention which is different from the prior art is an output circuit 28.

According to the present invention, the output circuit 28 incorporates a binary drive circuit 32 in addition to the conventionally known analog buffer 30 for each data line output S1, S2, S3. ) In response to the display mode switching signal from 11, the analog buffer 30 or the binary drive circuit 32 is operated.
In the detailed display mode, in response to the display mode switching signal from the monitoring unit (control unit) 11, the output circuit 28 puts the binary drive circuit 32 into a non-operating state and puts the analog buffer 30 into an operating state. Each analog buffer 30 receives the gradation voltage output from the D / A converter 24 and outputs, for example, a drive voltage of 8 gradation levels to the data line outputs S1, S2, S3,.
On the other hand, in the simple display mode, upon receiving a display mode switching signal from the monitoring unit (control unit) 11, the output circuit 28 puts the analog buffer 30 into a non-operating state and puts the binary driving circuit 32 into an operating state. The binary drive circuit 32 receives the most significant bit of the digital signal output from the data latch 22 to the D / A converter 24, and outputs a binary drive voltage to the data line outputs S1, S2, S3. To do.

  FIG. 5 shows a configuration of a gradation voltage generation circuit 26, a D / A converter 24 corresponding to one data line output S1, and an output circuit 28 in a data line driving circuit that performs 8-gradation display using 3-bit digital data. FIG. The gradation voltage generation circuit 26 has eight levels of gradation voltages V1 to V8 corresponding to 3-bit digital data, and V1> V2>...> V8 or V1 <V2 <.・ <V8. The D / A converter 24 is composed of a CMOS switch, selects a gradation voltage in accordance with the 3-bit digital signal output from the data latch 22, and outputs it to the analog buffer 30. Further, the most significant bit D0 of the 3-bit digital signal is supplied to the inverter constituting the binary drive circuit 32. In the description of each embodiment of the present invention, it is assumed that the most significant bit is a bit for selecting either the high voltage side half or the low voltage side half of all gradation levels.

The analog buffer 30 normally requires a steady idling current for maintaining the operation, but if the binary driving circuit 32 is configured by an inverter circuit, the binary driving circuit 32 does not require an idling current. Therefore, in the simple display mode, the analog buffer 30 is stopped and the inverter 32 is operated, so that the power consumption can be reduced by the static current consumption of the analog buffer.
Since the gradation voltage generation circuit 26 is generally configured to connect a number of resistors corresponding to the number of gradations in series, and to cause a current to flow through the series resistance, the gradation voltage is extracted from the intermediate tap. Furthermore, if the gradation voltage generation circuit 26 is also stopped (that is, if supply of current is stopped), power consumption in the gradation voltage generation circuit 26 is also reduced.
5 shows an example in which the D / A converter 24 is composed of a CMOS switch. However, the D / A converter 24 and the gradation voltage generation circuit 26 are configured to generate a gradation level using capacitive coupling. It can be replaced with an A converter and a gradation voltage generation circuit.

FIG. 6 is a detailed circuit diagram of a circuit corresponding to one data line output in the output circuit 28 including the polarity inversion signal.
The display mode switching signal controls the operation of the binary drive circuit 32A by controlling on / off of the switches 1 and 2, and shuts off the output of the analog buffer 30A by controlling the on / off of the switch 3, and also operates the analog buffer 30A. Control. The most significant bit signal and the polarity inversion signal are input to the exclusive NOR circuit 34, and the output thereof is supplied to the input of the inverter constituting the binary drive circuit 32A. Therefore, the binary drive circuit 32A outputs the power supply voltage VDD2 or VSS2 to the data line according to the most significant bit signal and the polarity inversion signal. On the other hand, the analog buffer 30A amplifies the gradation voltage selected according to the digital data and polarity in the D / A converter and outputs the amplified voltage to the data line.

Here, it is assumed that the detailed display mode is designated when the display mode switching signal is H, and the simple display mode is designated when the display mode switching signal is L.
In the detailed display mode, the display mode switching signal becomes H, the switch 3 is turned on to operate the analog buffer 30A, the switches 1 and 2 are turned off, the binary drive circuit 32A is stopped, and the output is set to the high impedance state. . When the analog buffer is configured to perform different operations depending on the polarity, the polarity buffer signal is received and the operation corresponding to the polarity is performed.
In the simple display mode, the display mode switching signal becomes L, the switch 3 is turned off to cut off the output of the analog buffer 30A, the analog buffer 30A is stopped, and the output is set to a high impedance state. On the other hand, when the switches 1 and 2 are turned on and the binary drive circuit 32A is operable, the binary drive circuit 32A is driven by the most significant bit signal and the polarity inversion signal.
As described above, in the detailed display mode, the output circuit 28 stops the inverter circuit constituting the binary drive circuit 32A, operates the analog buffer 30A, and outputs the gradation voltage corresponding to the polarity to the data line. On the other hand, in the simple display mode, the output of the analog buffer 30A and the idling current are stopped, the inverter circuit constituting the binary drive circuit 32A is operated, and the power supply is turned on according to the most significant bit signal and the polarity inversion signal of the digital data. The voltage VDD2 or VSS2 is output to the data line.

  Note that in the case where the analog buffer has a configuration that requires a data line precharge circuit, the binary drive circuit can also be used as a precharge circuit. In this case, in the detailed display mode (display mode switching signal = H), not only the switch 3 is turned on and the analog buffer is operated, but also the switches 1 and 2 are turned on only during a precharge period (precharge period). The binary drive circuit is also operated. In the simple display mode (display mode switching signal = L), the switch 3 is turned off, the analog buffer is stopped, and the binary drive circuit is operated not only in the precharge period but also in each horizontal period.

FIG. 7 is a block diagram showing an embodiment in the case of driving the entire liquid crystal display unit by lowering the liquid crystal driving voltage in the simple display mode. The same components as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.
As can be seen from the comparison between FIG. 4 and FIG. 7, in the example of FIG. 7, the output circuit 28 does not include a binary drive circuit. Instead, two different liquid crystal drive voltages VDD2 and VDD3 are alternatively supplied to the D / A converter 24 and the output circuit 28 via the liquid crystal drive voltage changeover switch 36. The liquid crystal drive voltage changeover switch 36 is controlled by a display mode changeover signal. Here, VDD2 is a liquid crystal drive voltage used in the detailed display mode, and VDD3 is a liquid crystal drive voltage used in the simple display mode, which is a voltage lower than VDD2. If VDD2 is 5V, VDD3 is 3V, for example. Alternatively, the logic power supply voltage VDD1 may be used as VDD3.

In the detailed display mode, the H-level display mode switching signal switches the liquid crystal drive voltage changeover switch 36 to the liquid crystal drive voltage VDD2, and supplies the liquid crystal drive voltage VDD2 to the D / A converter 24 and the output circuit 28. In the simple display mode, the L-level display mode switching signal switches the liquid crystal driving voltage switch 36 to the liquid crystal driving voltage VDD3 and supplies the low-voltage liquid crystal driving voltage VDD3 to the D / A converter 24 and the output circuit 28. . As a result, the brightness is lowered and the contrast is lowered, but the power consumption can be reduced.
Note that the configuration of FIG. 7 and the configuration of FIG. 4 can be combined, and power consumption can be further reduced.

FIG. 8 is a block diagram of a circuit corresponding to one data line output of the output circuit when the binary drive circuit described above is also used as a data line precharge circuit. In other words, as disclosed in Japanese Patent Application Laid-Open No. 11-119750 and Japanese Patent Application No. 11-145768 (there is no distinction between the detailed display mode and the simple display mode as in the present invention, In a normal display corresponding to the detailed display mode, in a driving circuit of a liquid crystal display device configured to precharge a data line at the beginning of one output period, the precharge circuit is It is an example used as a value driving circuit.
JP 11-119750 A Japanese Patent Application No. 11-145768

The output circuit shown in FIG. 8 includes an analog buffer 30B configured by connecting a buffer 10 having a strong step-down action and a buffer 20 having a strong step-up action in parallel, and a precharge circuit / binary drive circuit connected to the output of the analog buffer. 32B. The analog buffer 30B and the precharge circuit / binary drive circuit 32B are controlled by the display mode switching signal, the most significant bit signal, and the polarity inversion signal.
In the detailed display mode in which the display mode switching signal is H, when the grayscale voltage on the high voltage side is output, the switch 1 of the precharge circuit / binary drive circuit is turned on at the beginning of one output period, and the data line Is precharged to VDD2 and then the buffer 10 is operated to step down the voltage to a predetermined gradation voltage. At this time, the switch 2 of the precharge circuit / binary drive circuit is turned off and the buffer 20 is stopped.

In the detailed display mode in which the display mode switching signal is H, when the gradation voltage on the low voltage side is output, the switch 2 of the precharge circuit / binary drive circuit is turned on at the beginning of one output period, and the data line Is precharged to VSS2, and then the buffer 20 is operated to boost the voltage to a predetermined gradation voltage. At this time, the switch 1 of the precharge circuit / binary drive circuit is turned off and the buffer 10 is stopped. Note that VDD2 is higher than VSS2.
In the simple display mode in which the display mode switching signal is L, both the buffers 10 and 20 are stopped and only the precharge circuit / binary drive circuit is operated. The precharge circuit / binary drive circuit is operated not only in the precharge period but also in each output period.
Here, as in the example of FIG. 6, the polarity inversion signal and the most significant bit signal are combined into one control signal via the exclusive NOR circuit, and the analog buffer and the precharge circuit / binary drive circuit are combined. And control. For example, when both the polarity inversion signal and the most significant bit signal are at the L level or the H level, the switch 1 and the buffer 10 can be operated while the switch 2 and the buffer 20 are stopped. When one of the polarity inversion signal and the most significant bit signal is at L level and the other is at H level, the switch 2 and the buffer 20 can be operated, while the switch 1 and the buffer 10 are stopped.

FIG. 9 is a circuit diagram showing a specific example of the circuit of FIG. In the circuit of FIG. 9, each of the buffers 10 and 20 of the analog buffer 30B is configured by a conventionally known operational amplifier circuit having a phase compensation capacitor. In the operational amplifier of the buffer 10, the output amplification stage is composed of an N-channel transistor 40 and a constant current source 42, and the boosting action depends on the current controlled by the constant current source 42. Operation is possible. On the other hand, the output amplifier stage of the operational amplifier of the buffer 20 is composed of a P-channel transistor 44 and a constant current source 46, and the step-down operation depends on the current controlled by the constant current source 46, but the step-up operation is P-channel transistor 44. High speed operation is possible. By combining the buffers 10 and 20 with the precharge circuit / binary drive circuit, high speed operation is possible even if the idling currents of the buffers 10 and 20 are kept low, and an analog buffer with low power consumption is realized. be able to.
The buffers 10 and 20 and the precharge circuit / binary drive circuit of FIG. 9 are controlled by the display mode switching signal, the most significant bit signal, and the polarity inversion signal, as in the description of FIG. Each of the buffers 10 and 20 is provided with switches 48, 49, 50, 52, 53, 54 for cutting off the idling current, and the operation and non-operation of each buffer can be controlled by controlling on / off of the switches. Be controlled.

  FIG. 10 is a circuit diagram showing another specific example of the circuit of FIG. In the circuit of FIG. 10, each of the buffers 10 and 20 of the analog buffer 30B is configured by a drive circuit as disclosed in Japanese Patent Application No. 11-145768. Each of the buffers 10 and 20 is configured to use a source follower operation of a transistor. By combining the precharge circuit / binary drive circuit 32B, the buffers 10 and 20 can operate at high speed even if the idling current of each of the buffers 10 and 20 is kept low. Therefore, an analog buffer with low power consumption can be realized.

  In the buffer 20, a switch 111 is connected between VDD2 and the common gate of the transistors 101 and 102 in order to precharge the common gate of the NMOS transistors 101 and 102, and an output terminal T2 in order to precharge the output terminal T2. And a switch 112 are connected between VSS2 and VSS2. The drain of the transistor 101 is connected to VDD2 through the constant current source 103, and further connected to its own gate. Further, a switch 121 that can cut off a drain-source current of the transistor 101 is connected between the source of the transistor 101 and the input terminal T1. A constant current source 104 and a switch 122 are connected in series between the input terminal T1 and VSS2. The source of the transistor 102 is connected to the output terminal T2, and a switch 123 that can cut off the drain-source current of the transistor 102 is connected between VDD2 and the drain of the transistor 102, and the output terminal T2, VSS2 Between them, a constant current source 105 and a switch 124 are connected in series. The currents controlled by the constant current sources 103 and 105 are I11 and I13, respectively.

  In the buffer 10, a switch 211 is connected between VSS2 and the common gates of the transistors 201 and 202 in order to precharge the common gates of the PMOS transistors 201 and 202, and an output terminal T2 in order to precharge the output terminal T2. And a switch 212 is connected between VDD2 and VDD2. The drain of the transistor 201 is connected to VSS2 via the constant current source 203, and further connected to its own gate. Further, a switch 221 that can cut off a drain-source current of the transistor 201 is connected between the source of the transistor 201 and the input terminal T1. A constant current source 204 and a switch 222 are connected in series between the input terminal T1 and VDD2. The source of the transistor 202 is connected to the output terminal T2, and a switch 223 that can cut off the drain-source current of the transistor 202 is connected between VSS2 and the drain of the transistor 202, and the output terminal T2, VDD2 and Between them, a constant current source 205 and a switch 224 are connected in series. The currents controlled by the constant current sources 203 and 205 are I21 and I23, respectively.

  In the circuit of FIG. 10, the operation and non-operation of the switches 112 and 212 and the buffers 10 and 20 are controlled by the most significant bit of the digital signal and the polarity inversion signal as described above. In the detailed display mode, when the high voltage side gradation voltage is input as Vin, the switch 112 and all the switches in the buffer 10 are kept OFF during the output period, and the low voltage side gradation voltage is maintained. When the voltage is input as Vin, the switch 212 and all the switches in the buffer 20 are kept OFF during the output period.

  FIG. 11 is a timing diagram illustrating the operation of the circuit of FIG. 10 in the detailed display mode. FIG. 11 shows one output period (time t0-t3) for outputting an arbitrary gradation voltage on the low voltage side and one output period (time t0′-t3 ′) for outputting an arbitrary gradation voltage on the high voltage side. ) And two output periods. The operation will be described with reference to FIG. 11. At times t0 to t3, the switches 111, 112, 121, 122, 123, and 124 are controlled as shown in FIG. 11, and the switches 211, 212, 221, 222, and 223 are controlled. 224 are all turned off.

At time t0, the output voltage Vout is precharged to the voltage VSS2, while the common gate voltage V10 of the transistors 101 and 102 is precharged to the voltage VDD2. The precharge of the voltage V10 is completed at time t1, and after time t1, the voltage V10 changes to a voltage shifted from the input voltage Vin by the gate-source voltage Vgs101 (I11) of the transistor 101,
V10 = Vin + Vgs101 (I11)
It becomes stable at. Here, Vgs101 (I11) represents a gate-source voltage when the drain current is I11. The output voltage Vout precharged to the voltage VSS2 at time t0 is completed at time t2, and after time t2, changes to a voltage shifted from the voltage V10 by the gate-source voltage Vgs102 (I13) of the transistor 102. ,
Vout = V10−Vgs102 (I13)
It becomes stable at. Here, if the currents I11 and I13 are controlled so that Vgs101 (I11) and Vgs102 (I13) are both positive values, the output voltage Vout becomes equal to the input voltage Vin according to the above two equations. At this time, the output voltage range is
VSS2 ≦ Vout ≦ VDD2-Vgs102 (I13)
It becomes.

At time t0′-t3 ′, the switches 211, 212, 221, 222, 223, and 224 are controlled as shown in FIG. 11, and the switches 111, 112, 121, 122, 123, and 124 are all turned off.
At time t0 ′, the output voltage Vout is precharged to the voltage VDD2 at time t0, while the common gate voltage V20 of the transistors 201 and 202 is precharged to the voltage VSS2. At time t1 ′, the precharge of the voltage V20 is completed, and after time t1 ′, the voltage V20 changes to a voltage shifted from the input voltage Vin by the gate-source voltage Vgs201 (I21) of the transistor 201,
V20 = Vin + Vgs201 (I21)
It becomes stable at. The output voltage Vout precharged to the voltage VDD2 at time t0 ′ is precharged at time t2 ′, and is shifted from the voltage V20 by the gate-source voltage Vgs202 (I23) of the transistor 202 after time t2 ′. Change to
Vout = V20−Vgs202 (I23)
It becomes stable. Here, if the currents I21 and I23 are controlled so that Vgs201 (I21) and Vgs202 (I23) are both negative and equal, the output voltage Vout becomes equal to the input voltage Vin according to the above two equations. At this time, the output voltage range is
VSS2-Vgs202 (I23) ≦ Vout ≦ VDD2
It becomes.
It should be noted that when the gradation voltage on the low voltage side is lower than {VDD2-Vgs102 (I13)} and the gradation voltage on the high voltage side is higher than {VSS2-Vgs202 (I23)}, output is performed. The voltage range can be the power supply voltage range.

FIG. 12 is a timing diagram illustrating the operation of the circuit of FIG. 10 in the simple display mode. In the simple display mode, all the switches in the buffers 10 and 20 are kept OFF.
In one output period (time t0-t3) in which an arbitrary gradation voltage is output on the low voltage side, the switch 112 is turned on and the switch 212 is turned off throughout the entire period. In one output period (time t0′-t3 ′) in which the voltage is output, the switch 212 is turned on and the switch 112 is turned off over the entire period. That is, the precharge composed of the switch 112 and the switch 212 is used as a binary drive circuit.

The embodiments of the various drive circuits have been described above. However, these embodiments are based on the assumption that the polarity inversion signal is supplied to the gradation voltage generation circuit 26 and the output circuit 28 as shown in FIG. Is. However, the polarity inversion signal is supplied to the D / A converter 24 instead of being supplied to the gradation voltage generation circuit 26 and the output circuit 28, or is supplied to the data latch 22 to invert the digital data according to the polarity. There is also a drive circuit configured to do this. In the case of the drive circuit configured as described above, a configuration in which the polarity inversion signal is not necessarily supplied to the output circuit 28 is possible, and the drive circuits shown in FIGS. 5, 6, and 8 to 10 have the polarity inversion signal. It will be apparent to those skilled in the art that modifications can be made so as not to be subject to

As described above, the example in which the present invention is applied to the mobile phone has been described. For example, it can be applied to a wristwatch with a TFT-LCD display device.
The switching function between the simple display mode and the detailed display mode of the present invention can also be applied to a portable device with a TFT-LCD display device that does not have a telephone call function, and can reduce power consumption.

FIG. 13 is a diagram illustrating an aspect of the power saving driving method of the portable device of the present invention. When the power of the portable device in the power-off state is turned on, the portable device displays a menu screen on the display unit under the control of the monitoring unit (control unit) 11 in the portable device. Various software tools can be selected from the menu screen, and when the tool is finished, the menu screen returns. Further, when a predetermined time elapses in the non-operation state due to the operation of the timer, the power of the portable device is automatically turned off under the control of the monitoring unit (control unit) 11.
The monitoring unit (control unit) in the portable device is configured to be able to discriminate between a text mode that displays only character information, icons, and the like and an image mode that displays image information and the like when the portable device is powered on. . The monitoring unit (control unit) places the liquid crystal display of the portable device in the simple display mode in the text mode and the detailed display mode in the image mode. In the detailed display mode, display is performed at all gradation levels, and in the simple display mode, display is performed with a reduced number of gradations. This is because when only character information is displayed or when an icon is displayed on a menu screen, multi-color display of hundreds of colors or more is not necessarily required, and therefore, display with less power consumption is performed by reducing the number of gradations.

  Note that the determination of the text mode and the image mode by the monitoring unit (control unit) is relatively easy to perform in association with a software tool for displaying an image. For example, in the text mode tool selection screen, when a tool that displays an image is activated, it can be easily realized by switching to the image mode so that all gradations can be displayed and returning to the text mode when the tool ends. Can do.

Furthermore, in mobile devices equipped with a TFT-LCD display unit including a mobile phone, not only the simple display mode and the detailed display mode are automatically selected by the control of the monitoring unit (control unit) but also the user can The simple display mode and the detailed display mode can be freely selected. For example, even if the mobile device is set in the simple display mode in advance and the TFT-LCD display unit is driven in the simple display mode when used, the user can detail the mobile device every time or during use. You may make it switch to display mode. This setting or switching can be easily realized by those skilled in the art regardless of whether it is assigned to an operation button of the portable device or realized by software.
As a liquid crystal driving method in the simple display mode, the same methods as those in the embodiments of FIGS. 4 to 6 and FIGS. 8 to 12 can be used.

  As described above, according to the present invention, in the mobile phone having the liquid crystal display unit, the entire liquid crystal display unit is displayed in the simple display mode at least in the no-operation waiting state. In this simple display mode, the entire liquid crystal display unit is driven by reducing the number of gradations, or the entire liquid crystal display unit is driven by lowering the liquid crystal driving voltage. Such control can reduce the power consumption of the liquid crystal display unit in the no-operation standby state, while necessary displays such as a time display and a remaining battery level are displayed in a legible manner.

It is a figure illustrating the 1st aspect of the power-saving drive method of the mobile telephone of this invention. It is a figure illustrating the 2nd aspect of the power-saving drive method of the mobile telephone of this invention. It is a figure illustrating the 3rd aspect of the power-saving drive method of the mobile telephone of this invention. FIG. 11 is a block diagram showing an embodiment in the case of driving the entire liquid crystal display unit by reducing the number of gradations in the simple display mode. FIG. 3 is a circuit diagram showing a configuration of a gradation voltage generation circuit, a D / A converter corresponding to one data line output, and an output circuit in a data line driving circuit that performs 8-gradation display using 3-bit digital data. It is a detailed circuit diagram of a circuit corresponding to one data line output in an output circuit including a polarity inversion signal. FIG. 11 is a block diagram showing an embodiment in the case of driving the entire liquid crystal display unit by lowering the liquid crystal driving voltage in the simple display mode. It is a block diagram of a circuit corresponding to one data line output of an output circuit when the binary driving circuit described above is also used as a data line precharge circuit. It is a circuit diagram which shows the specific example of the circuit of FIG. FIG. 9 is a circuit diagram showing another specific example of the circuit of FIG. 8. FIG. 11 is a timing diagram illustrating the operation of the circuit of FIG. 10 in a detailed display mode. FIG. 11 is a timing diagram illustrating the operation of the circuit of FIG. 10 in the simple display mode. It is a figure illustrating the aspect of the power saving drive method of the portable device of this invention.

Explanation of symbols

1 switch 2 switch 3 switch 10 buffer 20 buffer

Claims (9)

It provided as a display portion of portable devices including mobile phones, in a thin film transistor liquid crystal display for driving the liquid crystal by a voltage signal corresponding to the gradation level, and the detailed display mode for displaying the entire display section at all gradation levels, 2 a simple display mode for displaying the entire display section at the gradation level, and a control unit which determines the display information, and outputs the mode switching signal to switch between the simple display mode and the detailed display mode in accordance with the display information, A data line driving circuit for receiving the digital data corresponding to the display information and the mode switching signal to drive the display unit,
The data line driving circuit includes an analog buffer and a binary voltage driving circuit each having an output connected to a data line of the display unit,
When the detailed display mode is selected by said mode switching signal, a gray-scale voltage selected by D / A converter in accordance with the digital data corresponding to the display information inputted to the analog buffer, the output of the analog buffer To drive the data line,
When the simple display mode is selected by the mode switching signal, a bit signal of the digital data is input to the binary driving circuit, the data line is driven by the output of the binary driving circuit, and the analog buffer A thin film transistor type liquid crystal display characterized in that the liquid crystal display is inactive. The mobile device is configured as a mobile phone, and in the no-operation standby state, the control unit selects the simple display mode, the data line driving circuit drives the data line by the output of the binary driving circuit, In a state other than the no-operation waiting state, the control unit selects the detailed display mode or the simple display mode according to the display information, and the data line driving circuit is configured to output the analog buffer or the binary driving circuit based on the output. 2. The thin film transistor type liquid crystal display according to claim 1, wherein the data line is driven. 3. The thin film transistor type liquid crystal display according to claim 1, wherein in the simple display mode, display is performed in eight colors according to RGB two gradation levels. The analog buffer TFT type liquid crystal display according to any one of claims 1 to 3, characterized in that it comprises an operational amplifier. The binary voltage driving circuit includes an inverter, the inverter, thin film transistor according to claim 1, any one of 4, characterized in that switches the voltage value according to the bit signal and the polarity inversion signal LCD display. The bit signal input to the binary drive circuit is a bit for selecting one of the half on the high voltage side and the half on the low voltage side among all the gradation levels of the thin film transistor type liquid crystal display. thin film transistor liquid crystal display according to any one of claims 1 to 5, wherein. The thin film transistor type according to any one of claims 1 to 6 , wherein switching between the detailed display mode and the simple display mode by the control unit is performed in association with an operation of a specific software tool. LCD display. Thin film transistor liquid crystal display according to any one of claims 1 to 6, the user and wherein the said can select the detailed display mode and free the simple display mode. The thin film transistor type liquid crystal display according to any one of claims 1 to 6 , wherein the control unit controls the simple display mode when the menu screen is based on icon display or character information.

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