JP4427885B2 - Voltage control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage control circuit, and more particularly to a voltage control circuit for a memory cell substrate of a capacity storage type semiconductor memory device.
[0002]
[Prior art]
Conventionally, semiconductor memory devices are widely used in various fields. Among these, dynamic RAM (hereinafter referred to as DRAM) is widely used as a main memory of a computer because of its high storage density and low cost per storage capacity.
[0003]
In such a DRAM, a bit line precharge potential of 1/2 Vcc level is used, and a cell plate potential (hereinafter referred to as VCP potential) corresponding to a counter electrode potential of a storage node is usually a 1/2 Vcc generation circuit (hereinafter referred to as HVcc). Circuit). The storage node stores data with a potential difference between 1/2 Vcc and Vcc or between 1/2 Vcc and GND.
[0004]
This VCP potential is generally controlled by the output characteristics of the HVcc circuit. FIG. 4 is an output characteristic diagram of a conventional HVcc circuit. In the HVcc circuit, if the VCP potential becomes higher than the 1/2 Vcc level for some reason, the current is pulled back to the 1/2 Vcc level. If the VCP potential becomes lower than the 1/2 Vcc level, a current is supplied to return to the 1/2 Vcc level. In the vicinity of ½ Vcc, there is a part called a dead zone in which there is almost no current capability (high impedance), and the VCP potential is maintained. This dead zone is set in a wide range so as not to increase the through current during standby.
[0005]
[Problems to be solved by the invention]
However, the conventional voltage control circuit has a problem in that fluctuations in the VCP potential cannot be suppressed and a malfunction occurs.
[0006]
A change in the VCP potential according to the operation of the DRAM will be described. FIG. 5 is a characteristic diagram of the VCP potential corresponding to the DRAM operation in the conventional voltage control circuit.
When the DRAM is in a standby state (a state in which power is turned on and there is no access), the internal operation for changing the VCP potential is not performed, so the VCP potential does not change.
[0007]
Subsequently, in the read state (the state where data is being read), the data (Vcc or GND) of the memory cell to be read and the data (Vcc) of the previous memory cell connected to the row address (word line). Or GND) are connected to the 1/2 Vcc level line all at once, so that VCP fluctuates temporarily. FIG. 5 shows a case where the data in the memory cell (storage capacity) is all 0 and a case where all 1 are stored. Each of them fluctuates temporarily to the high side (or low side) due to the pumping effect, but returns to the 1/2 Vcc level by the subsequent sensing operation. That is, if the relationship between the original VCP (1/2 Vcc) and the stored data potential (Vcc or GND) is maintained, the VCP fluctuation is restored. That is, if the VCP recovers while the row address is selected, data corruption does not occur.
[0008]
Next, in the write state (particularly in a state where reverse data is written), the reverse data is written in comparison with the data once read. To be exact, when bit line inversion is involved, a pumping effect is caused by the memory cell, and VCP fluctuates. This differs from the read operation in that there is no return of VCP due to the sensing operation. The principle of VCP fluctuation will be described. FIG. 6 shows a DRAM core circuit composed of 1Tr1CAP memory cells.
[0009]
The counter electrode potential of the storage capacity is VCP. A VCP is connected to a DRAM memory capacity, for example, a 16 Mbit DRAM if it is a 16 Mbit DRAM, and the total capacity is from several hundred pF to several thousand pF. For this VCP, the write operation of bit line inversion causes a pumping effect that acts through a storage capacity of several tens of fF. The variation ΔV of VCP in the pumping effect due to the write operation of 1-bit inverted data can be obtained by the following equation.
[0010]
[Expression 1]
ΔV = ((VCP total capacity × 0.5) + (storage capacity × 1)) ÷ (VCP capacity + storage capacity) (1)
For example, when the total capacity of VCP is 100 pF and the storage capacity is 20 fF, it can be seen that this corresponds to a fluctuation of about 0.02 percent with respect to 1/2 Vcc. When Vcc is 2V, the fluctuation is 0.2 mV. For example, here, if 2048 times (bits) of continuous inverted data write are performed, this corresponds to giving a fluctuation amount of 409 mV to VCP. When this variation is in the dead zone, it is difficult to replenish within a desired time (during row address selection).
[0011]
As described above, the 1-bit inverted data write has a slight fluctuation, but when continuously performed, the VCP fluctuation amount increases in a stacked manner. The maximum fluctuation amount (voltage) is a balance between the output characteristics of the HVcc circuit and the fluctuation amount, specifically, up to a full dead zone.
[0012]
A mechanism for destroying data stored by such a variation in VCP will be described. FIG. 7 is an example of data loss due to VCP fluctuation. First, write data 1 is written when the VCP potential fluctuates to the Vcc side dead zone (dead zone +) to the full by the continuous inversion data write of 1. After that, VCP fluctuates to the dead zone (dead zone-) on the GND side due to the continuous inverted data write of 0 of other bits. The data amount α is lost due to the fluctuation of the VCP. If the VCP potential at the time of writing is different from the VCP potential at the time of reading, there is a difference in the initial potential obtained by being connected by the bit line of 1/2 Vcc level, which causes data destruction.
[0013]
As described above, a large amount of variation in VCP causes a data error, but even if data destruction does not occur, a decrease in the initial potential caused by the loss of charge amount deteriorates the low voltage operation margin and the high speed margin. become.
[0014]
As means for suppressing VCP fluctuations caused by a write operation involving bit line inversion, a method of narrowing the dead band of the HVcc circuit and a method of adding a stabilization capacitor are general countermeasures. However, the technique of narrowing the dead zone increases unnecessary through current during standby or operation. In addition, although the method of adding the stabilizing capacity can suppress the instantaneous amount of VCP fluctuation, it does not have current supply capability, and therefore, the maximum amount of VCP fluctuation in question cannot be reduced. Furthermore, the layout area is increased.
[0015]
The present invention has been made in view of these points, and an object of the present invention is to provide a voltage control circuit that cancels fluctuations in the VCP potential and prevents malfunction.
[0016]
[Means for Solving the Problems]
In the present invention, in order to solve the above-mentioned problem, in the voltage control circuit of the memory cell substrate of the capacity storage type semiconductor memory device, the memory cell generated when new information is written to the information stored in the capacity A reverse potential fluctuation generation circuit that generates a predetermined potential fluctuation that cancels the potential fluctuation of the substrate; and an information inversion determination circuit that determines whether or not the newly written information is inverted with respect to the information accumulated in the capacitor. A drive signal selection circuit that drives the reverse potential fluctuation generation circuit so as to generate a potential fluctuation opposite to the potential fluctuation of the memory cell substrate in accordance with a judgment result of the information inversion judgment circuit. A voltage control circuit is provided.
[0017]
In the voltage control circuit having such a configuration, the potential fluctuation of the memory cell substrate occurs when new information is written to the information stored in the capacity of the memory cell substrate. The information inversion determination circuit determines whether newly written information is inverted with respect to the information stored in the capacitor, that is, whether inverted data is written, and sends the determination result to the drive signal selection circuit. . The drive signal selection circuit has a reverse potential according to the determination result of the information inversion determination circuit, that is, when reverse data is written, so as to generate a potential variation opposite to the potential variation of the memory cell substrate. Drives the fluctuation generation circuit. The reverse electron fluctuation generating means generates a potential fluctuation in the reverse direction that cancels the potential fluctuation generated during information writing in accordance with the drive signal of the drive signal selection circuit.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the configuration of the entire DRAM will be described. FIG. 1 is a configuration diagram of an entire DRAM incorporating a voltage control circuit according to an embodiment of the present invention.
[0019]
The DRAM according to the present invention includes a row address buffer 1, a row decoder 2, a row control 3, a column buffer 4, a memory array 5, a column control 6, a column decoder 7, a sense amplifier 8, an input / output buffer 9, and 1/2 Vcc generation. Circuit 10.
[0020]
A read operation, a write operation, and a standby operation in the DRAM having such a configuration will be described.
The read operation is an operation for reading data stored in the memory array 5 to the input / output buffer 9. First, an external signal is input from the RASB terminal connected to the row control 3 that controls the row address buffer 1 and the row decoder 2. An internal signal generated by the row control 3 in response to an external input signal holds the address input by the row address buffer 1, and the row address decoder 2 selects one word line on the memory array 5 based on the address. To do. All memory cells connected to the selected word line are amplified by the sense amplifier 8 to Vcc or GND level. At substantially the same time, an external signal is input from the CASB terminal connected to the column control 6. An internal signal generated by the column control 6 according to an external input signal holds an address in the column address buffer 4. The column decoder 7 sends the data of the corresponding address from the plurality of sense amplifiers 8 to the input / output buffer 9. The input / output buffer 9 outputs read data in response to the OEB signal. Thereby, data reading from the memory array 5 (AXn, AYn) is performed.
[0021]
Next, the write operation is an operation of writing data written in the input / output buffer 9 into the memory array 5 via the sense amplifier 8. An external signal is input from the RASB terminal connected to the row control 3. An internal signal generated by the row control 3 in response to an external input signal holds the address input by the row address buffer 1, and the row address decoder 2 selects one word line on the memory array 5 based on the address. To do. All memory cells connected to the selected word line are amplified by the sense amplifier 8 to Vcc or GND level. At substantially the same time, an external signal is input from the WEB terminal connected to the column control 6. The input / output buffer 9 holds write data by an internal signal generated by the column control 6 in response to an external input signal from the WEB terminal. In addition, writing is performed by forcibly transferring write data from the plurality of sense amplifiers 8 to the sense amplifiers 8 at the corresponding addresses by the column decoder 4.
[0022]
Next, the standby operation is an operation for holding data stored in the memory array 5. When the control signal input to RASB, CASB, OEB, and WEB is at a constant value of the normal Vcc level, all previous memory cell data is held.
[0023]
Next, a circuit for canceling the VCP fluctuation according to the present invention will be described. FIG. 2 is a circuit diagram of a voltage control circuit according to an embodiment of the present invention.
The voltage control circuit according to the present invention activates an information inversion determination circuit 11 that determines whether or not inverted data is written, and reverse potential fluctuation generation circuits 13a, 13b, 13d, and 13c according to the determination result of the information inversion determination circuit 11. Drive signal selection circuit 12, and reverse potential fluctuation generation circuits 13a, 13b, 13d, and 13c for connecting charge amounts for canceling VCP fluctuations.
[0024]
The information inversion determination circuit 11 inputs data obtained by reading 1-bit information stored in the capacitor and newly written 1-bit data, and obtains an exclusive OR of these data (hereinafter referred to as EXOR11). ). The EXOR 11 determines whether the read 1-bit data is 0 and the newly written 1-bit data is 1 and the read 1-bit data is 1 and the newly written 1-bit data is 0. Then, the determination result is output to the drive signal selection circuit 12 from the two terminals a and b corresponding to each case. The terminal a outputs 1 when 1-bit data is inverted from 0 to 1, and the terminal b outputs 1 when 1-bit data is inverted from 1 to 0.
[0025]
The drive signal selection circuit 12 performs logic corresponding to DRAM-specific region inversion using the determination result of the EXOR 11 and the two bit lines (BL and BLB), and the reverse potential fluctuation generation circuits 13a, 13b, 13c, Any one of 13d is selected and driven. In a DRAM using two bit lines (BL, BLB), a region inversion process is performed in which external data is treated as 1 even if it is 0. Specifically, it is composed of four AND circuits AND1, AND2, AND3, and AND4. AND1 has an input terminal connected to the b terminal and BLB of EXOR11, and drives the reverse potential fluctuation generation circuit 13a when the b terminal is 1 and BLB is 1, that is, when the BLB side is inverted from 1 to 0. The AND2 has an input terminal connected to the a terminal of the EXOR 11 and BL, and when the a terminal is 1 and BL is 1, that is, when the BL side is inverted from 0 to 1, the reverse potential fluctuation generation circuit 13b is driven. The AND3 has an input terminal connected to the a terminal of the EXOR 11 and the BLB. When the a terminal is 1 and BLB is 1, that is, when the BLB side is inverted from 0 to 1, the reverse potential fluctuation generation circuit 13c is driven. The AND 4 has an input terminal connected to the b terminal of the EXOR 11 and the BL, and drives the reverse potential fluctuation generating circuit 13d when the b terminal is 1 and the BL is 1, that is, when the BL side is inverted from 0 to 1.
[0026]
The reverse potential fluctuation generation circuits 13a, 13b, 13c, and 13d are positive or negative via a first switch circuit that is opened / closed by inverted signals (RST, RSTB) of the 1-bit information write control signal and the first switch circuit. And a second switch circuit that opens and closes by the drive output from the drive signal selection circuit 12 described above and applies the charge accumulated in the reverse potential generation capacitor to the memory cell substrate. And. Specifically, the reverse potential fluctuation generation circuit 13a is a second switch circuit that is opened and closed by a drive output from a transistor Q1, a reverse potential generation capacitor C1, and AND1, which is a first switch circuit opened and closed by RSTB. A certain transistor Q2 is connected in series with VCP. The reverse potential fluctuation generation circuit 13b includes a transistor Q4 that is a first switch circuit that is opened and closed by an RST, a transistor Q3 that is a second switch circuit that is opened and closed by a drive output from the reverse potential generation capacitor C2, and AND2. Are connected in series to the VCP. The reverse potential fluctuation generation circuit 13c includes a transistor Q5 which is a first switch circuit opened and closed by RSTB, a reverse potential generation capacitor C3, and a transistor Q6 which is a second switch circuit opened and closed by a drive output from AND3. Are connected in series to the VCP. The reverse potential fluctuation generation circuit 13d includes a transistor Q8 that is a first switch circuit that is opened and closed by an RST, a reverse potential generation capacitor C4, and a transistor Q7 that is a second switch circuit that is opened and closed by a drive output from the AND4. Are connected in series to the VCP.
[0027]
In the reverse potential fluctuation generation circuits 13a, 13b, 13c, and 13d having such a configuration, the reverse potential generation capacitors C1, C2, C3, and C4 are previously set to Vcc or Vcc by the inverted signals (RSTB and RST) of the write control signal. Precharged to GND level. The reverse potential generation capacitors C1, C2, C3, and C4 of the reverse potential fluctuation generation circuits 13a, 13b, 13c, and 13d selected by the AND1, AND2, AND3, and AND4 of the drive signal selection circuit 12 are connected to the VCP and the VCP potential. Fluctuations are offset.
[0028]
Next, the operation of the voltage control circuit having such a configuration will be described. FIG. 3 is a timing chart of the voltage control circuit according to the embodiment of the present invention. This is a timing chart when inverted data from 0 to 1 is written on the BL side.
[0029]
The reverse potential generation capacitors C1, C2, C3, and C4 are precharged to the VCC or GND level in advance by inverted signals (RST and RSTB) of the write control signal. For example, the reverse potential generation capacitor C2 of the reverse potential fluctuation generation circuit 13b is precharged between GND and Vcc. Since the inverted data of 0 to 1 is written on the BL side, the read data (Readdata) is 0 and the write data (Writedata) is 1, and the EXOR 11 detects the inverted write from 0 to 1, and the a terminal The output of (0 → 1) is set to 1. In the memory array 5, if the BL side is positive logic and 0 → 1 bit line inversion write is performed, the AND2 output of the drive signal selection circuit 12 becomes 1, and the reverse potential fluctuation generation circuit 13b is selected. As a result, the reverse potential generating capacitor C2 of the reverse potential fluctuation generating circuit 13b is connected to VCP. Since the reverse potential generation capacitor C2 of the reverse potential fluctuation generation circuit 13b is precharged between GND and Vcc, it functions to lower VCP by the amount of charge relative to VCP. In the calculation, if there is a capacity twice the storage capacity of the memory array 5, it can be canceled.
[0030]
The circuit described above is necessary for each bit to be written. For example, if the internal operation is 8 bits, 8 circuits are prepared and processing for each write data is performed. In addition, this circuit can obtain the effect regardless of where it is arranged in the DRAM circuit, and VCP fluctuation can be canceled by operating within the row address selection time.
[0031]
【The invention's effect】
As described above, according to the present invention, it is determined whether or not the inverted data is written, and the potential fluctuation in the direction opposite to the potential fluctuation caused when the inverted data is written is generated. Counteract.
[0032]
As described above, since it is possible to take a fundamental measure of canceling the VCP fluctuation, it is possible to prevent data destruction due to the VCP fluctuation.
Furthermore, unnecessary shoot-through current consumption in the HVcc circuit can be prevented, the layout area can be prevented from increasing by adding a stabilizing capacitor, VCP fluctuation due to high-speed write operation, and VCP fluctuation due to low-voltage write operation can be prevented.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an entire DRAM incorporating a voltage control circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a voltage control circuit according to an embodiment of the present invention.
FIG. 3 is a timing chart of a voltage control circuit according to an embodiment of the present invention.
FIG. 4 is an output characteristic diagram of a conventional HVcc circuit.
FIG. 5 is a characteristic diagram of a VCP potential corresponding to a DRAM operation in a conventional voltage control circuit.
FIG. 6 is a DRAM core circuit composed of 1Tr1CAP memory cells;
FIG. 7 is an example of data loss due to VCP fluctuation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Row address buffer, 2 ... Row address decoder, 3 ... Row control, 4 ... Column address buffer, 5 ... Memory array, 6 ... Column control, 7 ... Column address decoder, 8 ... Sense amplifier, 9 ... I / O buffer, DESCRIPTION OF SYMBOLS 10 ... 1 / 2Vcc generation circuit, 11 ... Information inversion determination circuit (EXOR), 12 ... Drive signal selection circuit, 13a, 13b, 13c, 13d ... Reverse potential fluctuation generation circuit

Claims (6)

In the voltage control circuit of the memory cell substrate of the capacity storage type semiconductor memory device,
A reverse potential fluctuation generating circuit that generates a predetermined potential fluctuation that cancels the potential fluctuation of the memory cell substrate that is generated when another information is newly written to the information accumulated in the capacitor;
An information inversion determination circuit for determining whether the newly written information is inverted with respect to the information stored in the capacitor;
A drive signal selection circuit for driving the reverse potential fluctuation generation circuit so as to generate a potential fluctuation opposite to the potential fluctuation of the memory cell substrate according to a judgment result of the information inversion judgment circuit;
A voltage control circuit comprising: The reverse potential fluctuation generation circuit includes a first switch circuit that is opened and closed by an information write control signal;
A reverse potential generating capacitor for accumulating positive or negative charges via the first switch circuit;
A second switch circuit that is opened and closed by a drive output from the drive signal selection circuit and applies the charge accumulated in the reverse potential generation capacitor to the memory cell substrate;
2. The voltage control circuit according to claim 1, wherein the voltage control circuit is configured by using a plurality of unit configuration circuits. The voltage control circuit according to claim 1, wherein the information inversion determination circuit is an exclusive logic circuit that compares information stored in the capacitor and the newly written information by exclusive OR. In the exclusive logic circuit, when the information stored in the capacity is 0 and the newly written information is 1, and when the information stored in the capacity is 1 and the newly written information is 0 4. The voltage control circuit according to claim 3, further comprising two output terminals corresponding to each case. The drive signal selection circuit generates a selection signal by performing a product logical synthesis of the logic output of the information inversion determination circuit, the bit line information in phase with the newly written information, and the inverted information thereof, and generates a selection signal according to the selection signal. 3. The voltage control circuit according to claim 2, wherein the second switch circuit in each unit circuit of the reverse potential fluctuation generation circuit is opened and closed. The reverse potential fluctuation generation circuit, the information inversion determination circuit, and the drive signal selection circuit have at least a number equal to the number of bits of a word of the capacity storage type semiconductor memory on or outside the capacity storage type semiconductor memory. The voltage control circuit according to claim 1.

Images