JP4425518B2 - Automatic offset correction integration circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integration circuit for automatically adjusting an offset (hereinafter referred to as zero point deviation) in integration of an electronic circuit or full-wave rectification / synchronous rectification.
[0002]
[Prior art]
In a DC amplifier such as an operational amplifier used in an electronic circuit, there is a so-called zero point shift that causes a shift in potential on the output side even though there is no input. In that case, if there is an input to the amplifier, an output corresponding to the input + zero point deviation appears in the output. Therefore, correct measurement cannot be performed without canceling the zero point deviation.
In order to eliminate the influence of the zero point deviation, conventionally, the offset was adjusted by using a semi-fixed resistor, etc., or an operational amplifier with good characteristics with little zero point deviation was used.
[0003]
[Problems to be solved by the invention]
However, the conventional method has a problem of high cost.
When adjusting the zero point deviation with a semi-fixed resistor, the cost of the semi-fixed resistor and the labor of adjustment were incurred. For example, every time a semi-fixed resistor is added to a 20 yen operational amplifier, the cost increases by 300 yen. In addition, the operational amplifier has a zero point shift over time, and regular adjustment is necessary to maintain accuracy.
When using an op amp with good characteristics with little zero point deviation, it was expensive. For example, an operational amplifier with a normal characteristic of 20 yen has a good characteristic of 2000 yen, and using a plurality of operational amplifiers is very expensive.
There is also a method of canceling the zero point deviation by using a circuit with zero point deviation, shorting the input signal terminal, reading the output value at that time, and subtracting it from the output value when the input signal is added. When used for measuring instruments, the measurement accuracy for each range is usually set to ±% of the maximum value for each range. If the zero point deviation is relatively larger than the input signal, The input signal to be measured must be measured in a range larger than the appropriate measurement range, and measurement in a large range will reduce the measurement accuracy for the input signal. Therefore, if the measurement error for the input signal is to be made the same even if the range is changed, it is necessary to design the parts and circuit configuration to be used with an accuracy of one rank, which is expensive.
[0004]
Accordingly, an object of the present invention is to provide an automatic zero-point correction integration circuit that automatically adjusts the zero-point deviation even if an inexpensive operational amplifier is used.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, in claim 1 of the present invention, in an integrating circuit configured using a differential amplifier,
As an input signal that is input to the inverting input terminal (−input terminal) of the differential amplifier via an integral input resistor,
Measurement input signal InS and input zero side signal In0
The measurement input signal InS and the input zero-side signal In0 are input via input switching means that can be switched and selected at predetermined time intervals .
In a current path proportional to the input signal flowing between the output terminal of the differential amplifier and the negative input terminal ,
At least the first path selector switch, the integrating capacitor C1, and the second path selector switch are connected in series,
By switching the route switching switches and the second path switching switch of the first, the direction of current flowing through the integrating capacitor C1, a first direction (forward direction) at predetermined time intervals a second direction ( Switch to the opposite direction)
In each current direction, a first integration circuit state and a second integration circuit state are formed, and an integration circuit is formed so that the voltage across the capacitor C1 for integration is obtained as an integration result.
The difference between (the voltage at the −input terminal of the differential amplifier) and (the voltage at the + input terminal of the differential amplifier) between the non-inverting input terminal (+ input terminal) and the −input terminal in the differential amplifier itself.
The first offset voltage (V1) represented by
Difference between (voltage of the electronic circuit ground) and (voltage of the input zero side) generated between the input zero side and the ground of the electronic circuit to which the positive input terminal of the differential amplifier is connected
The second offset voltage (V2) represented by
When said input switching means selects the measured input signal InS side, at which the flow through the measurement input signal InS and the integral input resistor integral capacitor C1 to the differential amplifier connected in a forward direction, A second integration circuit state is formed in which a current proportional to (the voltage of the measurement input signal InS −V2−V1 ) is passed and integration is performed at the integration time T2.
When said input switching means selects the signal In0 side, at which the flow through the integral input resistor and the signal In0 connecting the integrating capacitor C1 to the differential amplifier in the reverse direction, the (signal In0 voltage - V2-V1) to form a first integration circuit state integrated by the integration time T1 by supplying a current proportional,
After discharging the charges of the integration capacitor C1, so that the integration time is T1 = T2, in the second integration circuit with said first integrating circuit condition, it said by performing integration by the same time the An integration result obtained by removing the first offset voltage and the second offset voltage is obtained, and the voltage across the integration capacitor C1 is proportional to the difference between the voltage of the measurement input signal InS and the voltage of the input zero side signal In0. it is obtained by providing an automatic offset correction integration circuit, characterized in Rukoto obtain the first and the voltage which the second offset voltage is removed.
[0006]
Further, in claim 2, the integration times T1 and T2 are divided by the same even number, the divided individual times are set to TH and TL in time order, and the input signal is integrated as it is during the time TH, and the time TL 2. An automatic offset correction integration circuit according to claim 1 , wherein the integration is performed by inverting the input signal by a polarity inverting circuit using a differential amplifier during the interval, and the TH time and the TL time are alternately repeated. It is a thing.
[0007]
Further, in claim 3, the integration times T1 and T2 are each divided by the same even number, the divided individual times are TH and TL in time order, and the time TH and the time TL are one set, and two sets are provided. The signal inversion timing of one TH, TL and the other TH, TL is shifted by half the time TH, TL so that the switching of one TH and TL occurs in synchronization with the switching timing of T1 and T2. Each of the integration circuits is provided, and the input selection of the integration circuit selects the input signal as it is during each time TH, and selects the signal obtained by inverting the input signal by the polarity inversion circuit using a differential amplifier during each time TL. 3. The automatic offset compensation according to claim 2, wherein two integration capacitors of the two integration circuits are switched simultaneously and integrated at the same time. A positive integration circuit is provided.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0009]
FIG. 1 shows an integration circuit, which is usually configured by combining a differential amplifier (op amp) and a capacitor.
[0010]
FIG. 2 shows an integration output of a conventional integration circuit. The thick line is the integration output when there is no measurement input signal, and the value at the end of the integration is due to a so-called offset (zero point deviation). The thin line is the integrated output when there is a measurement input signal, and includes the integrated value due to the zero point shift described above.
[0011]
FIG. 4 shows an embodiment of the first invention of the present invention. In FIG. 4, A1 and A2 are differential amplifiers, and SW1 to SW4 are electronically controlled by a changeover switch. C1 is an integrating capacitor connected to the amplifier A2, and C1, R2, and A2 constitute an integrator. A1 is a so-called buffer amplifier that blocks the influence of the internal resistance of SW1 on the integrator. Initially, SW1 to SW4 are switched to the positions shown in the figure, and both ends of C1 and R2 discharge electric charges through SW2 to SW4. Next, SW2 is switched to the lower side of the figure while being connected to the input signal In0 (input zero) side. In this case, the short circuit at both ends of C1 and R2 is disconnected and integration is started. However, since the input is zero, a zero point shift due to the offset occurs in the output. After integration for the T1 time, the changeover switches SW3 and SW4 are inverted by the control signal DIR, and the integration capacitor is reversely connected to A2, and at the same time, the switch SW1 is switched to the measurement input signal InS and the integration is performed for T2 time. I do.
[0012]
FIG. 3 shows the state of the output Out at time T1 and time T2. At the end of the T1 time, the integral value due to the offset appears inverted as the connection polarity of C1 with respect to A2 is switched. At the time T2, the integrated value is integrated including the offset and the InS input signal. Since the offset is the same, if T1 and T2 are set to the same time, the offset is canceled at the beginning of T1 and at the end of T2, and only the integrated value at the time T2 corresponding to the input signal of InS is obtained. It is done.
[0013]
FIG. 5 shows an embodiment of the second invention of the present invention. In the embodiment shown in FIG. 5, a circuit composed of the differential amplifiers A11 and A12 and a changeover switch SW11 are inserted between the differential amplifiers A1 and A2. A11 is a polarity inversion circuit using a differential amplifier, and A12 functions as the same buffer as A1. FIG. 7 shows the relationship between the output of the Out terminal corresponding to FIG. 3 of the embodiment shown in FIG. 5 and the times T1 and T2. The relationship between the switching of SW1 to SW4 and the time of T1 and T2 is the same as in the first embodiment shown in FIG. As shown in FIG. 7, SW11 in FIG. 5 divides T1 time and T2 time into two even numbers, TH and TL, and integrates the selection signal as it is during switching time TH at each time. During the time TL, the selection signal is inverted and integration is performed. Such switching is used as a synchronous rectifier circuit. In T1 and T2, an input signal and an inverted signal of the input signal are selected by synchronous control so that TH time and TL time are alternately and continuously repeated. TH and TL are selected and used as a half-wave period of the AC signal. If the synchronization timing is set to the zero point of the AC signal, the output of A12 becomes a full-wave rectified waveform, and the output value of A2 can obtain a DC voltage proportional to the magnitude of the AC signal. Assuming that the inverting operational amplifier also has a zero point shift, the same control is performed during the integration of the T1 time and the integration of the T2 time. Accordingly, the amount of charge flowing into the capacitor C1 is the same. However, since C1 is reversely connected, it just exits and flows out, and the zero point deviation is corrected.
[0014]
FIG. 6 shows an embodiment of the third invention according to the present invention. As shown in FIG. 8, the switching timings TH1 and TL1 by SW11 and the switching times TH2 and TL2 by SW21 are switched to TH and TL as shown in FIG. The zero point shift is corrected by shifting the time by half. Such a circuit is a synchronous circuit that measures separately the alternating current that flows when the resistance and capacitance are combined with the AC voltage and how much the current due to the resistance component and how much the current due to the capacitance component is. It can be used for rectification.
[0015]
FIG. 9 shows an embodiment obtained by improving the first invention of the present invention. The difference from the first embodiment of FIG. 4 is that the part A1 in FIG. 4 is replaced with an internal circuit and SW32 is inserted between SW2 and A2. The internal circuit includes A1 in FIG. 4 and other peripheral circuits. In such an example, each time SW1 is switched, the signal may become unstable due to a transient phenomenon, and it may take some time to stabilize the circuit state according to the input signal. Therefore, in this embodiment, when switching the state from T1 to T2 in FIG. 3, the SW32 is disconnected so as to hold the output value of Out, and then the state is maintained (held) for a while after switching SW1 from In0 to InS. By entering the state of T2, integration is performed after stabilization, so that a correct value can be obtained. The output state of Out is shown in FIG.
[0016]
FIG. 11 shows an ideal full-wave rectified waveform. As described above, full-wave rectification is used to measure the magnitude of alternating current. In order to obtain an accurate full-wave rectified waveform with a measuring instrument or the like, a circuit using an operational amplifier is well known. However, as described at the beginning, an operational amplifier always causes a zero point shift due to an offset.
[0017]
FIG. 12 shows a full-wave rectified waveform when there is a zero point shift in a circuit using a normal operational amplifier.
While the negative side waveform needs to be inverted at the original AC ± center level, the level to be inverted shifts by the zero point deviation, and the positive side and negative side waveforms do not become equal. When the rectified waveform as shown in FIG. 12 is integrated, the integrated output becomes a value far from that when the accurate full-wave rectified waveform as shown in FIG. 11 is integrated, and the correct AC signal size cannot be obtained. In order to correctly measure the magnitude of the AC signal, the full-wave rectifier circuit must not have a zero point shift.
[0018]
FIG. 13 is a diagram showing an output waveform of A12 in the circuit of FIG. 5 which is the second embodiment of the present invention, and shows a case where the differential amplifier of A1 to A12 and the measurement input signal InS have a zero point shift. Show. The waveform in FIG. 13 is a combined waveform of the ideal full-wave rectification shown in FIG. 11 and the waveform in the case of synchronous rectification of the voltage drift (DC voltage) due to the zero point shift shown in FIG. Among these, if the waveform shown in FIG. 14 is integrated by the circuit shown in FIG. 5, the DC component is canceled and becomes zero. Therefore, the waveform integration of FIG. 13 is equal to the ideal full-wave rectification integration of FIG. Therefore, when the circuit of FIG. 5 is used as a full-wave rectifier circuit, a full-wave rectifier circuit that cancels up to the zero-point deviation of the measurement input signal InS without any zero-point deviation is obtained.
[0019]
By using the third invention of the present invention, it is possible to measure the leakage current of the resistance component and the leakage current of the capacitance component to the ground as well as the absolute value of the leakage current.
By using the second invention of the present invention, it is possible to realize a leakage ammeter that measures only the leakage current of the resistance component by eliminating the influence of the electrostatic capacitance of the leakage current.
[0020]
In the present invention, T1 = T2, TH = TL, TH1 = TL1, and TH2 = TL2, but what the present invention requires is to make them practically equal. This is because it may be difficult to be exactly equal. For example, when implemented with a timer, one may be odd and the other may be even.
[0021]
According to the present invention, an auto-zero integration circuit configured to select a plurality of input signals can be easily realized. The T1 time and T2 time of the present invention have been described in the order in which the T2 time comes after the T1 time. This order is because the maximum value of the integral value is smaller and the possibility of saturation is reduced. However, in the claims, the order of the two integrals is not touched, and either is acceptable. This is because the zero point can be corrected in exactly the same way even if the T1 time comes after the T2 time as long as the saturation does not occur during the integration.
[0022]
By making the integration times T1 and T2 an integer multiple of the noise period, the noise contained in the input signal InS is canceled. For example, by integrating for a multiple of 100 ms, it is possible to perform measurement that is not affected by the power line frequency 50 Hz or 60 Hz.
[0023]
【The invention's effect】
As described above, according to the first aspect of the present invention, an automatic offset correction integration circuit free from zero point deviation can be provided. In the example of FIG. 4, the zero point deviation can be eliminated with a cost increase of about 20 yen only by adding SW3 and SW4, which is economical. Moreover, the accuracy is good. It is possible to cope with changes in the value of capacitors and resistors. Any circuit can be used as the internal circuit in the example of FIG. Automatically responds to secular change of zero point deviation. As described above, according to the first aspect of the present invention, it is possible to provide an automatic offset correction integration circuit that completely solves the problem of zero point deviation and uses a low-cost component and that is highly accurate.
[0024]
According to the second and third aspects of the present invention, there are provided an automatic offset correction integration circuit with a synchronous rectification function and an automatic offset correction integration circuit with a quadrature synchronous rectification function that automatically cancels and measures alternating current with zero point deviation. it can. When used for full-wave rectification, the effect of zero point deviation is completely eliminated.
[Brief description of the drawings]
FIG. 1 is a diagram showing an integration circuit. FIG. 2 is a diagram showing an integration output of a conventional integration circuit. FIG. 3 is a diagram showing an integration output waveform of an auto-zero integration circuit according to claim 1. FIG. FIG. 5 is a diagram of the second embodiment. FIG. 6 is a diagram of the third embodiment. FIG. 7 is a diagram showing an integrated output waveform of the second embodiment. FIG. 9 is a diagram showing an integrated output waveform of the fourth embodiment. FIG. 9 is a diagram showing the integrated output waveform of the fourth embodiment. FIG. 11 is an ideal full-wave rectified waveform. [Figure 12] Diagram of full-wave rectification waveform when there is a zero point shift [Fig. 13] Diagram of waveform of synchronous rectification [Fig. 14] Diagram of DC component added by synchronous rectification [Explanation of symbols]
InS Measurement input signal In0 Zero input signal C1 Integration capacitor a C1 terminal b C1 terminal A Integration circuit terminal B Integration circuit terminal IA Current A1 to A22 due to zero point deviation Differential amplifier (op amp)
SW1 to SW31 changeover switch R1 to R21 Control signal R2 for changing the connection of the resistor DIR C1 The current direction I2 when the resistors I1 SW3 and SW4 are switched to the opposite side of the figure I2 SW3 and SW4 are connected as shown in the figure Current direction Out integral output TH, TL synchronous rectification time SW32 HOLD analog switch HOLD control signal internal circuit for holding

Claims (3)

In an integrating circuit configured using a differential amplifier,
As an input signal that is input to the inverting input terminal (−input terminal) of the differential amplifier via an integral input resistor,
Measurement input signal InS and input zero side signal In0
The measurement input signal InS and the input zero-side signal In0 are input via input switching means that can be switched and selected at predetermined time intervals .
In a current path proportional to the input signal flowing between the output terminal of the differential amplifier and the negative input terminal ,
At least the first path selector switch, the integrating capacitor C1, and the second path selector switch are connected in series,
By switching the route switching switches and the second path switching switch of the first, the direction of current flowing through the integrating capacitor C1, a first direction (forward direction) at predetermined time intervals a second direction ( Switch to the opposite direction)
In each current direction, a first integration circuit state and a second integration circuit state are formed, and an integration circuit is formed so that the voltage across the capacitor C1 for integration is obtained as an integration result.
The difference between (the voltage at the −input terminal of the differential amplifier) and (the voltage at the + input terminal of the differential amplifier) between the non-inverting input terminal (+ input terminal) and the −input terminal in the differential amplifier itself.
The first offset voltage (V1) represented by
Difference between (voltage of the electronic circuit ground) and (voltage of the input zero side) generated between the input zero side and the ground of the electronic circuit to which the positive input terminal of the differential amplifier is connected
The second offset voltage (V2) represented by
When said input switching means selects the measured input signal InS side, at which the flow through the measurement input signal InS and the integral input resistor integral capacitor C1 to the differential amplifier connected in a forward direction, A second integration circuit state is formed in which a current proportional to (the voltage of the measurement input signal InS −V2−V1 ) is passed and integration is performed at the integration time T2.
When said input switching means selects the signal In0 side, at which the flow through the integral input resistor and the signal In0 connecting the integrating capacitor C1 to the differential amplifier in the reverse direction, the (signal In0 voltage - V2-V1) to form a first integration circuit state integrated by the integration time T1 by supplying a current proportional,
After discharging the charges of the integration capacitor C1, so that the integration time is T1 = T2, in the second integration circuit with said first integrating circuit condition, it said by performing integration by the same time the An integration result obtained by removing the first offset voltage and the second offset voltage is obtained, and the voltage across the integration capacitor C1 is proportional to the difference between the voltage of the measurement input signal InS and the voltage of the input zero side signal In0. It said first and second automatic offset correction integration circuit, characterized in Rukoto obtain a voltage offset voltage is removed. The integration times T1 and T2 are divided by the same even number, and the divided individual times are set to TH and TL in time order, and the input signal is integrated as it is during the time TH, and during the time TL, the differential amplifier is used. 2. The automatic offset correction integration circuit according to claim 1, wherein the input signal is inverted by a polarity inversion circuit to perform integration, and TH time and TL time are alternately repeated. The integration times T1 and T2 are divided by the same even number, and the divided individual times are TH and TL in time order, and the time TH and the time TL are set as one set, and two TH, TL, The timing of signal inversion of the other TH and TL is shifted by half the time TH and TL so that the switching of one TH and TL occurs in synchronization with the switching timing of T1 and T2.
Each integration circuit is provided, and the input selection of the integration circuit selects an input signal as it is during each time TH, and selects a signal obtained by inverting the input signal by a polarity inversion circuit using a differential amplifier during each time TL. Like
3. The automatic offset correction integration circuit according to claim 2, wherein the integration capacitors of the two integration circuits are switched simultaneously and integrated at the same time.

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