JP4423994B2 - Power factor correction circuit - Google Patents

Description

  The present invention relates to a simple and inexpensive power factor correction circuit, and more particularly to the technology of its control circuit.

  FIG. 21 shows a configuration diagram of a conventional power factor correction circuit (Patent Document 1). In the power factor correction circuit shown in FIG. 21, a series circuit composed of a boost reactor L1, a switch Q1 composed of a MOSFET and the like, and a current detection resistor Rsh is provided at both ends of the output of the full-wave rectifier circuit B that rectifies the alternating voltage of the alternating current power supply Vac. It is connected. A series circuit composed of a diode Do and a smoothing capacitor Co is connected to both ends (between drain and source) of the switch Q1, and a load Ro is connected to both ends of the smoothing capacitor Co. The diode Do and the smoothing capacitor Co constitute a rectifying / smoothing circuit. The switch Q1 is turned on / off by PWM control of the control circuit 10.

  The current detection resistor Rsh is connected between the negative output terminal P2 of the full-wave rectifier circuit B and one end of the switch Q1 and one end of the smoothing capacitor Co, and detects an input current flowing through the full-wave rectifier circuit B.

  The control circuit 10 includes an output voltage detection operational amplifier 11, a multiplier 12, a current detection operational amplifier 13, and a pulse width modulator 14.

  The output voltage detection operational amplifier 11 amplifies an error between the voltage of the smoothing capacitor Co and the reference voltage Vref, generates an error voltage, and outputs the error voltage to the multiplier 12. The multiplier 12 multiplies the error voltage from the output voltage detection operational amplifier 11 by the full-wave rectified voltage from the positive-side output terminal P1 of the full-wave rectifier circuit B, and outputs the multiplied output voltage to the current detection operational amplifier 13.

  The current detection operational amplifier 13 amplifies an error between a voltage proportional to the input current detected by the current detection resistor Rsh and the multiplication output voltage from the multiplier 12, generates an error voltage, and pulses the error voltage as a comparison input signal. Output to the width modulator 14.

  The pulse width modulator 14 receives the triangular wave signal and the comparison input signal from the current detection operational amplifier 13, and is turned on, for example, when the value of the comparison input signal is equal to or larger than the value of the triangular wave signal, and the value of the comparison input signal is the triangular wave signal. For example, a pulse signal that is turned off when it is less than the value of is generated, and the pulse signal is applied to the gate of the switch Q1.

  That is, the full-wave rectified voltage obtained by rectifying the input voltage (AC voltage) of the AC power source Vac by the full-wave rectifier circuit B has a sine wave shape every half cycle. The multiplier 12 receives the half-cycle sine wave voltage from the full-wave rectifier circuit B, receives the voltage from the output voltage detection operational amplifier 11, and multiplies these two voltages to change the magnitude of the sine wave. Output. The current detection operational amplifier 13 compares the half-cycle sine wave voltage from the full-wave rectifier circuit B with the voltage Vrsh proportional to the current detection resistor Rsh generated by the input current so that the input current becomes a half-cycle sine wave. Is controlling. For this reason, since the input current flowing through the current detection resistor Rsh can be a sine wave similar to the input voltage of the AC power supply Vac every half cycle, the power factor can be improved.

  Next, the operation of the power factor correction circuit configured as described above will be described. First, when the switch Q1 is turned on, a current flows from B → L1 → Q1 → Rsh → B. This current increases linearly with time.

  Next, when the switch Q1 changes from the on state to the off state, the voltage of the switch Q1 rises due to the voltage induced in the boost reactor L1. Further, since the switch Q1 is turned off, the current flowing through the switch Q1 becomes zero. Further, a current flows through L1 → Do → Co, and power is supplied to the load Ro.

As a related technology of the conventional power factor correction circuit, for example, there is Patent Document 2.
JP 2000-37072 A (FIG. 5) Japanese Patent Laid-Open No. 3-284168 (FIG. 1)

  However, in the step-up type power factor correction circuit shown in FIG. 21, the voltage input from the AC power supply Vac is a high voltage such as AC100V or AC230V, so that the positive-side output terminal P1 of the full-wave rectifier circuit B is supplied to the multiplier 12. The supplied full-wave rectified voltage is also high. Therefore, in the actual power factor correction circuit, the full-wave rectified voltage output from the positive output terminal P1 of the full-wave rectifier circuit B is converted to a low voltage by resistance division and supplied to the multiplier 12. For this reason, there is a problem in that the loss of power is large and the efficiency is deteriorated, and parts having a large withstand voltage and shape must be used, and the circuit becomes expensive.

  It is an object of the present invention to provide a power factor correction circuit that can be made inexpensive by reducing the number of components and having a simple configuration, and that can reduce the number of wires.

  The present invention has the following configuration in order to solve the above problems. According to the first aspect of the present invention, a rectified voltage obtained by rectifying an AC power supply voltage of an AC power supply by a rectifier circuit is input to a series circuit of a boosting reactor and a main switch, and is turned on / off by the main switch. And a current detection means for detecting a current flowing through the AC power supply, a current flowing through the rectifier circuit, or a current flowing through the main switch. An error voltage generating means for amplifying an error between the output voltage and the first reference voltage to generate an error voltage; and an error between the voltage proportional to the current detected by the current detecting means and the second reference voltage Current detection amplifying means that outputs the current detection amplifying means, and the output of the current detection amplifying means is variable according to the value of the error voltage from the error voltage generating means, and the variable voltage is used as the second reference voltage A voltage variable means for outputting to the current detection amplifying means and a pulse signal whose pulse width is controlled according to the output value of the current detection amplifying means are generated, and the pulse voltage is applied to the main switch to generate the output voltage. And pulse width control means for controlling to a predetermined voltage.

  According to the first aspect of the present invention, since the output voltage is a direct current and substantially constant, and the input voltage is a half-wave sine wave, the output of the current detection amplification means (input of the pulse width control means) is half It becomes a sine wave. The voltage varying means varies the output of the current detection amplifying means according to the value of the error voltage (DC voltage) from the error voltage generating means, and changes the variable voltage to the second reference voltage (half-wave sine wave reference voltage). Is output to the current detection amplification means, so that the current detection amplification means amplifies the error between the voltage proportional to the current detected by the current detection means and the second reference voltage (half wave sine wave reference voltage). A sine wave is output to the pulse width control means. For this reason, the input current detected by the current detection means is a half-wave sine wave. That is, since the input current waveform and the input voltage waveform of the pulse width control means are similar, the power factor is improved. Further, by reducing the number of wirings, the circuit can be easily made into an IC, and an inexpensive IC can be provided.

  According to a second aspect of the present invention, in the power factor correction circuit according to the first aspect, a peak value of the current detected by the current detection unit is detected, and a voltage proportional to the peak value of the current is supplied to the current detection amplification unit. It has the peak detection means to output, It is characterized by the above-mentioned.

  According to a third aspect of the present invention, in the power factor correction circuit according to the first or second aspect, the voltage variable means divides the output voltage of the current detection amplification means by the error voltage of the error voltage generation means. It is characterized by comprising.

  According to a fourth aspect of the present invention, in the power factor correction circuit according to any one of the first to third aspects, the rectifying / smoothing circuit is a first series of a capacitor and a diode connected to both ends of the main switch. It is characterized by comprising a circuit and a second series circuit of a reactor and a smoothing capacitor connected to both ends of the diode.

  According to a fifth aspect of the present invention, in the power factor correction circuit according to any one of the first to third aspects, the rectifying and smoothing circuit is a first series of a capacitor and a reactor connected to both ends of the main switch. The circuit includes a second series circuit of a smoothing capacitor and a diode connected to both ends of the reactor.

  According to a sixth aspect of the present invention, there is provided a first series circuit of an AC power supply and a boosting reactor, and a bridge connected to both ends of the first series circuit and comprising a first diode, a second diode, a first switch, and a second switch. A smoothing capacitor connected to a connection point between the circuit, the first diode and the second diode, and a connection point between the first switch and the second switch, and the first switch and the second switch A power factor correction circuit for obtaining a DC output voltage as well as improving the power factor of the AC power supply by simultaneously turning on and off the switch, current detection means for detecting the AC power supply current of the AC power supply, and the current A rectifying circuit for rectifying the AC power supply current detected by the detecting means, an error voltage generating means for amplifying an error between the output voltage and the first reference voltage and generating an error voltage, and rectified by the rectifying circuit. Current detection amplification means for amplifying and outputting an error between the voltage proportional to the measured current and the second reference voltage, and the output of the current detection amplification means is variable in accordance with the value of the error voltage from the error voltage generation means. A voltage variable means for outputting the variable voltage as the second reference voltage to the current detection amplification means, and a pulse signal whose pulse width is controlled according to the value of the output of the current detection amplification means, the pulse signal And pulse width control means for controlling the output voltage to a predetermined voltage by applying the voltage to the first switch and the second switch.

  The invention of claim 7 is connected to both ends of a rectifier circuit that rectifies an AC power supply voltage of an AC power supply, and includes a first series circuit of a boost reactor, a first switch, a third switch, and current detection means, and the boost reactor. A second series circuit of a second switch and a fourth switch, a first switch and a third switch connected to a connection point of the first switch and a connection point of the third switch and the current detection means; A rectifying / smoothing circuit for rectifying and smoothing the voltage of the primary winding of the transformer connected to the connection point of the switch, the connection point of the second switch and the fourth switch, and the output winding on the secondary side of the transformer A power factor correction circuit for improving the power factor of the AC power source by turning on / off the first switch to the fourth switch and obtaining a DC output voltage, wherein the output voltage and the first switch Error from 1 reference voltage Error voltage generating means for amplifying and generating an error voltage, current detection amplifying means for amplifying and outputting an error between a voltage proportional to the current detected by the current detecting means and the second reference voltage, and the current detection A voltage varying means for varying the output of the amplifying means in accordance with the value of the error voltage from the error voltage generating means and outputting the variable voltage as the second reference voltage to the current detecting amplifying means; and the current detecting amplifying means Pulse width control means for generating a pulse signal whose pulse width is controlled in accordance with the output value of the output, a pulse inversion signal obtained by inverting the pulse signal, and generating one of the pulse signal or the pulse inversion signal as the second signal. Applying the other of the pulse signal or the pulse inverted signal to the first switch and the fourth switch, and applying the other to the first switch and the previous switch. Characterized by a switch control means for controlling the output voltage to a predetermined voltage by turning on / off control of the fourth switch.

  The power factor correction circuit according to any one of claims 1 to 7, wherein the voltage varying means includes a first main electrode, a second main electrode, and a control electrode. A semiconductor element having a resistance value changed by a voltage applied to the control electrode; and a fixed resistor having one end connected to the first main electrode of the semiconductor element, and the current detection amplification at the other end of the fixed resistor The output voltage of the means is input, and the error voltage of the error voltage generating means is applied to the control electrode of the semiconductor element.

  A ninth aspect of the present invention is the power factor correction circuit according to any one of the first to seventh aspects, wherein the voltage varying means includes a first main electrode, a second main electrode, and a control electrode. A semiconductor element having a resistance value changed by a voltage applied to the control electrode, and an operational amplifier having an inverting terminal connected to the first main electrode of the semiconductor element and a feedback resistor connected to the inverting terminal and the output terminal; The output voltage of the current detection amplification means is input to the second main electrode of the semiconductor element, and the error voltage of the error voltage generation means is applied to the control electrode of the semiconductor element. To do.

  According to the present invention, it is possible to provide an inexpensive power factor correction circuit by reducing the number of parts and providing a simple configuration. Further, by reducing the number of wirings, the circuit can be easily made into an IC, and an inexpensive IC can be provided.

  Embodiments of a power factor correction circuit according to the present invention will be described below in detail with reference to the drawings.

  The power factor correction circuit of the first embodiment shown in FIG. 1 differs from the conventional power factor correction circuit shown in FIG. 21 only in the configuration of the control circuit 10a.

  The other configuration shown in FIG. 1 is the same as the configuration shown in FIG. 21, and thus the same reference numerals are given to the same parts, and detailed descriptions thereof are omitted.

  The control circuit 10 a includes an output voltage detection operational amplifier 11, a multiplier 12, a current detection operational amplifier 13, and a pulse width modulator 14.

  The output voltage detection operational amplifier 11 amplifies an error between the voltage of the smoothing capacitor Co and the reference voltage Vref, generates an error voltage, and outputs the error voltage to the multiplier 12. The multiplier 12 multiplies the error voltage from the output voltage detection operational amplifier 11 by the output of the current detection operational amplifier 13 (input of the pulse width modulator 14), and outputs the multiplied output voltage to the current detection operational amplifier 13.

  The current detection operational amplifier 13 amplifies an error between a voltage proportional to the input current detected by the current detection resistor Rsh and the multiplication output voltage from the multiplier 12, generates an error voltage, and pulses the error voltage as a comparison input signal. Output to the width modulator 14. Further, the current detection operational amplifier 13 feeds back the generated error voltage to the multiplier 12 as described above.

  In the first embodiment, the multiplier 12 is used as voltage varying means for varying the output of the current detection operational amplifier 13 in accordance with the error voltage from the output voltage detection operational amplifier 11, but instead of the multiplier 12, A divider or a variable gain amplifier can be used. A specific example of the variable gain amplifier will be described later.

  As shown in FIG. 2A, the pulse width modulator 14 inputs a triangular wave oscillator 141 that generates a triangular wave signal, and a triangular wave signal from the triangular wave oscillator 141 to the + terminal, and a comparison input from the voltage detection operational amplifier 13. When the signal is input to the-terminal and the value of the triangular wave signal is greater than or equal to the value of the comparison input signal, for example, it is on (H level), and when the value of the triangular wave signal is less than the value of the comparison input signal, for example And a comparator 142 that controls the output voltage of the smoothing capacitor Co to a predetermined voltage by applying the pulse signal to the gate of the switch Q1.

  FIG. 4A and FIG. 4B are diagrams showing an example of input / output characteristics of the pulse width modulator. FIG. 4A shows input / output characteristics of the pulse width modulator in which the input voltage Es and the duty cycle D are in a proportional relationship, and the relationship Es = D is satisfied. FIG. 4B shows input / output characteristics of the pulse width modulator in which the input voltage Es and the duty cycle D have a relationship of Es = 1−D.

  In the pulse width modulator 14 shown in FIG. 2A, the input / output waveform is a waveform like “output 1” in FIG. 3, and the input / output characteristics of the pulse width modulator 14 are as shown in FIG. 4A. It becomes a characteristic.

  The comparator 142 generates a pulse signal that is on, for example, when the value of the comparison input signal is greater than or equal to the value of the triangular wave signal, and that is off, for example, when the value of the comparison input signal is less than the value of the triangular wave signal. A signal may be applied to the gate of the switch Q1 to control the output voltage of the smoothing capacitor Co to a predetermined voltage. In other words, if “+” and “−” of the input terminal of the comparator 142 shown in FIG. 2A are connected in reverse, the output voltage is inverted, and the input / output waveform is a waveform like “output 2” in FIG. Thus, the input / output characteristics are as shown in FIG.

  FIG. 2B shows another configuration example of the pulse width modulator 14a. The pulse width modulator 14 a is such that the comparison input signal is inverted by an inverter 143 composed of an operational amplifier and supplied to the negative terminal of the comparator 142. The inverter 143 has a resistor r2 connected between the output terminal and the − terminal, a comparison input signal is input to the − terminal via the resistor r1, and a voltage divided by the resistor r3 and the resistor r4 is input to the + terminal. And the inverted output is output to the negative terminal of the comparator 142.

  According to such a configuration, when the voltage of the comparison input signal is low, the voltage at the negative terminal of the comparator 142 is high, so that the input / output characteristics of the pulse width modulator 14a are as shown in FIG. Cycle D becomes smaller. When the “+” and “−” of the input terminal of the comparator 142 shown in FIG. 2B are connected in reverse, when the voltage of the comparison input signal is high, the voltage of the − terminal of the comparator 142 becomes low. The input / output characteristics of the device 14 are as shown in FIG. 4A, and the duty cycle D increases when the comparison input signal is at a low voltage.

  Next, the operation principle of the power factor correction circuit according to the first embodiment will be described. Here, the operation of the control circuit 10a will be described.

  First, it is assumed that the current of the boost reactor L1 continuously flows, and the duty cycle in which the switch Q1 is turned on (T1 is the switching cycle of the switch Q1, and T2 is the on-time of the switch Q1). / T1) is D, the relationship between the input voltage Ei that is the voltage across the full-wave rectifier circuit B and the output voltage Eo that is the voltage across the load Ro is Eo / Ei = 1 / (1 -D).

  Further, assuming that the characteristic of the pulse width modulator 14 is as shown in FIG. 3 and Es is the input voltage of the pulse width modulator 14, Es = 1-D, so Es = 1-D = Ei. / Eo.

  Since the output voltage Eo is a direct current and has a substantially constant value, and the input voltage Ei is a half-cycle sine wave, the input voltage Es is an amplified output of the current detection operational amplifier 13 and becomes a half-cycle sine wave. The multiplier 12 varies the output of the current detection operational amplifier 13 in accordance with the value of the error voltage (DC voltage) from the output voltage detection operational amplifier 11, and changes the variable voltage to the second reference voltage (half-wave sine wave reference voltage). ) To the current detection operational amplifier 13. The current detection operational amplifier 13 amplifies an error between the voltage Vrsh proportional to the current detected by the current detection resistor Rsh and the half-wave sine wave reference voltage, and outputs the half-wave sine wave to the pulse width modulator 14. For this reason, the input current detected by the current detection resistor Rsh is a half-wave sine wave. Therefore, the input current flowing through the current detection resistor Rsh becomes a half-wave sine wave in proportion to the input voltage Ei, so that the power factor can be improved.

  Further, since the output voltage from the output voltage detection operational amplifier 11 is input to the other input terminal of the multiplier 12, the multiplier 12 has a gain (in accordance with the value of the output voltage from the output voltage detection operational amplifier 11 ( Output). For this reason, the magnitude of the half-wave sine wave voltage input to the pulse width modulator 14 can be changed.

  If the output voltage Eo decreases for some reason, the output voltage detection operational amplifier 11 decreases the output voltage according to the decrease in the output voltage Eo. Since the multiplier 12 reduces the gain (output) due to the decrease in the output voltage of the output voltage detection operational amplifier 11, the comparison input signal output from the current detection operational amplifier 13 also decreases, and the pulse width modulator 14 The average duty cycle D of the pulse signal is increased by lowering the comparison input signal from the detection operational amplifier 13 (in the case of output 1 shown in FIG. 3). For this reason, since the ratio of the time for which the switch Q1 is on increases and the input current increases, the output voltage Eo rises and the output voltage Eo is held constant.

  Next, the overall operation of the power factor correction circuit will be described with reference to the waveforms of the respective parts in FIG. First, when a sine wave input voltage Vi of the AC power supply Vac is input, a sine wave input current Ii flows. Then, the input voltage Vi of the AC power supply Vac is rectified by the full-wave rectifier circuit B, and the full-wave rectified voltage Ei is output.

  Next, when the switch Q1 is turned on, a current flows through B → L1 → Q1 → Rsh → B. Next, when the switch Q1 changes from the on state to the off state, the voltage of the switch Q1 rises due to the voltage induced in the boost reactor L1. Further, since the switch Q1 is turned off, the current flowing through the switch Q1 becomes zero. Further, a current flows through L1 → Do → Co, and power is supplied to the load Ro.

  By turning on / off the switch Q1 at the switching frequency in this way, a half-cycle sine wave current flows through both ends of the current detection resistor Rsh. A voltage from the current detection operational amplifier 13 (a negative half-cycle sine wave voltage indicated by “multiplier input 2” in FIG. 5) is input to one end of the multiplier 12. The voltage from the output voltage detection operational amplifier 11 (positive DC voltage indicated by “multiplier input 1” in FIG. 5) is input to the other end of the multiplier 12. The multiplier 12 varies the output of the current detection operational amplifier 13 according to the value of the error voltage (DC voltage) from the output voltage detection operational amplifier 11. This variable voltage becomes a half-wave sine wave reference voltage.

  The current detection operational amplifier 13 amplifies the error between the voltage Vrsh proportional to the current detected by the current detection resistor Rsh and the half-wave sine wave reference voltage, and outputs the half-wave sine wave to the pulse width modulator 14. To do. As shown in FIG. 5, the “current detection operational amplifier output” is output as a half-cycle sine wave output voltage similar to the input.

  Next, the “current detection operational amplifier output” shown in FIG. 5 is input to the pulse width modulator 14 to control the pulse width of the pulse signal. At this time, since the pulse width modulator 14 has the characteristics as shown in FIG. 4B, the duty cycle of the switch Q1 is as shown in FIG. FIG. 6 shows the actual input voltage Vi and input current Ii of this power factor correction circuit. In the waveform shown in FIG. 6, the vicinity of the zero current is slightly shifted from the sine wave, but it is very close to the sine wave, and both the power factor and the distortion rate are good.

  As described above, according to the power factor correction circuit of the first embodiment, the power factor can be improved and the output of the current detection operational amplifier 13 is input to the multiplier 12. A resistor for dividing the full-wave rectified voltage output from P1 is not required, and the number of components can be reduced compared to the control circuit 10 shown in FIG. Adjustment becomes easy.

  Further, in the conventional power factor correction circuit shown in FIG. 21, (1) the current is detected by the current detection resistor Rsh, passed through the current detection operational amplifier 13 and the pulse width modulator 14, and the switch Q1 is PWM-controlled to (2) The output voltage of the smoothing capacitor Co is detected and the switch Q1 is controlled through the output voltage detection operational amplifier 11, the multiplier 12, the current detection operational amplifier 13, and the pulse width modulator 14 to control the output voltage. And (3) three negative feedback loops that detect the voltage from the full-wave rectifier circuit B, control the switch Q1 through the multiplier 12 and the pulse width modulator 14, and control the output voltage. However, in the power factor correction circuit of the first embodiment, the voltage detection loop that detects the voltage from the full-wave rectifier circuit B and inputs it to the multiplier 12 can be reduced by one. Kill eliminates the instability of the control circuit 10a due to this loop, the circuit 2 loop can be stably controlled.

  In the control circuit 10a, connection pins PN1 to PN5 are provided, and the connection pin PN1 connects one end of the current detection resistor Rsh and the current detection operational amplifier 13. The connection pin PN2 connects the gate of the switch Q1 and the pulse width modulator 14. The connection pin PN3 connects one end of the load Ro and the output voltage detection operational amplifier 11. The connection pin PN4 is connected to the IC power supply + B and supplies the power supply + B to each part in the control circuit 10a. The connection pin PN5 is connected to the negative electrode (ground) of the reference voltage Vref. In the first embodiment, the number of wirings to the control circuit 10a is reduced from six (control circuit 10 shown in FIG. 21) to five, so that the control circuit 10a can be easily integrated and an inexpensive IC is provided. it can. Further, when the control circuit 10a is made into an IC, the number of connection pins (PN1 to PN5) of the IC can be reduced, and an inexpensive IC can be provided.

  FIG. 7 is a configuration diagram illustrating a power factor correction circuit according to the second embodiment. The second embodiment is different from the first embodiment shown in FIG. 1 in the input current detection method, and is a method for detecting the current flowing through the switch Q1.

  In the power factor correction circuit shown in FIG. 7, a series circuit including a boost reactor L1, a diode Do, and a smoothing capacitor Co is connected to both ends of the output of the full-wave rectifier circuit B that rectifies the AC voltage of the AC power supply Vac. A load Ro is connected to both ends of the capacitor Co.

  The control circuit 10b includes a switch Q1, a current detection resistor Rsh, a peak detector 16, an output voltage detection operational amplifier 11, a multiplier 12, a current detection operational amplifier 13, and a pulse width modulator 14.

  One end (drain) of the switch Q1 is connected to a connection point between the boost reactor L1 and the anode of the diode Do via a connection pin PN1, and the other end (source) of the switch Q1 is grounded via a current detection resistor Rsh. Yes. The peak detector 16 inputs a voltage proportional to the current flowing through the current detection resistor Rsh, detects the peak value of the input voltage, and outputs it as a peak voltage. The multiplier 12 varies the gain according to the value of the error voltage from the output voltage detection operational amplifier 11 and outputs it to the current detection operational amplifier 13. Thus, the current detection operational amplifier 13 amplifies the peak voltage from the peak detector 16 and outputs the amplified output to the pulse width modulator 14 as a comparison input signal.

  According to the power factor correction circuit of the second embodiment configured as described above, the switch Q1 is turned on at the switching frequency (frequency sufficiently higher than the AC power supply frequency) even if the input current is a sine wave of the AC power supply frequency. Since the drain current flowing through the switch Q1 is also turned on / off, the average drain current does not become a sine wave.

  For this reason, the peak detector 16 samples the peak value of the voltage of the current detection resistor Rsh for each switching frequency, and outputs a peak voltage in which a curve connecting the peak values becomes a sine wave. That is, the peak voltage can be a sine wave substantially the same as the input current. Then, by inputting the peak voltage from the peak detector 16 to the current detection operational amplifier 13, the input current can be controlled to a sine wave.

  Further, the control circuit 10b has four wires and four connection pins. In addition, the control circuit 10b configured by including the switch Q1, the current detection resistor Rsh, the peak detector 16, the output voltage detection operational amplifier 11, the multiplier 12, the current detection operational amplifier 13, and the pulse width modulator 14 is integrated into an IC. The configuration is further simplified and inexpensive.

  FIG. 8 is a configuration diagram illustrating a power factor correction circuit according to the third embodiment. The power factor correction circuit shown in FIG. 8 is an example applied to a converter called a Chuuk converter. The third embodiment is different from the first embodiment in the configuration of the rectifying and smoothing circuit connected to both ends of the switch Q1. This rectifying / smoothing circuit includes a first series circuit of a capacitor Cx and a diode Do connected to both ends (between the drain and source) of the switch Q1, and a reactor Lo and a smoothing capacitor Co connected to both ends of the diode Do. It consists of two series circuits. The control circuit 10c is different from the control circuit 10a shown in FIG. 1 in that the negative electrode of the reference voltage Vref is connected to the output voltage detection operational amplifier 11 and the positive electrode is grounded.

  Such a power factor correction circuit according to the third embodiment operates in the same manner as the power factor correction circuit shown in FIG. In this case, the input voltage Ei, which is the voltage across the full-wave rectifier circuit B, and the input voltage Es of the pulse width modulator 14 have a relational expression of Es = Ei / (Eo + Ei), which is an input current of a sine wave. The value of harmonic regulation can be cleared. Further, the same effect as that of the first embodiment can be obtained.

  FIG. 9 is a configuration diagram illustrating a power factor correction circuit according to the fourth embodiment. The power factor correction circuit shown in FIG. 9 is an example applied to a converter called a sepic converter. The fourth embodiment differs from the first embodiment in the configuration of the rectifying and smoothing circuit connected to both ends of the switch Q1. This rectifying / smoothing circuit includes a first series circuit of a capacitor Cx and a reactor Lo connected to both ends (between the drain and source) of the switch Q1, a diode Do connected to both ends of the reactor Lo, and a smoothing capacitor Co. It consists of two series circuits.

  The power factor correction circuit according to the fourth embodiment operates in the same manner as the power factor correction circuit shown in FIG. Further, the same effect as that of the first embodiment can be obtained.

  FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to the fifth embodiment. The power factor correction circuit shown in FIG. 10 is an example applied to a converter called an inversion type. In the fifth embodiment, one end (source) of the switch Q1 is connected to the positive output terminal P1 of the full-wave rectifier circuit B, and the other end (drain) of the switch Q1 is connected to one end of the step-up reactor L1 and the cathode of the diode Do. The other end of the step-up reactor L1 is connected to the negative output terminal P2 of the full-wave rectifier circuit B through the current detection resistor Rsh, and the anode of the diode Do is connected to the other end of the step-up reactor L1 through the smoothing capacitor Co. The control circuit 10c shown in FIG. 8 is used.

  The power factor correction circuit of the fifth embodiment operates in the same manner as the power factor correction circuit shown in FIG. Further, the same effect as that of the first embodiment can be obtained.

  FIG. 11 is a configuration diagram illustrating a power factor correction circuit according to the sixth embodiment. In the power factor correction circuit shown in FIG. 11, the control circuit 10d includes a multiplier 12a, a current detection operational amplifier 13, an output voltage detection operational amplifier 11a, and a pulse width modulator 14.

  The multiplier 12a has a characteristic that the gain decreases when the voltage from the output voltage detection operational amplifier 11a increases. The voltage from the current detection operational amplifier 13 (“multiplier input 2” in FIG. 12) is connected to one end of the multiplier 12a. Negative half-cycle sine wave voltage). The voltage from the output voltage detection operational amplifier 11a (positive DC voltage indicated by “multiplier input 1” in FIG. 12) is input to the other end of the multiplier 12a. The multiplier 12a varies the output of the current detection operational amplifier 13 according to the value of the error voltage (DC voltage) from the output voltage detection operational amplifier 11a. This variable voltage becomes a half-wave sine wave reference voltage.

  The current detection operational amplifier 13 amplifies the error between the voltage Vrsh proportional to the current detected by the current detection resistor Rsh and the half-wave sine wave reference voltage, and outputs the half-wave sine wave to the pulse width modulator 14. To do. As shown in FIG. 12, the “current detection operational amplifier output” is output as a half-cycle sine wave output voltage similar to the input.

  Here, if the output voltage Eo decreases for some reason, the output voltage detection operational amplifier 11a increases the output voltage in accordance with the decrease in the output voltage Eo. Then, the multiplier 12a decreases the gain by increasing the output voltage of the output voltage detection operational amplifier 11a and outputs it to the current detection operational amplifier 13. The current detection operational amplifier 13 outputs the comparison input signal with the reduced gain, and the pulse width. The modulator 14 increases the average duty cycle D of the pulse signal by decreasing the comparison input signal from the current detection operational amplifier 13 (in the case of output 1 shown in FIG. 3). For this reason, since the ratio of the time for which the switch Q1 is on increases and the input current increases, the output voltage Eo rises and the output voltage Eo is held constant. The waveform of each part at this time is shown in FIG. In the sixth embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 13 is a configuration diagram illustrating a power factor correction circuit according to the seventh embodiment. In the power factor correction circuit shown in FIG. 13, the control circuit 10 e includes a divider 17, an output voltage detection operational amplifier 11, a current detection operational amplifier 13, and a pulse width modulator 14 as voltage variable means.

  The divider 17 divides the output voltage of the current detection operational amplifier 13 by the output voltage of the output voltage detection operational amplifier 11. Here, it is assumed that the pulse width modulator 14 has characteristics as shown in FIG.

  According to such a configuration, the divider 17 receives the output voltage (DC voltage) of the output voltage detection operational amplifier 11 as “divider input 1” as shown in FIG. The half-wave sine wave that is the output of the current detection operational amplifier 13 is input. Then, the divider 17 calculates (−1 × “divider input 2” ÷ “divider input 1”). The output of the divider 17 is a half-wave sine wave voltage.

  The current detection operational amplifier 13 amplifies an error between the voltage Vrsh proportional to the current detected by the current detection resistor Rsh and the output of the divider 17 (half-wave sine wave voltage), and converts the half-wave sine wave into a pulse width modulator. 14 for output. As shown in FIG. 14, the “current detection operational amplifier output” is output as a half-cycle sine wave output voltage similar to the input.

  Since the pulse width modulator 14 has the characteristics shown in FIG. 4A, the duty cycle of the switch Q1 is as shown in FIG. In the seventh embodiment, the same effect as that of the first embodiment can be obtained.

  It should be noted that the divider 1 in FIG. 13 may replace the inputs 1 and 2 and the divider in FIG. 13 may calculate (−1 × “divider input 1” ÷ “divider input 2”).

  FIG. 15 is a configuration diagram illustrating a power factor correction circuit according to the eighth embodiment. The power factor correction circuit according to the eighth embodiment is an example applied to a step-up bridge converter. The power factor correction circuit includes a series circuit of an AC power supply Vac and a boosting reactor L1, a bridge circuit that is connected to both ends of the series circuit and includes a diode D1, a diode D2, a switch Q1, and a switch Q2, and a diode D1 and a diode. It has a smoothing capacitor Co connected to the connection point between D2 and the connection point between the switches Q1 and Q2, and a load Ro connected in parallel to the smoothing capacitor Co.

  The power factor correction circuit includes a current transformer (CT) 19 that detects an alternating current of the AC power supply Vac, a full-wave rectifier circuit B that rectifies the alternating current from the current transformer 19, and a control circuit 10a. ing.

  According to the power factor correction circuit of the eighth embodiment configured as described above, the full-wave rectification circuit B rectifies the alternating current detected by the current transformer 19 and converts a half-cycle sine wave as a current signal to a current detection operational amplifier. 13 is output. The current detection operational amplifier 13 outputs the amplified output to the pulse width modulator 14 having the characteristics shown in FIG. The pulse width modulator 14 applies a pulse signal to the switches Q1 and Q2 to turn on / off the switches Q1 and Q2 simultaneously. When the two switches Q1 and Q2 are simultaneously turned on, current flows through Vac → L1 → Q1 → Q2 → Vac or Vac → Q2 → Q1 → L1 → Vac, and energy is stored in the boost reactor L1.

  Next, when the two switches Q1 and Q2 are simultaneously turned off, the energy stored in the step-up reactor L1 is charged to the capacitor Co through either the diode D1 or D2 depending on the direction of current flow. Even in the case of the eighth embodiment, since the waveform obtained by rectifying the current of the current transformer 19 and the waveform of the input voltage of the pulse width modulator 14 are the same waveform, the input current can be a sine wave.

  FIG. 16 is a configuration diagram illustrating a power factor correction circuit according to the ninth embodiment. The power factor correction circuit shown in FIG. 19 is an example applied to an insulating converter. A series circuit of a boost reactor L1, a switch Q1, a switch Q3, and a current detection resistor Rsh is connected to both ends of a full-wave rectifier circuit B that rectifies an AC voltage of the AC power supply Vac. A series circuit of a switch Q2 and a switch Q4 is connected to a connection point between the boost reactor L1 and the switch Q1 and a connection point between the switch Q3 and the current detection resistor Rsh. A primary winding 5a of the transformer T is connected to a connection point between the switch Q1 and the switch Q3 and a connection point between the switch Q2 and the switch Q4.

  A series circuit of a diode Do1 and a diode Do2 is connected to both ends of a series circuit of the secondary winding 5b and the tertiary winding 5c of the transformer T, and the connection between the secondary winding 5b and the tertiary winding 5c is connected. A smoothing capacitor Co is connected to the point and a connection point between the diode Do1 and the diode Do2. A load Ro is connected to both ends of the smoothing capacitor Co.

  The control circuit 10 f includes an output voltage detection operational amplifier 11, a multiplier 12, a current detection operational amplifier 13, a pulse width modulator 14, a flip-flop (FF) 21 that inputs a clock of the pulse width modulator 14, and one output Q of the FF 21. A NAND circuit 22 for inputting the pulse signal of the pulse width modulator 14, and a NAND circuit 23 for inputting the other output (inverted output of the output Q) of the FF 21 and the pulse signal of the pulse width modulator 14 are configured. The The FF 21 and NAND circuits 22 and 23 constitute the switch control means of the present invention.

  Next, the operation of the ninth embodiment configured as described above will be described with reference to the waveforms of the respective parts shown in FIG.

  First, a voltage proportional to the current detected by the current detection resistor Rsh and a voltage via the multiplier 12 are input from the output voltage detection operational amplifier 11 to the current detection operational amplifier 13. The output of the current detection operational amplifier 13 is input to the pulse width modulator 14, and the output of the pulse width modulator 14 is output to the FF 21.

  Further, the clock is output from the pulse width modulator 14 to the FF 21 and the FF 21 is driven. Then, one output Q of the FF 21 and the pulse signal of the pulse width modulator 14 are input to the NAND circuit 22, and the other output (inverted output of the output Q) of the FF 21 and the pulse signal of the pulse width modulator 14 are NANDed. Input to the circuit 23.

  The output of the NAND circuit 22 is applied to the gate of the switch Q2 via the gate of the switch Q3 and the high side driver 25b. The output of the NAND circuit 23 is applied to the gate of the switch Q1 via the gate of the switch Q4 and the high side driver 25a.

  Next, the on / off operation of the switches Q1 to Q4 will be described with reference to FIG.

First, at time t _0, the switches Q1 and Q4 are simultaneously turned on by the output of the NAND circuit 23, the switch Q2 and the switch Q3 is turned on at the same time by an output of the NAND circuit 22. For this reason, the voltages of the switches Q1 and Q4 are zero, and the voltages of the switches Q2 and Q3 are also zero. At this time, a current flows through B → L1 → Q1 → Q3 → Rsh → B. Further, a current flows through B → L1 → Q2 → Q4 → Rsh → B.

Next, at time _{t 1,} the switch Q2 and the switch Q3 is turned off at the same time by the output of the NAND circuit 22. For this reason, the voltage of the switches Q2 and Q3 increases, and the current becomes zero. At this time, current flows through B → L1 → Q1 → 5a → Q4 → Rsh → B, and the currents of the switches Q1 and Q4 increase.

Then, at time _{t 2, the} the switch Q2 and the switch Q3 is turned on at the same time by an output of the NAND circuit 22. For this reason, the voltages of the switches Q2 and Q3 are zero. That is, the operation at this time is the same as the operation at time t ₀ . From time t ₁ to time t ₂ , current flows in the order of 5c → Do2 → Co → 5c, and DC power is supplied to the load Ro.

Then, at time _{t 3,} the switches Q1 and Q4 are simultaneously turned off by the output of the NAND circuit 23. For this reason, the voltages of the switches Q1 and Q4 rise and the current becomes zero. At this time, current flows through B → L1 → Q2 → 5a → Q3 → Rsh → B, and the currents of the switches Q2 and Q3 increase. From time t ₃ to time t ₄ , a current flows from 5b → Do1 → Co → 5b, and DC power is supplied to the load Ro.

  In the ninth embodiment, the same effect as that of the first embodiment can be obtained.

(Specific example of variable gain amplifier)
FIG. 18 is a block diagram showing an example of a variable gain amplifier used as an example of voltage variable means. FIG. 18 (a) shows the principle of the variable gain amplifier. The input terminal comprises a resistor R1 and a gain adjusting variable resistor Rv connected in series to the resistor R1, and one end of the resistor R1 is connected. An input signal is input to 51, and an output is taken out to the output terminal 52 from a connection point between the resistor R1 and the variable resistor Rv. In this case, the gain is less than one.

  The example of FIG. 18B is a specific example of that shown in FIG. 18A. The FET Q5 has a drain, a source, and a gate, and the resistance value changes depending on the voltage applied to the gate, and the drain of the FET Q5. And a voltage proportional to the current detected by the current detection resistor Rsh is input to the input terminal 51 connected to the other end of the resistor R1, and output to the gate terminal 53 of the FET Q5. The error voltage of the voltage detection operational amplifier 11 is applied, and an output is taken out from the connection point between the resistor R1 and the drain of the FET Q5 to the output terminal 52.

  Thus, the resistance value of the FET Q5 changes depending on the value of the voltage input to the gate of the FET Q5, so that the gain changes.

  FIG. 19 is a block diagram showing another example of the variable gain amplifier. FIG. 19A shows the principle of the variable gain amplifier, which includes a variable resistor Rv and an operational amplifier 31 having an inverting terminal connected to one end of the variable resistor Rv. A feedback resistor R2 is connected to the inverting terminal and the output terminal of the operational amplifier 31, and the non-inverting terminal is grounded. An input signal is input to the input terminal 51 connected to one end of the variable resistor Rv, and an output is taken out from the output terminal 52. The gain at this time is R2 / Rv.

  The example of FIG. 19B is a specific implementation of the one shown in FIG. 19A. The FET Q6 has a drain, a source, and a gate, and the resistance value changes depending on the voltage applied to the gate, and the drain of the FET Q6. And an operational amplifier 31 having a feedback resistor R2 connected to the inverting terminal and the output terminal. The current detected by the current detection resistor Rsh is input to the input terminal 51 connected to the source of the FET Q6. A proportional voltage is input, the error voltage of the output voltage detection operational amplifier 11 is applied to the gate terminal 53 of the FET Q6, and the output is taken out to the output terminal 52.

  As described above, the resistance value of the FET Q6 changes depending on the value of the voltage input to the gate of the FET Q6, so that the gain greatly changes.

  FIG. 20 is a diagram showing the characteristics of the FET used in the variable gain amplifier. FIG. 20 shows characteristics of the drain voltage Vd and the drain current Id of the FET, and the characteristics change with changes in the gate-source voltage Vgs. That is, in the FET, the slope of the graph changes depending on the magnitude of the gate signal, and the resistance value changes.

  The present invention is not limited to the first to ninth embodiments. The current can be detected not only by the input current but also by the current of a switch such as an FET or the current of a rectifier diode, and may be detected by the average value, peak value, or effective value of the current. In this case, the input current may not be an accurate sine wave, but the standard value of the harmonic regulation can be set to a value that can be cleared.

  Further, the pulse width modulator 14 is not limited to pulse width modulation with a fixed frequency. For example, the ON width and the OFF width are controlled by an OFF width control with a constant ON width or an ON width control in which the ON width changes with a constant OFF width. Even if the frequency changes, it is sufficient if the ON / OFF ratio changes. Further, in the present invention, two or more embodiments of Embodiments 1 to 9 may be combined.

  The present invention is applicable to an AC-DC conversion type power supply circuit.

FIG. 3 is a configuration diagram illustrating a power factor correction circuit according to the first embodiment. 3 is a configuration diagram illustrating a pulse width modulator provided in a control circuit in the power factor correction circuit according to Embodiment 1. FIG. It is a figure which shows the input-output waveform of a pulse width modulator. It is a figure which shows one example of the input-output characteristic of a pulse width modulator. It is a figure which shows the waveform of each part of the power factor improvement circuit of Example 1. FIG. It is a figure which shows the waveform of the input voltage and input current of the power factor improvement circuit of Example 1. FIG. 6 is a configuration diagram illustrating a power factor correction circuit according to Embodiment 2. FIG. FIG. 6 is a configuration diagram illustrating a power factor correction circuit according to a third embodiment. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to a fourth embodiment. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to a fifth embodiment. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to a sixth embodiment. It is a figure which shows the waveform of each part of the power factor improvement circuit of Example 6. FIG. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to a seventh embodiment. It is a figure which shows the waveform of each part of the power factor improvement circuit of Example 7. FIG. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to an eighth embodiment. FIG. 10 is a configuration diagram illustrating a power factor correction circuit according to a ninth embodiment. It is a figure which shows the waveform of each part of the power factor improvement circuit of Example 9. FIG. It is a block diagram which shows an example of a variable gain amplifier. It is a block diagram which shows another example of a variable gain amplifier. It is a figure which shows the characteristic of FET used for a variable gain amplifier. It is a block diagram of the conventional power factor improvement circuit.

Explanation of symbols

Vac AC power supply B Full-wave rectifier circuit 10, 10a to 10f Control circuit 11 Output voltage detection operational amplifier (error voltage generating means)
12 Multiplier (Voltage variable means)
13 Current detection operational amplifier (current detection amplification means)
14 Pulse width modulator (pulse width control means)
16 Peak detector (peak detection means)
17 Divider (Voltage variable means)
19 Current transformer (CT) (current detection means)
21 FF (flip-flop)
22, 23 NAND circuit 25a, 25b High side driver 141 Triangle wave oscillator 142 Comparator Q1-Q4 Switch Do, D1, D2, Do1, Do2 Diode
L1 Step-up reactor Co Smoothing capacitor Ro Load Rsh Current detection resistor (current detection means)
T transformer 5a Primary winding (n1)
5b Secondary winding (n2)
5c Tertiary winding (n3)

Claims (9)

A rectified voltage obtained by rectifying the AC power supply voltage of the AC power supply using a rectifier circuit is input to a series circuit of a boosting reactor and a main switch, and is turned on / off by the main switch to improve the power factor of the AC power supply and rectify and smooth A power factor correction circuit that obtains a DC output voltage by a circuit,
Current detection means for detecting a current flowing through the AC power supply, a current flowing through the rectifier circuit, or a current flowing through the main switch;
Error voltage generating means for amplifying an error between the output voltage and the first reference voltage to generate an error voltage;
Current detection amplification means for amplifying and outputting an error between a voltage proportional to the current detected by the current detection means and a second reference voltage;
A voltage varying means for varying the output of the current detection amplifying means according to the value of the error voltage from the error voltage generating means and outputting a variable voltage to the current detection amplifying means as the second reference voltage;
A pulse width control means for generating a pulse signal whose pulse width is controlled according to an output value of the current detection amplification means, and applying the pulse signal to the main switch to control the output voltage to a predetermined voltage;
A power factor correction circuit comprising:   2. The force according to claim 1, further comprising: a peak detection unit that detects a peak value of the current detected by the current detection unit and outputs a voltage proportional to the peak value of the current to the current detection amplification unit. Rate improvement circuit.   3. The power factor correction circuit according to claim 1, wherein the voltage varying means comprises a divider that divides the output voltage of the current detection amplification means by the error voltage of the error voltage generation means.   The rectifying / smoothing circuit includes a first series circuit of a capacitor and a diode connected to both ends of the main switch, and a second series circuit of a reactor and a smoothing capacitor connected to both ends of the diode. The power factor correction circuit according to any one of claims 1 to 3.   The rectifying / smoothing circuit includes a first series circuit of a capacitor and a reactor connected to both ends of the main switch, and a second series circuit of a diode and a smoothing capacitor connected to both ends of the reactor. The power factor correction circuit according to any one of claims 1 to 3. A first series circuit of an AC power supply and a boosting reactor, a bridge circuit connected to both ends of the first series circuit and including a first diode, a second diode, a first switch, and a second switch, and the first diode And a smoothing capacitor connected to a connection point between the first diode and the second diode, and a connection point between the first switch and the second switch, and simultaneously turning on and off the first switch and the second switch. A power factor correction circuit for improving the power factor of the AC power source and obtaining a DC output voltage,
Current detection means for detecting an AC power supply current of the AC power supply;
A rectifier circuit for rectifying the AC power supply current detected by the current detection means;
Error voltage generating means for amplifying an error between the output voltage and the first reference voltage to generate an error voltage;
Current detection amplification means for amplifying and outputting an error between a voltage proportional to the current rectified by the rectifier circuit and a second reference voltage;
A voltage varying means for varying the output of the current detection amplifying means according to the value of the error voltage from the error voltage generating means and outputting a variable voltage to the current detection amplifying means as the second reference voltage;
A pulse for generating a pulse signal whose pulse width is controlled in accordance with the output value of the current detection amplification means, and applying the pulse signal to the first switch and the second switch to control the output voltage to a predetermined voltage. Width control means;
A power factor correction circuit comprising: Connected to both ends of a rectifier circuit that rectifies an AC power supply voltage of an AC power supply, a first series circuit of a boost reactor, a first switch, a third switch, and current detection means, and a connection between the boost reactor and the first switch And a connection point between the first switch and the third switch, a connection point between the first switch and the third switch, and a connection point between the first switch and the third switch; A transformer primary coil connected to a connection point between the second switch and the fourth switch; and a rectifying / smoothing circuit that rectifies and smoothes the voltage of the secondary output coil of the transformer; A power factor improving circuit for improving a power factor of the AC power source by turning on / off one switch to the fourth switch and obtaining a DC output voltage;
Error voltage generating means for amplifying an error between the output voltage and the first reference voltage to generate an error voltage;
Current detection amplification means for amplifying and outputting an error between a voltage proportional to the current detected by the current detection means and a second reference voltage;
A voltage varying means for varying the output of the current detection amplifying means according to the value of the error voltage from the error voltage generating means and outputting a variable voltage to the current detection amplifying means as the second reference voltage;
Pulse width control means for generating a pulse signal in which the pulse width is controlled according to the value of the output of the current detection amplification means;
A pulse inversion signal obtained by inverting the pulse signal is generated, one of the pulse signal or the pulse inversion signal is applied to the second switch and the third switch, and the other of the pulse signal or the pulse inversion signal is applied to the first switch. Switch control means for controlling the output voltage to a predetermined voltage by applying ON / OFF control to the first switch and the fourth switch by applying to one switch and the fourth switch;
A power factor correction circuit comprising:   The voltage variable means includes a first main electrode, a second main electrode, and a control electrode, a semiconductor element whose resistance value varies depending on a voltage applied to the control electrode, and the first main electrode of the semiconductor element. A fixed resistor having one end connected thereto, an output voltage of the current detection amplification unit is input to the other end of the fixed resistor, and an error voltage of the error voltage generation unit is applied to the control electrode of the semiconductor element. The power factor correction circuit according to any one of claims 1 to 7, wherein the power factor correction circuit according to any one of claims 1 to 7 is provided. The voltage variable means includes a first main electrode, a second main electrode, and a control electrode, a semiconductor element whose resistance value varies depending on a voltage applied to the control electrode, and the first main electrode of the semiconductor element. An operational amplifier having an inverting terminal connected thereto and a feedback resistor connected to the inverting terminal and the output terminal, the output voltage of the current detection amplification means being input to the second main electrode of the semiconductor element; 8. The power factor correction circuit according to claim 1, wherein an error voltage of the error voltage generating unit is applied to the control electrode of the semiconductor element. 9.

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