JP4421242B2 - Method for manufacturing crystalline semiconductor film, method for manufacturing thin film transistor having crystalline semiconductor film, and method for manufacturing semiconductor device having crystalline semiconductor film - Google Patents

Description

  The present invention relates to a method for manufacturing a crystalline semiconductor film, specifically a crystalline silicon film, for controlling the generation position of a crystal grain boundary. Furthermore, the present invention relates to a thin film transistor (TFT) having the crystalline semiconductor film and a method for manufacturing a semiconductor device having the TFT.

  In a conventional method for manufacturing a crystalline semiconductor film, an insulating film is formed on a substrate, a quadrangular pyramid hole is formed at a predetermined position in the surface of the insulating film, an amorphous silicon film is formed, and a laser is used. There is a type in which a thin film transistor is formed using a silicon film having a substantially single crystal state as a semiconductor film in a region centered on a hole by irradiation (see Patent Document 1).

    In addition, as a manufacturing method that eliminates the variation in characteristics associated with the increase in the grain size of a polycrystalline silicon film, a region where crystal nuclei are preferentially generated in the amorphous silicon film is selected prior to solid phase crystallization. (See Patent Document 2).

  As a method for increasing the crystallinity of the semiconductor film, a metal element typified by nickel element (Ni) is added to the semiconductor film, and the film is formed or applied, and then subjected to heat treatment to form a crystalline semiconductor film. A crystallization method has been performed (see, for example, Patent Document 3). In such a crystallization process, by using a metal element that promotes crystallization, such as Ni, a crystalline semiconductor film having a large grain size can be obtained, and the continuity of atomic arrangement at the grain boundary can be maintained. A crystalline semiconductor film with high probability and few intragranular defects has been obtained.

JP 2003-92260 A Japanese Patent Laid-Open No. 5-67635 Japanese Patent Laid-Open No. 7-161634

  However, in the method for producing a crystalline silicon film disclosed in Patent Documents 1 and 2, control of the generation position of crystal grains, particularly crystal grain boundaries, is insufficient. When a thin film transistor (also referred to as a TFT) is formed using such a crystalline semiconductor film, mobility due to a grain boundary and variation in electrical characteristics of the TFT are caused.

  Further, from the method for producing a crystalline silicon film disclosed in Patent Documents 1 and 2, a crystalline semiconductor in which crystal orientation of crystal grains (simply referred to as orientation) is controlled as disclosed in Patent Document 3 In the case of using a film, it has been difficult to produce a crystalline semiconductor film in consideration of the orientation.

  Therefore, an object of the present invention is to provide a new method for manufacturing a crystalline semiconductor film in which generation positions of crystal grains and crystal grain boundaries are controlled. In particular, an object is to provide a method for manufacturing a crystalline semiconductor film in which the orientation of crystal grains is controlled.

  In view of the above problems, the present invention controls the position of a selectively formed metal element that promotes crystallization (hereinafter referred to as a metal element), and uses the region where the metal element is formed as a seed crystal region for crystallinity. A semiconductor film is formed. For example, the formation position of the opening formed in the insulating film is controlled, the metal element of the amorphous semiconductor film is formed on the bottom surface of the opening, and the amorphous semiconductor film is formed so as to cover the opening and the insulating film. The crystalline semiconductor film is formed using a region where the crystallization of the amorphous semiconductor film is accelerated by the metal element, that is, a region where crystallization starts at a low temperature is used as a seed crystal region. The shape of the opening can be a point, a line, a rectangle, or a combination thereof. Further, the end face of the opening may be tapered.

  According to the present invention, the arrangement of the openings, that is, the arrangement of the seed crystal regions can be controlled.

  According to a specific configuration example of the present invention, an insulating film is formed, an opening is formed in the insulating film, a metal element that promotes crystallization is formed on a bottom surface of the opening, and the opening and the insulating film are formed. A crystalline semiconductor film is formed by forming an amorphous semiconductor film and heating the amorphous semiconductor film.

  The depth of the opening is set to 0.5 to 1.5 μm so that the orientation can be controlled by the metal element. Furthermore, the diameter of the opening is 0.1 to 100 μm, preferably 0.1 to 1 μm.

  In the present invention, the metal elements are nickel (Ni), iron (Fe), cobalt (Co), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), silver (Ag) indium (In ), Tin (Sn), etc., and one or more selected from these may be used.

  As a method for manufacturing a semiconductor film containing a metal element, a solution (including an aqueous solution and an acetic acid solution) containing the metal element is applied by a coating method such as a spin coating method or a dip method. Alternatively, metal element ions may be implanted by an ion implantation method, heated in a water vapor atmosphere containing the metal element, or a semiconductor film containing the metal element may be formed by a sputtering method.

  Further, in the case where an aqueous solution containing a metal element is selectively formed on the bottom surface of the opening, the bottom surface of the opening improves wettability with respect to the aqueous solution containing the metal element, and the upper surface, that is, the surface of the insulating film is formed of the metal element. It is preferable to reduce wettability with respect to the aqueous solution. In order to improve wettability, for example, an oxide film containing silicon is preferably formed in the opening, and in order to reduce wettability, for example, a silicon film is preferably formed on the upper surface of the insulating film.

  In another configuration example of the present invention, a first insulating film is formed to reduce the diameter of the opening, and the first opening is formed in the first insulating film by using an etching method. Using a CVD method, a second insulating film is formed so as to reduce the diameter of the first opening, thereby forming the second opening, and crystallization is promoted on the bottom surface of the second opening. Forming a metal element, covering the second opening and the second insulating film, forming an amorphous semiconductor film, and heating the amorphous semiconductor film, thereby forming a crystalline semiconductor film Form.

  In order to selectively form a metal element, the metal element may be ion-doped using a metal mask or the like.

  In the present invention, a gettering step may be performed in order to reduce the concentration of the metal element or remove the metal element. The gettering step may be performed after the crystalline semiconductor film is formed.

  The amorphous semiconductor film may be heated by a heating furnace, laser, lamp annealing, or a combination thereof. Crystal growth of the semiconductor film can be promoted by laser irradiation after heating in a heating furnace. When the amorphous semiconductor film is heated in this manner, crystallization is performed from the opening, that is, the seed crystal region, and a crystalline semiconductor film can be formed.

  In addition, a channel formation region of a thin film transistor including the crystalline semiconductor film of the present invention (simply referred to as a channel formation region) is formed. When patterning a TFT channel formation region and an active layer having an impurity region (simply referred to as an active layer), it is preferable to remove the seed crystal region from the active layer. This is because the metal element adversely affects the electrical characteristics and the like (also referred to as TFT characteristics) of the thin film transistor. Further, even if the active layer has a seed crystal region, the seed crystal region may be disposed under the impurity region. That is, patterning may be performed so that at least the channel formation region has no seed crystal region.

  Further, according to the present invention in which crystal growth is performed from one seed crystal region, a crystalline semiconductor film in which at least a channel formation region does not include a grain boundary, or a crystalline semiconductor film in which at least a grain boundary included in the channel formation region becomes a corresponding grain boundary It can be. The corresponding grain boundary is characterized in that the continuity of the atomic arrangement at the grain boundary is maintained, and an example is a twin grain boundary. This twin grain boundary is unlikely to adversely affect the TFT characteristics as compared with a normal crystal grain boundary in which atomic arrangement is discontinuous (simply referred to as a crystal grain boundary). Therefore, the semiconductor film may have twin grain boundaries, but it is necessary to pattern the semiconductor film so that it does not have at least crystal grain boundaries. In addition, if the semiconductor film, particularly the channel formation region has irregular crystal grain boundaries, the TFT characteristics are adversely affected, particularly the TFT characteristics vary, which is not preferable. Therefore, the crystal is grown from the seed crystal region and the generation position of the crystal grain boundary, that is, the arrangement of the crystal grain boundary is controlled. Furthermore, in the channel formation region, if there are twin grain boundaries so as to cross the carrier moving direction, it may not be preferable for improving the mobility. Therefore, it is more preferable to pattern so that the twin grain boundary and the direction in which the current flows in the channel formation region are aligned, that is, parallel.

  Note that in a crystalline semiconductor film, a range of crystal growth from one seed crystal region is referred to as a crystal grain. That is, the crystal grains of the present invention do not have a plurality of grain boundaries. Further, the crystal grains of the present invention may have a plurality of twins and twin grain boundaries.

  By providing one or a plurality of TFTs in such crystal grains, TFTs with uniform electrical characteristics can be formed. Further, by using the TFT, a high-quality semiconductor device can be formed.

  In the present invention, the seed crystal region can be formed by a simple method of selectively adding a metal element, for example, selectively adding a metal element by providing an opening in an insulating film. In the present invention, a crystalline semiconductor film can be formed by controlling the seed crystal region, that is, the arrangement of crystals. Further, according to the present invention, a crystalline semiconductor film can be formed by controlling the arrangement of crystal grain boundaries.

  As described above, since the crystalline semiconductor film can be formed by controlling the arrangement of crystal grain boundaries, the channel formation region can be patterned so as not to have crystal grain boundaries. As a result, a TFT with little variation, in particular, a driving TFT provided in the pixel portion can be obtained. Furthermore, since the semiconductor film is patterned so that there is no crystal grain boundary that hinders carrier movement and the twin grain boundary is aligned with the carrier movement direction, a TFT having extremely high movement can be provided. .

  A TFT having such a TFT makes it possible to manufacture a high-quality semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a specific method for manufacturing a crystalline semiconductor film is described.

  First, as illustrated in FIG. 1A, a base film 101 is formed over a substrate 100 having an insulating surface. As the substrate 100, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. In addition, plastics typified by PET, PES, and PEN, and substrates made of a synthetic resin having flexibility such as acrylic generally tend to have a lower heat resistant temperature than other substrates. Any material can be used as long as it can withstand the processing temperature.

  The base film 101 is provided to prevent alkali metal such as Na or alkaline earth metal contained in the substrate 100 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, the insulating film is formed using an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film. In this embodiment, a silicon nitride oxide film is formed to a thickness of 10 to 400 nm (preferably 50 to 300 nm) by a plasma CVD method. Note that the base film 401 may have a stacked structure. For example, a silicon oxynitride film is stacked in the order of 10 to 200 nm (preferably 50 to 100 nm) and a silicon oxynitride film is stacked in the order of 50 to 200 nm (preferably 100 to 150 nm). May be.

  When using a substrate that contains alkali metal or alkaline earth metal, such as a glass substrate, stainless steel substrate, or plastic substrate, it is effective to provide a base film from the viewpoint of preventing impurity diffusion. In the case where diffusion of impurities does not cause any problem, such as a quartz substrate, it is not necessarily provided.

  An insulating film 103 is formed over the base film 101. As the insulating film 103, an insulating film containing silicon is formed with a thickness of 0.5 to 1.5 μm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxide film is formed with a thickness of 1.0 μm by a plasma CVD method. The insulating film 103 may be formed of a silicon nitride film or a silicon nitride oxide film in addition to the silicon oxide film. Next, an opening 130 is formed in the insulating film 103 by a dry etching method or a wet etching method using a mask. In this embodiment mode, an opening is formed by a dry etching method using a resist mask. The diameter of the opening may be 0.1 to 100 μm. As the diameter of the opening is reduced, the crystal orientation control is preferably improved.

  As shown in FIG. 1B, a metal element is formed in the opening. Note that this embodiment will be described using Ni as a metal element.

  For example, a Ni solution (including an aqueous solution and an acetic acid solution) is applied by a coating method such as spin coating or dip coating, and a film containing Ni (however, it is extremely thin and may not be observed as a film) is formed in the opening. To do. Alternatively, Ni may be formed in the opening by injecting Ni ions into the opening by ion implantation, heating in a water vapor atmosphere containing Ni, or sputtering with Ar plasma using a Ni material as a target. .

  When the metal element is formed in the opening by the above-described coating method, the wettability of the bottom surface 131 of the opening is improved and the aqueous solution is spread. For example, it is desirable to form an oxide film with a thickness of 10 to 50 mm on the opening, at least on the bottom, by irradiation with UV light in an oxygen atmosphere, thermal oxidation, treatment with ozone water or hydrogen peroxide containing hydroxy radicals, and the like.

  In addition, the surface 132 of the insulating film in which the opening is not provided should have low wettability so that an aqueous solution containing a metal element is not applied. For example, when a silicon film is formed after the insulating film 103 is formed, the surface of the insulating film can reduce wettability with respect to an aqueous solution containing a metal element.

  In this embodiment mode, a mask is formed over the insulating film 103, an oxide film is formed on the bottom surface 131 and the side surface 133 of the opening with hydrogen peroxide solution, and then an aqueous solution containing Ni acetate 10 ppm is spin-coated. By applying, metal element 105 is formed in the opening. Further, by controlling the rotation speed of the spin coating, for example, by gradually increasing the rotation speed, the Ni acetate salt applied to the surface of the insulating film not provided with the opening is removed. Thus, the region where the metal element 105 is formed becomes the seed crystal region 104.

  As shown in FIG. 1C, an amorphous semiconductor film 106 is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like so that the thickness from the insulating film 103 becomes 50 to 200 nm. As the amorphous semiconductor, not only a semiconductor film containing silicon as a main component but also a semiconductor film made of silicon containing germanium (referred to as silicon germanium) can be used. When silicon germanium is used, the germanium concentration is 0. It is preferably about 01 to 4.5 atomic%. In this embodiment mode, a semiconductor film containing silicon as a main component (also referred to as an amorphous silicon film) 106 is formed to a thickness of 100 nm by a plasma CVD method.

  Thereafter, heat treatment is performed to crystallize the amorphous semiconductor film 106. As the heat treatment, a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or the like can be used.

  When using a heating furnace, the temperature may be set in multiple stages in the range of 500 to 550 ° C. so that the temperature gradually increases. For example, heat treatment is performed at 550 ° C. for 4 hours after heat treatment at 500 ° C. for 1 hour using a vertical furnace.

  When laser irradiation is used, a pulsed excimer laser beam processed into a linear shape, an argon laser beam or an excimer laser beam which is a continuous wave laser (also referred to as a CW laser) can be used.

  When lamp annealing is used, infrared light (for example, a wavelength of 1.2 μm) can be irradiated.

  In the case of performing such crystallization, it is preferable that the substrate is further heated to about 250 to 500 ° C. In particular, when the amorphous semiconductor film 106 is crystal-grown in the lateral direction from the tip, the crystal is grown longer when there is no temperature difference between the substrate and the amorphous semiconductor film 106.

  A combination of the above heating furnace, laser irradiation or heating by lamp annealing may be used. For example, after performing a heat treatment using a heating furnace, laser irradiation or lamp annealing can be performed. As a result, crystal growth can be promoted, and crystal grains having a larger grain size can be formed.

  At this time, since the temperature at which the crystallization of the amorphous semiconductor film starts decreasing in the opening where the metal element is formed, crystallization starts first. Further, the amorphous semiconductor film 106 is crystal-grown so that the orientation is controlled by the metal element. The amorphous semiconductor film 106 thus formed in the opening becomes a seed crystal region in which the orientation is controlled.

  FIG. 3 is a schematic diagram of the crystal grains 115 of the amorphous semiconductor film 106 that performs such crystal growth. With the seed crystal region 104 as the center, the crystal grains 115 grow in the same direction, and grow to the point where they meet adjacent crystal grains. Therefore, the interval for forming the opening can be determined based on the required crystal grain size. For example, when it is desired to obtain a crystal grain having a side of approximately 10 μm, seed crystal regions in which openings are formed may be formed in a lattice pattern at intervals of 10 μm. Further, by making the intervals between the seed crystal regions different, the shape of the crystal grains can be made rectangular or other rectangular shapes. Furthermore, by scratching the insulating film 103, the end point of crystal growth can be controlled, and crystal grains having various shapes can be formed.

  After the crystallization process as described above, that is, after the metal element becomes unnecessary, it is preferable to perform a gettering process in order to reduce or remove the metal element. Specifically, an amorphous semiconductor film to which an inert element such as Ar is added is formed as a gettering sink, and a gettering step is performed in which heat treatment is performed. The amorphous semiconductor film serving as a gettering sink can be formed by a sputtering method using a Si-containing target or a CVD method. For example, in a sputtering apparatus, a high frequency power source is operated, a high frequency is applied to the target, and a magnetic field is applied using a permanent magnet.

  Note that when an amorphous semiconductor film serving as a gettering sink is formed, it is preferable to form an oxide film so that wettability is improved and film peeling does not occur. As the oxide film, a thin film (chemical oxide) formed by treatment with ozone water or an aqueous solution mixed with hydrogen peroxide such as sulfuric acid, hydrochloric acid, or nitric acid can be used. As another method, the plasma treatment in an oxygen atmosphere or the oxidation treatment may be performed by generating ozone by irradiating ultraviolet rays in an oxygen-containing atmosphere.

  After the amorphous semiconductor film to be a gettering sink is thus formed, heat treatment is performed. Then, the metal element diffuses and is captured by the amorphous semiconductor film to which the inert element is added. Thereafter, the amorphous semiconductor film serving as a gettering sink is removed with hydrofluoric acid or the like.

  As described above, a crystallized semiconductor film 106 (referred to as a crystalline semiconductor film) in which crystal growth is performed around the seed crystal region can be formed.

  Next, a process of forming a thin film transistor by patterning the crystalline semiconductor film will be described.

  As shown in FIG. 2A, the crystalline semiconductor film 106 is patterned into a predetermined shape, so that an island-shaped semiconductor film 107 is formed. At this time, patterning may be performed so that at least the seed crystal region does not enter the channel formation region.

  At this time, a crystal grain grown from one seed crystal may include a corresponding grain boundary. Since the corresponding grain boundary has little influence on the TFT characteristics, the semiconductor film 107 may include the corresponding grain boundary. However, it is desirable that the carrier moving direction be substantially parallel to the corresponding grain boundary.

  Here, a patterning example of the crystalline semiconductor film 106 having the crystal grains 115 will be described. FIG. 9 shows the patterning shape of the crystalline semiconductor film 106 as viewed from above.

  As shown in FIG. 9A, the crystalline semiconductor film 106 is patterned so as to remove the seed crystal region 104 to form an island-shaped semiconductor film 107 (patterning portion 170 in the drawing). This is because the semiconductor film 102 and the amorphous semiconductor film 103 containing a metal element have the possibility that the metal element may remain and eliminate the possibility of adversely affecting the TFT characteristics.

  Furthermore, it is preferable that the crystalline semiconductor film 107 be patterned diagonally with the seed crystal region as the center so that the crystal growth direction of the twin crystal, that is, the direction in which the current flows in the twin crystal grain boundary and the channel forming region flows. That is, when the seed crystal regions are arranged at equal intervals, it can be expressed that the channel formation regions are arranged along a line that obliquely connects the seed crystal regions. This is because it is preferable that the channel formation region does not include a twin grain boundary or that the carrier moving direction and the twin grain boundary direction are parallel to improve the mobility of the TFT. That is, in the channel formation region, it is preferable that the carrier movement direction does not cross the twin grain boundary because the mobility of the TFT can be improved.

  Further, patterning may be performed so that the seed crystal region 104 does not enter at least the channel formation region, and the seed crystal region 104 may be disposed in the impurity region as illustrated in FIG. That is, the island-shaped semiconductor film 107 may be formed so that the source region or the drain region which is an impurity region is formed above the seed crystal region (patterning portion 170 in the drawing). Also in this case, it is preferable to pattern the crystallized semiconductor film 107 so as to follow the crystal growth direction and the direction in which the current in the channel formation region flows.

  The crystal grains grow radially until they hit adjacent crystal grains, and a crystal grain boundary is formed in the area where the crystal grains hit. Therefore, as described above, the crystal grains can be formed not only in a square shape but also in a rectangular shape and other rectangular shapes. That is, the shape of the crystal grains can be controlled by the interval at which the seed crystal regions are arranged. For example, as shown in FIG. 9C, when the vertical interval of the seed crystal region 104 is made larger than the horizontal interval, rectangular crystal grains 115 having a major axis in the vertical direction can be formed.

  Further, as shown in FIG. 9C, the direction of crystal growth radially, that is, the direction of crystal growth if twin grain boundaries exist and the direction of current flow in the channel formation region are aligned. That is, it is more preferable that the island-shaped semiconductor film 107 is formed by patterning so as to be parallel to each other (patterning portion 170 in the drawing). As described above, twin grain boundaries hardly affect TFT characteristics, but the mobility of TFTs can be improved by patterning along the corresponding grain boundaries and the direction of current flow in the channel formation region. Because.

  Further, the twin grain boundaries and the direction in which the electricity flows in the channel formation region may be inclined.

  Next, as shown in FIG. 2B, the surface of the patterned island-shaped semiconductor film 107 is washed with an etchant containing hydrofluoric acid, and a gate insulating film 108 is formed so as to cover the semiconductor film 107. The gate insulating film 108 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by a plasma CVD method, an ECR-CVD method, an LPCVD method, or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed with a thickness of 115 nm by a plasma CVD method. Note that the gate insulating film 108 is not limited to a silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a stacked structure.

  After that, a conductive film is formed over the gate insulating film 108, the conductive film is patterned, and a gate electrode 109 is formed over the patterned semiconductor film 107. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be formed by an LPCVD method or a PCVD method to serve as a gate electrode. The gate electrode has a single layer structure or a stacked structure. In the case of a stacked structure, a polycrystalline silicon film doped with an impurity element and a conductive film may be stacked. In this embodiment, the gate electrode 109 is formed by patterning a conductive film in which a tantalum nitride film with a thickness of 50 nm and a tungsten film with a thickness of 370 nm are sequentially stacked.

  Next, as shown in FIG. 2C, an impurity element is added using the gate electrode 109 as a mask. In this embodiment mode, B (boron) is added to form an impurity region 110 serving as a source region and a drain region, and P (phosphorus) is added to form an impurity region 111 serving as a source region and a drain region. At this time, a gettering step of capturing a metal element in the source region and the drain region may be performed. After that, a passivation film is preferably provided so as to cover the gate electrode 109 and the gate insulating film 108. Then, the interlayer insulating film 112 is formed using an inorganic material or an organic material. In particular, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and the substituent includes at least hydrogen, or the substituent includes at least one of fluorine, an alkyl group, and an aromatic hydrocarbon. The interlayer insulating film 112 is preferably formed from a material, so-called siloxane.

  As shown in FIG. 2D, wirings (corresponding to source wiring and drain wiring) 113 connected to the impurity regions 110 and 111 are formed. For the wiring 113, a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements may be used. In this embodiment, a titanium film / titanium-aluminum alloy film / titanium film (Ti / Al—Si / Ti) is laminated to 100/350/100 nm, respectively, and then patterned and etched into a desired shape to form the wiring 113. Form.

  As described above, a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. The arrangement of crystal grain boundaries can be controlled by controlling the position of the crystal, that is, the seed crystal region.

  Then, a semiconductor device having the thin film transistor formed as described above can be manufactured. A semiconductor device is an integrated circuit or a semiconductor display device. In particular, a liquid crystal display device, a light emitting device including a light emitting element represented by an organic light emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel). A thin film transistor can be used for a pixel portion and a driver circuit portion of a semiconductor display device such as a field emission display (FED). In particular, in a light emitting device, a structure in which light from an organic light emitting element is emitted from an upper surface emitted to the sealing substrate side, emitted from the lower surface emitted to the substrate side, and emitted from the sealing substrate and the substrate side is used. Can do.

  In particular, since the crystal grains can be reduced by the distance between the seed crystal regions, the thin film transistor is suitable for a thin film transistor having a small channel size such as a thin film transistor of a CPU having an integrated circuit.

(Embodiment 2)
In this embodiment mode, a method for forming a crystalline semiconductor film by a method different from that in Embodiment Mode 2 will be described.

  As shown in FIG. 4A, as in Embodiment Mode 1, a base film 101, an insulating film 103, and a silicon film 115 are formed over a substrate 100, and an opening is formed. However, in this embodiment, the opening is formed in a linear shape. A metal element 105 is formed in the opening by spin coating. In this embodiment, the metal element 105 is formed in the opening by applying an aqueous solution containing 10 ppm of Ni acetate to the opening by a spin coating method. At this time, since an insulating film containing silicon, for example, a silicon oxide film, formed as the base film 101 is formed on the bottom surface of the opening, wettability with respect to Ni acetate is enhanced. On the other hand, since the silicon film 115 is formed on the surface of the insulating film 103, the wettability with respect to Ni acetate is lowered and repels.

As shown in FIG. 4B, an amorphous semiconductor film 106 is formed as in the first embodiment. Then, heat treatment is performed as in Embodiment 1 to form a crystalline semiconductor film. In this embodiment, a continuous wave laser (CW laser) 116 is used. This is because the CW laser is suitable for crystal growth of the amorphous semiconductor film 106 in the lateral direction from the seed crystal region. In particular, as shown in a perspective view corresponding to FIG. 4B shown in FIG. 4C, the CW laser 116 is applied to a linear opening portion serving as a seed crystal region having a depth 150, a width 151, and a length 152. Can be crystallized by a single scan. As a result, the non-uniform crystallization region due to the overlapping region of the laser is preferably reduced. The width of the laser is, for example, a second harmonic such as an excimer laser, a YAG laser, or a YVO ₄ laser. be able to.

  Since subsequent steps such as patterning may refer to the first embodiment, description thereof is omitted.

  As described above, a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. The arrangement of crystal grain boundaries can be controlled by controlling the position of the crystal, that is, the seed crystal region.

  Then, a semiconductor device having the thin film transistor formed as described above can be manufactured. A semiconductor device is an integrated circuit or a semiconductor display device. In particular, a liquid crystal display device, a light emitting device including a light emitting element represented by an organic light emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel). A thin film transistor can be used for a pixel portion and a driver circuit portion of a semiconductor display device such as a field emission display (FED).

(Embodiment 3)
In this embodiment, a method for selectively forming a metal element by a method different from those in Embodiments 1 and 2 will be described.

  As shown in FIG. 9A, a base film 101 and an insulating film 103 are formed over a substrate 100, and an opening is formed in the insulating film by a dry etching method. The second insulating film 120 is formed by a CVD method, for example, a plasma CVD method so as to cover the opening. Then, a second opening having a smaller diameter or width is formed in the opening.

  After that, as in Embodiment Mode 1, the metal element 105 can be formed and crystallized to form a crystalline semiconductor film.

  In this way, the diameter or width of the opening can be accurately reduced. As a result, a region where the metal element 105 and the amorphous semiconductor film 106 are in contact with each other is small, and a seed crystal region with more controlled orientation can be formed. Further, when a seed crystal having a plurality of orientations is formed, only a seed crystal having one orientation can be obtained by controlling the height of the insulating film 103.

  As shown in FIG. 9B, a base film 101 is formed over a substrate 100, a mask 121 is placed over the base film, and a metal element 105 is formed by ion implantation or the like. As the mask, for example, a resist mask or a metal mask can be used.

  Next, the mask 121 is removed, and the amorphous semiconductor film 106 is formed. In order to remove the mask, it is preferable to use a method of fixing a metal element such as ion implantation rather than a coating method such as a spin coating method.

  After that, crystallization can be performed similarly to Embodiment Mode 1 to form a crystalline semiconductor film.

  A metal element can be selectively added using a mask capable of forming such a small slit width. As a result, the insulating film 103 can be dispensed with.

  As described above, a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. The arrangement of crystal grain boundaries can be controlled by controlling the position of the crystal, that is, the seed crystal region.

  Then, a semiconductor device having the thin film transistor formed as described above can be manufactured. A semiconductor device is an integrated circuit or a semiconductor display device. In particular, a liquid crystal display device, a light emitting device including a light emitting element represented by an organic light emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel). A thin film transistor can be used for a pixel portion and a driver circuit portion of a semiconductor display device such as a field emission display (FED).

(Embodiment 4)
In this embodiment, a specific method for manufacturing a thin film transistor formed in a pixel portion will be described.

  FIG. 5A illustrates an example of a top view of a pixel portion having a light emitting element. A signal line 201, a switching transistor 204 connected to the scanning line 203, a driving transistor 205 connected to the switching transistor 204 for driving the light emitting element, and a gate and a source of the driving transistor 205 are provided. And the power source line 202 connected to the other end of the driving transistor 205.

  FIG. 5B is a top view of the pixel portion corresponding to FIG. The crystalline semiconductor film 107 obtained by the above embodiment, the conductive film 109 that serves as a scanning line and a gate electrode, the wiring 113 that serves as a signal line, a source wiring, and a drain wiring, and a wiring that is formed in an interlayer insulating film A contact hole 210 is shown.

  In such a pixel portion, as shown in FIG. 5C, a seed crystal region 104 is formed at the center of one pixel, and twins are grown radially from the seed crystal region to form one crystal grain 115. . Then, as shown in FIG. 5C, the semiconductor film of the switching TFT 204 and the driving TFT 205 is patterned from one crystal grain 115. At this time, with the seed crystal region 104 as the center, in one crystal grain, the switching TFT 204 is formed on one crystal grain boundary side, and the driving TFT 205 is formed on the other crystal grain boundary side. Therefore, the twin grain boundary is not patterned so as to follow the current flow direction of the switching TFT 204 and the driving TFT 205. However, as described above, the twin grain boundaries are unlikely to adversely affect the TFT characteristics, so the layout shown in FIG.

  Further, as shown in FIG. 5D, a linear seed crystal region 104 is formed at the end of one pixel, and a crystal is grown in a direction perpendicular to the direction extending linearly from the seed crystal region. Crystal grains 115 are formed. Then, as shown in FIG. 5D, the semiconductor film of the switching TFT 204 and the driving TFT 205 is patterned from one crystal grain 115. 5D differs from FIG. 5C in that the crystal growth direction is a direction perpendicular to the linear extending direction of the linear seed crystal region. Therefore, the degree of freedom of layout of each TFT is improved. Therefore, it is more preferable to pattern the switching TFT 204 so that the current flows and the direction of crystal growth.

  At this time, if the channel length of the driving TFT is increased, the operation can be reliably performed in the saturation region. It is preferable to operate in the saturation region because variation between driving TFTs due to deterioration with time can be further reduced. Specifically, the semiconductor film of the driving TFT may be patterned in a so-called zigzag state in which a rectangular shape is repeated.

  FIG. 6 illustrates a case where a semiconductor film is patterned with a layout different from that in FIG. In particular, a layout example is shown in which the twin grain boundaries are aligned with the direction of current flow in the switching TFT 204 and the driving TFT 205.

  FIG. 6A shows a top view of the pixel portion as in FIG. 5C and shows the arrangement of the switching TFT 204 and the driving TFT 205. In addition, a seed crystal region 104 and crystal grains 115 grown from the seed crystal region are shown. The positional relationship between the TFTs and the seed crystal regions is such that the twin grain boundaries radially grown from the seed crystal regions 104 are aligned with the current flow directions of the switching TFT 204 and the driving TFT 205. That is, the switching TFT 204 is disposed immediately to the left of the seed crystal region, and the driving TFT 205 is disposed immediately below the seed crystal region. As a result, the twin grain boundaries are aligned with the current flow directions of the switching TFT 204 and the driving TFT 205, so that the mobility of the TFT can be improved.

  In FIG. 6B, there are four switching TFTs 204 and four driving TFTs 205 in a crystal grain 115 formed from one seed crystal region 104. Further, a plurality of TFTs are provided symmetrically with respect to the seed crystal region 104 in order to follow the direction of current flow of the plurality of TFTs and the twin grain boundary.

  In particular, when the definition of the display device is increased, the arrangement interval of the switching TFT 204 and the driving TFT 205, that is, the pixel interval becomes narrower. In such a case, a plurality of switching TFTs 204 and driving TFTs 205 can be provided in crystal grains grown from one seed crystal region, which is suitable for forming a so-called submicron TFT.

  FIG. 7 illustrates a case where a semiconductor film is patterned with a linear seed crystal region and a layout different from that in FIG. 5D is different from FIG. 5C in that the crystal growth direction is a direction perpendicular to the linear extending direction of the seed crystal region 104 as described above. Therefore, as shown in FIG. 7, it is more preferable to perform patterning along the direction in which the current flows through the switching TFT 204 and the direction of crystal growth.

  As described above, a pixel portion including a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. Note that the arrangement of crystal grain boundaries can be controlled by controlling the crystal position.

  This embodiment can be freely combined with the above embodiment.

(Embodiment 5)
In this embodiment, a case where the present invention is applied to a driver circuit portion including a signal line driver circuit and a scan line driver circuit will be described.

  For example, FIG. 8 shows an analog switch provided in the drive circuit unit. As shown in FIG. 8A, the analog switch includes a switch SW1 in which a p-channel TFT 301 and an n-channel TFT 302 are connected, and a switch SW2 in which a p-channel TFT 303 and an n-channel TFT 304 are connected. . SW1 and SW2 are respectively connected to a wiring to which a signal (Signal) is input and a wiring to which an inverted signal (Signalb) of the signal is input. An input voltage (Vin) is applied to one connection location of the p-channel TFT and the n-channel TFT, and the voltage is output from the other connection location by a combination of signals (Vout).

  FIG. 8B is a top view of the pixel portion corresponding to FIG. A crystalline semiconductor film 107 obtained by the above embodiment, a conductive film 109 to be a gate electrode, a wiring 113 to be a source wiring and a drain wiring, and a contact hole 310 for wiring formed in an interlayer insulating film are shown.

  In such an analog switch, a seed crystal region 104 is formed between the n-channel TFTs 301 and 303 as shown in FIG. A seed crystal region is formed between the p-channel TFTs 302 and 304. Crystals are grown from these seed crystal regions to form crystal grains 115. The direction of current flow in each TFT can be formed so as to be substantially along the twin grain boundary where crystals grow from the seed crystal region. As a result, the movement of each TFT can be improved. In addition, since TFTs having the same polarity are patterned from one crystal grain, variation in characteristics of the analog switch can be reduced.

  Further, as shown in FIG. 8D, a linear seed crystal region 104 is formed in the vicinity of the n-channel TFT 301 and the p-channel TFT 302, respectively. From these linear seed crystal regions, crystals are grown in a direction perpendicular to the direction of linear extension of the seed crystal regions to form crystal grains 115. The direction of current flow in each TFT can be formed so as to be along a twin grain boundary where crystals grow from the seed crystal region as compared with FIG. 8C. As a result, the movement of each TFT can be further improved. In addition, since TFTs having the same polarity are patterned from one crystal grain, variation in characteristics of the analog switch can be reduced.

  As described above, an analog switch including a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. Note that the arrangement of crystal grain boundaries can be controlled by controlling the crystal position.

  This embodiment can be freely combined with the above embodiment.

(Embodiment 6)
In this embodiment, a method for forming a panel from a crystalline semiconductor film using any of the above embodiments is described.

  FIG. 11A is a perspective view of a crystalline semiconductor film formed based on the above embodiment mode. A base film 101 is formed over the substrate 100 having an insulating surface, an insulating film 103 is formed over the base film 101, and an opening 130 is formed in the insulating film 103. A metal element is formed in the opening 130 to form a seed crystal region. In FIG. 14A, since the seed crystal regions are highlighted, the interval between the seed crystal regions is different from the actual one. The above embodiment may be referred to for an interval at which an actual seed crystal region is provided.

  As shown in FIG. 11B, an amorphous semiconductor film 106 is formed over the insulating film 103 and crystallized based on the above embodiment mode. As a result, a crystalline semiconductor film with controlled crystals and crystal grain boundaries can be obtained. Note that in this embodiment, a pixel portion, a signal line driver circuit, and a scan line driver circuit are formed using a crystalline semiconductor film in which crystals and crystal grain boundaries are controlled. Therefore, in FIG. 11B, a region to be a pixel portion (pixel portion region) 160, a region to be a signal line driver circuit (signal line driver circuit region) 161, a region to be a scanning line driver circuit (scanning line driver circuit region). 162 is indicated by a dashed line. In addition, the position where the pixel portion, the signal line driver circuit, and the scan line driver circuit are formed is not limited to this embodiment mode, and the pixel portion, the signal line driver circuit, and the scan line driver circuit are symmetrical with respect to the plurality of signal line driver circuits or the pixel portion. A plurality of scanning line driving circuits may be formed at various positions.

  Then, as shown in FIG. 11C, the crystallized semiconductor film is patterned to form an island-shaped semiconductor film 107. At this time, patterning is preferably performed so as to remove the seed crystal region.

  Then, a TFT manufacturing process is performed on the crystalline semiconductor film formed as shown in FIGS. 11A, 11B, and 11C to form a panel having a pixel portion, a signal line driver circuit, and a scan line driver circuit. .

  As described above, a panel including a thin film transistor including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. Note that the arrangement of crystal grain boundaries can be controlled by controlling the crystal position.

  This embodiment can be freely combined with the above embodiment.

(Embodiment 7)
In this embodiment, a module that is completed by mounting an IC including a control circuit, a power supply circuit, an I / F, and the like formed on a printed circuit board through the panel FPC shown in the above embodiment, and a system thereof explain.

  FIG. 13 illustrates a module system.

  Power is supplied from the power supply circuit 930 outside the module to the video signal processing circuit 909. The power circuit 930 outside the module is a power circuit formed on a wiring board mounted on an electronic device. The video signal processing circuit 909 receives a signal from an interface (I / F) unit 908. Further, the video signal processing circuit 909 exchanges signals with the video RAM 910. Then, a signal is input from the video signal processing circuit 909 to the control circuit 901. The control circuit 901 is supplied with power from the power supply circuit 902. The signal is input via the gradation power supply 911, and a signal is input from the video signal processing circuit 909 to the control circuit 901, and power is supplied from the power supply circuit 902. Signals are input from the control circuit 901 to the scan line driver circuit 904 and the signal line driver circuit 905. In addition, power is supplied from the gradation power supply 911 to the signal line driver circuit 905. Signals are input from the scan line driver circuit 904 and the signal line driver circuit 905 to the pixel portion 903 provided over the same substrate 900 as the scan line driver circuit 904 and the signal line driver circuit 905.

  Note that in a light-emitting device having a light-emitting element, the gradation power source 911 is a power source for applying a voltage to the cathode. In a liquid crystal display device having a liquid crystal element, the gradation power source 911 is a power source that applies a voltage to an electrode that applies a voltage to the liquid crystal layer, that is, a so-called counter electrode.

  The module includes a system including a pixel portion 903, a scanning line drive circuit 904, a signal line drive circuit 905, a control circuit 901, a gradation power supply 911, a power supply circuit 902, a video signal processing circuit 909, a video RAM 910, and an I / F unit 908. Have.

  FIG. 12 shows an external view of a module in which the control circuit 901 and the power supply circuit 902 are mounted on the panel 800. The panel includes a pixel portion 903 formed over the substrate 900 and provided with a light emitting element or a liquid crystal element for each pixel, a scanning line driving circuit 904 for selecting a pixel included in the pixel portion 903, and a selected pixel. A signal line driver circuit 905 for supplying a video signal is provided. At this time, the semiconductor element included in the pixel portion 903, the scan line driver circuit 904, or the signal line driver circuit 905 is a crystalline semiconductor film formed by controlling crystallinity and crystal position as in the above embodiment mode. Can have.

  Note that the scan line driver circuit 904 and the signal line driver circuit 905 are not necessarily formed over the same substrate. For example, only the scan line driver circuit 904 is formed over the same substrate, and the signal line driver circuit 905 is formed using an IC chip. May be implemented.

  The printed circuit board 907 is provided with a control circuit 901 and a power supply circuit 902. Various signals and power supply voltages output from the control circuit 901 or the power supply circuit 902 are supplied to the pixel portion 903 and the scan line driver circuit 904 via the FPC 906. , And supplied to the signal line driver circuit 905.

  The power supply voltage and various signals of the printed circuit board 907 are supplied via an interface (I / F) unit 908 in which a plurality of input terminals are arranged.

  Note that in this embodiment mode, the printed board 907 is mounted on the panel using the FPC 906; however, the structure is not necessarily limited thereto. The control circuit 901 and the power supply circuit 902 may be directly mounted on the panel using a COG (Chip on Glass) method.

  Further, in the printed circuit board 907, noise may occur in a power supply voltage or a signal, or a signal may be slow to rise due to a capacitance formed between the drawn wirings or a resistance of the wiring itself. Therefore, various elements such as a capacitor and a buffer may be provided on the printed circuit board 907 so as to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  As described above, a module including a panel including a crystalline semiconductor film in which crystallinity and crystal position are controlled can be formed. Note that the arrangement of crystal grain boundaries can be controlled by controlling the crystal position.

  This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 8)
In this embodiment, a module form different from that of the seventh embodiment will be described.

  The feature of the module shown in FIG. 14 is that a control circuit 901, a video signal processing circuit 909, and a video RAM 910 are formed on a substrate 900. That is, the control circuit 901, the video signal processing circuit 909, and the video RAM 910 are formed over the substrate 900 by the TFT having the crystalline semiconductor film formed by controlling the crystallinity and the crystal position according to the above embodiment mode. Other configurations are the same as those in FIG.

  14 is a system in which a control circuit 901, a video signal processing circuit 909, and a video RAM 910 are provided on a substrate 900 in the system shown in FIG.

  Thus, by integrally forming the control circuit 901, the video signal processing circuit 909, and the video RAM 910 on the substrate 900, the module can be reduced in size and weight. Furthermore, another circuit, for example, a gradation power source 911 may be formed on the substrate 900.

  As described above, modules having various configurations including the above can be formed.

  This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 9)
As an example of an electronic device manufactured by applying the present invention, a digital camera, a sound reproduction device such as a car audio, a notebook personal computer, a game device, a portable information terminal (a mobile phone, a portable game machine, etc.), a home use An image reproducing device including a recording medium such as a game machine may be used. Specific examples of these electronic devices are shown in FIGS.

  FIG. 15A illustrates a mobile phone among mobile terminals, which includes a main body 2101, a housing 2102, a display portion 2103, an audio input portion 2104, an audio output portion 2105, operation keys 2106, an antenna 2107, and the like. The display portion 2103 is provided with a module having a pixel portion and a driver circuit portion. The pixel portion includes a light emitting element or a liquid crystal element, and includes a TFT formed so as to have a crystalline semiconductor film formed by controlling the crystallinity and crystal position of the present invention. Further, a TFT formed so as to have a crystalline semiconductor film formed by controlling the crystal position of the present invention may be provided in the driver circuit portion. Furthermore, the cost of the cellular phone can be reduced by forming the display portion 2103 by multi-cavity.

  FIG. 15B illustrates a mobile computer, which includes a main body 2201, a display portion 2202, a slices 2203, operation buttons 2204, an external interface 2205, and the like. The display portion 2202 is provided with a module having a pixel portion and a driver circuit portion. The pixel portion includes a light emitting element or a liquid crystal element, and includes a TFT formed so as to have a crystalline semiconductor film formed by controlling the crystallinity and crystal position of the present invention. Further, a TFT formed so as to have a crystalline semiconductor film formed by controlling the crystal position of the present invention may be provided in the driver circuit portion. Furthermore, the cost of the mobile computer can be reduced by forming the display portion 2202 by multi-cavity.

  FIG. 15C shows a sheet-type mobile phone, which includes a main body 2301, a display portion 2303, an audio input portion 2304, an audio output portion 2305, a switch 2306, an external connection port 2307, and the like. A separately prepared earphone 2308 can be connected through the external connection port 2307. A touch panel display screen including a sensor is used for the display portion 2303, and a series of operations can be performed by touching a touch panel operation key 2309 displayed on the display portion 2303. The display portion 2303 is provided with a module having a pixel portion and a driver circuit portion. The pixel portion includes a light-emitting element or a liquid crystal element, and includes a TFT formed to have a crystalline semiconductor film formed by controlling the crystallinity and crystal position of the present invention. Further, a TFT formed so as to have a crystalline semiconductor film formed by controlling the crystal position of the present invention may be provided in the driver circuit portion. Further, by forming the display portion 2303 by multi-cavity, the cost of the sheet-type mobile phone can be reduced.

  Crystals in a display device, a notebook personal computer, an image reproducing device (so-called DVD display device or the like) provided with a recording medium, a goggle type display, a video camera, and a driving circuit portion are electronic devices other than those described above. A TFT formed so as to have a crystalline semiconductor film formed by controlling the property and the crystal position can be provided.

  This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 10)
In this embodiment, a structure of a CPU including a thin film transistor obtained by a crystal method for controlling crystals and crystal grain boundaries will be described with reference to block diagrams.

  The CPU shown in FIG. 16 has an arithmetic circuit (ALU) 601, an arithmetic circuit controller (ALU Controller) 602, an instruction analyzer (Instruction Decoder) 603, an interrupt controller (Interrupt Controller) on a substrate 600. 604, timing controller (Timing Controller) 605, register (Register) 606, register controller (Register Controller) 607, bus interface (Bus I / F) 608, rewritable ROM 609, ROM interface (ROM I / F) 620 mainly. The ROM 609 and the ROM I / F 620 may be provided in separate chips.

  Needless to say, the CPU illustrated in FIG. 16 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

  Various circuits as described above can be formed using the thin film transistor formed by the crystal method for controlling the crystal and crystal grain boundary described in the above embodiment mode, particularly the thin film transistor formed on the glass substrate.

  An instruction input to the CPU via the bus I / F 608 is input to the instruction decoder 603 and decoded, and then input to the ALU controller 602, interrupt controller 604, register controller 607, and timing controller 605.

  The ALU Controller 602, Interrupt Controller 604, Register Controller 607, and Timing Controller 605 perform various controls based on the decoded instructions. Specifically, the ALU Controller 602 generates a signal for controlling the operation of the ALU 601. The Interrupt Controller 604 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 607 generates an address of the register 606, and reads and writes the register 606 according to the state of the CPU.

  The timing controller 605 generates a signal for controlling the operation timing of the ALU 601, ALU Controller 602, Instruction Decoder 603, Interrupt Controller 604, and Register Controller 607. For example, the timing controller 605 includes an internal clock generation unit that generates an internal clock signal CLK2 (622) based on the reference clock signal CLK1 (621), and supplies the clock signal CLK2 to the various circuits.

  In particular, a reduction in driving voltage can be expected by reducing the length of the gate electrode of the thin film transistor in the channel length direction (so-called gate length).

  A thin-film transistor on a glass substrate formed by a crystal method for controlling crystals and crystal grain boundaries can provide a low-cost CPU that can be realized only by an inexpensive machine.

It is sectional drawing which showed the crystallization process of this invention. It is a cross-sectional view illustrating a manufacturing process of a thin film transistor of the present invention. It is the top view which showed the crystal grain of this invention. It is sectional drawing which showed the crystallization process of this invention. It is the top view which showed the example of a layout which applied the crystal grain of this invention to the pixel part. It is the top view which showed the example of a layout which applied the crystal grain of this invention to the pixel part. It is the top view which showed the example of a layout which applied the crystal grain of this invention to the pixel part. It is the top view which showed the example of a layout which applied the crystal grain of this invention to the analog switch. It is the top view which showed the example of a layout of the island-like semiconductor film patterned from the crystal grain of this invention. It is sectional drawing which showed the crystallization process of this invention. It is the figure which showed the manufacturing process of the panel of this invention. It is the figure which showed the form of the module of this invention. It is the flowchart which showed the system of the display apparatus of this invention. It is the figure which showed the form of the module of this invention. It is the figure which showed the electronic device which has a crystal grain of this invention. It is the figure which showed CPU which has the crystal grain of this invention.

Claims (10)

Forming an insulating film,
Forming an opening in the insulating film;
Forming a metal element that promotes crystallization on the bottom surface of the opening,
An amorphous semiconductor film is formed to cover the opening and the insulating film,
By heating the amorphous semiconductor film, a crystalline semiconductor film grown from the opening is formed,
And wherein the allowed increase the wettability to the metal element, causes lower wettability to the metal element by forming a silicon film on the upper surface of the insulating film by forming an oxide film on the bottom surface of the opening A method for manufacturing a crystalline semiconductor film. Forming a first insulating film;
An etching method is used to form a first opening in the first insulating film,
Using the CVD method, the second opening is formed by forming the second insulating film so as to narrow the diameter of the first opening,
Forming a metal element that promotes crystallization on the bottom surface of the second opening;
An amorphous semiconductor film is formed to cover the second opening and the second insulating film;
By heating the amorphous semiconductor film, a crystalline semiconductor film grown from the second opening is formed,
Let enhance wettability to the metal element by forming an oxide film on the bottom surface of the second opening, by forming a silicon film on the upper surface of the front Stories second insulating film wettability to the metal element A method for manufacturing a crystalline semiconductor film, characterized by lowering. In claim 1 or claim 2,
A method for manufacturing a crystalline semiconductor film, wherein a gettering sink is formed over the crystalline semiconductor film and the concentration of the metal element is reduced by heating. A method for manufacturing a thin film transistor using the crystalline semiconductor film according to any one of claims 1 to 3 ,
Patterning the crystalline semiconductor film to remove the region where the metal element is formed;
Forming a gate electrode on the patterned crystalline semiconductor film through a gate insulating film;
An impurity region is formed by adding an impurity element to the patterned crystalline semiconductor film using the gate electrode as a mask,
A method for manufacturing a thin film transistor, comprising forming a conductive film connected to the impurity region. In claim 4 ,
A method of manufacturing a thin film transistor, wherein the crystalline semiconductor film is patterned so as to remove a crystal grain boundary of the crystalline semiconductor film that has grown. A method for manufacturing a semiconductor device having the thin film transistor according to claim 4 or 5 ,
In the pixel portion having the switching thin film transistor and the driving thin film transistor,
A semiconductor characterized by patterning the crystalline semiconductor film so as to follow a direction of current flow in a channel formation region of the switching thin film transistor and the driving thin film transistor and a direction of crystal growth of the crystalline semiconductor film Device fabrication method. A method for manufacturing a semiconductor device having the thin film transistor according to claim 4 or 5 ,
In the pixel portion having the switching thin film transistor and the driving thin film transistor,
An opening in which the metal element is formed is formed in a linear shape, and a current flows in a channel formation region of the switching thin film transistor and the driving thin film transistor through the crystalline semiconductor film grown from the linear opening. A method for manufacturing a semiconductor device, characterized in that patterning is performed so that a direction and a direction of crystal growth of the crystalline semiconductor film are aligned. A method for manufacturing a semiconductor device having the thin film transistor according to claim 4 or 5 ,
In the pixel portion having the switching thin film transistor and the driving thin film transistor,
The opening formed with the metal element is formed in a dot shape, and a plurality of switching thin film transistors and driving thin film transistors are arranged symmetrically with respect to the pointed opening.
A semiconductor characterized by patterning the crystalline semiconductor film so as to follow a direction of current flow in a channel formation region of the switching thin film transistor and the driving thin film transistor and a direction of crystal growth of the crystalline semiconductor film Device fabrication method. In any one of Claims 6 thru | or 8 ,
A semiconductor characterized by patterning the crystalline semiconductor film so as to follow a direction of current flow in a channel formation region of the switching thin film transistor and the driving thin film transistor and a twin grain boundary of the crystalline semiconductor film Device fabrication method. A method for manufacturing a semiconductor device having the thin film transistor according to claim 4 or 5 ,
In a driving circuit portion including an analog switch having a plurality of n-channel thin film transistors and a plurality of p-channel thin film transistors,
The plurality of n-channel thin film transistors are formed from the same crystal grains of the crystalline semiconductor film,
The method for manufacturing a semiconductor device, wherein the plurality of p-channel thin film transistors are formed from the same crystal grain of the crystalline semiconductor film.

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