JP4413198B2 - Floating point data summation processing method and computer system - Google Patents

Description

  The present invention relates to a floating point data sum operation processing method and computer system for calculating the sum of floating point data, and more particularly to a floating point data sum operation processing method and computer for calculating the sum of floating point data of a plurality of computer nodes. About the system.

  A parallel computing computer system is provided in which a plurality of nodes including computers are provided and these nodes are connected by a network. In such a parallel computer, one job is calculated in parallel by a plurality of nodes, and these processing data are exchanged via a network. Such a parallel computer is composed of hundreds to thousands of nodes in a large-scale computer.

  In such a parallel computer, data of a plurality of nodes is collected and a specified operation is executed. This is called reduction processing. As such reduction processing, there are an operation for obtaining the sum of the data of all the nodes, an operation for obtaining the maximum value and the minimum value of the data of all the nodes, and the like.

  On the other hand, as a data format handled by a computer, a floating-point format that expresses a numerical value by an exponent part and a mantissa part can express a wider range of numerical values than an expression by a fixed-point format in which the position of the decimal point is constant. FIG. 19 is an explanatory diagram of the floating point format, and shows the IEEE standard floating point format.

  FIG. 19 shows 32-bit single precision floating point data and 64-bit double precision floating point data. Both are composed of a sign bit, an exponent part, and a mantissa part. The sign bit indicates the sign of a numerical value, where “1” represents a negative number and “0” represents a positive number. The exponent part represents an integer value that is a power of 2, and the mantissa part represents a value (normalized number) of 1.0 or more and less than 2.0. Then, the result of exponential expression is multiplied by the mantissa part to represent an actual numerical value.

  In such a sum operation of floating point data, when three or more floating point data are added, the numerical value of the operation result differs depending on the addition order of the three data. 20 and 21 are explanatory diagrams of the sum operation. Here, the value of the double precision floating point data is shown in hexadecimal.

  As shown in FIG. 20, when adding floating-point data 1, 2, 3, 4 consisting of an exponent part and a mantissa part, if data 1, 2, 3, 4 are added in this order, data 1 and data 2 The addition result 1 and the data 3 are added, and the addition result 2 and the data 4 are added.

  On the other hand, as shown in FIG. 21, when data 1, 3, 4, and 2 are added in this order, data 1 and data 3 are added, the addition result 1 and data 4 are added, and the addition result 2 and data 2 are added.

  As shown in the numerical examples of FIGS. 20 and 21, a difference appears in the addition result of the four data. This is because the calculation result for each time is normalized, so that the mantissa part is lost.

  In a parallel computer, since one job is executed in parallel by a plurality of computers, operations such as collecting intermediate results and final results executed in parallel and obtaining a sum may be required. At this time, if the data format is a floating-point format, the fact that the calculation results differ depending on the calculation order affects the accuracy of the parallel calculation. For this reason, there has been proposed a method for guaranteeing the sameness of the calculation results without obeying the calculation order.

  FIG. 22 is an explanatory diagram of such a conventional summation operation of floating point data, and shows a method of guaranteeing the sameness of the operation results without keeping the operation order.

  As shown in FIG. 22, it is effective in terms of processing efficiency to provide a reduction mechanism that performs summation of floating point data of a plurality of nodes separately from each node. First, each of the nodes instructs the reduction mechanism to extract only the exponent part of the floating-point data and obtain the maximum value of the exponent part.

  The reduction mechanism compares the exponent part data sent from each node, holds only the exponent part of the maximum value, and when the comparison of the exponent part data from all nodes is completed, the exponent part of the maximum value is all nodes. Return to.

  Each node performs digit alignment of the mantissa part according to the exponent part of the maximum value returned from the reduction mechanism. Each node then instructs the reduction mechanism to calculate the sum of the mantissa data that has been aligned.

  The reduction mechanism adds the mantissa data sent from each node, and when the addition of the mantissa data from all the nodes is completed, returns the result to all the nodes.

  Each node creates normalized floating point data from the sum of the exponent part data and mantissa part data of the maximum value.

In this way, in the conventional technique, each node performs digit alignment of mantissa data in accordance with the maximum value of the exponent, and the digitized data is sent to the reduction mechanism. Summation can be performed without worrying about the order (for example, Patent Document 1).
JP 2005-506596 A

  However, in the conventional technique, when calculating the sum of floating-point data, two operations of comparing the magnitude of the exponent part and adding the mantissa part are required. For this reason, data exchange between each node and the reduction mechanism is also required twice, and the reduction processing time becomes long. In particular, when the number of nodes increases from several hundred to several thousand, the processing time becomes long, which is an impediment to speeding up parallel processing.

  On the other hand, in order to keep the calculation order, it is conceivable to provide a storage circuit for storing data of all nodes in the reduction mechanism, and to perform addition in order after receiving data of all nodes. However, when the number of nodes increases, the scale of the memory circuit increases, causing an increase in cost. In addition, if the calculation is started after receiving the data of all the nodes, the processing time is increased accordingly. In particular, when the number of nodes increases from several hundred to several thousand, the circuit scale increases and the length of processing time becomes significant.

  An object of the present invention is to provide a floating point data sum operation processing method and a computer system for speeding up the sum operation of floating point data of a large number of nodes.

  Another object of the present invention is to provide a floating point data summation processing method and a computer system that are effective for parallel processing by speeding up the summation of floating point data of a large number of nodes without observing the order of operations. There is.

  Furthermore, another object of the present invention is to provide a floating point data sum operation processing method and computer system for speeding up the sum operation of floating point data of a large number of nodes without providing an unnecessary storage circuit. There is.

To achieve these objects, the present invention includes three or more the sum of the floating point data, the summation processing method for floating point data for computing using a computer, the size of the upper bits of the exponent part of the floating point data the sum of the mantissa sections of a group of maximum upper bit of the exponent portion of the plurality of groups sifts is done, the calculation of the sum of the mantissa sections of a group of maximum upper bits of the exponent sections have the second computer processing performed the steps of circuit calculates a sum of the mantissa sections of a group of maximum upper bits of the exponent is, the addition of the sum of the mantissa sections of a group of maximum upper bit in the second of the exponent And a step of executing an arithmetic circuit of a computer

The computer system of the present invention includes a plurality of nodes and a reduction mechanism that receives floating point data from each of the nodes and calculates a sum of the received floating point data, and the reduction mechanism receives the received The sum of the mantissa part of the group in which the upper bits of the exponent part of the plurality of groups divided by the size of the upper bits of the exponent part of the floating point data is the maximum value, and the upper bit of the exponent part is the second highest value The sum of the mantissa part of the group is calculated, and the sum of the mantissa part of the group having the maximum exponent part is added to the sum of the mantissa part of the group having the second largest exponent part.

A plurality of nodes; and a reduction mechanism for receiving floating point data from each of the nodes and calculating a sum of the received floating point data, wherein each node has an exponent part of the floating point data in the node. the sum of the mantissa sections of a group of maximum upper bits of the exponent portion of the plurality of groups obtained by dividing by the size of the upper bits of the sum of the mantissa sections of a group of maximum upper bits of the exponent sections have the second And sending the calculation result calculated for each group to the reduction mechanism, wherein the reduction mechanism is divided into a plurality of groups divided according to the size of the upper bits of the exponent part of the floating-point data received from a plurality of nodes. receiving in the sum of the mantissa sections of a group of maximum upper bit of the exponent part of the floating point data received from the multiple nodes, from the plurality of nodes in the The upper bits of the exponent part of the floating point data to calculate the sum of the mantissa sections of a group of a second highest value, returns the calculation results calculated for each group in said reduction mechanism in each node, each node The sum of the mantissa part of the group with the maximum exponent part returned from the reduction mechanism and the sum of the mantissa part of the group with the second largest exponent part are added.

  Further, in the present invention, it is preferable that the calculation step compares the high-order bits of the exponent part and, based on the comparison result, the sum of the mantissa part of the group having the maximum exponent part, and the exponent part is 2 And the step of calculating the sum of the mantissa part of the maximum value group.

  Further, in the present invention, it is preferable that the calculating step shifts the mantissa part according to a value of a lower bit of the exponent part to create a mantissa part by expanding a data width; and the data width And calculating the sum of the mantissa part of the group whose exponent part is the maximum value and the sum of the mantissa part of the group whose exponent part is the second largest value.

  Furthermore, in the present invention, it is preferable that the adding step includes a digit of a sum result of a mantissa part of a group having the second largest exponent part and a sum result of a mantissa part of a group having the largest exponent part. And a step of adding the summation result of the group having the maximum exponent part and the summation result of the mantissa part of the group having the second largest exponent part.

  Furthermore, the present invention preferably includes a step of creating the floating point data from the addition result of the mantissa part and the upper bits of the exponent part.

  In the present invention, the calculation result of the group having the maximum exponent is not influenced by the calculation result of the group having the index value of 2 or more, so the group having the maximum exponent is the second largest. By calculating the sum of only the group of values, and adding the sum of the group with the largest exponent part and the group with the second largest exponent part, The identity of calculation results can be guaranteed.

  Hereinafter, embodiments of the present invention will be described in the order of the configuration of a computer system, the configuration of a reduction mechanism, the first embodiment, the second embodiment, and other embodiments. The present invention is not limited to this embodiment.

--Computer system configuration--
1 is a block diagram of an embodiment of a computer system of the present invention, FIG. 2 is a block diagram of a node in FIG. 1, FIG. 3 is a block diagram of a network adapter in FIG. 1, and FIG. It is a frame format figure of transfer data.

  FIG. 1 shows a parallel computer as a computer system. As shown in FIG. 1, the parallel computer includes a plurality of (here, four) nodes 10, 11, 12, and 13, two crossbar switches (in the figure, SWA and SWB) 20, 21 and a reduction mechanism. 22. Each node 10, 11, 12, 13 has three network adapters (indicated by A, B, C in the figure) 14A, 14B, 14C. The network adapters 14A and 14B of the nodes 10, 11, 12, and 13 communicate with each other via the crossbar switches 20 and 21, respectively. In addition, the network adapter 14 </ b> C of each node 10, 11, 12, 13 communicates with the reduction mechanism 22. That is, each of the network adapters 14A, 14B, and 14C of each of the nodes 10, 11, 12, and 13 is connected to the crossbar switches 20 and 21 and the reduction mechanism 22 through a transmission line through an interface such as Ethernet (registered trademark). Is done.

  In the node 10 (11, 12, 13), as shown in FIG. 2, a CPU 40, a memory 44, an IO adapter 46, and the network adapters 14A to 14C are connected via a system controller 42. It is a calculator. A plurality of CPUs 40, memories 44, and IO adapters 46 may be provided according to the processing capability required for this node.

  As shown in FIG. 3, the network adapter 14A (14B, 14C) in FIGS. 1 and 2 includes a host interface control circuit 50 connected to the system controller 42, a transmission control circuit 52, and a network interface connected to the transmission path. A control circuit 54 and a reception control circuit 56 are included. This network adapter 14A (14B, 14C) is in charge of data communication between nodes and with the reduction mechanism 22.

  When data is transferred via the network adapter 14A (14B, 14C), communication is performed in a frame format as shown in FIG. The frame format shown in FIG. 4 is a frame format used in Ethernet (registered trademark), and includes a destination address, a transmission source address, a frame type (for example, command type, data size, etc.), data, and frame. Checksum (for example, CRC (Cyclic Redundancy Code)). The data length (data size) of the data area is variable, and the transfer data is divided into a plurality of frames and transferred as necessary.

--Reduction mechanism configuration--
FIG. 5 is a configuration diagram of the reduction mechanism of FIG. As shown in FIG. 5, the main part of the reduction mechanism 22 is a network control unit 22-1 for controlling transmission / reception from each node, converts floating point data from each node described later into a predetermined data format, and A data converter 22-2 for converting the calculation result into floating point data, a register 22-3 for holding the received data after the data conversion, an arithmetic circuit (ALU1, ALU2) 22-4 for executing various reduction operations 22-7, registers (R1, R2) 22-5 and 22-8 for holding operation results, comparison circuit (CMP) 22-6 for comparing data, and registers 22-5 and 22-8 are selected. Multiplexer 22-9.

  The reception data converted by the data converter 22-2 is held in the first register 22-3 and input to the first arithmetic circuit 22-4, the second arithmetic circuit 22-7, and the comparison circuit 22-6. Is done. The comparison circuit 22-6 compares the upper bits of the exponent part as will be described later. The calculation result of the first calculation circuit 22-4 is held in the second register 22-5 and input to the first calculation circuit 22-4, the comparison circuit 22-6, and the third register 22-8. Is done.

  Furthermore, the data held in the third register 22-8 is input to the second arithmetic circuit 22-7. The first and second arithmetic circuits 22-4 and 22-7 perform addition in accordance with the comparison result of the comparison circuit 22-6. The second register 22-5 holds the operation result of the mantissa part corresponding to the group whose exponent part is the maximum value, and the third register 22-8 corresponds to the group whose exponent part is the second largest value Holds the mantissa result.

  In this embodiment, a data converter 22-2, an arithmetic circuit 22-7, a register 22-8, and a multiplexer 22-9 are added to the configuration of the conventional reduction mechanism.

-First embodiment-
FIG. 6 is an explanatory diagram of the first embodiment of the floating point sum operation processing of the present invention, FIG. 7 is an explanatory diagram of the data conversion processing of FIG. 6, and FIG. 8 is a complement of the data conversion processing of FIG. FIG. 9 is an explanatory diagram of the arithmetic processing based on the comparison result of FIG. 5 and FIG. 6, FIGS. 10 and 11 are explanatory diagrams of the processing for converting the arithmetic result into floating point data, FIG. FIG. 4 is a relationship diagram between the upper bits of the exponent part and the absolute values of the mantissa part.

  As shown in FIG. 6, the nodes 10, 11, 12, and 13 send the floating point data to be reduced to the reduction mechanism 22 as it is, and instruct the calculation of the sum.

  The reduction mechanism 22 adds the floating point data from all nodes in the order of arrival and returns the calculation result to all nodes. In this addition processing, data conversion processing described later in FIGS. 7 and 8, addition processing based on magnitude comparison described later in FIG. 9, and processing for converting operation results described later in FIGS. 10 and 11 into floating point data are executed. To do. Then, the nodes 10, 11, 12, and 13 receive the calculation result from the reduction mechanism 22.

  Next, the sum calculation process of the reduction mechanism 22 will be described. In the following description, the 64-bit double-precision floating point data shown in FIG. 19 will be described as an example, but 32-bit single-precision floating point data can be processed in the same manner.

  As shown in FIG. 7, the data width of the sum operation is determined. When the maximum number of data to be calculated is 127, in the calculation for calculating the sum, there is a possibility that the effective digits increase to a maximum of 7 digits (2 7 = 128). Therefore, first, the number of digits of the mantissa part of floating point data (52 bits in double precision) and the number of digits (7 bits) are summed. That is, 52 + 7 = 59 bits.

  Next, the number of bits to be reduced in the lower bits of the exponent part is determined. The condition is that the number of digits that can be expressed by the number of bits to be reduced is larger than the total number of digits described above. The number of bits to be reduced is 31 in 5 bits and 63 in 6 bits (2 6 = 64). In double precision, the total number of digits described above is 59 bits, and the number of bits reduced beyond the total value satisfies the condition with the lower 6 bits of the exponent part.

  Therefore, the necessary data width is 52 (mantissa part) +7 (increment number of digits) +63 (shift amount) +2 (others) = 124 bits. The other bits are the most significant digit in which the mantissa part is omitted and the sign bit.

  Thus, when the calculation data width is determined, the floating point data is converted into conversion data having this data width as shown in FIG. That is, in the case of the 124-bit width of the double-precision floating point data, the most significant digit of the mantissa is supplemented, and the mantissa is set at a position shifted by the lower 6 bits of the exponent. Also, except for the mantissa part, “0” is set. In the floating point, when the value is other than zero, the most significant digit “1” is omitted, and thus the above-described compensation is required.

  If the sign indicates a negative number, as shown in FIG. 8, it is converted to a 124-bit width and then converted to a two's complement expression. The mantissa part is converted by the data converter 22-2 of FIG. 5, and the first bit of the exponent part and the converted mantissa part are set in the first register 22-3.

  Next, the sum calculation process will be described with reference to FIG. In FIG. 9, exponent 1 and mantissa 1 represent the newly received exponent part upper bits and mantissa part, exponent 3 and mantissa 3 represent the maximum value of the exponent part upper bits and the mantissa part of the operation result, and the mantissa 4 represents a mantissa part corresponding to the second maximum value in the exponent part upper bits of the operation result.

  In FIG. 5, the exponent 1 and mantissa 1 are in the first register 22-3, the exponent 3, mantissa 3 is in the second register 22-5, and the mantissa 4 is in the third register 22-8. Set. When the high-order bit and mantissa part of the newly received floating-point data are set in the first register 22-3, the comparison circuit 22-6 makes the exponent 1 and the exponent 3 of the second register 22-5. And compare.

  As shown in FIG. 9, when the comparison result of the comparison circuit 22-6 is exponent 1> exponential 3 + 1, the exponent 1 is the maximum, so the second register 22-5 is passed through the arithmetic circuit 22-4. Then, the exponent 1 and the mantissa 1 are set as the new exponent 3 and the new mantissa 3, and “0” is set in the third register 22-8 because the exponent 3 is not the second maximum value.

  Further, when the comparison result of the comparison circuit 22-6 is exponent 1 = exponent 3 + 1, the exponent 1 is the maximum. Therefore, the exponent 1, 1 is stored in the second register 22-5 via the arithmetic circuit 22-4. The mantissa 1 is set as the new exponent 3 and the new mantissa 3, and since the exponent 3 is the second maximum value, the mantissa 3 of the second register 22-5 is set in the third register 22-8. .

  When the comparison result of the comparison circuit 22-6 is index 1 = index 3, the index 1 and the index 3 are the same maximum value group, so that the arithmetic circuit 22-4 includes the second register 22-5. Instructs the mantissa 3 to add the mantissa 1, sets the exponent 3 and the mantissa 1 + mantissa 3 as the new exponent 3 and the new mantissa 3 in the second register 22-5, and sets the third register 22-8. The value (mantissa 4) is not changed.

  When the comparison result of the comparison circuit 22-6 is exponent 1 + 1 = exponent 3, the exponent 3 is the maximum. Therefore, the exponent 3 and mantissa 3 of the second register 22-5 are not changed, and the exponent 1 is Since it is the second maximum value, the arithmetic circuit 22-7 is instructed to add the mantissa 4 of the third register 22-8 and the mantissa 1, and the mantissa 1 + mantissa is stored in the third register 22-8. 4 is set as the new mantissa 4.

  When the comparison result of the comparison circuit 22-6 is exponent 1 + 1 <exponent 3, the exponent 3 is the maximum, and the exponent 1 is not the second maximum value, so that the exponent 3 and mantissa 3 of the second register 22-5 The mantissa 4 of the third register 22-8 is not changed.

  In this way, the exponent with the highest value of the upper part of the exponent part (new exponent 3), the operation result of the mantissa part with the highest exponent bit (new mantissa 3), and the upper bit of the exponent part An operation result (new mantissa 4) of the mantissa part having the second largest value is obtained.

  Next, conversion processing from the obtained three values of the new exponent 3, the new mantissa 3 and the new mantissa 4 to the normalized floating point data will be described with reference to FIGS.

  First, as shown in FIG. 10, the mantissa 4 which is the result of the operation of the mantissa part having the second highest value of the exponent part is aligned with the mantissa part having the maximum value of the upper bit of the exponent part. Therefore, the value is shifted to the right by 64 bits, and the value of bit 123 (all “0” or “1”) is filled in the upper bits. Next, the value of mantissa 4 and the value of mantissa 3 that have been aligned are added to obtain the sum.

  Next, as shown in FIG. 11, the sum of the exponent 3 which is the maximum value of the exponent upper bits and the mantissa obtained in FIG. 10 is converted into double precision floating point data. For example, a 1-bit code, an 11-bit exponent, and a 52-bit mantissa are created from a 5-bit (bits 62 to 58) exponent and a 124-bit mantissa, as will be described later.

  In FIG. 5, the data conversion unit 22-2 obtains the holding values of the second register 22-5 and the third register 22-8, and performs the above-described digit alignment, summation, and conversion.

  FIG. 12 is a diagram showing the relationship between the exponent upper bits and the range of absolute values indicated by the mantissa part. First, as described above, the lower-order bits of the exponent part are deleted and reflected in the mantissa part, so that the arithmetic data is expressed by the exponent part of 5 bits (bits 62 to 58) and the mantissa part of 124 bits. The mantissa part is determined in consideration of the maximum number of data to be calculated (127 in FIG. 7 described above) so as not to overflow even when the total sum is obtained.

  As shown in FIG. 12, a certain exponent number group (here, from a group having the same value of the high-order bits of the exponent and a range of absolute values of numerical values represented by an exponent part and a mantissa part as a result of calculating the sum for each group) In this case, the least significant bit of n) indicates a value whose exponent value is larger than the most significant bit of an exponent value group (here, n−2) that is separated by two.

  That is, it can be understood that the calculation result of the group having the exponent value of 2 or more is not affected by the calculation result of the group having the maximum exponent part. This is the same meaning as when zero is added when the mantissa part digit alignment is executed due to the exponent part difference.

  And in the calculation to find the sum of groups with the same exponent part, the mantissa part is shifted and the significant digits are increased according to the lower bits (here, 6 bits) of the exponent part. Does not occur. For this reason, in the calculation between groups having the same exponent shown in FIG. 9, the same calculation result is obtained regardless of the calculation order.

  Furthermore, as described above, the calculation result of the group having the maximum exponent is not affected by the calculation result of the group having the index value of 2 or more, so the group having the maximum value of the exponent and the second maximum value are not affected. Calculate the sum of only the groups. Then, calculate the sum of the group with the largest exponent and the group with the second largest value separately, and finally, align the digits and calculate the sum of both. Even if there is no calculation, the same result can be guaranteed.

  Next, an embodiment including actual numerical values will be described with reference to FIGS. Here, an example will be described in which the lower 6 bits of the exponent part is deleted and the mantissa part is expanded in the IEEE standard double precision floating point format data, and the arithmetic data is four. The numerical values are all expressed as hexadecimal values, and when the number of bits is less than “4”, they are expressed as the right hand.

  FIG. 13 shows converted data in which the lower 6 bits of the exponent part of data 1, 2, 3, 4 are deleted and the mantissa part is extended. The data 1, 2, 3, and 4 are expressed in decimal values, and are “2.59407338553641E + 18”, “2.8882303761571212E + 18”, “−2.266735911777743E + 23”, and “2.266777049994257E + 23”. “E + 18” indicates 10 to the 18th power.

  As shown in FIG. 13, before conversion, data 1 has an exponent = 44C, a mantissa = 8 0018 0000 0000, and a sign is +. In midway 1, the omitted most significant digit “1” is filled in, and the mantissa is expanded to 124 bits. Next, the mantissa part of 124 bits is shifted 12 bits to the left by the lower 6 bits (= 0C) of the exponent part. The exponent part stores the upper 5 bits. This 5-bit exponent value indicates an exponent group.

  The same applies to data 2, and since the sign indicates a negative number, a complement operation for the converted data is added. Thereafter, conversion data of data 3 and 4 is obtained in the same manner.

  Next, the data 1, 2, 3, and 4 are calculated for each exponent value group. As can be understood from FIG. 13, data 1 and 2 are the same exponent value group, and data 3 and 4 are another same exponent value group. As shown in FIG. 14, the mantissa part of data 1 and the mantissa part of data 2 are added to obtain mantissa 3 (see FIG. 9) of the exponent value group (exponent = 11).

  Next, similarly, the mantissa part of the data 3 and the mantissa part of the data 4 are added to obtain the mantissa 4 (see FIG. 9) of the exponent value group (exponent = 10). Since the mantissa 4 is different from the mantissa 3 in the exponent part by 64 (= 6 bits), the mantissa 4 is shifted to the right by 64 bits to match the exponent part according to the principle of FIG. Then, the shifted value is added to the mantissa 3, and the final calculation result is obtained.

  This final operation result is converted into a double precision floating point format as shown in FIG. On the way 1, since the exponent group is indicated by the upper 5 bits, zeros are filled in the omitted lower 6 bits. Next, on the way 2, since the number of significant digits of the mantissa part of the double-precision floating point is 53 bits, it is converted to a mantissa part of 53 bits. At this time, the left end of 53 bits of the mantissa is converted to “1”. In FIG. 15, the value obtained by shifting the lower 53 bits to the left by 3 bits becomes the mantissa part, and since the value is shifted by 3 bits to the left, the exponent part is changed to a value of “−3”. In the converted code, the leftmost value of the mantissa part of 124 bits becomes the sign bit as it is.

  On the way 3, the leftmost 1 bit in the 53-bit mantissa is omitted, so the floating point format uses 52 bits. After conversion, double-precision floating-point format data consisting of a 1-bit sign bit, an 11-bit exponent part, and a 52-bit mantissa part is obtained.

-Second embodiment-
FIG. 16 is an explanatory diagram of the floating-point sum calculation processing according to the second embodiment of the present invention, FIG. 17 is a configuration diagram of the reduction mechanism, and FIG. 18 is a relationship diagram between the comparison result of FIG. is there. In this embodiment, there are a plurality of CPUs 40 in a node. First, the floating point summation operation in the node is performed in the node, and then the reduction mechanism 22 performs the floating point summation operation in all the nodes. It is an example which implements.

  As shown in FIG. 16, each of the nodes 10, 11, 12, and 13 calculates the sum of each floating point data summation of each of the plurality of CPUs by the processing shown in FIGS. Then, the obtained exponent part and mantissa part are sent to the reduction mechanism 22 to instruct the calculation of the sum between the nodes.

  As shown in FIG. 17, the reduction mechanism 22 does not include a data conversion unit 22-2 as compared with the configuration of FIG. That is, since the converted exponent part and mantissa part are sent, no conversion operation is necessary. Then, the reduction mechanism 22 adds the exponent and mantissa data from all nodes in the order of arrival and returns the calculation result to all nodes. In this addition process, an addition process based on size comparison, which will be described later with reference to FIG. 18, is executed. Then, the nodes 10, 11, 12, and 13 receive the calculation result from the reduction mechanism 22, and create the normalized floating point data shown in FIGS.

  Next, the sum calculation process of the reduction mechanism 22 will be described with reference to FIG. In FIG. 18, as in FIG. 9, exponent 1 and mantissa 1 represent the newly received exponent part upper bits and mantissa part, and mantissa 2 represents the second largest exponent part upper bit of the newly received data. The mantissa part corresponding to the value, the exponent 3, and the mantissa 3 represent the maximum value and the mantissa part of the exponent part upper bit of the operation result, and the mantissa 4 corresponds to the second highest value of the exponent part upper bit of the operation result Represents the mantissa part.

  In FIG. 17, the exponent 1, mantissa 1 and mantissa 2 are in the first register 22-3, the exponent 3 and mantissa 3 are in the second register 22-5, and the mantissa 4 is in the third register 22. Set to -8. When the high-order bit and mantissa part of the newly received floating-point data are set in the first register 22-3, the comparison circuit 22-6 makes the exponent 1 and the exponent 3 of the second register 22-5. And compare.

  As shown in FIG. 18, when the comparison result of the comparison circuit 22-6 is exponent 1> exponential 3 + 1, the exponent 1 is the maximum, and therefore the second register 22-5 is passed through the arithmetic circuit 22-4. The exponent 1 and the mantissa 1 are set as the new exponent 3 and the new mantissa 3, and the mantissa 2 is set in the third register 22-8.

  Further, when the comparison result of the comparison circuit 22-6 is exponent 1 = exponent 3 + 1, the exponent 1 is the maximum. Therefore, the exponent 1, 1 is stored in the second register 22-5 via the arithmetic circuit 22-4. The mantissa 1 is set as a new exponent 3 and a new mantissa 3, and since the second maximum value is the exponent 3 in the third register 22-8, the mantissa 2 + mantissa 3 is set in the arithmetic circuit 22-7. The mantissa 2 + the mantissa 3 is set.

  When the comparison result of the comparison circuit 22-6 is index 1 = index 3, the index 1 and the index 3 are the same maximum value group, so that the arithmetic circuit 22-4 includes the second register 22-5. Instructs mantissa 3 to add mantissa 1, sets exponent 3 and mantissa 1 + mantissa 3 as new exponent 3 and new mantissa 3 in second register 22-5, and stores in third register 22-8 The arithmetic circuit 22-7 calculates the mantissa 2 + the mantissa 4, and sets the mantissa 2 + the mantissa 4.

  When the comparison result of the comparison circuit 22-6 is exponent 1 + 1 = exponent 3, the exponent 3 is the maximum. Therefore, the exponent 3 and mantissa 3 of the second register 22-5 are not changed, and the exponent 1 is Since it is the second maximum value, the arithmetic circuit 22-4 is instructed to add the mantissa 4 of the third register 22-8 and the mantissa 1, and the mantissa 1 + mantissa 4 is instructed to the third register 22-8. Is set as the new mantissa 4.

  When the comparison result of the comparison circuit 22-6 is exponent 1 + 1 <exponent 3, the exponent 3 is the maximum, and the exponent 1 is not the second maximum value, so that the exponent 3 and mantissa 3 of the second register 22-5 The mantissa 4 of the third register 22-8 is not changed.

  In this way, the exponent with the highest value of the upper part of the exponent part (new exponent 3), the operation result of the mantissa part with the highest exponent bit (new mantissa 3), and the upper bit of the exponent part An operation result (new mantissa 4) of the mantissa part having the second largest value is obtained.

  Finally, three data of exponent 3, mantissa 3, and mantissa 4 are returned to all nodes. All nodes create normalized floating point data from the received exponent 3, mantissa 3, and mantissa 4.

  In this way, it is also possible to perform floating point summation calculation within a node and to perform floating point summation calculation between nodes by a reduction mechanism.

-Other embodiments-
In the above-described embodiment, the 64-bit double-precision floating point data has been described. However, the present invention can also be applied to 32-bit single-precision floating point data. In this case, since the number of increased digits depends on the maximum number of data, it is the same as 7 bits. However, since the shift amount may be 5 bits, the data width is 23 (mantissa part). + 7 + 31 + 2 = 63 bits.

  In addition, although the description has been given for the four-node parallel computer, the invention can be applied to a parallel computer having two or more nodes. Further, the configuration of the node has been described with a computer unit such as a CPU and a memory, but other computer configurations may be used. Furthermore, the format of the transmission path is not limited to Ethernet (registered trademark), and other network protocols can be applied.

  (Supplementary note 1) In the floating point data sum operation processing method for calculating the sum of three or more floating point data, the exponent part of a plurality of groups divided by the size of the exponent part of the floating point data has a maximum value. Calculating the sum of the mantissa part of the group and the sum of the mantissa part of the group whose exponent part is the second largest value; the sum of the mantissa part of the group whose exponent part is the maximum value; And a step of adding the sum of the mantissa part of the second largest value group to the sum of mantissa parts.

  (Additional remark 2) The said calculation step compares the high-order bit of the said exponent part, According to the said comparison result, the sum total of the mantissa part of the group whose exponent part is the maximum value, and the said exponent part are the 2nd maximum value The floating point data sum operation processing method according to appendix 1, characterized by comprising the step of calculating the sum of the mantissa part of the group.

  (Supplementary Note 3) The calculation step includes a step of creating a mantissa part by expanding the data width by shifting the mantissa part according to a value of a lower bit of the exponent part, and a mantissa part by extending the data width And calculating the sum of the mantissa part of the group whose exponent part is the maximum value and the sum of the mantissa part of the group whose exponent part is the second largest value using Method for summation processing of floating point data.

  (Supplementary Note 4) The adding step includes a step of performing digit alignment between the summation result of the mantissa part of the group having the second largest exponent part and the summation result of the mantissa part of the group having the largest exponent part; And adding the summation result of the group having the maximum exponent part and the summation result of the mantissa part of the mantissa part of the group having the second largest exponent value. Method for summation processing of floating point data.

  (Supplementary note 5) The floating point data sum operation processing method according to supplementary note 1, further comprising the step of creating the floating point data from the addition result of the mantissa part and the upper bits of the exponent part.

  (Supplementary note 6) A plurality of nodes and a reduction mechanism for calculating the sum of the floating point data of each of the nodes, wherein the reduction mechanism includes a plurality of groups divided according to the size of the exponent part of the floating point data. The sum of the mantissa part of the group whose exponent part is the maximum value and the sum of the mantissa part of the group whose exponent part is the second largest value are calculated, and the sum of the mantissa part of the group whose exponent part is the maximum value and The computer system is characterized in that the exponent part is added to the sum of the mantissa part of the group having the second largest value.

  (Supplementary note 7) The reduction mechanism compares the higher order bits of the exponent part, and, according to the comparison result, the sum of the mantissa part of the group having the maximum exponent part and the exponent part having the second highest value The computer system according to appendix 6, wherein the sum of the mantissa part of the group is calculated.

  (Supplementary Note 8) The reduction mechanism shifts the mantissa part according to the value of the low-order bit of the exponent part, creates a mantissa part with an expanded data width, and uses the mantissa part with the expanded data width The computer system according to appendix 6, wherein the sum of the mantissa part of the group having the maximum exponent part and the sum of the mantissa part of the group having the second largest exponent part are calculated.

  (Supplementary Note 9) The reduction mechanism performs digit alignment between the summation result of the mantissa part of the group having the second largest exponent part and the summation result of the mantissa part of the group having the largest exponent part, The computer system according to appendix 6, wherein the summation result of the group having the maximum exponent part and the summation result of the mantissa part of the group having the second largest exponent value are added to the digit part.

  (Supplementary note 10) The computer system according to supplementary note 6, wherein the reduction mechanism creates the floating point data from the addition result of the mantissa part and the upper bits of the exponent part.

  (Supplementary note 11) A plurality of nodes and a reduction mechanism for calculating the sum of the floating point data of each of the nodes, wherein each of the nodes is divided by the size of the exponent part of the floating point data in the node The sum of the mantissa part of the group having the maximum value in the exponent part of the group and the sum of the mantissa part of the group having the second largest value in the exponent part is sent to the reduction mechanism, and the reduction mechanism Calculates the sum of the mantissa part of the group having the largest exponent part of the plurality of nodes and the sum of the mantissa part of the group having the second largest value of the exponent part, and returns the calculation result to each node. The exponent part returned from the reduction mechanism adds the sum of the mantissa part of the group with the maximum value and the sum of the mantissa part of the group with the second largest value of the exponent part. Computer systems that.

  (Additional remark 12) Each said node compares the high-order bit of the said exponent part, and according to the said comparison result, the sum total of the mantissa part of the group whose said exponent part is the maximum value, and the said exponent part are the 2nd largest The computer system according to appendix 11, wherein the sum of the mantissa part of the group is calculated.

  (Additional remark 13) Each said node shifts the said mantissa part according to the value of the low-order bit of the said exponent part, creates the mantissa part which expanded the data width, and uses the mantissa part which expanded the said data width The computer system according to claim 11, wherein the sum of the mantissa part of the group having the maximum exponent part and the sum of the mantissa part of the group having the second largest exponent part are calculated.

  (Supplementary Note 14) Each of the nodes performs digit alignment of the summation result of the mantissa part of the group having the second largest exponent part and the summation result of the mantissa part of the group having the largest exponent part, The computer system according to appendix 11, wherein the summation result of the group having the maximum exponent part and the summation result of the mantissa part of the group having the second largest exponent value are added to the digit part.

  (Supplementary note 15) The computer system according to supplementary note 11, wherein each node creates the floating-point data from the addition result of the mantissa part and the upper bits of the exponent part.

  (Supplementary note 16) A plurality of nodes and a reduction mechanism for calculating the sum of the floating point data of each of the nodes, wherein each of the nodes is divided by the size of the exponent part of the floating point data in the node The sum of the mantissa part of the group having the maximum value in the exponent part and the sum of the mantissa part of the group having the second largest value in the exponent part is sent to the reduction mechanism, and the reduction result is sent to the reduction mechanism. The mechanism calculates the sum of the mantissa part of the group having the largest exponent part of the plurality of nodes and the sum of the mantissa part of the group having the second largest value of the exponent part, and the mantissa of the group having the largest exponent part. A computer system characterized by adding the sum of the parts and the sum of the mantissa part of the group having the second largest value in the exponent part.

  (Supplementary note 17) A program for causing a computer to calculate the sum of three or more floating-point data, wherein the exponent part of a plurality of groups divided by the size of the exponent part of the floating-point data is a group having the maximum value Calculating the sum of the mantissa part, the sum of the mantissa part of the group with the second largest value of the exponent part, the sum of the mantissa part of the group with the largest value of the exponent part, and the second part of the exponent part And causing the computer to execute the step of adding to the sum of the mantissa part of the maximum value group.

  Since the calculation result of the group with the maximum exponent is not affected by the calculation result of the group with the index value of 2 or more, the sum of only the group with the maximum value of the exponent and the group with the second maximum value is added. By calculating and adding the sum of the group having the maximum exponent part and the group having the second largest value, the sameness of the calculation result can be guaranteed even if the calculation is performed regardless of the numerical calculation order.

It is a block diagram of the computer system of one embodiment of this invention. It is a block diagram of the node of FIG. It is a block diagram of the network adapter of FIG.1 and FIG.2. FIG. 2 is a format diagram of a transmission frame in FIG. 1. It is a block diagram of the reduction mechanism of FIG. It is explanatory drawing of the sum total calculation process of the floating point data of the 1st Embodiment of this invention. It is explanatory drawing of the data conversion process of FIG. It is explanatory drawing of the complement data creation process of FIG. FIG. 6 is a relationship diagram between the comparison result of FIG. 5 and arithmetic processing. It is explanatory drawing of the sum total addition process of FIG. It is explanatory drawing of the conversion process to the floating point data of FIG. FIG. 7 is a relationship diagram between the upper bits of the exponent of FIG. 6 and the absolute value of the mantissa part. It is explanatory drawing of the Example of the data conversion process of FIG. It is explanatory drawing of the Example of the sum total addition process of FIG. It is explanatory drawing of the Example of the conversion process to the floating point data of FIG. It is explanatory drawing of the sum total calculation process of the floating point data of the 2nd Embodiment of this invention. It is a block diagram of the reduction mechanism of FIG. FIG. 18 is a relationship diagram between the comparison result of FIG. 17 and arithmetic processing. It is explanatory drawing of the format of floating point data. It is explanatory drawing of the sum total calculation process of the conventional floating point data. It is explanatory drawing of the sum total calculation process of the conventional floating point data which replaced the calculation order of FIG. It is explanatory drawing of the sum total calculation process of the floating point data which does not need to follow the conventional calculation order.

Explanation of symbols

10, 11, 12, 13 Nodes 14A, 14B, 14C Network adapter 20, 21 Crossbar switch 22 Reduction mechanism (floating point summation circuit)
40 CPU
42 System Controller 44 Memory 46 IO Adapter 50 Host Interface Control Circuit 52 Transmission Control Circuit 54 Network Interface Control Circuit 56 Reception Control Circuit

Claims (3)

In a floating point data sum operation processing method for calculating the sum of three or more floating point data using a computer ,
The sum of the mantissa part of the group in which the upper bits of the exponent part of the plurality of groups divided by the size of the upper bits of the exponent part of the floating point data is the maximum value, and the upper bit of the exponent part is the second largest value A calculation circuit of a computer calculates a sum of mantissa parts of the group of
The sum of the mantissa sections of a group of maximum upper bits of the exponent section, a mantissa operation circuit processing computers for adding the sum of a group of maximum upper bits of the exponent sections have the second run summation processing method for floating point data, comprising the steps of:. Multiple nodes,
A reduction mechanism that receives floating point data from each of the nodes and calculates the sum of the received floating point data;
The reduction mechanism includes the sum of the mantissa part of the group having the highest value of the upper bits of the exponent part of the plurality of groups divided by the size of the upper bits of the exponent part of the received floating-point data, and the upper part of the exponent part . bits calculated the sum of the mantissa sections of a group of a second highest value, the sum of the mantissa sections of a group of which exponent sections have a maximum value, the sum of the mantissa sections of the group of the maximum value the exponent sections have the second A computer system characterized by performing addition with. Multiple nodes,
A reduction mechanism that receives floating point data from each of the nodes and calculates the sum of the received floating point data;
Wherein each node includes: the total upper bit of the exponent portion of the plurality of groups divided by the size of the upper bits of the exponent part of the floating point data of the mantissa sections of a group of maximum value in the node, the exponent a sum of the mantissa sections of a group of maximum calculated upper bits in the second, feeding the calculation results calculated for each group in the reduction mechanism,
In the reduction mechanism, the upper bits of the exponent part of the floating-point data received from the plurality of nodes have the maximum value among the groups divided by the size of the upper bits of the exponent part of the floating-point data received from the nodes . Calculate the sum of the mantissa part of the group and the sum of the mantissa part of the group with the second highest value of the exponent part of the floating-point data received from the multiple nodes , and calculate for each group in the reduction mechanism Returns the calculated result to each node,
Each node adds the sum of the mantissa part of the group whose exponent part is the maximum value returned from the reduction mechanism and the sum of the mantissa part of the group whose index part is the second largest value. A featured computer system.

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