JP4410297B2 - Reconfigurable circuit - Google Patents

Description

  The present invention relates to a technology for controlling state transition of a reconfigurable circuit.

  Conventionally, in a reconfigurable circuit, the operation of each computing element (hereinafter referred to as processing element PE) and the connection information between PEs are defined on the memory as configuration data to realize the desired processing. Yes. Then, it is possible to change the processing to be implemented by changing the configuration data. Therefore, by treating the configuration data as one state and providing a state management unit for managing transitions between states, it is possible to realize processing while dynamically switching between a plurality of states.

  FIG. 9 shows a configuration of a conventional reconfigurable circuit. The reconfigurable circuit includes a state management unit 91, a plurality of processing elements 92, and a configuration memory 93. In the example shown in FIG. 9, the state management unit 91 manages four states. The four states are: 1) A-c1, B-c1 state, 2) A-c2, B-c1 state, 3) A-c1, B-c2 state, 4) A-c2, B-c2 It is a state. The elements corresponding to 1) to 4) are stored as configuration data in the configuration memory 93 provided in each PE 92 (PE-A, PE-B... PE-E, PE-F). The contents stored in each configuration memory 93 are different for each PE 92. In this way, large-scale data processing is executed by the PE 92 that realizes processing while dynamically switching a plurality of states.

  However, a plurality of states are required, for example, when the state transition of the large number of PEs 92 is managed by one state management unit 91, that is, when a plurality of loop transitions are executed together. The number of states becomes enormous as the number of state transitions to be combined and the number of states in each transition increases, which impedes the operation efficiency of the PE. In particular, when there is a conditional branch in the state transition, the number of states to be managed becomes enormous and it becomes difficult to manage by the state management unit.

  According to Patent Documents 1 to 3 for such problems, a plurality of state management units are introduced as a method for effectively using the memory by reducing the number of states stored in the configuration memory, A method has been proposed in which the management unit manages the state of the processing element under management while synchronizing the state management units.

  Further, Patent Document 4 discloses that in a SIMD array processor, a fixed decoder logic circuit and an LUT method are provided in a PE, so that a selected bit of a global instruction is modified locally by the LUT method. I have a proposal to improve.

  In Patent Document 5, an LUT method is used in an array processor that processes image data at high speed. In Patent Document 6, a series of processing data input from the outside is distributed to a large number of bits and a fractional bit and processed in parallel for each PE to improve the efficiency of the array processor.

However, in Patent Documents 1 to 3, a computing element under the jurisdiction of one state management unit holds configuration data at a memory address corresponding to a state managed by the state management unit. For this reason, there are many PEs that perform the same processing when viewed in units of PE even in different states. In such a case, the same function must be duplicated at different addresses, and the memory is used redundantly. Further, since configuration memory spaces corresponding to the number of states of the entire PE group are required, there is a problem that there are more redundant memory spaces than the number of states in each PE. Patent Documents 4 to 6 describe the LUT method in the PE, but are different from the present invention.
JP 2001-0312481 A JP 2004-0133780 A JP 2004-0133781 A Japanese Patent Laid-Open No. 01-014982 Japanese Patent Laid-Open No. 06-0110852 JP 2003-0076668 A

The present invention has been made in view of the above circumstances, and an object thereof is to provide a dynamic reconfigurable circuit that efficiently uses a configuration memory.
A reconfigurable circuit comprising a plurality of processing elements and a configuration memory according to one aspect of the present invention,
A state management unit that generates management information for managing state transitions of the configuration of the processing element; and the configuration memory that receives the management information from the state management unit and corresponds to the processing element based on the management information And a state decoding unit that reads configuration data corresponding to the state transition state and generates state transition information for the processing element to perform state transition.

Preferably, the state decoding unit may be provided for each processing element.
Preferably, the state decoding unit may be provided for a plurality of the processing elements.

Preferably, the configuration memory includes a first configuration memory that transfers configuration data to the processing element;
You may comprise from the 2nd configuration memory which transfers the said configuration data to the said 1st configuration memory.

  Further, when the configuration data not stored in the first configuration memory corresponding to the processing element is necessary, the necessary configuration data is transferred from the second configuration memory to the first A transfer control signal stored in a configuration memory and instructing transfer control for reading the configuration data necessary for the configuration memory of the processing element is received from the state management unit, and the transfer control signal is received. A configuration for generating a signal instructing the transfer control based on the first configuration memory, and notifying each of the first configuration memory, the second configuration memory, and the state decoding unit. It may be configured to include a over de section.

  Preferably, the state management unit recognizes the state of the processing element and the configuration data of the first configuration memory corresponding to the processing element, and generates the transfer control signal based on the recognition result. It is good also as a structure.

  Preferably, the state decoding unit includes a RAM that stores an address of the configuration data in the configuration memory of the processing element, and the address generated based on the management information managed by the state management unit is It is good also as a structure which inputs into RAM and outputs the said state transition information.

  Preferably, the state decoding unit includes a look-up table circuit in which addresses of the configuration data in the configuration memory of the processing element are held in a plurality of registers, based on the management information managed by the state management unit. The address generated in this manner may be input to a look-up table circuit, and the state transition information may be generated and output by selecting the corresponding register.

  Preferably, the state management unit stores a state storage unit that stores state data indicating a state, a state determination unit that determines a next state based on the state data, and downloading the configuration data. The state determination unit refers to a download start flag included in the state data for necessary configuration data, and when the download start flag is valid, It may be configured to write that it is valid and to instruct the configuration loading unit to perform configuration loading.

  Preferably, the status data refers to the download start flag indicating when the configuration data should be downloaded and the download flag portion indicating that the download is in progress, and determines whether or not the process should be interrupted. In this case, a download check flag indicating execution may be provided.

  Each processing element is provided with a state decoding unit. The state decoding unit receives the state of the entire PE group from the state management unit, analyzes the state of its own PE, and outputs the state of the PE. Based on the output PE state, configuration data corresponding to the state is loaded from the configuration memory and mounted on the functional circuit.

  As described above, even in different states, the memory can be used efficiently without copying the same function to different addresses. Further, the configuration memory space corresponding to the number of states of the entire PE group and the redundant memory space larger than the number of states in each PE are not required.

It is a figure which shows the configuration data management mechanism which uses state decoding. FIG. 2A is a diagram showing an LUT method as an example of implementation of the state decoding unit. FIG. 2B is a diagram showing a RAM system as an implementation example of the state decoding unit. It is a figure which shows the example of mounting of the state decoding part by the system which uses LUT, and the system which uses RAM. FIG. 4A is a diagram showing a time chart of the operation of the LUT method. FIG. 4B is a diagram showing a time chart of the operation of the RAM system. It is a figure which shows the example of mounting by which one state decoding part respond | corresponds to multiple processing elements. It is a figure which shows the mechanism which downloads configuration data on memory dynamically at the time of execution. It is a figure which shows the structure of a state management part. It is a figure which shows the time chart of the dynamic configuration at the time of execution. It is a figure which shows the management mechanism of the configuration data in a conventional system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Principle explanation)
The present invention will be described with reference to FIG. The reconfigurable circuit shown in the first embodiment is a circuit diagram including a state management unit 1, a processing element 2 (PE), a configuration memory 3, and a state decoding unit 4. A state management unit 1 having a function added to a conventional reconfigurable circuit and a state decoding unit 4 are newly provided.

  The state management unit 1 generates management information for managing the state transition of the configuration of PE2. The state decoding unit 4 receives management information from the state management unit 1. Based on the received management information, state transition information for the state transition of PE2 is generated. Then, configuration data corresponding to the state transition state is read from the configuration memory 3 corresponding to each PE2.

With this configuration, the memory can be used efficiently.
Example 1
A method using a look-up table (LUT) method for the state decoding unit 4 in the circuit diagram shown in FIG. 1 will be described.

  FIG. 2A is a diagram showing a configuration of the LUT method. The memory address where the configuration data 3 of the PE 2 is recorded is stored on the LUT corresponding to the ID number (management information) of the state managed by the state management unit 1. At execution time, the ID number of the state is received as an input of the LUT, and the memory address of the corresponding PE is output from the LUT.

  FIG. 3 shows the operation of the state decoding unit 4. The state management unit 1 has four states as described with reference to FIG. 9, and generates an ID number for each of the four states. The four ID numbers are 1) status data indicating the status of A-c1, B-c1, ID1, 2) status data indicating the status of A-c2, B-c1, ID2, 3) A-c1, B- Status data indicating the status of c2 is indicated by ID3, 4) Status data indicating the status of A-c2 and B-c2 is indicated by management information ID4.

  The management information ID2 shown in FIG. The state management unit 1 issues an ID number to each state decoding unit 4 provided to correspond to PE2 as ID2. In FIG. 3, “2” (b × 0010) is transferred to the state decoding units 4 of PE-A and PE-B as indicated by ID2. When the decoding unit 4 of the PE-A receives “2”, it is decoded to 2 and configuration data corresponding to A-c2 is selected from the address 2 of the configuration memory 3. Similarly, when the decoding unit 4 of PE-B receives “2”, it is decoded to 1, and configuration data corresponding to B-c1 is selected from address 1 of the configuration memory 3. Then, each configuration data currently required by each PE 2 is output from the configuration memory 3 to the PE-A and PE-B. Similarly, the other PE2 outputs the configuration data currently required.

  FIG. 4A is a time chart showing the operation of the LUT method. From the top 1) clock signal, 2) state management unit output, 3) state decoding unit output (PE-A), 4) state decoding unit output (PE-B), 5) configuration memory unit output (PE-A) 6) Indicates the configuration memory section output (PE-B), and the operations of management information (X), state transition information (YA, YB), and configuration data (ZA, ZB). Show.

  When the management information (X) is output from the state management unit 1, 1) the state decoding unit 4 performs processing without synchronizing with the clock signal indicated by the clock. Each state decoding unit 4 outputs LUT processing result state transition information (YA, YB). In the configuration memory unit 3, configuration data (ZA, BB) is selected and output.

With this configuration, the memory can be used efficiently.
(Example 2)
On the other hand, FIG. 2B is an example in which the state decoding unit 4 is configured by a RAM system. The memory address where the configuration data of PE2 is recorded is stored in the memory using the ID number (management information) of the state managed by the state management unit 1 as an address. By inputting the ID number corresponding to the state as an address signal, the state of PE2 is output.

  In the example shown in FIG. 4A, since the clock is synchronized from the whole state input to the output (without passing through the FF), signal propagation at 0 clock is possible. In FIG. 4B, since RAM is used, an overhead of 1 clock is required. That is, clock synchronization. In FIG. 4B, the RAM is accessed, state transition information corresponding to the ID number is selected using a 4-bit width data path, and output using a 2-bit width data path. Based on the state transition information, configuration data is selected from the configuration memory 3 and output to the PE 2.

  The state decoding unit 4 acquires the management information (X) from the state management unit 1 to the rising edge of the clock signal indicated by 1) clock. Each state decoding unit 4 outputs state transition information (YA, YB), which is a processing result of the RAM. In synchronization with the clock signal, the configuration memory unit 3 acquires state transition information (YA, YB) as a processing result. Thereafter, configuration data (ZA, Z-B) is selected by the configuration memory unit 3 and output to the PE 2.

With this configuration, the memory can be used efficiently.
(Example 3)
In the configuration of the first and second embodiments illustrated in FIG. 1, one state decoding unit 4 corresponds to one PE 2. In this example, as shown in FIG. 5, one state decoding unit 5 is associated with a plurality of PEs 2.

  The state decoding unit 5 has the same configuration as the state decoding unit 4 but controls the PE 2 for each block. For example, the state decoding unit 5 controls a group consisting of PE-A, PE-B... And a group consisting of PE-E, PE-F.

  When considering a group including PE-A and PE-B, the management information indicating all states of PE-A, PE-B... Is notified to all PEs 2 in the same group. The state decoding unit 5 that has received the management information generates state transition information and transmits it to each configuration memory 3. Based on the state transition information, the configuration data required by PE2 is selected and output.

This example can be implemented by either the LUT method or the RAM method.
Example 4
Next, an example in which a large-scale application having a large number of configuration data (such as the number of contexts) is implemented will be described. When attempting to implement a large-scale application, the configuration memory size increases and the circuit scale increases. As a method for avoiding this, FIG. 6 shows a configuration in which configuration data stored in the state management unit is dynamically rewritten when an application is executed.
(Principle explanation)
The configuration circuit shown in FIG. 6 includes a state management unit 61, a processing element 62 (PE), a configuration memory 63 (first configuration memory), a state decoding unit 64, a configuration load unit 65, and a main memory 66 (second memory). 1 is a block diagram including a configuration memory.

  In FIG. 6, configuration data that cannot be stored in the configuration memory 63 is stored in the main memory 66. In addition to the state transition, the state management unit 61 stores the contents of analyzing the current state of each PE 62 and the contents of the configuration data downloaded to the configuration memory 63.

  When configuration data that does not exist in the configuration memory 63 is required during execution of the application, the state management unit 61 sends an instruction to download the necessary configuration data to the configuration load unit 65. That is, the state management unit 61 analyzes the state of the PE 62 and each configuration data of the configuration memory 63 corresponding to the PE 62, and generates necessary configuration data information (transfer control signal) based on the analysis result. The configuration load unit 65 generates a signal for instructing transfer control based on the transfer control signal, and notifies the configuration memory 63, the main memory 66, and the state decoding unit 64 of each.

Decoding information is loaded from the main memory 66 to the state decoding unit 64, and configuration data is loaded to the configuration memory 63.
The PE 62 reads necessary configuration data from the configuration memory 63.

A reconfigurable circuit having a hierarchical memory structure in which a configuration memory 66 is provided outside may be used.
(Status management section and configuration load section)
FIG. 7 shows a block diagram of the state management unit 61 and the configuration load unit 65 for realizing dynamic configuration data reading.

  The download which shows execution of the judgment whether it should interrupt processing with reference to the download start flag which showed at what timing configuration data should be downloaded to the state data in the figure, and the download flag 71 which shows that download is in progress A check flag is provided.

  The state management unit 61 includes a state storage unit 72 that stores state data, and a state determination unit 73 that determines the next state based on the state data. Further, the state determination unit 73 refers to the download start flag included in the state data, and writes that the download flag unit 71 is ON (valid) when the flag is ON (valid). The configuration loading unit 65 is instructed to execute configuration loading (transfer control signal).

  The configuration loading unit 65 includes a configuration memory control unit 74 that receives an instruction from the state management unit 61 and downloads configuration data from the main memory 66. Further, a download data storage unit 75 is provided that stores information (download information) indicating where the configuration data in the configuration memories 63 and 66 should be transferred.

However, the download information can be downloaded from the external configuration memory 66 (general-purpose memory) without having the download storage unit 75.
(Description of operation)
FIG. 8 illustrates the flow of processing using a time chart. When the state determination unit 73 receives the state data from the state storage unit 72, the state management unit 61 checks the download start flag together with determining the next state (T1). If the download start flag is ON (valid), the fact that it is ON (valid) is written to the download flag 71 (T2). Also, a download start signal is transmitted to the configuration load unit 74 (T1). The configuration load unit 74 receives the download start signal and executes the download (T2).

  For example, information necessary for downloading (downloading information) is stored in the download storage unit 75 using information on the area of the configuration memory 66 storing the configuration data to be downloaded and the area of the configuration memory 63 at the download destination. The Then, the data is read from the download data storage unit 75 in response to the reception of the download start signal.

  A configuration in which the download data is stored in the configuration memory 66 and is called from the configuration memory 66 as necessary is such that the download data storage unit 75 is eliminated.

  The configuration memory control unit 74 instructs data transfer processing from the configuration memory 66 to the configuration memory 63 based on the download information.

  On the other hand, the state determination unit 73 continues the state transition process even during download execution. This makes it possible to rewrite the configuration data without interrupting the processing in the reconfigurable circuit.

  However, depending on the processing content, the download may not be completed before the next processing is executed. Therefore, a download check flag is added to the status data. If this flag is not set (valid), the processing is continued regardless of whether or not the download is executed. If this flag is set, the download flag 71 is referred to and a stall signal is displayed during the download. Is generated, and the processing inside the reconfigurable circuit is temporarily suspended.

  When the download of the predetermined configuration is completed, the configuration load unit 65 transmits a download process completion signal to the state determination unit 73 (T3). In response to the download processing completion signal, the state determination unit 73 turns the download flag OFF (invalid) (T4). If the stall signal is generated and the processing in the reconfigurable circuit is suspended, the stall signal is canceled (T4).

  By analyzing the state of each PE with the above configuration and storing necessary configuration data in the configuration memory, the configuration memory can be used efficiently.

The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.
According to the present invention, since the state of each PE is analyzed and the configuration data is stored in the configuration memory, the configuration memory can be used efficiently.

Claims (10)

A reconfigurable circuit composed of a plurality of processing elements and a configuration memory,
A state management unit that generates management information for managing the state transition of the configuration of the processing element;
Receiving the management information from the state management unit, reading configuration data corresponding to the state transition state from the configuration memory corresponding to the processing element based on the management information, and transitioning the processing element to the state transition state; A state decoding unit for generating state transition information for
A reconfigurable circuit comprising:   The reconfigurable circuit according to claim 1, further comprising the state decoding unit for each of the processing elements.   The reconfigurable circuit according to claim 1, wherein the state decoding unit is provided for a plurality of the processing elements. A first configuration memory for transferring configuration data to the processing element;
The reconfigurable circuit according to claim 1, comprising a second configuration memory that transfers the configuration data to the first configuration memory. Further, when the configuration data not stored in the first configuration memory corresponding to the processing element is required according to claim 4,
Transfer of the necessary configuration data from the second configuration memory, storing it in the second configuration memory, and reading the necessary configuration data on the configuration memory of the processing element A transfer control signal for instructing control is received from the state management unit;
A configuration load unit that generates a signal instructing the transfer control based on the transfer control signal and notifies the first configuration memory, the second configuration memory, and the state decoding unit, respectively;
The reconfigurable circuit according to claim 4, further comprising:   The state management unit recognizes the state of the processing element and the configuration data of the first configuration memory corresponding to the processing element, and generates the transfer control signal based on the recognition result. The reconfigurable circuit according to claim 5. The state decoding unit includes a RAM that stores an address of the configuration data in the configuration memory of the processing element,
The recon according to any one of claims 1 to 6, wherein the address generated based on the management information managed by the state management unit is input to the RAM and the state transition information is output. Figurable circuit. The state decoding unit includes a look-up table circuit that holds the addresses of the configuration data in the configuration memory of the processing element in a plurality of registers,
The state transition information is generated and output by inputting the address generated based on the management information managed by the state management unit to a lookup table circuit and selecting the corresponding register. Item 7. The reconfigurable circuit according to any one of Items 1 to 6. The state management unit includes a state storage unit that stores state data indicating a state, a state determination unit that determines a next state based on the state data, and a download flag that indicates that the configuration data is being downloaded With
The state determination unit refers to a download start flag included in the state data for necessary configuration data, and writes that the download flag unit is valid when the download start flag is valid. The reconfigurable circuit according to claim 4, wherein the configuration loading unit is instructed to perform configuration loading. The status data includes the download start flag indicating when the configuration data should be downloaded, and
The reconfigurable circuit according to claim 9, further comprising a download check flag indicating execution by determining whether or not processing should be interrupted with reference to the download flag portion indicating that download is being performed.