JP4403659B2 - Disk drive device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk drive device capable of recording or reproducing corresponding to an optical disk-shaped recording medium, and in particular, a disk-shaped recording in which information is recorded by a series of predetermined unit information areas such as sectors. The present invention relates to a disk drive device corresponding to a medium.
[0002]
[Prior art]
A DVD (Digital Versatile Disc or Digital Video Disc) is known as a disk medium. As this DVD, in addition to reproduction-only, which is called DVD-ROM, which cannot record data, a DVD-RAM capable of rewriting data has been developed and has become widespread. The DVD-RAM performs data recording by forming recording pits by a so-called phase change method.
[0003]
As a track format of DVD-RAM, a recording track on which data is recorded / reproduced is divided into units called sectors along the circulation direction. A header area exists at the head of the recordable area as a sector.
Here, the header area is an area where data is recorded by a pit row, and the recordable area is an area where data can be rewritten by a phase change method. That is, the data recording method is different between the header area and the recordable area, and the amount of reflected laser light is also different depending on this.
[0004]
Although detailed description is omitted here, four addresses PID1, PID2, PID3, and PID4 indicating physical addresses are recorded in the header area. The pit rows of PID1 and PID2 are arranged with a 1/2 track pitch shifted in the outer circumferential direction from the center line of the groove track, and PID3 and PID4 are arranged with a 1/2 track pitch shifted in the inner circumferential direction. . In other words, the track position in the disc radial direction is shifted by 1/2 track pitch between the header area and the recordable area. The DVD-RAM employs a so-called land / groove recording method in which recording is performed on both lands and grooves.
[0005]
For this reason, in a disk drive device compatible with DVD, for example, when a laser beam tracing a track during data reproduction passes through the header area, it is necessary to hold the tracking servo. In other words, if the tracking servo is held when passing through the header area, the trace position of the laser beam in the tracking direction is prevented from being shifted from the track of the recordable area.
Further, as described above, since the recording method is different in each area, it is necessary to change various parameters in the reproduction signal processing circuit system.
[0006]
In order to execute processing such as tracking servo control hold and various reproduction parameter changes as described above at an appropriate timing, it is necessary to recognize, for example, which position in the sector is the current reproduction position. There is.
As position detection in such a sector, detection of timing at which the laser beam passes through the header area is performed. That is, “header detection”.
[0007]
The header detection as a conventional example will be described with reference to FIGS.
FIG. 46 shows an example of the configuration of the header detection circuit.
The optical pickup 101 irradiates a disk 1 as a DVD with a laser beam for reproduction, and receives and detects the reflected light of the irradiated laser beam by a photodetector (not shown here). A light reception signal is obtained. This light reception signal is input to the push-pull signal generation circuit 102. The push-pull signal generation circuit 102 generates a push-pull signal PP using the input light reception signal. Although the detailed description here is omitted, the push-pull signal is obtained, for example, by taking a difference between detection signals detected in each light receiving region obtained by dividing the photodetector into two in the track direction.
[0008]
In this case, the push-pull signal PP output from the push-pull signal generation circuit 102 passes through the low-pass filter 103, thereby removing a high-frequency component and obtaining a smooth envelope waveform. The push-pull signal PPL that has passed through the low-pass filter branches and is input to the comparators 104 and 105.
[0009]
Here, as a waveform of the push-pull signal PPL, for example, when a header is properly detected, the waveform is as shown in FIG. In other words, in the header section that is supposed to pass through the header area, according to the detection of the pit rows of PID 1 and 2 and the detection of the pit rows of PID 3 and 4 shifted by one track pitch with respect to this, As shown in the figure, the detected waveform is inverted in the first half section and the second half section. In this case, for example, the first half section is reversed so that the positive polarity direction and the latter half section are in the negative polarity direction, but the first half section is reversed so that the negative polarity direction and the latter half section is in the positive polarity direction. is there. This is determined depending on whether the recording track of the subsequent recordable area is a land or a groove.
[0010]
In FIG. 46, the push-pull signal PPL is branched and input to the comparators 104 and 105 as a comparison target. As a reference value for comparison, a predetermined threshold th1 set corresponding to the detection waveform in the positive polarity direction is input to the comparator 104. On the other hand, to the comparator 105, a predetermined threshold th2 set corresponding to the detection waveform in the negative polarity direction is input. These threshold values th1 and th2 are both fixed values determined in advance, and their levels are indicated by broken lines in FIG. 47A, for example.
[0011]
The comparator 104 compares the input push-pull signal PPL with the threshold value th1, and when the absolute value of the level of the push-pull signal PPL exceeds the absolute value of the threshold value th1, FIG. ), An H level is output as the detection signal DT · h1.
Similarly, the comparator 105 compares the input push-pull signal PPL with the threshold value th2, and when the absolute value of the level of the push-pull signal PPL exceeds the absolute value of the threshold value th2, FIG. As shown in c), the H level detection signal DT · h2 is output.
[0012]
In this way, the detection signal DT · h1 and the detection signal DT · h2 are at the H level corresponding to the first half period and the second half period of the header section, so that the period as the header section is detected. That is, header detection is performed.
[0013]
[Problems to be solved by the invention]
However, in the case of the above-described header detection configuration, detection with a fixed threshold and using a push-pull signal is likely to cause erroneous detection. This point will be described with reference to FIG.
For example, when a detrack due to the eccentricity of the disk, a fluctuation in the beam spot position of the laser beam, or a defect such as a base or dust on the disk occurs, the push-pull signal PPL in FIG. As shown, an unnecessary offset level may be given to the push-pull signal itself. In this case, a state in which an offset is applied due to the tendency of the level to increase is shown.
For example, when the push-pull signal PPL to which such an offset is given is compared with the thresholds th1 and th2 in the comparators 104 and 105, for example, as specifically shown in FIG. Since the absolute value level of the push-pull signal PPL does not exceed the threshold th2 although it is originally the latter half of the header section, the detection signal DT · h2 is at the H level as shown in FIG. The situation that the output of is not completed.
[0014]
In the case shown in FIG. 48A, an offset is given to the positive level with respect to the push-pull signal PPL. In such a case, not only the first half of the original header section but also the first section. For example, if a state where the level of the threshold th1 is exceeded in the section A other than the header section, an error such that the H level is output in the section other than the header section as shown in FIG. Detection also occurs.
[0015]
As described above, since the header detection is used for timing control of processing such as tracking servo hold corresponding to passage of the header area and change of the reproduction parameter, the higher the frequency of erroneous detection, the higher the reproduction performance. Reliability will be reduced. Therefore, it is required that detection of a specific area on the disk, such as this header detection, be performed as well as possible.
In addition, including the above-described detection of the header section, the data extraction timing for the recordable area following the header section in the sector needs to be properly executed.
In other words, when reproducing from a DVD-RAM, detection of a required data position in a sector as represented by a header section is performed as accurately as possible, and various signal processing timings are also accurate. This leads to an improvement in the reliability of the reproduction performance.
[0016]
Further, from the viewpoint of improving the reliability of the reproduction performance, in addition to the above-described data position detection in the sector, higher reliability can be obtained for the detection of the PID that is the address inserted in the header section. It is required to be able to
For example, conventionally, error detection processing using an error detection code is performed on a PID read from a disk, and if the detection result is NG, the PID is considered to be low in reliability. However, if such a process is performed, even if a 2-bit area called “PID number” that indicates PID 1, 2, 3, 4 is normal, it is detected. If the result is NG, it is discarded as invalid. For example, even in such a case, it is possible to improve the reproduction reliability if the PID is effectively discarded for the required reproduction control process without being discarded.
[0017]
Further, in the reproduction control of the DVD-RAM, it is necessary to obtain a value of NOS (Number Of Sector) indicating the number of sectors in one round track including the current sector currently being reproduced. The NOS information is important information used for land / groove determination, conversion to zone number, and the like in normal reproduction control.
In obtaining the NOS information, conventionally, for example, a conversion table having a predetermined content in which the NOS value is derived using information indicating the number of the current sector, which is called the sector number stored in the PID, is used. Although the process for referring to this conversion table is relatively heavy, for example, the scale of hardware for realizing the process for calculating NOS is increased, and the operation speed is reduced. It was also a hindrance to speeding up.
For example, if it becomes possible to calculate such NOS based on the data content of the PID detected as having high reliability without depending on the conversion table so far, It is possible to obtain a lighter process and faster operation than before.
[0018]
[Means for Solving the Problems]
In view of the above problems, the present invention is configured as a disk drive device as follows.
In the disk drive device of the present invention, information is recorded so as to form a circular track by a series of unit information areas consisting of a header area and a recordable area following the header area. In the header area, tracks are adjacent to each other. Among the recordable areas that are present, one or more first address information groups having an address value of one recordable area and one or more second address information having an address value of the other recordable area Recording or reproduction is performed corresponding to a disk-shaped recording medium on which a group is recorded.
Then, the address value of the address information belonging to the first address information group and the address value of the address information belonging to the second address information group read from the disk-shaped recording medium are read from the disk drive device. On the basis of this, there is provided area number information generating means for generating and outputting area number information indicating the number of unit information areas in one track.
[0019]
Depending on the above configuration, a predetermined value using the address value of the address information belonging to the first address information group stored in the header area in the unit information area and the address value of the address information belonging to the second address information group may be used. Based on the calculation result, area number information indicating the number of areas in one circular track including the current unit information area is obtained.
That is, in the present invention, the number of areas is obtained based on, for example, performing an operation on address values of a plurality of address information. In the past, for example, decoding was performed by referring to a conversion table having a predetermined content based on an address value included in a certain address information. However, according to the configuration of the present invention described above, the conversion table was used. There is no need to perform decoding.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described. The disk drive apparatus according to the embodiment of the present invention is configured to be able to reproduce a DVD-RAM. In practice, however, a DVD-ROM, a CD-DA (Digital Audio), a CD-ROM, etc. CD format discs can also be played.
The following description will be given in the following order.
1. DVD-RAM track format
2. Configuration of disk drive device
3. Position estimation within sector
3-1. Control based on in-sector position estimation results
3-2. Intra-sector position estimation operation (first example)
3-3. Intra-sector position estimation operation (second example)
3-4. Intra-sector position estimation operation (third example)
3-5. Intra-sector position estimation operation (fourth example)
4). Sector synchronization protection operation (first example)
5). Sector synchronization protection operation (second example)
6). PID storage processing
7). Representative PID decision processing
8). Playback parameter control
9. NOS calculation processing
[0021]
1. DVD-RAM track format
First, the track format of the DVD-RAM that can be reproduced by the disk drive device according to the embodiment of the present invention will be schematically described with reference to FIGS.
[0022]
The DVD-RAM is a rewritable disc medium based on a so-called phase change method, and currently has a storage capacity of 4.7 GB (unformatted) on one side.
FIG. 4 conceptually shows the structure of the entire disc as a track format of DVD-RAM.
The disk 1 shown in this figure is a DVD-RAM. The recording track in this DVD-RAM is a so-called single spiral, and a groove (concave) called a groove is formed, and a land that becomes a convex part is formed between two adjacent grooves. The The DVD-RAM employs a so-called land / groove recording method in which data is recorded using both the groove and land as recording tracks. The adoption of this method is one factor that increases the recording density.
The land track and the groove track are connected to each other one by one at a predetermined linear position along the disc radius indicated by an arrow a in the figure, for example, from the disc inner periphery side to the outer periphery side. In this case, one track is formed in a spiral shape.
[0023]
Further, a recording track composed of a land track and a groove track is divided into a plurality of sectors in the circulation direction as shown in FIG.
Here, what is shown in FIG. 4 is a track format in one existing zone, for example. Here, a zone is an area divided along the disk radial direction, and the number of sectors per track circumference varies from zone to zone. The number of sectors per track in each zone increases as the disk moves from the inner periphery to the outer periphery. The physical structure on the disk in units of sectors is shown in FIG.
[0024]
As shown in FIG. 5, in one sector, a header area is first provided, followed by a recordable area. In the header area, as shown in the figure, a PID (Physical ID) indicating a physical address on the disc is recorded by a pit string. The recordable area is an area where data can be rewritten by the phase change method, and the land track and the groove track are alternately arranged along the disk radial direction as shown in the figure. . Further, the land track and the groove track have a meandering shape with a period of 186 cycles in one sector, and a so-called wobble is formed. In the DVD-RAM, the clock is recorded by this wobble shape.
[0025]
In the header area, a set of headers is formed with PIDs 1, 2, 3, and 4. The same contents are recorded in PID1 and PID2. Similarly, the same contents are recorded in PID 3 and 4. The pit rows in the area including PID 1 and 2 are arranged so as to be shifted in the outer circumferential direction by ½ track pitch with respect to the center line of the groove track, and the pit strings in the area including PID 3 and 4 are The second pit row is arranged so as to be shifted in the inner circumferential direction of the ½ track pitch.
Such PID arrangement, that is, address arrangement, is called CAPA (Complimentary Allocated Pit Address). When tracing a certain groove track within one sector, a land track adjacent to this groove track is assigned. It shares the address when operating.
By such an address arrangement, for example, crosstalk between addresses of adjacent pit rows is eliminated. Compared with the method of assigning addresses to each of the land track and the groove track, the header length can be halved, and the redundancy can be reduced and the recording capacity can be increased accordingly.
[0026]
Here, taking a set of headers of PID1 (m + N), PID2 (m + N), PID3 (m), and PID4 (m) in FIG. 5 as an example, PID1 (m + N) and PID2 (m + N) The pit rows as PID3 (m) and PID4 (m) are arranged in the inner circumferential direction of the ½ track pitch. They are arranged so as to be displaced. Here, N indicates the number of sectors per track.
Depending on PID1 (m + N) and PID2 (m + N), the address position in the sector as the land track (m + N) adjacent to the groove track (m) in the outer circumferential direction is indicated, and PID3 (m), PID4 ( Depending on m), the address position in the sector as the groove track (m) is indicated.
[0027]
6 and 7 show the data arrangement structure in one sector.
One sector consists of a 128-byte header area and a recordable area in which data is recorded, and a 2-byte (32 channel bit) mirror area between the header field and the recordable area. (mirror field) is provided.
[0028]
First, in the header area, there are four PIDs (Phisical IDs) 1, 2, 3 and 4 as shown in these figures. In particular, as shown in FIG. These are also classified as Header Fields 1, 2, 3, and 4, respectively.
[0029]
Header Field 1 has 36 bytes of VF0 (Variable Frequency Oscillator) 1, 3 bytes of AM (Address Mark), PID 1, 2 bytes of IED (ID Error Detection code) 1, 1 byte of PA (Postamble) 1 It is arranged.
Header Field 2 is composed of VF02, AM (Address Mark), PID2, IED2, and PA2 of 8 bytes from the top.
Header Field 3 includes VF01, AM, PID3, IED3, and PA1 arranged from the top.
In the Header Field 4, VF02, AM, PID4, IED4, and PA2 are arranged from the top.
[0030]
The VFOs 1 and 2 are used for a pull-in operation performed by a PLL circuit of a disk drive device described later. That is, it is used for clock recovery. Here, the 36-byte VFO1 has a length of 576 channel bits, and the 8-byte VFO2 has a length of 128 channel bits.
The AM is used to provide subsequent PID byte synchronization to the device and has a pattern with a predetermined 48 channel bits. PA1 and PA2 are boundary areas that can indicate the end of IED1,3, IED2,4.
In the IEDs 1, 2, 3, and 4, codes for error checking are recorded for the PIDs 1, 2, 3, and 4 positioned immediately before the IEDs.
[0031]
In the recordable area, a gap (Gap Field), a guard 1 (Guard1 Field), and a VFO 3 are provided from the top.
The gap has a size of 160 channel bits (10 bytes) + J (0-15) channel bits, and guard 1 has a size of 20 + K (0-7) bytes. These gap and guard 1 areas are provided to physically protect a data area described later. VFO3 has a size of 560 channel bits by 35 bytes, and is used for clock reproduction corresponding to a recordable area.
A PS (Pre-Synchronous Code Field) is arranged behind the VFO 3. This PS has a predetermined pattern of 48 channel bits (36 bytes), and is an area for achieving byte synchronization in the subsequent data area.
The data area has 2418 bytes, and user data is recorded in this area. Following the data area, PA3 (1 byte) is arranged.
[0032]
Following PA3, Guard 2 (Guard Field 2) is arranged. The guard 2 has a size of 55-K (0-7) bytes. Subsequent to the guard 2, a buffer field is provided. The buffer has a size of 400 channel bits (25 bytes) -J channel bits. This buffer is provided, for example, to absorb variations in the actual length of write data affected by detracking during data writing or speed changes.
[0033]
Here, the structure of PID 1, 2, 3, 4 is shown in FIG. In the following description, PIDs 1, 2, 3, and 4 are simply expressed as PID unless otherwise distinguished.
As shown in FIG. 8A, the entire PID is composed of 1-byte sector information (Sector Information) from the beginning, followed by a 3-byte sector number (Sector number). The sector number stores an address value. The sector numbers of PID 1 and 2 indicate the sector number of the subsequent land sector, and the sector numbers of PID 3 and 4 indicate the sector number of the subsequent groove sector.
The sector information has a structure shown in FIG. 8B, and the first two bits are undefined. Subsequently, a physical ID number (Physical ID number: 2 bits), a sector type (sector type: 3 bits), and a layer number (Layer number: 1 bit) are arranged.
Depending on the physical ID number, PID 1, 2, 3, 4 is specified. The physical ID number is defined in association with 0 (00b) = PID1, 1 (01b) = PID2, 2 (10b) = PID3, 3 (11b) = PID4.
In the following description, it may be referred to as “PID number”, but this “PID number” refers to any of PID 1, 2, 3, and 4. That is, if the physical ID number = 0 (00b), the PID number = 1 (PID1). Similarly, if the physical ID number = 1 (01b), the PID number = 2 (PID2) and the physical ID number = 2. If (10b), PID number = 3 (PID3), and if physical ID number = 3 (11b), PID number = 4 (PID4).
[0034]
Further, depending on the sector type, the position of the current sector in one round track is indicated. That is, according to the value, it is specified which of the four types of sectors, that is, the start sector in the track, the last sector, the sector immediately before the last sector, or other sectors.
The layer number indicates to which layer the current sector belongs.
[0035]
Further, as shown in FIG. 9, data recorded in the data area in one sector is composed of 13 rows × 2 = 26 frames (1488 channel bits = 1456 + 32). A 32 channel bit frame sync is arranged at the head of each frame, and sync numbers of SY0 to SY7 are given to the frame sync as shown in the figure. The position in the frame data can be specified from the context as the sync number.
In this way, various information including the address of the succeeding sector is stored in the PID, and each of these pieces of information is used for reproduction control. That is, the PID can be said to be reproduction control information that stores information to be used for reproduction control.
[0036]
2. Configuration of disk drive device
Next, a configuration example of a disk drive device that can be played back in accordance with the DVD-RAM will be described with reference to the block diagram of FIG. Note that the actual disk drive device of the present embodiment is not limited to DVD-RAM playback, but DVD-ROM playback is also possible. Further, not only DVD but also CD-DA (Digital Audio) and CD-ROM can be reproduced. However, for convenience of explanation, only the configuration for reproducing a DVD-RAM will be mainly explained. In practice, however, each of the above-described discs can be played back by switching the playback signal processing system or changing the required playback parameters according to the disc type in each functional circuit section described below. It is what is said.
[0037]
The optical disk 1 here is the DVD-RAM described above. The optical disk 1 is placed on a turntable (not shown) and is rotationally controlled by a spindle motor 2.
[0038]
Here, a so-called ZCLV (Zoned Constant Linear Velocity) is adopted as a rotation control method for the DVD-RAM. As is well known, ZCLV first divides a disk into a plurality of zones in the radial direction as a disk format, and increases the number of sectors per track in each zone in the outer circumferential direction. In each zone, rotation control is performed with CAV (constant angular velocity), but the rotation speed of CAV increases toward the outer zone so that the linear velocity is almost constant over the entire disk surface. It is controlled to be low speed.
[0039]
In the optical pickup 3, the laser diode 30 irradiates the signal surface of the optical disk 1 with laser light, and the photodetector 37 detects the reflected light from the signal surface, whereby the data recorded on the optical disk 1 is recorded. Read.
[0040]
In the optical pickup 3, an objective lens 34, which is an output end of laser light, is held by a biaxial mechanism 3a so as to be movable in the tracking direction and the focus direction. The biaxial mechanism 3 a is formed with a focus coil that drives the objective lens 34 in the direction of moving toward and away from the optical disk 1 and a tracking coil that drives the objective lens 34 in the radial direction of the optical disk 1.
The entire optical pickup 3 can be moved in the radial direction of the optical disk 1 by a thread mechanism 19.
[0041]
The reflected light detected in the optical head 3 is converted into a current signal corresponding to the reflected light amount and supplied to the RF amplifier 4, and the focus error signal FE, A tracking error signal TE is generated, and an RF signal as reproduction information, a PI (pull-in) signal that is a sum signal, and the like can be generated.
[0042]
The focus error signal FE and tracking error signal TE generated by the RF amplifier 4 are supplied to the drive circuit 6 after being subjected to necessary processing such as phase compensation and gain adjustment by the servo processor 5, and are supplied to the focus drive signal and tracking. The drive signal is output to the focus coil and the tracking coil described above.
Further, a thread error signal is generated from the tracking error signal TE in the servo processor 5 via an LPF (low pass filter), and is output from the drive circuit 6 to the thread mechanism 14 as a thread drive signal.
As a result, so-called focus servo control, tracking servo control, and thread servo control are executed.
[0043]
The servo processor 5 supplies a signal for focus search operation and track jump operation to the drive circuit 6 based on an instruction from the system controller 11, and outputs a focus drive signal, a tracking drive signal, and a thread drive signal according to the signal. It is generated and a focus search of the optical head 3 or a track jump / access is executed.
[0044]
Focus search is to detect a so-called S-shaped curve as the waveform of the focus error signal FE while forcibly moving the objective lens 34 between the position farthest from the disk 1 and the closest position for focus servo pull-in. Is the action. As already known, as the focus error signal FE, an S-curve is observed in a narrow section before and after the point at which the objective lens 15 is in a focal point position with respect to the recording layer of the disk 1. By turning on the focus servo in the linear region of the character curve, the focus servo can be pulled. For such focus servo pull-in, focus search is performed, and a focus drive signal for this purpose is sent to the focus coil, and the objective lens 15 is moved.
[0045]
In the case of track jump or access, the objective lens 34 is moved in the radial direction of the disk by the biaxial mechanism 3a, and the optical head 3 is moved in the radial direction of the disk by the sled mechanism 14. The signal is output to the tracking coil and the thread mechanism 14 as a tracking drive signal and a thread drive signal.
[0046]
The reproduced RF signal generated by the RF amplifier 4 is binarized by being output to the binarization circuit 7 and becomes a so-called EFM + signal encoded by 8/16 modulation. The EFM + signal is output to the clock recovery circuit 8.
The clock recovery circuit 8 extracts, generates and outputs a recovery clock CLK synchronized with the EFM + signal by a PLL circuit or the like based on the input EFM + signal. The reproduction clock CLK is supplied as an operation clock in various circuits including the decode circuit and the servo processor 5. The EFM + signal from which the clock has been extracted is input to the transfer control circuit 20.
[0047]
In the clock reproduction circuit 8 of the present embodiment, a wobble signal obtained by detecting a wobble formed on a track in the recordable area is input, and a clock synchronized with the wobble signal is generated and output. Has been.
[0048]
In the transfer control circuit 20, for example, based on the detection result by the PID detection unit 16 to be described later and the intra-sector position estimation result in the timing generation unit 18, a necessary part of the signal is extracted from the input EFM + signal. Timing control for transfer to the decode circuit 9 is executed.
[0049]
The decoding circuit 9 performs EFM-Plus demodulation (eight to fourteen demodulation plus: demodulation for 8/16 modulation) on the input EFM + signal, and outputs it to the error correction circuit 10.
The error correction circuit 10 executes error correction processing according to the RS-PC method while using the buffer memory 11 as a work area. Note that the buffering controller 10 a provided in the error correction circuit 10 executes a control process related to writing to and reading from the buffer memory 11.
[0050]
The binarized data that has been subjected to error correction, that is, reproduction data, for example, in the case of this figure, is read out by the buffering controller 10a provided in the error correction circuit 10 by the reading control of the buffer memory 11. Are transferred via the data interface 12.
The data interface 12 is provided for communication with an external information processing apparatus such as the host computer 40 connected via the external data bus 41, and when reproduction data is transferred as described above. Further, the reproduced data can be transferred to the host computer 40 via the external data bus 41.
Also, via the data interface 12, for example, commands can be transmitted and received between the disk drive device and the host computer 40. In the disk drive apparatus, the system controller 13 executes processing for transmission / reception of this command.
[0051]
The system controller 13 is formed by a microcomputer as a part for controlling the whole.
The system controller 13 performs necessary control for various reproduction operations based on the current operation status, instructions from the host computer 40, and the like.
[0052]
Further, in the disk drive device of the present embodiment, a RAM block 14 is provided corresponding to the reproduction of the DVD-RAM as shown in the figure.
The RAM block 14 of the present embodiment includes a header detection unit 15, a PID detection unit 16, a land / groove detection unit 17, and a timing generation unit 18.
[0053]
The header detection unit 15 is a part for performing header detection. That is, the timing of passing through the header area of the DVD-RAM is detected as the laser beam trace position.
In this case, the header detection unit 15 detects each of an area where header fields 1 and 2 including PIDs 1 and 2 are continuous and an area where header fields 3 and 4 including PIDs 3 and 4 are continuous. However, if the configuration is based on, for example, Japanese Patent Application No. 2000-280144 previously filed by the present applicant, a more stable detection operation can be obtained.
[0054]
The PID detector 16 detects PID (1, 2, 3, 4), which is a physical address recorded in the header area. For this purpose, the PID detector 16 detects the address mark AM and outputs a PID signal to the decode circuit 9 based on the detection. The decode circuit 9 decodes the input PID in the course of the EFM + demodulation process to obtain data as PID. By using the PID acquired in this way, for example, the decoding circuit 9 and the system controller 13 can recognize the physical address of the recordable area following the header area.
[0055]
Further, as described with reference to FIG. 4, in the DVD-RAM, the land and the groove alternate every time the track goes around. For this reason, at the time of reproduction, it is detected whether the recordable area of the current sector is land / groove, and based on the detection result, for example, it is used for tracking servo control corresponding to land and groove. It is necessary to reverse the polarity of the tracking error signal TE to be performed.
The land / groove detector 17 detects the land / groove. In this case, the land / groove detector 17 receives a push-pull signal PP that is generated by the RF amplifier 4, for example.
[0056]
In the case where the land track is traced in one sector and the case where the groove track is traced, the push-pull signal PP detects the pit row of PID 1 and 2 and the PID 3 and 4 when the header area of the sector is detected. The detected waveforms are inverted from each other in the pit row. As for the inversion pattern, whether the track following the header is a land sector or a groove sector, whether it is in order of positive polarity → negative polarity or negative polarity → positive polarity. It is uniquely determined by. Therefore, the land / groove detection unit 17 detects a waveform inversion pattern corresponding to the header area described above for the input push-pull signal PP, and indicates the land or groove based on the detection result. A detection signal is generated. This detection signal is input, for example, by the servo processor 5 and used to invert the polarity of the tracking error signal TE at an appropriate timing.
Various other land / groove detection methods and configurations are conceivable. For example, detection can also be performed based on a PID decoding result, and determination can also be made from the periodicity of disk rotation. Therefore, the land / groove detection unit 17 is not limited to the above-described configuration.
[0057]
The timing generation unit 18 detects the data position in the sector (intra-sector position estimation (detection) process) using the detection output of the header detection unit 15, the PID detection unit 16, and the land / groove detection unit 17 described above. I do. Then, using this estimation result, a necessary setting change or the like is performed according to the data position in the sector.
[0058]
As an example, the servo processor 5 holds the tracking servo control operation corresponding to the period during which the header is reproduced based on the intra-sector position estimation result. That is, for example, the value of the tracking error signal TE immediately before the header area is detected is held, and tracking servo control by closed loop is executed. As a result, the tracking servo control does not follow the header area track (address pit string) shifted by ½ track pitch with respect to the recordable area track. The land track or groove track to be traced can be traced appropriately and satisfactorily.
[0059]
Here, a configuration example of an optical system corresponding to reproduction of the DVD-RAM will be described.
FIG. 2 shows the configuration of the optical system in the optical pickup 3.
In the optical system shown in this figure, the laser beam output from the laser diode 30 is collimated by the collimator lens 31 and then enters the beam splitter 33. Incident light from the beam splitter 33 is reflected 90 degrees to the optical disk 1 side and further passes through the objective lens 34 to be irradiated onto the optical disk 1 in a converged state.
The reflected light reflected by the optical disk 1 enters the beam splitter 33 via the objective lens 34, passes through as it is, and reaches the condenser lens 35. Then, after being condensed by the condenser lens 35, the light enters the photodetector 37 through the cylindrical lens (cylindrical lens) 36.
[0060]
Here, as described above, the laser diode 30 has a center wavelength of, for example, 650 nm and the objective lens 34 has NA = 0.6 on the assumption that the HD layer compliant with DVD can be reproduced. It is what.
[0061]
FIG. 3 shows a structural example of the photodetector 37.
As shown in the figure, the photodetector 37 in this case is provided with a four-divided detector including at least detectors A, B, C, and D. The four detectors A, B, C, and D in the photodetector 37 have the arrangement form shown in the figure, and are arranged in the direction in which the positional relationship with the recording track shown on the left side of the figure is obtained.
Hereinafter, the detection signals obtained by the detection units A to D will be referred to as detection signals A to D, respectively.
[0062]
In the present embodiment, a configuration using a pull-in signal PI for header detection, which will be described later, can be adopted. However, the pull-in signal PI is detected by the detection units A, B, C, The detection signals A, B, C, and D, which are the outputs of D, can be used to generate PI = (A + B + C + D).
[0063]
In addition, the DVD-RAM employs a so-called push-pull method as tracking servo control. In this method, the servo control is performed using the push-pull signal PP. However, when the push-pull signal PP is generated, the detection units A, B, C, and D are detected as shown in an equivalent circuit in the figure. The detection signals A, B, C, and D that are outputs can be used to calculate PP = (A + D) − (B + C) by a differential amplifier. A DPP (Differential Push Pull) method can also be adopted. Further, in the DVD-ROM, a phase difference method is used.
The focus error signal FE is not shown in an equivalent circuit diagram for calculation, but is generated by calculation of FE = (A + C) − (B + D) using the detection signals A, B, C, and D. Can do.
The calculation for generating each signal is actually performed in the RF amplifier 4.
[0064]
3. Position estimation within sector
3-1. Control based on in-sector position estimation results
In the disk drive device of the present embodiment, during DVD-RAM playback, the timing generation unit 18 (FIG. 1) estimates (detects) a required data position in the sector. Based on the above, various control processes during reproduction are executed.
The timing chart of FIG. 10 exemplifies various control timings based on such an intra-sector position estimation result.
Here, in FIG. 10A, data of one sector is shown in time series as data read from the disk.
The intra-sector position estimation counter in FIG. 10B shows the load timing (count start timing) of the counter for intra-sector position estimation that is provided in the timing generation unit 18 as described later. ing.
The intra-sector position estimation counter is cleared, for example, at a sector unit timing, and each of the PIDs 1, 2, 3, 4 according to the timing at which one of the PIDs 1, 2, 3, 4 in the header area is detected. It operates so as to start counting from a predetermined initial count value according to the above. For example, the count is performed by incrementing the count value one by one at regular time intervals. That is, it can be considered that the counting operation of the intra-sector position estimation counter measures time by synchronizing each sector unit.
In this case, the state where the intra-sector position estimation counter starts counting from the initial count value corresponding to PID1 in response to detection of the position of PID1 is shown.
[0065]
Then, when the count operation is performed in this way, based on the count value (time keeping time), one can obtain the timing of the track hold signal as shown in FIG. To be.
As described above, it is necessary to hold the tracking servo when passing through the header area during DVD-RAM playback. For example, the track hold signal is conventionally generated based on the header detection result. However, in the present embodiment, the track hold signal is based on the intra-sector position estimation result, so that the generation timing is further increased. High precision is made. In FIG. 10G, the hold state is set when the track hold signal is at the H level, and the hold state is canceled when the track hold signal is at the L level.
[0066]
The block diagram of FIG. 11 conceptually shows a tracking servo signal processing system that is assumed to be in the servo processor 5.
As shown in this figure, the tracking error signal TE is branched and supplied to the servo filter 5a and the hold signal output circuit 5b. The outputs of the servo filter 5a and the hold signal output circuit 5b are alternatively selected by the switch 5c and alternatively selected by the servo filter 5d and output as a focus drive signal.
Here, when the track hold signal is at the L level, the switch 5c selects the output of the servo filter 5a, whereby the tracking servo control according to the change of the tracking error signal TE is executed. It will be. That is, the hold is released.
On the other hand, when the track hold signal is at the H level, the switch 5c is switched so as to select the output of the hold signal output circuit 5b. In this state, the tracking error signal TE is The integrated value obtained by holding the value immediately before or by integrating with a predetermined time constant is output to the servo filter 5d without fluctuation.
By performing such an operation at the timing shown in FIGS. 10A and 10G, when tracing the recordable area, the tracking servo control is executed so that the laser spot follows the track. When tracing the header area, it is possible to obtain a state in which the tracking servo is held while the previous land or groove track is being traced.
[0067]
Further, based on the count value of the intra-sector position estimation counter, which is the intra-sector position estimation result, the DC value pull-in process of the RF signal is also executed.
The signal read from the disk is input to the RF amplifier 4 as an RF signal. The DC component (DC value) superimposed on the RF signal is a header area as shown in FIG. And the recordable area are different. In addition, the header fields are different between the header fields 1 and 2 and the header fields 3 and 4. For this reason, in order to properly execute signal processing in the RF amplifier 4, the DC value component is cut and the header area (Header Field 1, 2 / Header Field 3) is cut as shown in FIG. 4) and the recordable area RF signal must have the same center value. That is, it is necessary to perform DC pull-in on the RF signal.
[0068]
As such a configuration in the RF amplifier 4, as shown in FIG. 12, for example, an RF signal is cut by a DC value component by an HPF (High Pass Filter) 4a and amplified by a first-stage amplifier 4b. For the HPF 4a, the RF signal DC is pulled in at the timing shown in FIG.
That is, in the H level section shown in FIG. 10C, the time constant of the HPF 4a is set so that appropriate DC value pull-in is performed according to the data position in FIG. 10A corresponding to each H level section. Is to switch. By executing such processing at an appropriate timing as shown in FIG. 10C, for example, PID 1, 2, 3, 4 can be read with high reliability in the header area, and the recordable amount In the area, the reliability of reading the user data in the data area is improved.
[0069]
The transfer control circuit 20 needs to extract only the data (data) in the recordable area from the input binarized RF signal and output it to the decode circuit 9. The extraction timing can be obtained as shown in FIG. 10D based on the count value of the intra-sector position estimation counter.
FIG. 13 shows the transfer control circuit 20 and the subsequent decoding circuit 9. Here, when the data portion extraction timing shown in FIG. 10D is at the L level, the data transfer of the transfer control circuit 20 shown in FIG. 13 is turned off, and when it is at the H level, the data transfer is turned on. It is controlled to become. Therefore, as long as the data portion extraction timing shown in FIG. 10D is properly obtained based on the count value of the intra-sector position estimation counter, only the data portion signal is always properly extracted, and the decoding circuit 9 is output.
[0070]
Further, the clock recovery circuit 8 uses VFO1, 2 corresponding to the header area, and operates the PLL circuit using VFO3 in the recordable area, thereby converting the binarized RF signal. The synchronized channel clock CLK is reproduced. The pull-in timing of the PLL circuit at this time is also obtained as shown in FIG. 10E based on the count value of the intra-sector position estimation counter. Then, at the PLL pull-in start timing shown in FIG. 10E, the start timing of the pull-in operation for the PLL circuit 8a in the clock recovery circuit 8 is instructed as shown in FIG.
[0071]
For the PLL circuit, for example, the following timing control can be executed in addition to the timing shown in FIG.
Here, as an internal configuration of the PLL circuit 8a, a configuration corresponding to DVD-RAM playback is shown in FIG. In this case, the PLL circuit 8a includes a first PLL circuit 52 and a second PLL circuit 54 as shown in the figure.
Here, since the push-pull signal PP input from the RF amplifier 4 is affected by scratches and detracks on the disk, the waveform is shaped by the wobble protection circuit 51 in order to remove this effect. . The push-pull signal PP whose waveform is shaped by the wobble protection circuit 51 is input to the first PLL circuit 52.
The push-pull signal PP has a signal component obtained by detecting the wobble shape recorded on the track of the disk. In the first PLL circuit 52, the in-sector position estimation clock CLK-1 synchronized with the input wobble signal. Is played back. This intra-sector position estimation clock CLK-1 is used as a clock in various circuits that perform intra-sector position estimation as described later.
[0072]
The second PLL circuit 54 also receives the binarized RF signal from the binarization circuit 7 and regenerates the data read clock CLK.
In this embodiment, by providing the switch 53, the intra-sector position estimation clock CLK-1 and the binarized RF signal can be selected as signals to be input to the second PLL circuit 54. It is like that. For example, at the timing when data (PID, user data, etc.) is read by switching the switch 53, the binarized RF signal is input to the second PLL circuit 54. Then, the intra-sector position estimation clock CLK-1 is input.
With such a configuration, since the intra-sector position estimation clock CLK-1 is input during a period other than the data reading, the oscillation frequency of the second PLL circuit 54 during this period can be maintained at an appropriate value. it can. At the data reading timing, it is possible to perform highly reliable data reading by locking the PLL and obtaining an appropriate clock CLK simply by performing phase pull-in.
[0073]
In this case, the filter time constant for the second PLL circuit 54 is also switched. That is, at the start of data reading, the filter time constant is reduced to increase the gain so that a high-speed pull-in operation can be obtained.
[0074]
In addition, since the header area does not have a wobble structure as a track, the operation of the first PLL circuit 52 becomes unstable in the header area.
Therefore, at the timing when the header region is traced, the operation of the first PLL circuit 52 is held so that a constant oscillation frequency can be obtained.
[0075]
The control timing for such a PLL circuit is shown in FIG.
In this figure, the timing of the first PLL hold signal, the second PLL circuit switching signal, and the second PLL circuit time constant switching signal is shown for the sector unit data. When the first PLL hold signal becomes H level, a hold operation is performed. The second PLL circuit switching signal is used to control the switch 53. The binary RF signal is selected at the H level, and the intra-sector position estimation clock CLK-1 is selected at the L level. The second PLL circuit time constant switching signal decreases the filter time constant of the second PLL circuit 54 when it is at the H level and increases the filter time constant when it is at the L level. The period during which the second PLL circuit time constant switching signal is at the H level substantially corresponds to the detection timing of VFO1, 2, 3.
The timing of each signal shown in FIG. 16 (b) is also obtained based on the count value of the intra-sector position estimation counter.
[0076]
Returning to FIG.
Further, the data section can be counted by assigning a number in ascending order, for example, at the timing of each sync frame based on the count value of the intra-sector position estimation counter. As a result, as shown in FIG. 10F, it is possible to estimate which sync frame is currently located in the data portion. In the present specification, the number according to the appearance order of the sync frames obtained in this way is referred to as “sync frame number estimated value”.
Based on the sync frame number estimation value, for example, the buffering controller 10a in the error correction circuit 10 can execute data transfer to the buffer memory 11 in units of sync frames.
[0077]
3-2. Intra-sector position estimation operation (first example)
In the present embodiment, the timing of the various control processes as shown in FIG. 10 or FIG. 16B is performed by the timing generator 18 in the RAM block 14, for example, the PID detector 16, the header detector 15, the land / The detection result of the groove detection unit 17 is appropriately used. That is, the timing generation unit 18 operates an intra-sector position estimation counter (hereinafter also simply referred to as “counter”) at a required timing based on a detection result of a required data position for a signal read from the disk. Let The required data position in one sector is estimated from the count value (timed time) of this counter, and various required timing signals are generated based on the estimated data position. In this embodiment, as the intra-sector position estimation operation as described above, several configuration examples can be given as follows.
First, let us explain from the first example.
[0078]
The timing chart of FIG. 18 shows an intra-sector position estimation operation as a first example.
Here, assuming that the signal is read from the disc as shown in FIG. 18A, for example, the PID detector 16 detects AM at the timing shown in FIG. 18B. . When AM is detected, an area of a predetermined size that follows the detected AM is regarded as an area where PID-IED is continuous, and EFM + demodulation is executed. In this case, error detection is performed on the PID using the IED.
[0079]
As a result, as shown in FIG. 18C, at the timing when the PID-IED is read, an IED determination (error detection process) completion flag is set, and if the error detection result is NG, The flag of the IED determination result NG is set.
At this time, the PID number can be obtained by referring to the physical ID number (2 bits) in the PID. That is, it is detected which of PID 1, 2, 3, 4 is. At this time, as shown in FIG. 18E, one of the PID1 detection flag, the PID2 detection flag, the PID3 detection flag, and the PID4 detection flag is set according to the detected PID number value. As shown in FIG. 18D, the detected PID number value is identified.
[0080]
Here, if the IED determination result is OK, it can be estimated that the PID number is correct, but the PID number when the IED determination result is NG is low in reliability. It will be said.
For example, in this figure, when PID4 is detected, as shown in FIGS. 18 (d) and 18 (e), the flag of the IED determination result NG is set, and the PID number should be '3' originally. However, an erroneous value “1” indicating PID2 is detected.
[0081]
The timing generation unit 18 of the present embodiment basically loads the detected PID (1, 2, 3, 4) position into the counter with reference to the PID detection flag shown in FIG. To do. That is, a required count initial value uniquely determined according to PID (1, 2, 3, 4) is loaded to start counting.
[0082]
However, as described above, in consideration of the fact that reliability is lowered due to erroneous detection at the time of PID detection, in this embodiment, a protection window is set corresponding to the PID detection timing. To be generated. This is the PID (1, 2, 3, 4) detection window shown in FIG. This PID (1, 2, 3, 4) detection window is also generated by using the intra-sector position estimated value based on the count value of the counter with the configuration described later.
Then, only when the PID (1, 2, 3, 4) detection flag shown in FIG. 18 (e) is set in the PID (1, 2, 3, 4) detection window, FIG. ), The PID (1, 2, 3, 4) position is set.
In the case shown in this figure, as can be seen from FIGS. 18E and 18F, the PID1 detection flag is set when the first PID1 is detected, and this flag indicates that the PID1 detection window is at the H level. Thus, the PID1 position load flag is obtained at the same timing as the PID1 detection flag as shown in FIG. 18 (g). Then, the counter loads the initial count value corresponding to PID1 and starts counting at the timing of the PID1 position load flag, as shown in FIG.
[0083]
Also in this case, at the timing of PID2, 3, as in the case of PID1, PID (2, 3) is detected during the period (FIG. 18 (f)) in which the PID (2, 3) detection window is open. Since the flag is set (FIG. 18E), as shown in FIG. 18G, the PID (2,3) position load flag is set at the timing of the PID (2,3) detection flag. However, at this time, since the loading of the counter is already completed and the counting is started, the load flag is ignored.
[0084]
Then, when the counter shown in FIG. 18 (h) starts counting as described above, the count value is incremented every certain time. It is assumed that it was also shown in a). That is, it is treated as a timekeeping time synchronized with the sector timing.
Then, for example, the timings shown in FIGS. 10C, 10D, 10E, 10F, and 10G have a predetermined count value (timed time) of a counter that is an intra-sector estimated value. Then it will be activated.
[0085]
In FIG. 18, a track hold signal is shown in FIG. 18 (i) as the timing activated based on such an intra-sector position estimation value. As described above, the track hold signal is a control signal for holding the tracking servo control operation at the H level and normally executing the servo control according to the tracking error signal TE at the L level.
The timing of the track hold signal is determined by the track hold set signal and the track hold reset signal shown in FIG. 18 (i), and an H level section is obtained. That is, since the track hold set signal is raised when it is determined that the header area of the next sector is based on the intra-sector position estimated value by the counter, the track hold signal is switched from the L level to the H level from this point. To do. Then, a track hold reset signal is raised when an estimated position in the sector that is assumed to have moved to the recordable area through the header area is obtained, and the track hold signal is set to the L level accordingly. It will be made to go back.
[0086]
The configuration of the timing generator 18 for realizing the operation shown in FIG. 18, that is, the configuration of the intra-sector position estimation counter will be described with reference to FIGS.
In the block diagram of FIG. 19, a selector 61, a counter 62, and a decoder 63 are shown. In the selector 61, the counter initial value corresponding to the positions of PID1, 2, 3, 4 and PID1, the counter value corresponding to the PID2 detection position, the counter value corresponding to the PID2 detection position, and the counter value corresponding to the PID3 detection position are determined. , PID4 detection position equivalent counter value is input, and one of these is selected and output to the count input of the counter 62.
Further, the PID1 position load flag, the PID2 position load flag, the PID3 position load flag, and the PID4 position load flag shown in FIG. 18D are input to the load terminal of the counter 62.
A clock CLK-1 generated corresponding to the wobble period is input to the clock input of the counter 62, and the counter is counted up at regular time intervals corresponding to the frequency of the clock CLK-1.
[0087]
Here, if a certain PID position load flag is first obtained among the PID (1, 2, 3, 4) position load flags in the period within one sector, the PID corresponding to the PID position load flag is obtained. A counter value corresponding to position detection is selected by the selector 61 and output to the count input of the counter 62. At the same time, since the PID position load flag is input to the load terminal, the counter 62 starts counting up from the count value input to the count input. For example, if the PID1 position load flag corresponding to PID1 rises, an operation of counting up using a counter value corresponding to PID1 position detection as an initial value is started. That is, the counter value corresponding to PID1 position detection indicates the time corresponding to the position of PID1 in the sector, and the counter 62 performs time synchronization in synchronization with the sector from the time corresponding to PID1.
Then, the count value, which is the measured time, is output to the decoder 63.
[0088]
The decoder 63 generates a required timing signal when the input counter value (time keeping time) reaches a predetermined value set in advance. That is, in this case, as shown in the figure, a PID1 detection window set / reset signal, a PID2 detection window set / reset signal, a PID3 detection window set / reset signal, and a PID4 detection window set / reset signal are output. Also, a track hold set / reset signal (FIG. 18 (i)) is output. Further, the PLL pull-in start signal described with reference to FIG. 14 is output. Further, the sync frame number estimated value (FIG. 10 (f)) is output.
[0089]
For example, the track hold operation shown in FIG. 18I can be obtained by the circuit shown in FIG.
That is, by inputting each of the track hold set / reset signals to the set terminal and the reset terminal of the flip-flop 64, the flip-flop 64 outputs a track hold signal at the timing shown in FIG. It is what is done.
[0090]
In FIG. 19, the PID position load flag input to the counter 62 is generated by the circuit shown in FIG. Here, a circuit for the PID1 position load flag is shown.
In the flip-flop 65, since the PID1 detection window set / reset signal is input to the set terminal and the reset terminal, the PID1 detection window at the timing shown in FIG. The
The PID1 detection window is input to the AND gate 66. Since the PID1 detection window and the PID1 detection signal (FIG. 18 (e)) are input to the AND gate 66, the H level is output when both of these two signals become H level. This signal becomes the PID1 position load flag (FIG. 18 (g)).
In addition, what is necessary is just to make it take the same structure as what is shown by FIG. 21 as each circuit structure for outputting another PID (2, 3, 4) position load flag. That is, in the case of the PID2 position load flag, a circuit configuration may be adopted in which a PID detection window set / reset signal corresponding to PID2 is input to the flip-flop 65 and a PID2 detection signal is input to the AND gate 66. It is supposed to be.
[0091]
Further, as can be seen from the above description, the PID (1, 2, 3, 4) detection window has a count value counted based on the PID position load flag, that is, a sector, as shown in FIG. Since it is generated based on the value of the inner position estimation counter, it is always output at an appropriate timing corresponding to PID 1, 2, 3, 4 and effectively functions as a protection window. It will be.
By using the PID (1, 2, 3, 4) detection window generated in this way, for example, even if there is a false detection of the PID number and duplicate detection results are obtained, respectively. It can be used as a signal indicating a different PID. Further, since the window is generated corresponding to each PID detection signal, an appropriate value can be loaded into the counter even if the error detection result by IED is NG.
[0092]
3-3. Intra-sector position estimation operation (second example)
Subsequently, an intra-sector position estimation operation as a second example will be described as an application example of the first example. In the first example, the position in the sector is estimated based on the detection of the PID, but in the second example described below, the timing at which AM is detected as information in the header area is used as a reference. is there.
In order to detect AM, for example, a functional circuit unit that detects PA1 and PA2 may be configured in the timing generation unit 18, for example.
[0093]
The timing chart of FIG. 22 shows the intra-sector position estimation operation as the second example.
Also in this case, FIG. 22A shows data in units of sectors in time series. AM is an area arranged with a size of 3 bytes at the position immediately before PID 1, 2, 3, 4 in each of Header Fields 1, 2, 3, and 4, and has a predetermined signal pattern. As described above. In this case, it is assumed that AM is detected as shown in FIG. That is, the result is that three AMs in Header Fields 1, 2, and 4 were detected, but AMs in Header Field 3 were not detected.
[0094]
In this case, an AM corresponding PID (1, 2, 3, 4) detection window is generated at the timing shown in FIG. 22C based on the count value of the intra-sector position estimation counter. It has become. Since AM has the same signal pattern regardless of the position where it is inserted into Header Fields 1, 2, 3, and 4, the data position cannot be identified from its contents as in PID, for example. However, if the detection window based on the count value of the intra-sector position estimation counter is generated in this way, the detection timing can be made to correspond to PID 1, 2, 3, 4. .
[0095]
In this case, when the AM detection signal shown in FIG. 22B rises and the AM corresponding PID (1, 2, 3, 4) detection window shown in FIG. 22C is at the H level. In addition, the PID1 position load flag shown in FIG. 22 (d) is set. Therefore, the intra-sector position estimation counter starts counting from the initial count value corresponding to this position at the timing when the PID1 position load flag is obtained, as shown in FIG.
Also in this case, various control timings are generated based on the count value of the intra-sector position estimation counter, and for example, a track hold signal for holding tracking servo control is also generated as shown in FIG. can do.
Such an operation can be easily realized, for example, by applying the circuits of FIGS. 19 to 21 corresponding to the first example.
[0096]
3-4. Intra-sector position estimation operation (third example)
Subsequently, a third example of the intra-sector position estimation operation will be described. In the third example, the intra-sector position is estimated based on the detection of the PA in the header area.
Here, there are two types of PA, PA1 and PA2. PA1 is stored in Header Fields 1 and 3, and PA2 is stored in Header Fields 2 and 4. Therefore, the PID number cannot be identified directly from the detection result only by detecting PA1 and PA2. However, as long as header detection information and land / groove detection information are used as in the third example, the PID number can be specified from a logical combination of these pieces of information.
[0097]
Therefore, prior to the description of the operation, FIG. 24 shows the logic of PID number estimation based on the PA, header detection signal, and land / groove detection signal.
In view of this figure, for example, in the uppermost stage, the detection result of the land / groove indicates a land, and HD = 1 and HD = 0 for the header detection signals HD1 and HD2. Here, the header detection signal HD1 becomes “1” (H level) when passing through the header fields 1 and 3, and the header detection signal HD2 becomes “1” when passing through the header fields 2 and 4. (H level). Therefore, the case of HD = 1 and HD = 0 corresponds to the state of passing through Header Fields 1 and 2.
For PA1 and PA2, PA1 = 1 and PA = 0 indicate that PA1 is detected.
In such a logical state, the corresponding ID is PID3. That is, in this case, this corresponds to the state in which PA1 of Header Field 3 is detected.
Thus, even when PA1 and PA2 are detected, it is possible to uniquely identify the corresponding PID by using the land / groove information and the header detection signal.
[0098]
Based on the logic shown in FIG. 24, the intra-sector position estimation operation as a third example will be described with reference to the timing chart of FIG.
Also in this case, it is assumed that data is read from the disk as shown in FIG. Then, as shown in FIG. 23 (b), the header fields 1 and 2 and the header fields 3 and 4 are detected to detect the header corresponding to the header fields 1 and 2. The signal HD1 is at the H level, and the header detection signal HD2 is at the H level corresponding to the header fields 3 and 4.
[0099]
Further, as shown in FIG. 23C, a PA1 detection signal obtained by detecting PA1 and a PA2 detection signal obtained by detecting PA2 rise in correspondence with the position of PA in the header area. It will be. However, in the case of this figure, a state example in which detection for PA2 in Header Field 4 is an error is shown.
[0100]
At this time, the track is a groove, and as a detection result, as shown in FIG. 23D, the land / groove detection signal is at the L level indicating that it is a groove.
The header detection signals HD1 and HD2 shown in FIG. 23 (b) are detected by the header detection unit 15, and the land / groove detection signal shown in FIG. 23 (d) is detected by the land / groove detection unit 17.
For PA1 and PA2, for example, a functional circuit unit that detects PA1 and PA2 may be configured in the timing generation unit 18.
[0101]
In this case, a PID (1, 2, 3, 4) detection window is generated at the timing shown in FIG. 23E based on the count value of the intra-sector position estimation counter. As described above, the PID number corresponding to the detected PA cannot be specified only by the PA1 and PA2 detection signals. However, as described also with reference to FIG. 24, the header detection signals HD1 and HD2 (FIG. 23). (B)) By using the land / groove detection signal (FIG. 23D), the PID number can be estimated, and each PID (1, 2, 3, 3) of FIG. 4) The detection window is also generated according to the timing of each of PID1 to PID4 based on the logic shown in FIG. 24, so that the PID detection specifying the PID number is almost certain. It is what you are doing.
[0102]
In this case, based on the logical product of the PA (1,2) detection signal shown in FIG. 23 (c) and the PID (1,2,3,4) detection window shown in FIG. 23 (d). Thus, the PID (1, 2, 3, 4) position load flag shown in FIG. 23 (f) is generated.
In this case, since the PID1 position load flag, the PID2 position load flag, and the PID3 position load flag rise, as shown in FIG. 23 (g), the position in the sector is reached at the timing when the first PID1 position load flag rises. The count initial value of the estimation counter is loaded and the count is started.
Also in this case, the timing of various control operations including the tracking servo control hold shown in FIG. 23 (h) is generated based on the count value of the intra-sector position estimation counter. .
[0103]
3-5. Intra-sector position estimation operation (fourth example)
Subsequently, a fourth example of the intra-sector position estimation operation will be described. The fourth example is a simpler detection operation than the first to third examples. In the fourth example, the intra-sector position estimation counter is counted based on the header detection signals HD1 and HD2.
[0104]
The timing chart of FIG. 25 shows the intra-sector position estimation operation as the fourth example.
As shown in FIG. 25, each section of Header Fields 1, 2 and Header Fields 3 and 4 is detected from the data shown in FIG. 25A as shown in FIG. 25B. The periods during which the header detection signals HD1 and HD2 are at the H level are obtained at the timing shown in the figure.
In addition, the detection waveforms corresponding to Header Fields 1, 2 and Header Fields 3 and 4 are inverted in polarity depending on whether the track to be traced immediately is a land or a groove. Therefore, which of the header fields 1 and 2 and header fields 3 and 4 is detected according to the state of the land / groove detection signal obtained as shown in FIG. It becomes possible to identify whether the signal obtained by detection is HD1 or HD2.
[0105]
In this case, as shown in FIG. 25C, the rising edge of the header detection signal HD1 and the rising edge of the header detection signal HD2 are set as load signals.
In this case, a state is shown in which both the rising edge of the header detection signal HD1 and the rising edge of the header detection signal HD2 are obtained (FIG. 25 (c)). At the timing of the rising edge of the signal HD1, as shown in FIG. 25E, the in-sector position estimation counter is loaded to start counting. In this case, the count initial value is determined corresponding to the start position of Header Field 1.
Also in this case, the control timing including the tracking servo control hold shown in FIG. 25 (f) is generated by the counter value of the intra-sector position estimation counter.
[0106]
4). Sector synchronization protection operation (first example)
As described above, the intra-sector position estimation operation (first to fourth examples) as the present embodiment has been described with reference to FIGS. Of the intra-sector position estimation operations from the first example to the fourth example, it can be said that the highest accuracy is the operation of the first example.
The intra-sector position estimation operation of the first example is based on the PID detection result. In other words, if the count value of the intra-sector position estimation counter is not appropriate, the various control timings that are activated based on the count value are not appropriate, so that the PID can be read normally. It will not be. Therefore, by identifying whether or not the PID is properly read, it is possible to determine whether or not the intra-sector position estimation result is correct. The operation of the first example is based on the PID detection result, and has the highest accuracy as described above. However, when the PID cannot be read, the reliability cannot be ensured.
[0107]
On the other hand, for example, the intra-sector position estimation operation of the fourth example is based on the header detection result using the amplitude change peculiar to the header region, so that the estimation result is higher than the intra-sector position estimation operation of the first example. However, the signal detection for obtaining the reference timing is simple in that it is the detection of the header area. Therefore, for example, even if the PID cannot be read, the header area is detected and the position in the sector is detected. The possibility that the estimation operation can be performed is extremely high.
[0108]
Therefore, in this embodiment, in order to make the intra-sector position estimation operation more reliable, based on the background described above, the synchronization protection operation in the sector is performed as described below. It is also made to take the structure to obtain.
[0109]
The timing chart of FIG. 26 shows an outline of the sector synchronization protection operation (first example) as the present embodiment.
As the sector synchronization protection operation here, a state where the sector synchronization is not locked (unlock) and a state where it is locked (lock) are identified based on the result of PID detection. That is, as shown in FIG. 26 (d), a signal LOCK that is at the H level in the locked state and at the L level in the unlocked state is generated.
[0110]
The signal LOCK is generated at the following timing.
Here, FIG. 26A shows the PID evaluation timing. This PID evaluation timing flag stands for each sector, for example, and is obtained at the timing when reading of PIDs 1, 2, 3, and 4 in one sector and error detection are completed. When this PID evaluation timing flag is obtained, PID evaluation is performed. That is, for sector synchronization protection, PID evaluation within one sector is performed. The operation of the PID evaluation here will be described later. As a result of the PID evaluation, for example, if all of PID 1, 2, 3, 4 are properly detected, the PID is evaluated as shown in FIG. If the detection OK flag is set and NG, the PID detection OK flag cannot be obtained.
[0111]
Here, for example, as shown in FIG. 26 (d), it is assumed that the signal LOCK is at the L level and is in the unlocked state. Under such a state, the count value of the sector synchronization protection counter shown in FIG. 26C is reset to zero. If the PID detection OK flag is obtained for the first time under this state, the count is incremented here, and the count value becomes “1” as shown in FIG. Then, assuming that the PID detection OK flag is continuously obtained thereafter, the count value of the sector synchronization protection counter in FIG. 26 (c) is incremented every time the PID detection OK flag is obtained. It will be. Note that when the PID detection OK flag is not obtained four times in succession in the unlock state and the result is NG in the middle, the count value is reset to “0” at this timing.
[0112]
Further, the maximum value of the count value of the sector synchronization protection counter under the unlock state here is set to “4”. In this case, since the PID detection OK flag of FIG. 26B is obtained continuously four times or more, the count value of the sector synchronization protection counter is the maximum value. It will be counted up to “4”. In response to this, the signal LOCK becomes H level as shown in FIG. That is, a transition is made from the unlocked state to the locked state.
[0113]
At the timing when the signal LOCK is inverted to H level as described above, the count value is reset from “4” to “0”. Then, as long as the PID detection OK flag is continuously obtained for each sector period from the time when such a lock state is started, the count value is maintained at “0”. That is, it can be seen that the lock state is stably maintained when the lock state is set and the count value is “0”.
[0114]
Further, the maximum value of the count value in the lock state is set as “3”. Then, as shown in FIGS. 26 (b) and 26 (c), there is a continuous state in which the PID reading error occurs due to some factor under the lock state, and the PID detection OK flag does not stand in synchronization with the PID evaluation timing. In such a case, the count value is counted up.
When the state in which the PID detection OK flag is not raised continues three times and the maximum value of the count value reaches “3”, the signal LOCK becomes L level, indicating an unlocked state. At the same time, the count value is reset to “0”.
[0115]
When the counter value is “1” or “2” under the lock state and the PID detection result becomes OK again, the counter value is reset to “0”. ing.
[0116]
In this embodiment, as shown in FIGS. 26D and 26E, in the unlock state, the sector position estimation operation based on the header area detection shown in FIG. Switching is performed so that the intra-sector position estimation operation based on the PID detection shown in FIG.
Thus, if the intra-sector position estimation operation is switched in accordance with the lock / unlock state, a highly accurate intra-sector position estimation result based on PID detection is obtained in the lock state where the reproduction operation is stable. Will be. On the other hand, in an unlocked state where proper PID reading cannot be expected, the intra-sector position estimation based on header detection that does not depend on PID detection enables proper intra-sector position even when the reproduction signal is unstable. The estimation result is obtained. As a result, in the present embodiment, it is possible to obtain a highly reliable intra-sector position estimation result almost constantly regardless of the lock / unlock state.
[0117]
In addition, according to the signal LOCK generation operation shown in FIG. 26, the lock state is obtained when the result of OK for the PID detection is obtained continuously for 4 sectors under the unlock state, and the PID is obtained under the lock state. When the result of NG regarding the detection is obtained three times in succession, the unlock state is set.
For example, in order to generate the lock / unlock state, it is possible to simply correspond to the result of PID detection OK / NG as it is, but in such a case, the lock state is stably maintained. Even in the case where a sector in which a PID detection error has occurred temporarily occurs in the course of continuing, the operation is switched to the intra-sector position estimation operation based on header detection, and conversely the accuracy of the estimation result Will be lowered.
On the other hand, in the present embodiment, as described above, the switching of the lock / unlock state is performed on the condition that a certain degree of continuity is obtained with respect to the PID detection result. This avoids such inconvenience.
[0118]
The block diagram of FIG. 27 is a timing generation unit 18 (intra-sector position estimation counter) configured to be able to switch the intra-sector position estimation operation in accordance with the lock / unlock state as shown in FIG. The structure of is shown. Note that the configuration shown in this figure is based on the configuration of the PID detection reference intra-sector position estimation counter shown in FIG. 19, and therefore the same parts as those in FIG. To do.
[0119]
In the intra-sector position estimation counter shown in FIG. 27, a selector 64 and switches 65 and 66 are added to the configuration shown in FIG.
The selector 64 receives an HD1 detection position equivalent value and an HD2 detection position equivalent value. The HD1 detection position equivalent value is a count initial value corresponding to the detection timing of the first half of the header area consisting of Header Fields 1 and 2, and the HD2 detection position equivalent value is the detection timing of the latter half of the header area consisting of Header Fields 3 and 4. This is the initial count value corresponding to.
[0120]
Further, the switch 65 selectively selects the outputs of the selectors 61 and 64 and outputs it to the count input of the counter 62. The switch 66 selectively selects the PID (1, 2, 3, 4) position load flag and the HD (1, 2) position load flag and outputs them to the load terminal of the counter 62.
These switches 65 and 66 are both switched according to the state of sector synchronization lock / unlock. That is, when the signal LOCK shown in FIG. 26 (d) is at the H level (lock), the switch 65 selects the PID (1, 2, 3, 4) position load flag as a count input, and the switch 66 The (1, 2, 3, 4) position load flag is selected and used as a load input. That is, the signal path is equivalent to the circuit configuration shown in FIG. 19, and intra-sector position estimation based on PID detection is performed.
When the signal LOCK is at the L level (unlock), the switch 65 selects the HD (1, 2) position load flag and inputs the count, and the switch 66 selects the HD (1, 2) position load flag. Load input. In the case of this signal path, intra-sector position estimation based on header detection shown in the timing chart of FIG. 25 is performed. That is, the intra-sector position estimation operation is switched at the timing as shown in FIG.
[0121]
In order to realize the operation of the circuit shown in FIG. 27, it is necessary to generate the signal LOCK at an appropriate timing by the operations shown in FIGS. 26 (a), (b), (c), and (d). There is. Therefore, a configuration for generating the signal LOCK will be described next.
[0122]
The timing chart of FIG. 28 shows operations for PID detection determination corresponding to FIGS. 26 (a) and 26 (b). In addition, what is necessary is just to comprise so that the operation | movement shown by this figure may be performed in the PID detection part 16, for example.
For example, if PID1 is detected for a certain sector, a signal pid1 ldpedge is obtained according to the timing at the time of detection as shown in FIG. Similarly, if PIDs 2, 3, and 4 are detected, pid2 ldpedge, pid3 ldpedge, and pid4 ldpedge are obtained as shown in FIGS. 28B, 28C, and 28D at the timing of detection. It will be.
[0123]
Then, in correspondence with the detection timings shown in FIGS. 28A to 28D, as shown in FIGS. 28E to 28H, the protection windows pidldmask_rg [0] and pidldmask_rg [1 ], pidldmask_rg [2], pidldmask_rg [3] are generated. Then, for PID1, if the signal pid1 ldpedge is obtained within the period in which pidldmask_rg [0] is at the H level, as shown in FIG. 28 (i), the detection OK flag for each PID is obtained. Pidlddtct is made to stand. Similarly, for PIDs 2, 3, and 4, pid2 ldpedge, pid3 ldpedge, and pid4 ldpedge were obtained within a period in which pidldmask_rg [1], pidldmask_rg [2], and pidldmask_rg [3] are at the H level. Pidlddtct will stand up.
[0124]
In response to the detection OK flag pidlddtct in FIG. 28 (i), the signal pidlded_rg shown in FIG. 28 (j) is activated. This signal pidlded_rg rises from L level to H level when the detection OK flag pidlddtct corresponding to PID1 rises, and all four detection OK flags corresponding to PID1, 2, 3, 4 are shown in the figure. When pidlddtct is obtained, for example, in the current sector period, the signal is maintained at the H level. On the other hand, if one of the four detection OK flags pidlddtct corresponding to PID 1, 2, 3, 4 does not stand, this signal is at L level.
[0125]
As described above, the flag pideval indicating the PID evaluation timing is set at the required timing at which all the detections from PID1 to PID4 are completed. This flag pideval corresponds to the PID evaluation timing in FIG.
At this timing, it is referred to whether the signal pidlded_rg shown in FIG. 28 (j) is at the H level or the L level. That is, it is determined whether the detection result for PID1 to PID4 is OK or NG. If the PID detection result is OK because it is at the H level, the flag pidtmgok shown in FIG. 28 (l) is set. This is a PID detection OK flag shown in FIG.
On the other hand, if the signal pidlded_rg is at the L level, the flag pidtmgng shown in FIG. 28 (m) is set instead of the flag pidtmgok (PID detection OK flag).
[0126]
Then, by using the flag pidtmgok and the flag pidtmgng obtained as described above, the sector synchronization protection counter having the configuration shown in FIG. 29 is operated to generate the timing of the signal LOCK.
In the circuit shown in this figure, the flip-flop 81 generates the signal LOCK. The flip-flop 81 outputs an H level signal LOCK at the timing when the signal rpend input to the set terminal rises to H level, and the signal at the H level when the signal fpend input to the reset terminal rises to H level. Reset LOCK to L level. That is, the timing at which the signal LOCK becomes H level / L level is generated using the signals rpend and fpend as a trigger.
Note that the flip-flop 81 and a counter 78 which will be described later operate at the timing of the clock CLK.
[0127]
The timing of the signals rpend and fpend is generated by a circuit unit having a counter 78.
For the count input of the counter 78, the count initial value “0” described with reference to FIG.
The enable terminal receives the output of the logic circuit unit composed of AND gates 71 and 72 and an OR gate 73 using three signals of a signal LOCK, a flag pidtmgng, and pidtmgok. As an output of the logic circuit section (AND gates 71 and 72, OR gate 73), when the signal LOCK is at the H level, an H level signal is input to the enable terminal every time the flag pidtmgng rises, and the count up is performed. Let it run. On the other hand, when the signal LOCK is at the L level, every time the flag pidtmgok rises, an H level signal is input to the enable terminal to perform count up. As a result, as shown in FIG. 26, under the lock state, the PID detection is counted up every time NG is continuously detected.
[0128]
Further, the output of the logic circuit unit composed of the OR gate 74, the AND gates 75 and 76, and the OR gate 77 using the signal LOCK, the flags pidtmgng and pidtmgok, and the signals rpend and fpend is input to the load terminal.
Depending on the logic circuit section (OR gate 74, AND gates 75 and 76, OR gate 77), when one of the signals rpend and fpend rises, an H level load signal is output and the counter input is loaded. That is, the count value is reset to the initial value “0”. This corresponds to the operation of resetting the counter value to “0” when the state transition is made from lock → unlock or unlock → lock.
In addition, when the signal LOCK is at the H level, an H level load signal is output every time the flag pidtmgok (PID detection OK flag) is set, so that the count value is reset to the “0” level. can get. This corresponds to an operation in which the count value “0” is maintained as long as the PID detection OK flag is continuous under the lock state.
Further, when the signal LOCK is at the L level, an operation of resetting to the “0” level is obtained every time the flag pidtmgng is set. This corresponds to the operation of setting the count value to “0” unless the PID detection OK flag is obtained under the unlock state.
[0129]
In the counter 78, the count operation is performed after the count initial value = 0 is set by the enable signal and the load signal input as described above. The output of the count value is branched and input to the comparator 79 and the comparator 80.
The comparator 79 compares the count value with the reference value rpmax. Here, as the reference value rpmax, “4”, which is the maximum counter value in the unlock state, described in FIG. 26C is set. When the count value is equal to or greater than the reference value rpmax, an H level signal is output to the AND gate 82. The AND gate 82 calculates and outputs the logical product of the output of the comparator 79 and the inverted input of the signal LOCK. This is the signal rpend. That is, when the signal is input to the set terminal of the flip-flop 81 as the H level, the signal LOCK is raised from the L level to the H level, and transits from the unlock state to the lock state.
[0130]
On the other hand, the comparator 80 compares the count value with the reference value fpmax. As the reference value fpmax, the counter maximum value “3” in the lock state is set. When the count value is equal to or greater than the reference value fpmax, an H level signal is output to the AND gate 83. The AND gate 83 outputs the signal fpend by taking the logical product of the output of the comparator 79 and the signal LOCK. When the H level signal fpend is input to the reset terminal of the flip-flop 81, the signal LOCK is lowered from the L level to the H level, and the lock state is changed to the unlock state.
The signal RST_X is used for performing a hardware reset on the counter 78 and the flip-flop 81.
[0131]
5). Sector synchronization protection operation (second example)
Next, a second example of the sector synchronization protection operation will be described.
The sector synchronization protection operation as the first example described above is a transition between two states of lock / unlock. As shown in FIG. 30 (d) in the timing chart of FIG. In the second example, transition between three states of lock, unlock1, and unlock2 is performed.
[0132]
In this case, the transition operation between the three states is as follows.
Here, in obtaining the sector synchronization protection operation as the second example, as shown in FIGS. 30A, 30B and 30C, the PID evaluation timing, the PID detection OK flag, and the sector synchronization protection counter are used. The operation is the same. That is, the operation shown in FIG. 28 is executed, and the circuit configuration shown in FIG. 29 is applied. Also, the circuit configuration shown in FIG. 27 is applied as a configuration for switching the intra-sector position estimation operation based on the state transition.
[0133]
First, unlock1 is set when the count value of the sector synchronization protection counter is “0” when the lock state is not set. For example, when the PID detection result is OK from the state of unlock1 and any of the count values “1”, “2”, “3”, and “4” is obtained, the state transitions to the unlock2 state. is there. However, although not shown in this figure, when the PID detection result is NG even once in the state of unlock2, the state transits to unlock1.
When the count value is counted up to “4” in the unlock2 state, the state transits to lock. Then, when the PID detection result NG continues three times under the lock state and the count value reaches “3”, the state returns to the unlock1 state.
[0134]
For reference, FIG. 31 conceptually shows the transition between the three states of lock, unlock1, and unlock2 described above.
When the synchronization protection operation is started, for example, the state is initially unlock1. When the PID detection result is OK and the flag pdtmgok rises, the state transitions to the unlock2 state. However, if the PID detection result is NG even once under the unlock2 state and the flag pidtmgng is generated, the state is returned to the unlock1 state.
In addition, when the signal rpend rises four consecutive times in the unlock2 state and the result of the PID detection OK, the state transits to the lock state. Under the lock state, when the signal fpend rises three consecutive times of the NG PID detection result, the signal transits to unlock1.
[0135]
Here, the description is returned to FIG. 30. In response to the three states of lock, unlock 1 and unlock 2 which are shifted as described above, the intra-sector position estimation operation is switched as shown in FIG. To be done. That is, in the unlock1 state, the intra-sector position estimation operation based on header detection is performed, and in the lock and unlock2 states, the intra-sector position estimation operation is performed based on PID detection.
In this way, an opportunity for switching to the intra-sector position estimation operation based on header detection, which is considered to be inferior to the intra-sector position estimation operation based on PID detection, is used, for example, in the sector synchronization protection operation of the first example. Since the number can be smaller than that in the case, it is generally possible to obtain a more accurate in-sector position estimation result.
[0136]
In order to generate the three states of lock, unlock1, and unlock2 at the timing shown in FIG. 30 (d), for example, sector synchronization shown in FIG. 32 is performed with respect to the operation shown in FIG. 28 and the circuit shown in FIG. A configuration of a protection circuit is added.
The sector synchronization protection circuit shown in this figure includes a decoder 90, an OR gate 91, and flip-flops 91 and 92.
Here, seven types of signals are input to the decoder 90 as shown in the figure, and the decoder 90 outputs signals PPRSTT1 and PPRSTT2 in accordance with the truth table shown in FIG. The signal PPRSTT1 is input to the flip-flop 92, and the signal PPRSTT2 is input to the flip-flop 93. These flip-flops 92 and 93 operate by inputting a clock CLK.
The OR gate 91 outputs a logical sum of the same seven types of signals that are input to the decoder 90 as an enable signal for the flip-flops 92 and 93. That is, the output (Q) of the flip-flops 92 and 93 is valid if any one of the seven types of signals is rising.
[0137]
Then, the flip-flop 92 outputs the input signal PPRSTT1 as the signal PRSTT1. This signal PRSTT1 is a signal that becomes H level only corresponding to the timing of lock in FIG. In other words, the signal PRSTT1 is a signal that functions as a trigger for making a transition to the lock state when it becomes H level.
The flip-flop 93 outputs the input signal PPRSTT2 as the signal PRSTT2. The signal PRSTT2 is a signal that becomes L level corresponding to the timing of lock and unlock1 in FIG. 30D and becomes H level corresponding to the timing of unlock2.
That is, the signal PRSTT2 is shifted to unlock2 at the timing when it rises to the H level. Further, when the signal PRSTT1 is set to the L level and the signal PRSTT2 is also at the L level, the state is shifted to the unlock1 state.
Therefore, when the intra-sector position estimation counter shown in FIG. 27 is configured corresponding to the second example, as a signal for switching the switches 65 and 66, when the signal PPRSTT1 is at the H level and the signal PRSTT2 is A signal that is H level when it is H level and is L level when both the signal PPRSTT1 and the signal PRSTT2 are L level may be given.
[0138]
Note that the following application examples can be considered along with the sector synchronization protection operations of the first and second examples.
That is, the PID read reliability is high in the lock (and unlock2) state, and the PID read reliability is inferior to that in the lock state in the unlock (unlock1) state. Then, if at least one of the PIDs (1, 2, 3, 4) is read, the PID is adopted for signal processing control, and in the unlock state, the PID (1, 2, 3, 4) is used. Among them, for example, if reading of two or more PIDs is not OK, it is considered that the PIDs are not adopted.
In the sector synchronization protection operations of the first and second examples, the intra-sector position estimation operation is switched between the PID detection reference method and the header area detection reference method. A plurality of intra-sector position estimation operations to be adopted are not limited to these two. That is, for the intra-sector position estimation operation, the four examples from the first example to the fourth example are listed, and therefore, for example, two methods that are appropriate from these may be adopted. .
[0139]
6). PID storage processing
As can be seen from the above description of the DVD-RAM format, the sector address is performed based on the detection of the PID. That is, the address of the recordable area following the header area is specified based on the physical ID number and the sector number stored in the PID.
In the PID detection, error detection is performed using the IED arranged immediately thereafter. Conventionally, when the error detection result by the IED is NG, the detected PID is detected. Is considered to be extremely low in reliability, and the PID is discarded without being used for reproduction control.
However, in practice, even if the detection result due to the IED error results in an error, the cause of the error may be the information content other than the physical ID number in the PID. There is also a possibility that the value is normal. Since four PIDs of PIDs 1, 2, 3, and 4 are stored in one sector, if any one of these is OK, the PID may be used. For example, when the error detection result is NG for all four PIDs PID 1, 2, 3, and 4, there is a possibility that actually usable PID may exist as described above. Regardless, an inefficient process is executed in which all four PIDs must be discarded.
[0140]
In view of this, the present embodiment adopts a configuration for executing the following PID storage process on the premise of the intra-sector position estimation operation described so far. As a result, even if the error detection result by IED is NG, the PID number (that is, which of PIDs 1, 2, 3, and 4) can be estimated and the PID is not discarded. is there. Also, by obtaining such a configuration, as a result, the reliability of the reproduction performance is improved.
[0141]
FIG. 34 shows a circuit configuration for realizing the PID storing process as the present embodiment. The circuit shown in this figure is provided in the PID detector 16, for example.
However, the land / groove determiner 108 shown in this figure corresponds to, for example, the land / groove detector 17 shown in FIG. 1, and the HD1 / HD2 detector 109 corresponds to the header detector 15. Further, the intra-sector position estimator 113 corresponds to the timing generation unit 18 and adopts a configuration capable of executing any of the intra-sector position estimation operations from the first example to the fourth example described so far. In addition, a configuration capable of executing the sector synchronization protection operation of the first example or the second example can be adopted.
[0142]
For example, an EFM + signal that is a reproduction signal from a disc is input to an area storage 101 for storing PID, IED, and PA, and is also branched to an AM detector 104 and a PA detector 105. Entered.
The AM detector detects AM from the input EFM + signal and outputs the detected output to the PID read timing controller 106. The PID read timing controller 106 controls each processing timing of the area storage unit 101 and the EFM + demodulator 102 using the AM detection timing as a trigger. In accordance with this control timing, the area storage unit 101 extracts three types of information of PID, IED, and PA, and the EFM + demodulator 102 performs EFM + demodulation processing. In the PID storage 103, the PID is extracted from the signal demodulated by the EFM + demodulator 102 and stored. That is, the PID storage 103 stores the substance of the PID read from the disk.
[0143]
The PID and IED signals demodulated by the EFM + demodulator 102 are input to the IED check circuit 107. The IED check circuit 107 performs error detection on the PID using the input PID and IED. If the error detection result is NG, an IED error flag indicating that the IED error detection result is NG is output. This IED error flag is branched and output to the selector 114 and the first to fourth storage units (121, 122, 123, 124) described later.
[0144]
The PID demodulated by the EFM + demodulator 102 is also input to the first PID number estimator 110.
[0145]
The PA detector 105 detects PA from the input EFM + signal at the PA detection timing generated by the PID read timing controller 106. When PA is detected, a PA detection signal indicating this is output to second PID number estimator 111.
[0146]
The circuit shown in this figure includes three PID number estimators: a first PID number estimator 110, a second PID number estimator 111, and a third PID number estimator 112.
The first PID number estimator 110 receives the PID demodulated by the EFM + demodulator 102 and identifies a 2-bit physical ID number area stored in the PID, thereby estimating the PID number. The first PID number estimator 110 estimates the PID number directly from the physical ID number stored in the PID. For example, when there is no IED error, the second PID number estimator 111 described below is used. The third PID number estimator 112 can also expect an accurate estimation result.
The second PID number estimator 111 includes a PA (1, 2) detection signal detected by the PA detector 105, a land / groove detection signal determined by the land / groove determination unit 108, and an HD1 / HD2 detector 109. The PID number is estimated based on the detected header detection signals HD1 and HD2. That is, the PID number is estimated by performing decoding according to the logic shown in FIG. 24 based on the above information obtained at the timing shown in FIGS. 23 (a), (b), (c), and (d). To be done.
The third PID number estimator 112 detects the detection flags of PIDs 1, 2, 3, and 4 input from the PID read timing controller 106 according to the AM detection timing, and the PID (1, 2, 4) obtained by the intra-sector position estimator 113. 3,4) Estimate the PID number by taking the logical product with the detection window. That is, for example, according to the timing shown in FIGS. 22B and 22C, the PID number corresponding to the PID detection window opened when the AM detection flag corresponding to PID detection becomes H level is set as the estimated value. To do.
[0147]
The PID number estimation operation by the first to third PID number estimators 110, 111, and 112 is performed simultaneously at the timing at which each of the PIDs 1, 2, 3, and 4 should be detected for each sector period. The estimated value is output to the selector 114.
[0148]
In the selector 114, any one of the PID number estimated values input from the first to third PID number estimators 110, 111, and 112 is appropriate at the selection timing generated by the PID read timing controller 106. Or one can be selected. At this time, the selection is performed using the IED error flag output from the IED check circuit 107 and the PID (1, 2, 3, 4) detection window input from the intra-sector position estimator 113. Further, when a predetermined condition is satisfied, when it is determined that the PID number cannot be estimated, no estimated value is selected.
[0149]
When the estimated PID number is selected, buffering is enabled for the storage corresponding to the selected estimated PID number from the first to fourth storage units 121, 122, 123, and 124. Signal B-EN is output.
Specifically, since each of the first to fourth storage units 121 to 124 corresponds to the PIDs 1 to 4, this is PID number = “2” (PID2) as the selected PID number estimated value. Then, the selector 114 outputs the buffering enable signal B-EN to the second storage 122 corresponding to PID2.
However, when it is obtained that the PID number cannot be estimated, the buffering enable signal B-EN can be prevented from being output to any of the storage units. Note that how the selector 114 selects the PID estimated value and under what conditions it is determined that the estimation is impossible will be described later.
[0150]
As described above, when the buffering enable signal B-EN is output, the storage designated by the buffering enable signal B-EN among the first to fourth storages 121 to 124 is currently PID. The PID stored in the storage unit is captured and held. At the same time, if an IED error flag is obtained for the PID, the IED error flag is also captured and held. When the error detection by IED is OK, the IED error flag is not stored as a matter of course.
Further, in response to the buffering enable signal B-EN output from the selector 114, a buffering flag indicating that the buffering is normally performed is generated, and this buffering flag is also held. The buffering flag is stored regardless of whether the error detection by IED is OK / NG.
As described above, each storage unit (121 to 124) can store the substance of the PID, the IED error flag, and the buffering flag. As the present embodiment, by providing the first to fourth storage units 121 to 124, it is possible to buffer and hold all PIDs of PIDs 1, 2, 3, and 4 for each sector. It is said that.
[0151]
Further, the information stored in the first to fourth storage units 121 to 124 as described above is cleared at the timing when the clear signal CL obtained by the intra-sector position estimator is output, and the next sector is cleared. Preparations for storing the PIDs are made.
[0152]
The timing chart of FIG. 36 shows an operation example of the circuit shown in FIG.
Here, when the EFM + signal is input as shown in FIG. 36A, first, the AM detection circuit 104 detects AM in the EFM + signal, and at the timing shown in FIG. A level AM detection flag is obtained. Then, using this AM detection timing as a trigger, the PID read timing controller 106 generates the EFM demodulation timing shown in FIG. The EFM + demodulator executes this timing EFM demodulation process. Further, the PID read timing controller 106 generates the PID storage timing at the timing shown in FIG. 36 (d). As a result, the PID storage 103 stores the EFM + demodulated PID entity in FIG. ) Is stored at the timing shown in FIG.
[0153]
Further, the PID read timing controller 106 generates an I level check signal of H level at the timing shown in FIG. In response to this, the IED check circuit 107 performs error detection on the stored PID at the timing shown in FIG. 36 (e). In this case, the check result is NG. Accordingly, the H level IED error flag rises at the timing when the error detection shown in FIG.
[0154]
Further, for example, at the timing shown in FIG. 36H, which is substantially the same as the PID storage timing shown in FIG. 36E, the first PID number estimator 110 uses the PID based on the PID number of the PID. A number estimate is obtained.
[0155]
Further, in the second PID number estimator 111, as shown in FIG. 36 (i), the second PID number estimation value is obtained at the timing when the PA is detected.
Further, the third PID number estimator 112 also obtains the third PID number estimated value as shown in FIG. That is, when the PID detection flag obtained according to the PID detection timing becomes H level, the PID (1, 2, 3, 4) detection window output from the intra-sector position estimator 113 becomes H level. If so, the PID number corresponding to the PID detection window is set as the PID number estimated value. In this case, since the PID detection flag is obtained when the PID2 detection window is at the H level, the PID number estimated value is “2”.
[0156]
When three PID number estimated values of the first to third PID number estimated values are obtained in this way, the PID number estimated value among these three is estimated at the timing shown in FIG. From this, an appropriate PID number estimate is selected.
Various ways of selecting the estimated PID number in this case can be considered, but the following selection operation is exemplified.
First, when the PID error detection result is OK and the IED error flag shown in FIG. 36 (g) is not set, the data content of the PID read at this time is reliable including the physical ID number. Therefore, the first PID number estimated value is selected.
[0157]
On the other hand, when the PID error detection result is NG and the IED error flag is set, the possibility that an error has occurred in the physical ID number in the PID cannot be denied, so the first PID number estimated value should be selected. Instead, the second or third PID number estimation value is adopted.
In this case, whether to select the second PID number estimated value or the third PID number estimated value is selected. One is the state of lock (and unlock2) as the synchronization state in the sector synchronization protection circuit. In this case, it is conceivable to select the third PID number estimated value, and in the unlock (unlock1) state, select the second PID number estimated value. That is, when a certain degree of sector synchronization is assumed, the third PID number estimation value for obtaining the PID number estimation value based on the detection timing of the PID is used, and thereby the sector synchronization stability is obtained. In such a state, the second PID number estimated value for estimating the PID number based on the detection of the header area is used without depending on the PID detection.
[0158]
When the IED error check result is NG, the first PID number estimated value and the third PID number estimated value are compared, and if these estimated values match, this matched estimated value is selected and estimated. If the values do not match, it is possible to give a determination result that the PID number cannot be estimated.
In addition, when the IED error check result is NG, it can be considered that the determination result indicates that the PID number cannot be estimated.
[0159]
Assuming that a certain PID number estimated value is selected and adopted at the timing shown in FIG. 36 (k) as described above, the selector 114 performs the PID read timing controller as shown in FIG. 36 (l). The buffering enable signal B-EN is output in accordance with the H level selection timing generated at 106. In this case, assuming that the PID number adopted as shown in FIG. 36 (k) is “2”, as shown in FIG. 36 (l), as the buffering enable signal B-EN, PID2 A signal corresponding to is output. As a result, information is stored in the second storage 122 corresponding to PID2 among the first to fourth storages 121 to 124 as shown in FIG. 36 (m).
That is, the second storage 122 captures and holds the PID stored in the PID storage 103 at this time as PID2, and simultaneously holds the IED error flag and the buffering flag.
[0160]
With such a configuration, even if the error detection result by IED is NG, the PID number can be estimated without discarding the PID, and the reliability of the representative PID selected as will be described later Can be improved. The representative PID is a PID whose data content is referred to for actual reproduction control, and one PID is selected as a representative PID from among PIDs 1, 2, 3, and 4 for each sector.
For example, in the case of the present embodiment, first to third PID number estimators 110 to 112 are provided, which means that a plurality of PID number estimation methods are combined. Depending on this, as can be seen from the previous explanation, an appropriate PID number estimation method can be adopted according to the error detection status by IED, synchronization status, etc., so that a more accurate PID number detection result can be obtained. Can be expected.
Furthermore, by storing the PID data together with the IED error flag, the reliability of the representative PID described later can be improved also in this respect.
[0161]
7). Representative PID decision processing
Depending on the circuit shown in FIG. 34, it is possible to finally hold PIDs 1, 2, 3, and 4 in the first to fourth storage units 121 to 124. In this embodiment, for example, one PID to be used for reproduction control for the current sector is selected as the “representative PID” from among the PIDs stored in the first to fourth storage units 121 to 124. Is done.
[0162]
A circuit configuration for this purpose is shown in FIG. The circuit shown in this figure is provided for the subsequent stage of the first to fourth storage units 121 to 124 shown in FIG. 34. For example, the circuit shown in FIG. It is provided.
[0163]
The PID, IED error flag, and buffering flag held in the first to fourth storage units 121 to 124 are output to the PID (1, 2, 3, 4) correction circuits 131 to 134, respectively. .
In these PID (1, 2, 3, 4) correction circuits 131 to 134, the value of NOS (Number Of Sector) output from the NOS calculator 146 and the land / groove determiner 108 output from the land / groove determiner 108. By using the groove detection signal, the sector number value of the input PID is corrected.
The NOS (Number Of Sector) indicates the number of sectors in one track including the current sector. The configuration of the NOS calculator 146 for calculating the NOS will be described later.
[0164]
Further, the “correction” here means the following.
As described above, the value indicated by the sector number in the PID is the address (sector number) of the subsequent land track if the sector number is PID 1 or 2, and if the sector number is PID 3 or 4, the subsequent groove track is Address (sector number). Accordingly, if a predetermined calculation is performed on the sector number and the NOS value indicated by PID 1, 2, 3, 4 based on whether the current track is a land / groove track, the subsequent land or groove track An address (sector number) can be obtained. In this way, the process for obtaining the address of the subsequent track is referred to as “correction” here. If the data contents of PIDs 1, 2, 3, and 4 are accurate, all of the same values are obtained depending on the calculations performed by the PID (1, 2, 3, and 4) correction circuits 131 to 134. Will be.
[0165]
With respect to the correction processing executed by the PID (1, 2, 3, 4) correction circuits 131 to 134, FIG. 5 will be referred to again.
Here, the PIDs 1, 2, 3, and 4 read from the header area are PID1 (m-N), PID2 (m-N), PID3 (m), and PID1 (m) in FIG. . Therefore, from the trace locus, the subsequent track is a land track (m-N). As described above, the land track and the groove track are alternated every track. Therefore, one track including the current sector is a land track.
[0166]
In this case, a signal indicating a land / track is input as a land / groove detection signal from the land / groove determination unit 108 to the PID (1, 2, 3, 4) correction circuits 131-134. Will be. Also, the NOS value, which is the number of sectors in the current track, is input from the NOS calculator. This is represented by the variable N in the case of FIG.
[0167]
When the land / groove detection signal indicates a land track, the PID (1, 2) correction circuits 131 and 132 use the sector number values in PID 1 and 2 input to the correction values as they are. .
On the other hand, the PID (3, 4) correction circuits 133 and 134 obtain correction values by subtracting NOS = N for the sector number values in the PIDs 3 and 4 respectively input thereto.
[0168]
When such a calculation is performed, the following correction value is obtained.
Here, assuming that the PIDs 1, 2, 3, and 4 have appropriate data contents, the sector numbers of the PIDs 1 and 2 are (m−N), respectively. -N). Since the sector numbers of PID3 and PID4 are (m), the correction value is (m−N). In this way, if the PID 1, 2, 3, 4 has appropriate data contents and the sector number is correct, the correction value is the address of the subsequent land track (sector number). Where (m−N) is shown.
[0169]
When the land / groove detection signal indicates a groove track, the PID (1, 2) correction circuits 131 and 132 subtract the value of NOS = N from the sector number of PID 1 and 2. In the PID (3, 4) correction circuits 133 and 134, the sector number values in the PIDs 3 and 4 input to the PID (3 and 4) correction circuits are directly used as correction values.
[0170]
Then, in the PID (1, 2, 3, 4) correction circuits 131 to 134, the PIDs 1, 2, 3, and 4 whose sector number values are corrected as described above are used as the representative PID determiner 141 and the coincident PID number counter. 143 for output. At this time, if an IED error flag and a buffering flag are attached to these corrected PIDs, these flags are also output together.
[0171]
The representative PID determiner 141 determines a representative PID based on each information sequentially input from the PID (1, 2, 3, 4) correction circuits 131 to 134.
For example, as described above, if all of the PIDs 1, 2, 3, and 4 have proper data contents, since all the data contents match, any PID is adopted as the representative PID. However, if a read error occurs, an incorrect correction value is obtained for at least one of PIDs 1, 2, 3, and 4. Therefore, even in such a case, it is required to select a representative PID that is as reliable as possible.
[0172]
For this reason, in this embodiment, the representative PID determiner 141 determines the representative PID by majority vote. That is, if it is assumed that all PIDs 1, 2, 3, and 4 have been input, the data content indicated by these corrected PIDs is selected as the representative PID with the PID data having the largest number of matches. is there.
[0173]
For example, when the number of matching PIDs is the same, the PID with the smaller IED error flag may be adopted as the representative PID. Further, if the number of IED error flags is the same, for example, the representative PID is determined by the priority of PID4 → PID2 → PID3 → PID1.
The reason for the above priority is as follows.
For example, as can be seen by referring to FIG. 5, since PID4 and PID2 are both in Header Field2, the PLL circuit or the like locks more appropriately than PID3 and PID1 in Header Field1 located before this. There is a high possibility of reading. Further, even within the same Header Field, there is a high possibility that the subsequent PID is appropriately read for the same reason than the previous PID. For this reason, in view of the possibility of proper reading, the order is PID4 → PID2 → PID3 → PID1, and this is used as it is as a priority.
Alternatively, if the reliability such as PID2->PID4->PID1-> PID3 is considered to be more reliable than the above-mentioned priority due to the fact such as the stability of actual signal readout, such priority It is good.
Further, for example, in the case of a land track, the priority is PID4 → PID3 → PID2 → PID1, and in the case of a groove track, the respective tracks are traced so that the priority is PID2 → PID1 → PID4 → PID3. It is also conceivable to perform switching according to the situation.
[0174]
As the representative PID is determined in this way, the number of PIDs that match the representative PID is counted by the matching PID number counter 143. This count number is handled as information indicating the reliability of the representative PID as described below. That is, the greater the count value counted by the coincidence PID number counter 143, the higher the reliability of the representative PID. Note that when counting the number of matching PIDs, an IED error flag is not attached, and the number of PIDs matching the representative PID may be used. In this case, the reliability evaluation is more severe.
[0175]
Then, at the storage timing generated by the intra-sector position estimator 113, the representative PID data determined by the representative PID determiner 141 is taken into the representative PID storage 142 and stored therein. Further, the count value counted by the coincidence PID number counter 143 is fetched and stored in the representative PID reliability storage 144 as representative PID reliability information.
As the storage timing generated by the intra-sector position estimator 113, it is preferable to set at least a timing after passing through the header area, for example, a mirror area between the header area and the recordable area.
[0176]
In addition, as a supplementary description, the representative PID determiner 141 may determine the representative PID by a method other than simply taking a majority vote. For example, by using the error check result by the IED error flag more effectively, 2 points are given for a PID that has no IED error flag, and 1 point is given for a PID accompanied by an IED error flag. It is also conceivable that the PID is a representative PID. Accordingly, when obtaining the representative PID reliability, the total number of points given to the PID that matches the representative PID is not counted as the representative PID reliability information, instead of counting the number of matching PIDs. It can also be considered to store.
[0177]
By the way, as shown in FIG. 8, the PID data contents include physical ID number, sector type, and layer number information stored in the sector information in addition to the sector number.
Therefore. In practice, the representative PID determiner 141 according to the present embodiment is configured such that when the representative PID is determined as described above, there is a match between these pieces of information.
That is, for the corrected sector numbers, the number of matches is detected only for the corrected sector numbers stored in the PIDs sequentially input from the PID (1, 2, 3, 4) correction circuits 131 to 134. The sector number having the largest number of matches is determined as the sector number forming the representative PID. Similarly, the sector type and the layer number should match for each PID if the data content is normal. Therefore, the number of matches is detected, and the sector type having the maximum number of matches, and The layer number is determined as information forming the representative PID. In addition, the physical ID number can be used as a determination element for determining the representative PID by detecting whether the physical ID number is correct or incorrect. Then, the representative PID is obtained by reconstructing the data structure of the PID with the representative value for each piece of information in the PID thus determined.
[0178]
The timing chart of FIG. 37 shows the operation timing of the circuit shown in FIG.
FIG. 37 (a) shows a clear signal. This clear signal is shown in FIG. 34 and is output from the intra-sector position estimator 113 to the first to fourth storage units 121 to 124. The clear signal is output at the timing when the clear signal becomes H level. Information stored in the first to fourth storage units 121 to 124 is cleared. The timing when the clear signal becomes H level is, for example, the timing immediately before passing the current sector.
Then, for example, AM detection is performed as shown in FIG. According to this timing, as described above with reference to FIG. 34, the first to fourth storage units 121 to 124 are as shown in FIGS. 37 (c), (d), (e), and (f). Thus, the PID (1, 2, 3, 4), the IED error flag, and the buffering flag are fetched and held. However, in this figure, for PIDs 1, 3 and 4, the error detection result by IED was OK, so the IED error flag to be stored is at the L level. This may be considered as if the IED error flag was not stored.
[0179]
The information stored in the first to fourth storage units 121 to 124 as shown in FIGS. 37 (c) (d) (e) (f) is input to the representative PID determination unit 141. The representative PID determiner 141 determines the representative PID according to a predetermined rule. At the same time, the reliability information of the representative PID is also generated.
[0180]
If the representative PID is determined as described above and the representative PID reliability information is obtained, an H indicating the storage timing at a predetermined timing thereafter, for example, as shown in FIG. Level pulses will be generated. In response to this, the representative PID storage 142 stores the representative PID, and the representative PID reliability storage 144 stores and holds representative PID reliability information.
[0181]
When the representative PID is determined as described above, for example, the following merits are obtained.
For example, even if the error detection result by the IED is OK, there is a possibility that the data content of the PID has an error due to some accidental factor. Such a PID is determined as a representative PID as it is. If the control is executed, the reliability of reproduction is inferior. On the other hand, in the present embodiment, a PID whose error detection result is OK is not uniquely set as a representative PID, but a representative PID is determined after comprehensive determination is performed by the representative PID determiner 141. Therefore, the above inconvenience does not occur.
[0182]
The sector type stored in the PID includes four types of sectors: a start sector, a last sector, a sector immediately before the last sector, or another sector (others) with respect to the position of the current sector in one track. Therefore, since the sector type indicating others is continuous, it is not possible to protect by reading consecutive sectors. For this reason, in the conventional detection method, this sector type is erroneously detected, and there is a possibility that an error occurs in reproduction control.
On the other hand, in the present embodiment, as described above, when determining the representative PID, the sector type information is stored in the sector type information stored in the PID. The possibility of erroneous detection of the type can be made lower.
Regarding the sector type, it may be possible to determine both the representative sector type and the sector type reliability by adopting a configuration in which only the sector type is buffered. As shown above, the sector number in the PID has a relatively large size of 3 bytes, whereas the sector type is 3 bits, so the circuit scale can be reduced accordingly. It is.
[0183]
In the present embodiment, since the PID is corrected, even if the two PIDs in one Header Field that do not need to be subjected to calculation as correction cannot be read out together, The representative PID can be determined depending on the corrected PID assumed to be in the header field. Furthermore, since the representative PID is determined based on the corrected PID, the PID is not discarded unnecessarily, and it is possible to determine the representative PID with higher reliability and accuracy. is there. For example, if the representative PID is determined by majority decision without correction, the matching / mismatching is checked for PID1 and PID2 and for PID3 and PID4. And PID2 must be discarded together, or both PID3 and PID4 must be discarded.
[0184]
8). Playback parameter control
By the way, depending on the circuit configuration of the PID detector 16 shown in FIGS. 34 and 35, the representative PID and the representative PID reliability information indicating the reliability are finally obtained for each sector period.
As the use of the representative PID, for example, as in the case of the conventional adopted PID, the required reproduction control based on the data content can be performed. That is, since the address, the sector type, and the like are identified based on the PID, reproduction control, access control, and the like are executed based on the information. In addition, as the representative PID of the present embodiment, as can be understood from the above description, the data content has higher accuracy, so that higher reliability can be obtained for reproduction control. Be expected.
[0185]
In this embodiment, since information on representative PID reliability is also obtained, it is possible to realize highly reliable reproduction control by monitoring this information, for example, by the system. is there. For example, based on the reliability information of the representative PID, various reproduction parameters are changed according to the reliability. In this way, it is possible to obtain a more appropriate reproduction operation according to the sector synchronization state at that time, and the reproduction operation can be converged so as to increase the reliability of the PID. .
There are various possible playback parameters to be changed here. For example, the focus servo control bias value, tracking servo control offset value, servo hold width, RF signal DC pull-in signal can be realized. Width, PLL time constant variable range, PLL loop filter time constant variable width, PLL pull-in start position, and the like.
[0186]
Also, when using the representative PID reliability information for variable control of the reproduction parameter, it is not simply used, but the total for every certain number of sectors is obtained, and this total value increases. It is also conceivable to variably control the playback parameter.
FIG. 38 shows a circuit configuration for obtaining a total value of representative PID reliability for the purpose of such playback parameter control. In this figure, the same parts as those in FIG. 34 and FIG.
[0187]
The representative PID reliability value held in the representative PID reliability storage 144 also shown in FIG. 35 is input to the PID reliability integrator 191. The PID reliability integrator 191 executes a calculation process for performing a product sum with respect to a representative PID reliability value, for example, for each sector period, according to the product-sum timing generated by the intra-sector position estimator 113. The integral value is reset by an integral value reset signal corresponding to the land / groove change output from the land / groove determiner 108. That is, in this case, the representative PID reliability value is integrated / cleared for each number of sectors corresponding to one track where the land / groove is switched.
Thus, the integrated value of the representative PID reliability obtained by the PID reliability integrator 191 is captured and held by the storage 192 at the storage timing generated by the intra-sector position estimator 113. To be. For example, the storage timing may correspond to the sector period. Then, based on the integrated result of the PID reliability held in the storage 192, the reproduction parameter is controlled so that the PID reliability integrated value becomes as small as possible.
[0188]
From the viewpoint of variable control of the reproduction parameter, it is considered that such control can also be performed based on an error detection result (IED error check) by IED. Therefore, as a modification, FIG. 39 shows an example of a circuit configuration for generating information for reproduction parameter variable control based on the IED error check.
[0189]
In this case, the IED check circuit 107 shown in FIG. 34 is shown, and the IED error flag output from the IED check circuit is sent to the PID read timing controller 106 also shown in FIG. Are input to the AND gate 193 together with the IED check determination timing generated in the above. The AND gate 193 outputs an H level when an IED error flag of an H level is obtained within a period when the IED check determination timing is active and is at an H level.
The IED error counter 194 counts up in response to the H level signal from the AND gate 193 being input to the enable terminal. This count value is reset by the land / groove switching timing generated in accordance with the land / groove change output from the land / groove determiner 108. That is, also in this case, the integration of the number of IED errors is reset for each track.
The IED error count storage 195 loads and holds the current count value in the IED error counter 194 at the storage timing generated by the intra-sector position estimator 113. The storage timing at this time may also be a sector period, for example. Based on the number of IED errors stored in the IED error number storage 195 in this way, the reproduction parameter variable control is executed so that the number of IED errors becomes as small as possible.
[0190]
9. NOS calculation processing
The circuit for determining the representative PID shown in FIG. 35 requires NOS information indicating the number of sectors per track as described above. Therefore, a NOS calculator 146 is provided as the present embodiment.
Further, as shown in FIG. 35, this NOS information is used not only for sector number correction when representative PID is determined, but also for land / groove determination and zone number conversion in normal playback control. Therefore, high reliability is required.
[0191]
Conventionally, in order to obtain NOS information, first, PID is detected, a 3-byte sector number is recognized, and the recognized sector number is compared with the PID-Zone.No conversion table shown in FIG. Then, the zone number (Zone.No) is obtained. That is, the start logical sector number of the zone including the recognized sector number is searched, and the zone number associated with the searched start logical sector number is specified. Subsequently, the NOS value associated with the searched zone number is referenced using the NOS-zone number (Zone.No) conversion table shown in FIG. In this way, NOS information is obtained.
The above-described operation may be performed by the processing of the system controller 13, for example, but is often configured to be realized by hardware.
[0192]
However, in the conventional NOS information acquisition method as described above, since the individual value as the start logical sector No. in the PID-Zone.No conversion table shown in FIG. There was a disadvantage that the scale of the hardware for realizing the Zone.No conversion processing would increase. Further, in both hardware and software processing by the system controller 13, there is a problem that the operation speed is lowered due to a heavy processing load.
[0193]
Therefore, in the present embodiment, the NOS calculator 146 is configured as described below, so that the above-described problems can be solved and NOS information with sufficient and sufficient accuracy can be obtained. Is done.
[0194]
The operation of the NOS calculator 146 in the present embodiment will be briefly described. First, the first NOS calculation value is obtained by calculating the sector numbers of a plurality of PIDs obtained for each sector in the same track. Get to get NOS_1. For example, the value of NOS_1 may be used as it is as the NOS that is the output of the NOS calculator 146. However, in this embodiment, in order to increase the accuracy of the value of NOS, the state before the current time point for this NOS_1 And NOS_2, which is the second calculated NOS value determined based on the state, is obtained.
[0195]
The timing chart of FIG. 40 shows a specific operation example for the above-described NOS calculation.
First, every time information is read from the disk in units of sectors, PIDs 1, 2, 3, and 4 in the header area of the sector are detected. Based on the sector number of the detected PID, NOS_1 is calculated as shown in FIG. In this case, an example in which the value of NOS_1 is obtained in the order of 10 → 15 → 15 → 15 → 13 → 15 for each sector unit is shown. The value of NOS_1 is the number of sectors of the track (zone) including the current sector, but as described above, it is not a value determined as NOS information to be output from the NOS calculator 146.
A circuit configuration for calculating NOS_1 from PID will be described later.
[0196]
Further, in correspondence with the timing at which the calculation of NOS_1 is completed as shown in FIG. 40 (e), an H level pulse indicating the NOS_1 determination timing is generated as shown in FIG. 40 (a). It is like that. Then, with the NOS_1 determination timing as a reference, the timing pulses of NOS_2 calculation timings 1, 2, and 3 are generated at the timings shown in FIGS.
For NOS_1, the previous value (that is, the immediately preceding sector of the current sector) is always held at the timing shown in FIG. The previous NOS_1 holding timing is synchronized with the NOS_2 calculation timing 3 shown in FIG.
[0197]
For NOS_1, it is detected whether or not the values of the current NOS_1 shown in FIG. 40 (e) and the previous NOS_1 shown in FIG. 40 (f) match. When this is the case, the coincidence signal CNC indicating coincidence with the previous time is set to the H level as shown in FIG.
[0198]
When the coincidence signal CNC is at the L level, the value of the NOS protection counter shown in FIG. 40 (h) is reset to “0”. Thus, the count-up is performed at the timing of NOS_2 calculation timing 1.
In this case, the maximum count value RP of the NOS protection counter is set to “2” as shown in FIG. When the count value of the NOS protection counter shown in FIG. 40 (h) reaches “2”, the current NOS_1 value is NOS_2 at the timing of NOS_2 calculation timing 2 as shown in FIG. 40 (j). Loaded as a value.
That is, in the operation shown in this figure, when the time when the current NOS_1 matches the previous NOS_1 is obtained continuously, for example, two or more sectors, the value of NOS_1 is handled as NOS_2. In this way, NOS_2 is determined on the condition that NOS_1 continuously takes the same value, so that the NOS output from the NOS calculator 146 can be given higher accuracy. It has become.
[0199]
Next, the circuit configuration of the NOS calculator 146 for realizing the operation shown in FIG. 40 will be described with reference to FIGS.
FIG. 41 shows a circuit configuration example for calculating NOS_1 at the sector period.
The PID, buffering flag, and IED error flag stored in the first to fourth storage units 121 to 124 shown in FIG. 34 are input to the circuit shown in FIG.
PID1 and PID2 are input to the selector 151. Further, the non-inverted signal of the PID2: buffering flag and the inverted signal of the PID2: IED error flag are input to the OR gate 156. The OR gate 156 outputs the L level only when there is no IED error and the PID2 is normally buffered in the second storage 122, and in other cases, that is, there is an error in buffering for the PID2. When an error has occurred or an IED error has occurred, H level is output.
The selector 151 selects PID1 when the output of the OR gate 156 is at H level, and selects PID2 when the output is at L level. The output of the selector 151 is input to the L level terminal of the selector 152 and the H level terminal of the selector 154.
[0200]
PIDs 3 and 4 are input to the selector 153. Further, the non-inverted signal of PID4: buffering flag and the inverted signal of PID4: IED error flag are input to the OR gate 157.
Therefore, the OR gate 156 outputs the L level only when there is no IED error in the fourth storage 124 and the PID4 is normally buffered, and in other cases, that is, the buffering for the PID4. When an error has occurred or an IED error has occurred, H level is output. The selector 153 selects PID3 when the output of the OR gate 156 is H level, and selects PID4 when the output is L level. The output of the selector 151 is input to the L level terminal of the selector 152 and the H level terminal of the selector 154.
[0201]
The selector 152 and the selector 154 are switched by a land / groove detection signal output from the land / groove determiner 108.
The land / groove detection signal in this case is set to H level when a land is detected, and to L level when a groove is detected. The selector 152 and the selector 154 select and output the PID input to the H level terminal when the land / groove detection signal is H level, and select the PID input to the L level terminal when the land / groove detection signal is L level. Output.
[0202]
If the selector 152 and the selector 154 select the PID as described above and one of the PIDs 1 and 2 is output from the selector 152, the selector 154 outputs one of the PIDs 3 and 4. Will be. Further, if any one of PID3 and 4 is output from the selector 152, the selector 154 outputs one of PID1 and PID2. The set of PIDs output from the selector 152 has a larger sector number than the set of PIDs output from the selector 154.
[0203]
The PIDs output from the selector 152 and the selector 154 are input to the subtracter 155. The subtractor 155 subtracts the PID sector number output from the selector 154 from the PID sector number output from the selector 152. That is, an operation is performed in which the smaller sector number is subtracted from the larger sector number. The sector numbers of the PID 1 and 2 groups and the sector numbers of the PID 3 and 4 groups have a difference corresponding to the number N of sectors in one track, as shown in FIG. Therefore, if the PID sector number values input to the subtracter 155 are both appropriate, the number of sectors in one track is accurately indicated. The output of the subtracter 155 becomes NOS_1.
[0204]
Further, in PID detection within a sector, not all of one PID 1, 2, 3, 4 is stored in the first to fourth storage units 121-124. Further, not all PIDs have an IED error. Therefore, even if such an error state is ignored and an operation according to the timing chart of FIG. 40 is actually obtained, it is difficult to obtain highly reliable NOS_2. Therefore, in obtaining NOS_2, an error flag NOS_1_Err indicating an error state for NOS_1 is actually generated, and an operation according to the state of the error flag NOS_1_Err is executed as described later. It has become so.
[0205]
Therefore, FIG. 42 shows a configuration example of the error flag NOS_1_Err generation circuit.
In the circuit shown in this figure, each buffering flag and IED error flag stored in the first to fourth storage units 121 to 124 are input.
A non-inverted PID1: buffering flag and an inverted PID1: IED error flag are input to the AND gate 161. Further, a non-inverted PID2: buffering flag and an inverted PID2: IED error flag are input to the AND gate 162.
The outputs of the AND gates 161 and 162 are inverted and input to the AND gate 163.
[0206]
Further, a non-inverted PID3: buffering flag and an inverted PID3: IED error flag are input to the AND gate 164, and a non-inverted PID4: buffering flag is input to the AND gate 165. The inverted PID4: IED error flag is input. The outputs of the AND gates 164 and 165 are inverted and input to the AND gate 166.
[0207]
The outputs of the AND gate 163 and the AND gate 166 are output to the OR gate 167. The output of this OR gate is an error flag NOS_1_Err.
According to such a configuration of the logic circuit, the error flag NOS_1_Err = H level indicating an error indicates that both PID1 and PID2 are not buffered or an IED error, or PID3, 4 is a case where both are not buffered or an IED error.
[0208]
Note that the NOS_1_Err generation circuit is not limited to the above configuration, and various modifications can be made. For example, for all of the first to fourth storage units 121 to 124, NOS_1_Err = L level only when the buffering flag is obtained and the IED error does not occur, and otherwise NOS_1_Err = H level can also be regarded as an error state. In this case, the condition that it is not an error state is stricter than the configuration shown in FIG.
It is also conceivable to construct a circuit that sets the error flag NOS_1_Err = H level when the value shown as representative PID reliability obtained in the circuit shown in FIG.
[0209]
FIG. 43A shows a circuit configuration example for obtaining NOS_2. In this circuit, NOS_1 calculated by the circuit shown in FIG. 41 and the error flag NOS_1_Err generated by the circuit shown in FIG. 42 are used. In addition, the NOS_2 calculation timings 1, 2, and 3 shown in FIGS. 40B, 40C, and 40D are also used.
[0210]
Here, prior to the description of FIG. 43A, a circuit example for generating the NOS_2 calculation timings 1, 2, and 3 will be described with reference to FIG.
As shown in FIG. 40 (a), the NOS_1 determination timing is a pulse signal obtained at a predetermined timing corresponding to the time point when NOS_1 corresponding to one sector is output by the circuit shown in FIG. Then, the NOS_2 calculation timing controller 180 performs a counting process (time measurement) starting from the input pulse timing of the NOS_1 determination timing, as shown in FIGS. 40 (b), (c), and (d). Thus, an H level pulse is output as NOS_2 calculation timings 1, 2, and 3.
[0211]
Subsequently, the circuit of FIG. 43A will be described.
In the circuit shown in FIG. 43A, the non-inverted NOS_2 calculation timing 3 (FIG. 40D) and the inverted error flag NOS_1_Err are input to the AND gate 171. Accordingly, the AND gate 171 outputs an H level when the error flag NOS_1_Err is not obtained at the timing of NOS_2 calculation timing 3. The flip-flop 172 is enabled by this H level output.
[0212]
NOS_1 is input to the flip-flop 172, and when the H level is output from the AND gate 171 as described above, the flip-flop 172 is enabled and holds and outputs the value of NOS_1 input at that time. . The output of the flip-flop 172 is the previous value of NOS_1 shown in FIG. 40F, and NOS_1 input to the flip-flop 172 is the current value of NOS_1 shown in FIG. Then, the comparator 173 compares the input and output of the flip-flop 172. When the input (current NOS_1) matches the output (previous NOS_1) of the flip-flop 172, FIG. As shown in 40 (g), an H level coincidence signal CNC is output.
[0213]
The NOS protection counter 176 performs a counting operation as shown in FIG. 40 (h) when a signal is input as follows.
“0” is set to the count input terminal of the NOS protection counter 176. The value “0” set for the count input terminal is loaded when an H level signal rises to the load terminal, and the count value is reset to “0”.
A signal using the coincidence signal CNC and NOS_2 calculation timing 1 is input to the load terminal. That is, the inverted match signal CNC and the non-inverted NOS_2 calculation timing 1 are input to the NAND gate 175. The output of the NAND gate is inverted and input to the load terminal.
By using such an input signal at the load terminal, the coincidence signal CNC is at the L level at the timing when the NOS_2 calculation timing 1 pulse is obtained, as shown in FIG. Thus, the operation of resetting the counter value of the NOS protection counter 176 to “0” is obtained.
[0214]
The AND gate 174 receives four signals: a non-inverted coincidence signal CNC, a non-inverted NOS_2 calculation timing 1, an inverted error flag NOS_1_Err, and an inverted output of the comparator 177. . The comparator 177 compares the count output of the NOS protection counter 176 with the preset maximum count value RP and outputs an H level signal when they match.
When the four signals are input to the AND gate 174 as described above, the coincidence signal CNC is at the H level and the error flag NOS_1_Err is at the L level at the timing when the pulse of the NOS_2 calculation timing 1 is obtained. When the condition that the count output of the NOS protection counter 176 is smaller than the maximum count value RP is satisfied, the H level is output from the AND gate 174 to the enable terminal. Then, the count operation in the NOS protection counter 176 is executed by this H level enable input. That is, the counter is counted up as described in FIG.
[0215]
The count output of the NOS protection counter 176 is compared with the maximum count value RP by the comparator 177 as described above. Here, as shown in FIG. 40 (i), since the maximum count value RP = 2 is set, the comparator 177 is at the H level when the count output is counted up to “2”. This signal is output.
The AND gate 178 takes a logical product of the output of the comparator 177 and the NOS_2 calculation timing 2 and outputs the logical product to the enable terminal of the flip-flop 179.
[0216]
In the flip-flop 179 to which the enable signal is input, the value of NOS_1 output from the flip-flop 72 is held and output at the timing at which the enable signal is input.
The enable signal is output from the AND gate 178 at the timing as described above. Accordingly, when the count value of the NOS protection counter 176 is “2”, the flip-flop 179 performs an operation of outputting the previous value of NOS_1 at the pulse timing of the NOS_2 calculation timing 2. Become. The output of the flip-flop 179 thus obtained is NOS_2 shown in FIG. 40 (j).
[0217]
In the present embodiment, the NOS calculator 146 configured as described above is used to obtain the NOS, but in this configuration, the calculation is performed on the sector numbers of a plurality of PIDs obtained in one sector. To get NOS. Therefore, it is not necessary to use the PID-Zone No. conversion table and the NOS-Zone.No conversion table shown in FIGS. 44 and 45 to obtain NOS.
As a result, the hardware scale can be reduced, and the operation speed can be increased. In addition, since the hardware is reduced in scale, for example, as the actual circuit, the configuration of the NOS calculator 146 can be sufficiently implemented in an LSI or the like. In addition, it is very easy to use the NOS information for the correction of the PID shown in FIG. 35 or for the land / groove determination. Also, when determining which zone the area being reproduced belongs to, it is not necessary to use the NOS-Zone.No conversion table shown in FIG. 44, but the NOS-Zone.No conversion table shown in FIG. It is only necessary to use. As described above, the NOS-Zone.No conversion table of FIG. 44 has a logical start sector number of 3 bytes for each Zone.No. I must. On the other hand, in the NOS-Zone.No conversion table of FIG. 45, the NOS value corresponding to each Zone.No has a bit number that can express a numerical value of about two digits in decimal notation. The processing is very light. Accordingly, this is also advantageous in terms of downsizing the hardware and speeding up the operation.
[0218]
Further, in the configuration of the NOS calculator 146 of the present embodiment, NOS_1 is first calculated based on the PID, and then NOS_2 is obtained by protecting this NOS_1. That is, the continuity of NOS_1 is monitored by the protection counter, and NOS_2 is determined based on the monitoring result.
Further, an error flag NOS_1_Err indicating an error state for NOS_1 is generated, and this error flag NOS_1_Err is also used. That is, in the circuit shown in FIG. 43, when the error flag NOS_1_Err is obtained, the count value is cleared and the count-up is not performed, so that NOS_1 is not reliable. In this case, NOS_2 is not fixed. In other words, when NOS_1 is highly reliable, NOS_2 is determined by monitoring a small number of consecutive sectors, and when NOS_2 is low, NOS_2 is determined by monitoring a larger number of consecutive sectors. It is what.
Thereby, the reliability of NOS (NOS_2) output from the NOS calculator 146 can be increased. Further, in the present embodiment, the PID input to the NOS calculator 146 uses the buffered data with the configuration shown in FIG. 34, so that the reliability of the NOS finally obtained also by this is used. Has been raised.
Note that even if the count maximum value RP is changed according to the reliability information of NOS_1 indicated by the error flag NOS_1_Err or the like, if the reliability of NOS_1 is high, the number of consecutive sectors is monitored. When NOS_2 is determined and NOS_2 is unreliable, it is possible to obtain an operation of determining NOS_2 by monitoring a larger number of consecutive sectors. As the present embodiment, such a configuration that changes the count maximum value RP may be adopted instead of the count operation limitation based on the limitation of the error flag NOS_1_Err described above, or a configuration in which both are used together is also conceivable. Is.
[0219]
The present invention is not limited to the configuration described above, and can be changed as appropriate.
For example, in the above embodiment, the case of reproducing a DVD-RAM is taken as an example. However, the type of disc to be reproduced is not limited to this, and for example, a track format to which the present invention can be applied. As long as it is a disc, it is enough. Also, here, the operation is described as the operation at the time of reproduction. Similarly, at the time of recording, when the control processing needs to be executed in accordance with the position in the predetermined unit information area such as the sector, this operation is performed. The invention can be applied.
[0220]
【The invention's effect】
As described above, according to the present invention, any sector number of PID 1 or 2 (address value of address information belonging to the first address information group) and any sector number of PID 3 or 4 (second address information group) An NOS (number of unit information areas) indicating the number of sectors in one track is obtained based on the calculation result using the address value of the address information to which the track belongs.
In this way, if NOS is obtained based on the calculation, it is not necessary to use a conversion table. As a result, for example, the hardware can be reduced in size and the operation speed for obtaining the NOS can be increased.
[0221]
Further, according to the present invention, first, NOS_1 (temporary area number information) is calculated by performing an operation on one of the sector numbers of PID1 and PID2 and one of the sector numbers of PID3 and PID4. When a predetermined condition such that the same value is obtained over a predetermined number of sectors is satisfied, NOS_2 (determined area number information) is obtained from the value of NOS_1. As a result, for example, the reliability of the NOS information is improved rather than using NOS_1 as it is as the normal NOS information.
If the error flag NOS_1_Err (reliability information) indicating the error state (reliability) for NOS_1 is obtained, and NOS_2 is obtained by the error flag NOS_1_Err, the NOS information is even higher. Reliability can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a disk drive device according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing a configuration example of an optical system in the disk drive device of the present embodiment.
FIG. 3 is an explanatory diagram showing a photodetector and a signal generation method in the disk drive device according to the present embodiment;
FIG. 4 is an explanatory diagram showing a track format for the entire disc as a DVD-RAM.
FIG. 5 is an explanatory diagram conceptually showing a track arrangement within one sector as a DVD-RAM track format.
FIG. 6 is an explanatory diagram conceptually showing a data structure forming one sector as a track format of DVD-RAM.
FIG. 7 is an explanatory diagram showing a data structure forming one sector together with the size of each area as a track format of a DVD-RAM.
FIG. 8 is an explanatory diagram showing the structure of a PID.
FIG. 9 is an explanatory diagram showing a structure of data recorded in a data area in one sector.
FIG. 10 is a timing chart showing various control timing examples based on the intra-sector position estimation result of the present embodiment.
FIG. 11 is a block diagram showing a configuration example for tracking servo control hold based on the intra-sector position estimation result;
FIG. 12 is a block diagram showing a configuration example for RF signal DC acquisition based on the intra-sector position estimation result;
FIG. 13 is a block diagram illustrating a configuration example for data transfer control based on an intra-sector position estimation result;
FIG. 14 is a block diagram showing a configuration example for realizing PLL circuit pull-in control based on an intra-sector position estimation result;
FIG. 15 is a block diagram illustrating a configuration example for realizing transfer control of data to a buffer memory based on an intra-sector position estimation result;
FIG. 16 is a block diagram and a timing chart showing another configuration example for realizing PLL circuit pull-in control based on the intra-sector position estimation result.
FIG. 17 is an explanatory diagram conceptually showing an RF signal DC pull-in operation.
FIG. 18 is a timing chart showing an intra-sector position estimation operation (first example) according to the present embodiment;
FIG. 19 is a block diagram illustrating a configuration example of an intra-sector position estimation counter corresponding to an intra-sector position estimation operation as a first example;
20 is a block diagram showing a configuration example for generating a track hold signal based on a signal obtained by the intra-sector position estimation counter shown in FIG. 19;
FIG. 21 is a block diagram showing a configuration for generating a PID position load signal used by the intra-sector position estimation counter shown in FIG. 19;
FIG. 22 is a timing chart showing an intra-sector position estimation operation (second example) according to the present embodiment;
FIG. 23 is a timing chart showing an intra-sector position estimation operation (third example) according to the present embodiment;
24 is an explanatory diagram for explaining estimation of a PID number based on a signal obtained by the intra-sector position estimation operation shown in FIG. 23. FIG.
FIG. 25 is a timing chart showing an intra-sector position estimation operation (fourth example) according to the present embodiment;
FIG. 26 is a timing chart showing a sector synchronization protection operation (first example) according to the present embodiment;
FIG. 27 is a block diagram illustrating a configuration example of an intra-sector position estimation counter corresponding to the sector synchronization protection operation of the present embodiment;
FIG. 28 is a timing chart showing an operation of PID detection determination.
FIG. 29 is a logic circuit diagram showing a configuration example of a sector synchronization protection counter required for realizing the sector synchronization protection operation of the present embodiment.
FIG. 30 is a timing chart showing a sector synchronization protection operation (second example) according to the present embodiment;
FIG. 31 is an explanatory diagram conceptually showing state transition in a sector synchronization protection operation (second example).
FIG. 32 is a logic circuit diagram showing a configuration example of a sector synchronization protection circuit corresponding to a sector synchronization protection operation (second example).
FIG. 33 is an explanatory diagram showing truth values of the decoder shown in FIG. 32;
FIG. 34 is a block diagram illustrating a circuit configuration example for realizing the PID storing process according to the present embodiment;
FIG. 35 is a block diagram illustrating a circuit configuration example for realizing the PID reliability determination process according to the present embodiment;
FIG. 36 is a timing chart showing the PID storing process of the present embodiment.
FIG. 37 is a timing chart showing PID reliability determination processing according to the present embodiment;
FIG. 38 is a block diagram showing a circuit configuration example for obtaining a total value of representative PID reliability.
FIG. 39 is a block diagram showing a circuit configuration example for realizing reproduction parameter variable control based on IED error check.
FIG. 40 is a timing chart showing an operation in the NOS calculator of the present embodiment.
FIG. 41 is a logic circuit diagram showing a circuit configuration for NOS_1 calculation in the NOS calculator.
FIG. 42 is a logic circuit diagram showing a circuit configuration for generating an error flag NOS_1_Err in the NOS calculator.
FIG. 43 is a logic circuit diagram showing a circuit configuration for NOS_2 calculation in the NOS calculator.
FIG. 44 is an explanatory diagram showing a PID-Zone No. conversion table.
FIG. 45 is an explanatory diagram showing a NOS-Zone.No conversion table;
FIG. 46 is a block diagram illustrating a configuration example for header detection in a conventional example.
47 is an explanatory diagram showing a header detection operation by the circuit having the configuration shown in FIG. 46; FIG.
48 is an explanatory diagram showing a case where erroneous detection is performed as a header detection operation by the circuit having the configuration shown in FIG. 46; FIG.
[Explanation of symbols]
1 optical disk, 2 spindle motor, 3 optical pickup, 3a biaxial mechanism, 4 RF amplifier, 4a HPF, 4b first stage amplifier, 5 servo processor, 5a, 5d servo filter, 5b hold signal output circuit, 6 drive circuit, 7 2 Value conversion circuit, 8 clock recovery circuit, 8a PLL circuit, 9 decode circuit, 10 error correction circuit, 10a buffering controller, 11 buffer memory, 12 data interface, 13 system controller, 14 block for RAM, 15 header detection unit, 16 PID detection unit, 17 land / groove detection unit, 18 timing generation unit, 19 thread mechanism, 20 transfer control circuit, 30 laser diode, 34 objective lens, 37 photodetector, 40 host computer 51 wobble protection circuit, 52 PLL circuit, 54 second PLL circuit, 61, 64 selector, 62 counter, 63, 90 decoder, 65, 66 switch, 78 counter, 79, 80 comparator, 81, 92, 93 flip-flop, 106 PID read controller, 107 IED Check circuit, 110 to 112, first to third PID number estimators, 113 intra-sector position estimator, 114 selector, 121 to 124, first to fourth storage units, 131 to 134 PID (1 to 4) correction circuit, 141 representative PID determiner, 143 coincidence PID number counter, 142 representative PID storage, 144 representative PID reliability storage, 172, 179 flip-flop, 176 NOS protection counter, 180 NOS_2 calculation timing controller

Claims (1)

Information is recorded so that a circular track is formed by a series of unit information areas consisting of a header area and a recordable area following the header area. In the header area, information can be recorded that is present on adjacent tracks. Among the areas, one or more first address information groups having an address value of one recordable area, and one or more second address information groups having an address value of the other recordable area, In the disk drive device capable of recording or reproducing in correspondence with the disk-shaped recording medium recorded in order of the address information, the second address information, the third address information, and the fourth address information,
The address value of the address information belonging to the first address information group composed of the first address information and the second address information read from the disc-shaped recording medium, the third address information, The address value of the address information belonging to the second address information group composed of the fourth address information and the error check result of the first address information group and the second address information group are both Use
If no error has occurred as a result of the error check, the first address estimated value obtained from the first address information to the fourth address information is used as the address information.
As a result of the error check, when an error has occurred and the sector synchronization protection circuit indicates that it is in a synchronized state, the first address information to the fourth address information precede each of the first address information and the fourth address information. Thus, the address mark recorded incidentally is detected and included in the address detection window opened corresponding to each of the first address information to the fourth address information in which the address mark is detected. adopted third address estimate obtained from the address information as the address information,
The error check result, even when an error has occurred, to indicate that the sector synchronization protection circuit is not in the synchronized state, each of the upper Symbol first address information to the fourth address information Follow-up postamble detection signal to be followed , land / groove detection signal to detect in which area of land or groove the recording or reproduction operation is performed , and header detection indicating the head of the sector A second address estimated value obtained by specifying any one of the first address information to the fourth address information by a logical operation based on a signal, as address information,
Alternatively, if an error has occurred as a result of the error check, the first address estimated value and the third address estimated value are compared, and the first address estimated value and the third address estimated value are compared . If the address estimate matches, use this as address information,
A disk drive device comprising: area number information generating means for generating and outputting area number information indicating the number of unit information areas in one track.

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