JP4398856B2 - Electrostatic protective device and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor device for the purpose of electrostatic discharge protection and a semiconductor integrated circuit equipped with the semiconductor device.

  Usually, a semiconductor integrated circuit is provided with a semiconductor device for protecting an internal circuit from an overcurrent caused by electrostatic discharge. This electrostatic protection device is connected to a signal line or a power supply line that connects the pad connected to the external terminal and the internal circuit, and when the potential exceeds a predetermined value, the internal resistance decreases, and the overcurrent is released to the ground line. It plays the role of keeping the internal circuit potential at the normal operating potential.

  Examples of the electrostatic protection device include a GGMOSFET (Grounded-Gate Metal-Oxide-Semiconductor Field Effect Transistor) in which a ground line is connected to a gate electrode. During normal operation, the gate electrode is connected to a ground line or the like, and the internal resistance of the electrostatic protection device is high, so that current flows through the internal circuit. On the other hand, when a surge is applied by electrostatic discharge, collision ionization first occurs at the junction between the drain region and the semiconductor substrate. Next, the holes generated by impact ionization pass through the semiconductor substrate and flow to the ground line connected to the semiconductor substrate. At this time, the potential of the semiconductor substrate rises due to the resistance of the semiconductor substrate. Then, the parasitic bipolar transistor is turned on, and the surge current due to electrostatic discharge can be released in the order of the drain region, the channel region, the source region, and the ground line connected to the source region.

  Here, since the gate electrode of the GGMOSFET is connected to the ground line, 0 V potential is taken. On the other hand, the drain region takes a high potential when a surge is applied. For this reason, an extremely high electric field is locally formed between the gate electrode and the drain region, the lattice temperature rises in the vicinity of the junction between the channel region and the drain region immediately below the gate electrode, and thermal breakdown is likely to occur. .

In order to alleviate the concentration of the electric field, it has been proposed to form the drain region with a large area (see, for example, Patent Document 1). However, this method has a problem that the element area increases.
JP 2004-71799 A

  In view of the above circumstances, the present invention provides a semiconductor device and a semiconductor integrated circuit that have improved resistance to thermal breakdown during surge application due to electrostatic discharge without increasing the element area.

An electrostatic protection device of the present invention includes a semiconductor substrate to which a ground line is connected, a gate insulating film formed on the semiconductor substrate, a resistance gate portion formed on the gate insulating film, a gate insulating film, and a resistance gate The semiconductor substrate surface that is in contact with the other side of the gate side wall and the source region that is formed on the gate side wall made of a conductor, the surface of the semiconductor substrate that contacts one of the gate side walls, and the ground line connected And a drain region to which a signal line or a power supply line is connected.

In addition, an electrostatic protection device of the present invention includes a semiconductor substrate, a resistance region formed on the surface of the semiconductor substrate, a gate insulating film on the resistance region, and a channel portion including a semiconductor layer formed on the gate insulating film. The gate insulating film and the channel portion are sandwiched in the gate length direction, the gate side wall made of a conductor, the source region formed on the surface of the semiconductor substrate in contact with one of the gate side walls and the ground line connected to the other side of the gate side wall And a drain region formed on the surface of the semiconductor substrate in contact with the signal line and connected to a signal line or a power line.

  According to the present invention, it is possible to provide a semiconductor device and a semiconductor integrated circuit that have improved resistance to thermal breakdown during surge application due to electrostatic discharge without increasing the element area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

  In each embodiment, an electron conduction type semiconductor device using an oxide for a gate insulating film will be described. Needless to say, the present invention can also be applied to a hole conduction type semiconductor device. Further, the gate insulating film is not limited to an oxide, and other insulators such as nitride and fluoride may be used.

  In addition, a semiconductor integrated circuit such as a memory, a logic circuit and the like on which the semiconductor device of the present invention is mounted and a system LSI in which these are mixedly mounted on the same chip are also within the scope of the present invention.

(First embodiment)
An example of the semiconductor device according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a schematic cross-sectional view in the gate length direction of the bulk type semiconductor device according to the first embodiment.

  As shown in FIG. 1, a channel region is formed on the surface of a semiconductor substrate 1 made of p-type silicon to which a ground line is connected. On the channel region, a gate insulating film 2 and a resistance gate portion 3 having an n-type dopant are sequentially formed. On the semiconductor substrate 1, a pair of gate side walls 4a and 4b having a high concentration n-type dopant are formed so as to sandwich the gate insulating film 2 and the resistance gate portion 3 in the gate length direction. On the surface of the semiconductor substrate 1 in contact with the gate side walls 4a and 4b, n-type source / drain regions 5a and 5b are formed so as to sandwich the channel region in the gate length direction. The source / drain regions 5a and 5b are shallow regions formed from the surface of the semiconductor substrate 1 and having a low impurity concentration, and deep regions having a high impurity concentration and formed deep from the surface of the semiconductor substrate 1 with the shallow region sandwiched in the gate length direction. And having. A ground line is connected to the source region 5a, and a signal line or a power supply line is connected to the drain region 5b. The signal line or the power line is a wiring between the pad (pad) and the internal circuit, and the ground line is a wiring between the ground and the internal circuit. The bulk semiconductor device according to the first embodiment has a parallel relationship with the internal circuit by the signal line or the power line and the ground line.

  Here, the resistance gate section 3 has a higher resistance than at least the source / drain regions 5a and 5b, and is not energized during normal operation. Specifically, the impedance of the resistance gate unit 3 is higher than the input impedance of the internal circuit and is not more than 100 times the impedance of the channel region. The former suppresses energization during normal operation, and the latter makes the electric field generated in the channel region uniform during surge application. The resistance gate portion 3 does not need to be connected to the ground line. The gate sidewalls 4a and 4b are characterized by being made of a conductor, that is, a substance having a high electrical conductivity (see Iwanami Rikagaku Dictionary 5th edition).

  The operation mechanism of the bulk type semiconductor device according to the first embodiment will be described.

  During normal operation (except when surge is applied by electrostatic discharge), the resistance gate portion 3, the gate insulating film 2, and the channel region are in an electrically high resistance state. Therefore, the current does not flow through the bulk semiconductor device according to the first embodiment but flows through the internal circuit.

  On the other hand, when a surge is applied by electrostatic discharge, collision ionization first occurs at the junction between the drain region 5 b and the semiconductor substrate 1. At this time, the drain region 5b and the gate sidewall 4b on the drain region are at a high potential. On the other hand, the source region 5a and the gate sidewall 4a on the source region take 0V. Therefore, the electric field is formed in a wide range between the drain region 5b and the gate sidewall 4b on the drain region, and the source region 5a and the gate sidewall 4a on the source region.

  Thereafter, holes generated by impact ionization pass through the semiconductor substrate 1 and flow to a ground line connected to the semiconductor substrate 1. At this time, the potential of the semiconductor substrate 1 rises due to the resistance of the semiconductor substrate 1 itself. Then, the parasitic bipolar transistor is turned on, and the surge current due to electrostatic discharge can be released in the order of the drain region 5b, the channel region, the source region 5a, and the ground line connected to the source region.

  According to the first embodiment, since the concentration of a high electric field can be relaxed when a surge is applied, thermal breakdown can be reduced.

  FIG. 2 is a schematic cross-sectional view in the gate length direction of the SOI (Silicon On Insulator) type semiconductor device according to the first embodiment.

  As shown in FIG. 2, as the semiconductor substrate, an SOI substrate having a buried oxide film (BOX: Buried OXide) 6 in the semiconductor substrate under the source region, the drain region and the gate insulating film is used. It is the same.

  When the first embodiment is applied to an SOI type semiconductor device, the effect can be further exhibited. This is because the SOI type semiconductor substrate has a thermal conductivity of the buried oxide film of about 1/10 that of the semiconductor substrate, and the problem of thermal breakdown becomes more prominent.

  For the bulk type and SOI type examples according to the first embodiment and the comparative examples corresponding thereto, simulations were performed for temperature rise and snapback characteristics during surge application. Both simulations are in accordance with the test standard HBM (Human Body Mdel) JESD22-A114-B.

  The simulation conditions are described below.

Here, as shown in FIG. 2, L is the length of the resistance gate portion 3, W is the width of the resistance gate portion 3, t _OX is the thickness of the gate insulating film 2, and x _jEXT is the source / drain regions 5a and 5b. , X _jXN is the deep region depth in the source / drain regions 5a and 5b, and N _SUB is the impurity concentration in the channel region. Further, regarding the buried oxide film 6, T _SOI denotes the thickness of the semiconductor layer on the buried oxide film 6, and T _BOX denotes the film thickness of the buried oxide film 6. The simulation conditions were L = 0.45 μm, W = 500 μm, t _OX = 5 nm, x _jEXT = 50 nm, x _jXN = 175 nm, N _SUB = 5 × 10 ¹⁷ cm ⁻³ , T _SOI = 10 nm, and T _BOX = 200 nm. .

In the bulk type embodiment, a silicon substrate is used as the semiconductor substrate 1, a silicon oxide film is used as the gate insulating film 2, an n-type impurity region (impurity concentration: 1E15 cm ⁻³ ) is used as the resistance gate portion 3, and the gate sidewall 4a. 4b, n-type high concentration impurity regions (impurity concentration: 1E20 cm ⁻³ ), and source / drain regions 5a and 5b, shallow regions (impurity concentration: 6E19 cm ⁻³ ) and deep regions (impurity concentration: 1E20 cm ⁻³ ) An n-type high-concentration impurity region having n was used.

The bulk type comparative example was the same as the bulk type example except that an n-type high concentration impurity region (impurity concentration: 10E20 cm ⁻³ ) was used as the resistance gate portion 3.

  The SOI type examples and comparative examples also have the same configuration as the bulk type except that the buried oxide film 6 is used.

  FIG. 3 is a diagram illustrating a simulation result of a temperature rise of the bulk type and SOI type semiconductor device according to the first embodiment.

  As shown in FIG. 3, the bulk type example had a lower temperature rise than the bulk type comparative example, and the SOI type example had a lower temperature rise than the SOI type comparative example. Furthermore, for the SOI type, the effect of suppressing the temperature rise was remarkable.

  In addition, it is thought that the remarkable difference was not seen about the bulk type because heat diffusion to the semiconductor substrate 1 is easy in the bulk type. If the surge voltage is further increased from the test standard described above, it can be predicted that the effect of the temperature rise will be significant.

  FIG. 4 is a diagram illustrating a simulation result of snapback characteristics of the bulk type and SOI type semiconductor devices according to the first embodiment.

  As shown in FIG. 4, the bulk type and SOI type examples and comparative examples showed almost equivalent results.

  When applying a surge, the internal resistance of the electrostatic protection device decreases and the potential decreases after the potential of the drain region becomes equal to or higher than a predetermined value. The snapback characteristic refers to the current-voltage characteristic at this time, and is excellent as the current after exceeding a predetermined potential flows through a low voltage range. This is because a surge current can be quickly released as a large current can flow at a low voltage.

  A semiconductor device manufacturing method according to the first embodiment will be described with reference to FIGS. For convenience, the SOI type semiconductor device shown in FIG. 2 will be described.

  5 to 12 are cross-sectional schematic views in the gate length direction showing the first to eighth steps of the method for manufacturing the SOI type semiconductor device according to the first embodiment, respectively.

  As shown in FIG. 5, in the first step, first, an SOI substrate is manufactured using a known method such as oxygen ion implantation, substrate bonding, and epitaxial growth. Next, a p-type dopant is introduced into the semiconductor layer on the buried insulating film by ion implantation.

  As shown in FIG. 6, in the second step, first, the insulating film 12 is formed on the surface of the semiconductor substrate 1 by using thermal oxidation. Next, the polycrystalline silicon layer 13 is deposited on the insulating film 12 by using a known film forming method such as CVD (Chemical Vapor Deposition), sputtering, MBE (Molecular Beam Epitaxy). Next, an n-type dopant is introduced into the polycrystalline silicon layer 13 using ion implantation such as POCl3 gas.

  As shown in FIG. 7, in the third step, the polycrystalline silicon layer 13 and the insulating film 12 are processed using anisotropic etching such as RIE (Reactive Ion Etching), and the resistance gate portion 3 and the gate insulating film. 2 is formed.

  As shown in FIG. 8, in the fourth step, an n-type dopant is introduced into the semiconductor substrate 1 at a low concentration using ion implantation of POCl3 gas or the like to form a shallow region of the source / drain regions 5a and 5b.

  As shown in FIG. 9, in the fifth step, first, a polycrystalline silicon layer 14 is deposited using a known film forming method. Next, an n-type dopant is introduced into the polycrystalline silicon layer 14 using ion implantation such as POCl3 gas.

  As shown in FIG. 10, in the sixth step, the polycrystalline silicon layer 14 is processed using anisotropic etching such as RIE (Reactive Ion Etching) to form gate sidewalls 4a and 4b.

  As shown in FIG. 11, in the seventh step, an n-type dopant is introduced into the semiconductor substrate 1 at a high concentration using ion implantation of POCl3 gas or the like to form deep regions of the source / drain regions 5a and 5b.

  As shown in FIG. 12, in the eighth step, first, a silicon oxide layer 18 is deposited using a known film forming method. Next, the W electrode 19 connected to each of the source / drain regions 5a and 5b is buried using RIE.

  Through the above steps, the SOI type semiconductor device shown in FIG. 2 is manufactured. In addition, about the manufacturing method of the other semiconductor device which concerns on 1st and 2nd embodiment, with reference to the manufacturing method shown here, it manufactures suitably.

  The material of the semiconductor device according to the first embodiment will be described.

  The semiconductor substrate 1 uses Si, SiGe, Ge, strained Si, or the like.

  For the channel region, Si, SiGe, Ge, strained Si, SiC, or other channel region materials are used. An n-type dopant such as P, As, or Sb or a p-type dopant such as B is added as appropriate, and it is preferable that the p-type MOSFET be an n-type or an n-type MOSFET be a p-type.

Examples of the gate insulating film 2 include a silicon oxide film, a high dielectric insulating film (an insulating film material having a higher dielectric constant than the silicon oxide film), or a mixed material thereof. Examples of the high dielectric insulating film include Si ₃ N ₄ , Al ₂ O ₃ , Ta ₂ O ₅ , in addition to metal silicates (material obtained by adding metal ions to silicon oxide) such as Zr silicate and Hf silicate. _{TiO 2, La 2 O 5,} CeO 2, ZrO 2, HfO 2, SrTiO 3, Pr 2 O 3 and the like.

  The resistance gate unit 3 uses a semiconductor compound such as polycrystalline silicon (poly-Si) or SiGe. From the viewpoint of consistency in the manufacturing process, a semiconductor compound having a dopant having a conductivity type different from that of the channel region (the same conductivity type as that of the source / drain region when a high-concentration impurity region is used in the source / drain region), particularly a channel It is preferable to use polycrystalline silicon (poly-Si) having a dopant having a conductivity type different from that of the region. At this time, the impurity concentration of the dopant is preferably 1E15 cm −3 or more and 1E18 cm −3 or less.

  The gate side walls 4a and 4b are made of a conductor. For example, a high-concentration impurity region having a conductivity type different from that of the channel region (eg, 1E19 cm −3 or more), metal, metal silicide, or metal nitride is used. In particular, from the viewpoint of the simplicity of the manufacturing method, it is preferable to be made of a metal such as Ni, Co, Ti, W, Cu, NiSi, TiSi2, CoSi2, WSi2, or TiN, a metal silicide, or a metal nitride.

  The source / drain regions 5a and 5b use high-concentration impurity regions or metal silicide having a conductivity type different from that of the channel region. Metal silicides include metal silicides such as V, Cr, Mn, Y, Mo, Ru, Rh, Hf, Ta, W, Ir, Co, Ti, Pt, Pd, Zr, Gd, Dy, Ho, and Er. Can be mentioned.

  Note that materials of the semiconductor device of the embodiment described below are appropriately selected with reference to these materials described in the first embodiment.

(Second Embodiment)
An example of a semiconductor device according to the second embodiment will be described with reference to FIGS.

  FIG. 13 is a schematic cross-sectional view in the gate length direction of the bulk type semiconductor device according to the second embodiment.

  As shown in FIG. 13, a resistance region having an n-type dopant is formed on the surface of the semiconductor substrate 1. On the resistance region, the gate insulating film 2 and the channel portion 7 are sequentially formed. On the semiconductor substrate 1, a pair of gate sidewalls 4a and 4b having a high concentration n-type dopant are formed so as to sandwich the gate insulating film 2 and the channel portion 7 in the gate length direction. On the surface of the semiconductor substrate 1 in contact with the gate side walls 4a and 4b, n-type source / drain regions 5a and 5b are formed so as to sandwich the resistance region in the gate length direction. The source / drain regions 5a and 5b are shallow regions formed from the surface of the semiconductor substrate 1 and having a low impurity concentration, and deep regions having a high impurity concentration and formed deep from the surface of the semiconductor substrate 1 with the shallow region sandwiched in the gate length direction. And having. A ground line is connected to the source region 5a, and a signal line or a power supply line is connected to the drain region 5b. The signal line or the power supply line is a wiring between the pad and the internal circuit, and the ground line is a wiring between the ground and the internal circuit. The bulk type semiconductor device according to the second embodiment is in parallel with the internal circuit by the signal line or the power line and the ground line.

  Here, the resistance region has a higher resistance than at least the source / drain regions 5a and 5b, and is not energized during normal operation. Specifically, the impedance of the resistance region is higher than the input impedance of the internal circuit and is not more than 100 times the impedance of the channel portion 7. The former suppresses energization during normal operation, and the latter makes the electric field generated in the channel portion 7 uniform during surge application. The gate side walls 4a and 4b are made of a conductor.

  An operation mechanism of the bulk type semiconductor device according to the second embodiment will be described.

  During normal operation, the channel portion 7, the gate insulating film 2, and the resistance region are in an electrically high resistance state. Therefore, the current does not flow through the bulk semiconductor device according to the second embodiment but flows through the internal circuit.

  On the other hand, when a surge is applied by electrostatic discharge, collision ionization first occurs at the junction between the gate side wall 4b on the drain region and the channel portion 7. At this time, the drain region 5b and the gate sidewall 4b on the drain region are at a high potential. On the other hand, the source region 5a and the gate sidewall 4a on the source region take 0V. Therefore, the electric field is formed in a wide range between the drain region 5b and the gate sidewall 4b on the drain region, and the source region 5a and the gate sidewall 4a on the source region.

  Thereafter, holes generated by impact ionization are accumulated in the channel portion 7. At this time, the potential of the channel portion 7 rises. Then, the parasitic bipolar transistor is turned on, the drain region 5b, the gate sidewall 4b on the drain region, the channel portion 7, the gate sidewall 4a on the source region, the source region 5a, and the ground line connected to the source region in this order. Surge current due to electrostatic discharge can be released.

  According to the second embodiment, the concentration of a high electric field can be alleviated during surge application due to electrostatic discharge, so that thermal breakdown can be reduced. Further, according to the second embodiment, since the channel portion 7 having a large cross-sectional area in the gate width direction becomes a current path, a high current value can be taken and the snapback characteristics can be improved. This is because, in a semiconductor integrated circuit, generally, the restriction on the height of the channel portion 7 is loose with respect to the channel region in the semiconductor substrate 1.

  FIG. 14 is a schematic cross-sectional view in the gate length direction of the SOI semiconductor device according to the second embodiment.

  As shown in FIG. 14, as the semiconductor substrate, an SOI substrate having a buried oxide film (BOX: Buried OXide) 6 in the semiconductor substrate under the source region, the drain region, and the gate insulating film is used. It is the same.

When the second embodiment is applied to an SOI type semiconductor device, the effect can be further exhibited. This is because, firstly, the SOI type semiconductor substrate has a low thermal conductivity, and the problem of thermal breakdown becomes more remarkable. Secondly, in the SOI type semiconductor device according to the second embodiment, since the channel portion 7 can be formed thicker than the semiconductor layer, the current value can be easily increased. For example, the layer thickness T _SOI of the semiconductor layer on the buried oxide film 6 is in the range of 5 nm to 0.1 μm, while the height of the channel portion 7 is in the range of 0.1 μm to 1.0 μm.

  As described above, in the SOI type semiconductor device according to the first embodiment, the semiconductor layer on the buried insulating film 6 serves as a current path. However, in general, other semiconductor devices on the same substrate cannot increase the thickness of the semiconductor layer on the buried insulating film 6 because of a demand for suppressing the short channel effect. For this reason, assuming that the manufacturing process is shared between the electrostatic protection device and another semiconductor device, the SOI semiconductor device according to the first embodiment has a limit in the current value that can be taken.

  For the examples of the bulk type and the SOI type according to the second embodiment, the temperature rise and the snapback characteristic at the time of surge application are simulated as described above, and the bulk type and the SOI type according to the first embodiment are respectively And compared with the examples.

  The simulation conditions are the same as those in the first embodiment except that an n-type impurity region (impurity concentration: 1E15 cm−3) is used as the resistance region and a p-type impurity region (impurity concentration: 5E17 cm−3) is used as the channel portion 7. And the same.

  FIG. 15 is a diagram showing a simulation result of temperature rise of the bulk type and SOI type semiconductor device according to the second embodiment.

  As shown in FIG. 15, in both the bulk type and the SOI type, the example of the second embodiment showed almost the same result as the example of the first embodiment.

  FIG. 16 is a diagram illustrating a simulation result of snapback characteristics of the bulk type and SOI type semiconductor devices according to the second embodiment.

  As shown in FIG. 16, in the example of the second embodiment, it can be understood that the current after exceeding a predetermined potential flows in a lower voltage range as compared with the first embodiment. . Therefore, the example of the second embodiment is superior in snapback characteristics as compared to the first embodiment.

  The material of the semiconductor device according to the second embodiment will be described.

  The channel portion 7 uses a semiconductor compound having Si, SiGe, Ge, strained Si, SiC, or other channel region material. An n-type dopant such as P, As, or Sb or a p-type dopant such as B is added as appropriate, and it is preferable that the p-type MOSFET be an n-type or an n-type MOSFET be a p-type.

  The resistance region has a dopant having a conductivity type different from that of the channel portion 7. At this time, the impurity concentration of the dopant is preferably 1E15 cm −3 or more and 1E18 cm −3 or less.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

FIG. 3 is a schematic cross-sectional view in the gate length direction of the bulk type semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view in the gate length direction of the SOI semiconductor device according to the first embodiment. The figure which shows the simulation result of the temperature rise of the bulk type and SOI type semiconductor device which concerns on 1st Embodiment. The figure which shows the simulation result of the snapback characteristic of the bulk type and SOI type semiconductor device which concerns on 1st Embodiment. FIG. 3 is a schematic cross-sectional view in the gate length direction showing the first step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. 6 is a schematic cross-sectional view in the gate length direction showing a second step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. FIG. 6 is a schematic cross-sectional view in the gate length direction showing a third step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. 9 is a schematic cross-sectional view in the gate length direction showing a fourth step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. 10 is a schematic cross-sectional view in the gate length direction showing a fifth step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. 9 is a schematic cross-sectional view in the gate length direction showing a sixth step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. 9 is a schematic cross-sectional view in the gate length direction showing a seventh step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. FIG. 10 is a schematic cross-sectional view in the gate length direction showing an eighth step of the method for manufacturing the SOI type semiconductor device according to the first embodiment. The cross-sectional schematic diagram of the gate length direction of the bulk type semiconductor device which concerns on 2nd Embodiment. FIG. 6 is a schematic cross-sectional view in the gate length direction of an SOI type semiconductor device according to a second embodiment. The figure which shows the simulation result of the temperature rise of the bulk type and SOI type semiconductor device which concerns on 2nd Embodiment. The figure which shows the simulation result of the snapback characteristic of the bulk type and SOI type semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Resistive gate part 4a Gate side wall (source side)
4b Gate side wall (drain side)
5a Source region 5b Drain region 6 Buried oxide film 7 Channel portion 12 Gate insulating film precursor 13 Polycrystalline silicon (resistance gate portion precursor)
14 Polycrystalline silicon (gate sidewall precursor)
18 Silicon oxide layer 19 W electrode

Claims (7)

A semiconductor substrate to which a ground wire is connected;
A gate insulating film formed on the semiconductor substrate;
A resistance gate portion formed on the gate insulating film;
Sandwiching the gate insulating film and the resistance gate portion in the gate length direction, a gate sidewall made of a conductor, and
A source region formed on the surface of the semiconductor substrate in contact with one of the gate sidewalls and connected to a ground line;
A drain region formed on the surface of the semiconductor substrate in contact with the other side of the gate sidewall and connected to a signal line or a power line;
An electrostatic protection device comprising: The electrostatic protection device according to claim 1, wherein the resistance gate portion is made of a semiconductor compound having a dopant having a conductivity type different from that of a channel region sandwiched between the source region and the drain region. A semiconductor substrate;
A resistance region formed on the surface of the semiconductor substrate;
A gate insulating film on the resistance region;
A channel portion made of a semiconductor layer formed on the gate insulating film;
Sandwiching the gate insulating film and the channel portion in the gate length direction, a gate side wall made of a conductor, and
A source region formed on the surface of the semiconductor substrate in contact with one of the gate sidewalls and connected to a ground line;
A drain region formed on the surface of the semiconductor substrate in contact with the other side of the gate sidewall, and connected to a signal line or a power line;
An electrostatic protection device comprising: The electrostatic protection device according to claim 3, wherein the resistance region includes a dopant having a conductivity type different from that of the channel portion. 5. The electrostatic protection device according to claim 1, wherein the gate side wall is made of metal, metal silicide, or metal nitride. The electrostatic protection device according to claim 1, further comprising an insulating layer in the semiconductor substrate under the source region, the drain region, and the gate insulating film. The signal line or the power line is a wiring between the pad and one end of the internal circuit,
7. The semiconductor integrated circuit equipped with the electrostatic protection device according to claim 1, wherein the ground line is a wiring between a ground and the other end of the internal circuit.

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