JP4386852B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing technique, and more particularly to a signal processing apparatus including a master computer and a slave computer.

  In recent years, with the trend toward broadband communication lines, there is an increasing demand for high-speed data communication. This high speed is required not only for wired data communication but also for wireless data communication, and development is progressing in various communication methods such as wireless LAN, CDMA, GPRS and the like.

  FIG. 1 shows a configuration of a conventional signal processing apparatus. In the conventional signal processing apparatus 1, the DSP 10 controls the operation timing of the first coprocessor 12, the second coprocessor 16, the third coprocessor 20, the memory 22, the DMAC 30, and the clock control circuit 40. Each component in the signal processing device 1 is connected by a bus 2. Note that the CPU may control the operation timing of each lecturer instead of the DSP 10. Memory 14 is used by the first coprocessor 12 and memory 18 is used by the second coprocessor 16. The DMAC 30 transfers data between the first coprocessor 12 and the second coprocessor 16 without going through the DSP 10. For example, when the calculation result processed by the first coprocessor 12 is used by the second coprocessor 16, the DMAC 30 directly transfers the processing result of the first coprocessor 12 to the second coprocessor 16. The third coprocessor 20 is a reconfigurable circuit whose function can be dynamically changed, and constitutes an intended circuit by being supplied with predetermined data from the DSP 10. The memory 22 is composed of a RAM or the like. The clock control circuit 40 has an on / off function of supplying a clock to each component in the signal processing device 1.

  FIG. 2 shows a flowchart of signal processing by a conventional signal processing apparatus. FIG. 2 shows a processing flow when the signal processing result in the first coprocessor 12 is transferred to the second coprocessor 16 for processing. First, the DSP 10 sends a signal processing start instruction to the first coprocessor 12 (S1). The first coprocessor 12 receives the processing start instruction, executes signal processing (S2), and sends a signal processing end notification to the DSP 10 (S3).

The DSP 10 sends a data transfer start instruction to the DMAC 30 (S4). In response to the transfer start instruction, the DMAC 30 transfers the processing result of the first coprocessor 12 to the second coprocessor 16 (S5), and sends a transfer processing end notification to the DSP 10 (S6). Subsequently, the DSP 10 sends a signal processing start instruction to the second coprocessor 16 (S7). The second coprocessor 16 receives the processing start instruction, executes signal processing (S8), and sends a signal processing notification to the DSP 10 (S9).
JP-A-7-271413

  As shown in FIG. 2, in the conventional signal processing apparatus 1, the DSP 10 sends a command to each of the first coprocessor 12, the DMAC 30, and the second coprocessor 16, and receives a processing end notification from each of them. . In order to execute such schedule management, in the conventional signal processing apparatus 1, the processing load is concentrated on the DSP 10, and the processing performance of the DSP 10 is lowered. In addition, since interrupt signals are frequently input to the DSP 10, the original processing of the DSP is interrupted. Further, since the bus 2 whose main purpose is transmission and reception of signal processing data is occupied by the control signal, the data transfer efficiency of the bus 2 is lowered, and the processing efficiency of the entire signal processing device is lowered.

  In addition, the processing performance of the DSP 10 may decrease, and the third coprocessor 20 that can dynamically reconfigure the circuit may be limited in its circuit configuration speed. The circuit reconfiguration of the third coprocessor 20 is preferably performed dynamically in real time, and it is expected that the real time processing in the signal processing device 1 will be impaired due to a decrease in the circuit configuration speed.

  In addition, each coprocessor and the DMAC 30 can enter a sleep state by stopping the clock supply by the clock control circuit 40, thereby realizing low power consumption. However, since the operation of the clock control circuit 40 is controlled by the DSP 10, a situation in which fine power management by the clock control circuit 40 becomes difficult due to a decrease in processing performance of the DSP 10 occurs. In particular, when the signal processing device 1 is incorporated in a battery-driven portable terminal device, it is ideal to conserve the battery as much as possible. Can be a serious problem.

  The present invention has been made in view of such a situation, and an object thereof is to provide a signal processing device capable of reducing the processing load of a master processor such as a DSP or a CPU.

  In order to solve the above problems, a signal processing apparatus according to an aspect of the present invention includes a master processor that mainly executes various processes in the apparatus, a slave processor that executes a specific unit process according to an execution start instruction, A schedule management circuit that issues an execution start instruction instead of the master processor. The schedule management circuit detects the arrival of the start time for each unit process, and outputs an execution start instruction to the slave processor that should execute the unit process.

  According to this aspect, a schedule management function by a master processor such as a DSP or a CPU can be left to a schedule management circuit provided as a separate hardware component. As a result, the processing load on the master processor can be reduced, and the processing efficiency of the entire signal processing apparatus can be improved.

  The schedule management circuit includes a register that records a start time for each unit process, a timing circuit having a time counter, and the start time of the unit process according to the start time recorded in the register and the count value of the time counter. An output circuit that detects arrival and outputs an execution start instruction may be provided. The timekeeping counter functions as a timer, and the output circuit outputs an execution start instruction based on information from the timing circuit, so that the time management is converged by the schedule management circuit and the processing load on the master processor is reduced. can do.

  The timing circuit may record information for designating whether or not to issue an end notification signal for each unit process in the register. At this time, the output circuit detects the arrival of the end time for each unit process according to the count value of the time counter, and when the end time of the unit process designated to issue the end notification signal has arrived, the master processor An end notification signal may be issued. According to this aspect, the end notification signal for the master processor is issued only for those designated to be issued. Therefore, the frequency with which the interrupt signal is supplied to the master processor can be reduced, and the processing load on the master processor can be reduced.

  When the master processor executes communication control processing, the timing circuit has a plurality of time clock counters, and at least one of the time clock counters outputs a count value in accordance with the communication operation timing by the communication control processing. May be. Since the output circuit selects the output from the counter suitable for signal processing, it is not necessary to modify the schedule information that defines the operation timing of the slave processor, so that schedule management can be easily realized.

  The timing circuit may further include an adjustment circuit that adjusts the count value of the timekeeping counter in accordance with the communication operation timing in the communication control process of the master processor. Thereby, the time counter can output a count value in accordance with the communication operation timing.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the signal processing apparatus which reduces the processing load of master processors, such as DSP and CPU, can be provided.

  Before describing the present invention in detail, an outline will be described. In the signal processing apparatus according to the embodiment of the present invention, in addition to a master processor such as a DSP or a CPU that mainly executes various processes in the apparatus, the operation of a configuration such as a coprocessor or a DMAC included in the apparatus is time-managed. A schedule management circuit is provided. The schedule management circuit receives schedule information defining the operation schedule of each component in the apparatus from the master processor, and performs time management of the operation of each component based on the schedule information.

  FIG. 3 shows the configuration of the signal processing apparatus according to the embodiment of the present invention. The signal processing apparatus 100 according to the embodiment includes a DSP (Digital Signal Processor) 10, a first coprocessor 12, a second coprocessor 16, a third coprocessor 20, a DMAC (Direct Memory Access Controller) 30, a clock control circuit 40, and A schedule management circuit 50 is provided. In the signal processing apparatus 100, the DSP 10 functions as a master processor that mainly executes various processes in the apparatus. The master processor is a processor incorporating, for example, microcode, and may include a CPU (Central Processing Unit) (not shown). Below, DSP10 is demonstrated as an example of a master processor. When the DSP 10 and the CPU are provided in the signal processing apparatus 100, there are two master processors. The components in the signal processing apparatus 100 are connected to each other by a bus 2.

  The first coprocessor 12, the second coprocessor 16, the third coprocessor 20, the DMAC 30, and the clock control circuit 40 function as slave processors that execute specific unit processing in response to an execution start instruction. The slave processor is a processing circuit other than the master processor and the schedule management circuit 50, and does not execute the process independently, but executes a specific unit process according to the supplied execution start instruction. When the signal processing device 100 is used for a specific application such as a communication control device, the unit processing of the slave processor is a known processing, and the execution time can be calculated in advance. The first coprocessor 12 and the second coprocessor 16 are configured as coprocessors specialized in processing contents, and execute specific unit processing in response to an execution start instruction.

  The signal processing device 100 may be incorporated in a wireless communication terminal device such as a mobile phone to enable processing of communication signals. At this time, the signal processing device 100 functions as a wireless communication control device. For example, the first coprocessor 12 is configured as an arithmetic accelerator specialized for digital filter processing such as FIR. The second coprocessor 16 is configured as an arithmetic accelerator specialized for decoding processing of error correction codes. When the signal processing device 100 functions as a wireless communication control device, the received signal received from the outside is subjected to filtering processing by the first coprocessor 12 and subsequently the error correction code decoding processing is performed by the second coprocessor 16. Done.

  The processing result filtered by the first coprocessor 12 is temporarily stored in the memory 14. The DMAC 30 reads the processing result temporarily stored in the memory 14 and transfers it to the second coprocessor 16. The second coprocessor 16 decodes the error correction code included in the transferred data and temporarily stores it in the memory 18. The decrypted data is then transferred to, for example, the DSP 10 and used for audio reproduction or data reproduction.

  The third coprocessor 20 is a reconfigurable circuit whose function can be dynamically changed, and constitutes an intended circuit when supplied with predetermined setting data from the DSP 10. For example, the third coprocessor 20 has a plurality of ALU (Arithmetic and Logic Unit) groups, and the circuit configuration can be dynamically changed by sequentially setting the function of each ALU group. At this time, the setting data defines the function of the ALU group and the connection relationship between the ALU groups.

  The clock control circuit 40 performs clock control of slave processors such as the first coprocessor 12, the second coprocessor 16, the third coprocessor 20, and the DMAC 30. The clock control circuit 40 enables clock frequency control and clock supply on / off control (clock gating). In particular, when the signal processing device 100 is incorporated in a battery-driven portable terminal device, it is necessary to reduce battery waste in order to achieve long-term use. Therefore, the clock control circuit 40 stops the clock supply and reduces power consumption when each slave processor does not operate.

  The memory 22 includes a RAM (Random Access Memory) or the like. The memory 22 stores application data processed by the DSP 10.

  In the signal processing apparatus 100 of the present embodiment, the schedule management circuit 50 plays a role of issuing an execution start instruction for operating a slave processor instead of a master processor such as the DSP 10. The schedule management circuit 50 is configured as hardware different from the master processor, and executes schedule management in the signal processing device 100 instead of the master processor. The schedule management circuit 50 may perform time management of at least some of the slave processors in the signal processing apparatus 100, and does not need to perform time management of all slave processors. Further, the schedule management circuit 50 does not have to perform scheduling for all processes of the slave processor that performs time management, and may perform scheduling for at least some of the processes.

  The schedule management circuit 50 detects the arrival of the start time for each unit process of the slave processor, and outputs an execution start instruction to the slave processor that should execute the unit process. Thereby, the slave processor can execute unit processing. This start time may be an absolute time or a relative time. For example, when the processing result in the first coprocessor 12 is handed over to the second coprocessor 16, the unit processing (data transfer processing) by the DMAC 30 and the second coprocessor are based on the start time of the unit processing of the first coprocessor 12. The start time of the unit process (error decoding code decoding process) according to 16 may be set relatively.

  Since the schedule management circuit 50 is responsible for schedule management of the signal processing device 100, a master processor such as the DSP 10 can reduce the load on schedule management, and the processing efficiency in the signal processing device 100 can be improved.

  FIG. 4 shows the configuration of the schedule management circuit. The schedule management circuit 50 includes a timing circuit 120 and an output circuit 130. The timing circuit 120 includes a plurality of counters that function as timers, and can generate a plurality of desired timings. For example, there are three counters: a counter that outputs a reference count value, a counter that outputs a count value that matches the reception operation timing in communication control processing, and a counter that outputs a count value that matches the transmission operation timing in communication control processing May be.

  The timing circuit 120 includes a setting register 110, a free-run counter 112, a time adjustment circuit 114, a first offset counter 116, and a second offset counter 118. The free-run counter 112, the first offset counter 116, and the second offset counter 118 receive clock supply from the outside and function as a time counter in the timing circuit 120. The free-run counter 112, the first offset counter 116, and the second offset counter 118 are counters that update the count value at a predetermined cycle. Each counter may have the same structure or a separate structure. For example, the counter may have a structure of 12 bits × 5 stages, and the period may be set finely in each stage.

  In the setting register 110, schedule information of a slave processor provided in advance from a master processor such as the DSP 10 is recorded. The schedule information includes the identification number of the slave processor to be operated and the start time and end time of the unit processing by the slave processor. The start time and end time of unit processing by a plurality of slave processors are defined on the time axis. When the slave processor is configured to be able to execute a plurality of types of operations, the schedule information includes information for specifying the operations to be executed by the slave processor. The schedule information is supplied to the output circuit 130 for comparison with the count value.

  As an example, when the received signal from the outside is filtered by the first coprocessor 12, the processing result is transferred to the second coprocessor 16, and the error correction code is decoded by the second coprocessor 16. The schedule information will be described. At this time, an arbitrary time T is used as a reference. Note that the time required for the filtering process by the first coprocessor 12 is 100 clocks, the time required for the data transfer process by the DMAC 30 is 10 clocks, and the time required for the decoding process by the second coprocessor 16 is 100 clocks. The first coprocessor 12 and the second coprocessor 16 are assumed to execute specific processing, and the processing time can be accurately calculated. Time T is set as the start time of the filter processing of the first coprocessor 12.

  In the schedule information, the start time is set to time T and the end time is set to time (T + 99) for the time information of the filter processing of the first coprocessor 12. Regarding the time information of the data transfer processing of the DMAC 30, the start time is set to time (T + 100) and the end time is set to time (T + 109). Regarding the time information of the filter processing of the second coprocessor 16, the start time is set to time (T + 110). ), And the end time is set to time (T + 209). Here, since the processing time of each slave processor is accurately calculated, it is not necessary to take a time margin between unit processes.

  Further, as described above, the schedule information may include the contents of the unit processes executed by the first coprocessor 12, the DMAC 30, and the second coprocessor 16. The unit processing of the first coprocessor 12 is to filter the received signal, and the unit processing of the DMAC 30 is to transfer the data filtered in the first coprocessor 12 to the second coprocessor 16. The unit processing of the second coprocessor 16 is to perform error correction decoding processing on the transferred data. The schedule information may include an address area of the memory 14 that stores the processing result of the first coprocessor 12 and an address area of the memory 18 that temporarily stores data transferred to the second coprocessor 16. If the processing contents of the first coprocessor 12 and the second coprocessor 16 are specified, the contents of each unit process can be omitted from the schedule information.

  The above schedule information is recorded in the setting register 110 at the time of initial setting. The initial setting time may be, for example, when the signal processing apparatus 100 is turned on. The DSP 10 holds schedule information in advance and provides it to the setting register 110 at the time of initial setting.

  The setting register 110 holds the periods of the free-run counter 112, the first offset counter 116, and the second offset counter 118. This period is also supplied from the DSP 10 at the initial setting. The setting register 110 supplies the set period to each counter, and each counter updates the count value based on the supplied period. Note that the period set for each counter may be the same or different.

  The free-run counter 112 outputs a count value indicating a reference timing in the timing circuit 120. On the other hand, the first offset counter 116 and the second offset counter 118 are offset from the reference timing generated by the free-run counter 112 by a time corresponding to the communication operation timing by the communication control processing of the DSP 10. Is generated. The communication operation timing is determined by executing a communication signal tracking process. Specifically, the first offset counter 116 outputs a count value in accordance with the reception operation timing by the communication control process of the DSP 10. The second offset counter 118 outputs a count value in accordance with the transmission operation timing by the communication control process of the DSP 10.

  The time adjustment circuit 114 functions as an adjustment circuit that adjusts the count values of the first offset counter 116 and the second offset counter 118 in accordance with the communication operation timing in the communication control processing of the DSP 10. Specifically, the time adjustment circuit 114 receives the offset time of the reception process and the offset time of the transmission process from the setting register 110. The two offset times are determined by the DSP 10 performing communication control processing, and are supplied from the DSP 10 to the setting register 110. Note that the offset time may vary from moment to moment depending on the communication environment, and it is preferable that the time adjustment circuit 114 always updates and holds the latest offset time. The time adjustment circuit 114 supplies the offset time of the reception process to the first offset counter 116 and supplies the offset time of the transmission process to the second offset counter 118.

  The first offset counter 116 delays or advances the reference timing based on the offset time of the reception process, and generates a timing synchronized with the reception process. Similarly, the second offset counter 118 delays or advances the reference timing based on the offset time of the transmission process, and generates a timing synchronized with the transmission process. Note that the count value of each counter does not shift the phase, but shifts the number of clocks determined as the offset time forward or backward with respect to the reference timing.

  The output circuit 130 is configured as a compare match output circuit, and depends on the start time recorded in the setting register 110 and the count value output from any of the free-run counter 112, the first offset counter 116, and the second offset counter 118. The arrival of the start time of the unit processing of the slave processor is detected. Specifically, the output circuit 130 includes a count value output from any of the free-run counter 112, the first offset counter 116, and the second offset counter 118, and time information among schedule information supplied from the setting register 110. When the count value reaches the time information, the arrival of the start time of the unit processing of the slave processor is detected. When detecting the arrival of the start time, the output circuit 130 issues and outputs an execution start instruction to the slave processor. In the example described above, time information for starting the unit processing of the first coprocessor 12 at time T is set in the schedule information, and the output circuit 130 has the count value supplied from the timing circuit 120 as T. When this happens, a unit process execution start instruction is issued to the first coprocessor 12. The same applies to the start time of unit processing by other slave processors.

  The timing circuit 120 includes three types of counters, that is, a free-run counter 112, a first offset counter 116, and a second offset counter 118, and output different count values. For example, when the data to be processed by the first coprocessor 12 relates to the reception process, the output circuit 130 selects the count value from the first offset counter 116 that generates the timing synchronized with the reception process, and schedule information Compare with time information. When the data processed by the first coprocessor 12 relates to transmission processing, the output circuit 130 selects the count value from the second offset counter 118 that generates timing synchronized with the transmission processing, and schedule information Compare with time information. If the data processed by the first coprocessor 12 is not related to the transmission / reception process, the output circuit 130 selects the count value from the free-run counter 112 that generates the reference timing, and the time information of the schedule information Compare with

  In this way, the output circuit 130 can output an instruction to start execution of the slave processor at an appropriate timing by selecting the counter according to the type of data to be processed. Although it is possible to perform time management only by the free-run counter 112, in that case, it is necessary to correct the time information of the schedule information based on the offset time from the reference timing by tracking processing or the like. For example, when the data transfer process of the DMAC 30 starts at time (T + 100) but a time delay corresponding to two clocks occurs in the reception process, it is necessary to rewrite the start time of the data transfer process to time (T + 102). is there. This complicates schedule management in the schedule management circuit 50.

  On the other hand, a plurality of types of counters are prepared in advance as in this embodiment, and for example, by generating a counter value synchronized with signal transmission / reception, an appropriate counter can be set without correcting time information of schedule information related to transmission / reception processing. By selecting, it can be used as it is. Thereby, schedule management can be facilitated.

  The setting register 110 may record, as one piece of schedule information, information specifying whether or not to issue an end notification signal for each unit process. When the unit processes of the first coprocessor 12, the DMAC 30, and the second coprocessor 16 proceed as a series of reception control processes, the time of each unit process is known. The output circuit 130 detects the arrival of the end time for each unit process based on the count value of the counter. For example, the output circuit 130 detects the arrival of the end time of the unit processing of the first coprocessor 12 when the count value supplied from the timing circuit 120 reaches (T + 99).

  In this way, the output circuit 130 can detect the end time for each unit process, but in a series of reception control processes involving a plurality of slave processors, information other than the end of the last unit process. Is not required to be notified to the DSP 10. If a processing notification signal for notifying the end of unit processing is issued to the DSP 10, it is processed as an interrupt signal in the DSP 10, which may hinder smooth processing operation in the DSP 10.

  Therefore, the setting register 110 sets a flag that specifies whether or not to issue an end notification signal for each unit process. For example, for a series of reception control processes including a plurality of unit processes, a flag for issuing an end notification signal is set only for the last unit process. When the output circuit 130 recognizes that the flag for issuing the end notification signal for the last unit process is set, the output circuit 130 issues the end notification signal to the DSP 10 when the end time of the last unit process arrives. To do. In the example described above, when the count value reaches the time (T + 209) when the decoding process of the error correction code in the second coprocessor 16 ends, an end notification signal is issued to the DSP 10 and output.

  FIG. 5 is a flowchart of signal processing performed by the signal processing apparatus according to the embodiment. FIG. 5 shows a processing flow when the signal processing result in the first coprocessor 12 is transferred to the second coprocessor 16 for processing. At the initial setting, the DSP 10 sends schedule information to the schedule management circuit 50 (S10).

  The schedule management circuit 50 sends a unit process execution start instruction to the first coprocessor 12 according to the time information included in the schedule information (S12). When receiving the execution start instruction, the first coprocessor 12 executes a received signal filtering process (S14). This received signal is written in the memory 14 immediately before the filter processing. The filtered data is temporarily stored in the memory 14.

  When the unit processing in the first coprocessor 12 ends and the arrival of the unit processing start time in the first coprocessor 12 is detected, the schedule management circuit 50 sends an execution start instruction for unit processing to the DMAC 30 (S16). . When the DMAC 30 receives the execution start instruction, the DMAC 30 reads the data that has been filtered and temporarily stored in the memory 14 and writes it in the memory 18 of the second coprocessor 16 (S18).

  When the unit process in the DMAC 30 ends and the arrival of the start time of the unit process in the second coprocessor 16 is detected, the schedule management circuit 50 sends an execution start instruction for the unit process to the second coprocessor 16 (S20). . When the DMAC 30 receives the execution start instruction, the DMAC 30 reads the data stored in the memory 18 and executes the error correction code decoding process (S22).

  When the schedule management circuit 50 detects the arrival of the end time of the unit processing in the second coprocessor 16, it sends an end notification signal to the DSP 10. This is a process when it is specified that an end notification signal is issued only for the unit process in the second coprocessor 16.

  In the signal processing apparatus 100 according to the present embodiment, in addition to the DSP 10, by additionally providing a schedule management circuit 50 that executes schedule management, the processing load on the DSP 10 can be greatly reduced. As apparent from the comparison with FIG. 2, by leaving the time control of the slave processor to the schedule management circuit 50, the DSP 10 is released from the process related to the schedule management, and other processes such as the main signal calculation process and the control process. Can be executed efficiently.

  Further, the DSP 10 can maintain a smooth operation state by reducing the number of interrupt signals sent from the schedule management circuit 50 to the DSP 10. In the processing flow shown in FIG. 5, the schedule management circuit 50 sends an end notification signal to the DSP 10 only after the end of unit processing in the second coprocessor 16, and does not send it at any other timing. In this way, by reducing the transmission frequency of the signal that becomes an interrupt signal for the DSP 10, it is possible to reduce the processing load on the DSP 10 and improve the processing efficiency.

  Conventionally, when the DSP 10 manages the schedule, it has been difficult to accurately manage the time due to the overhead caused by the software control, but in this embodiment, the problem is solved by providing the schedule management circuit 50. It becomes possible to do. For example, although the third coprocessor 20 is a coprocessor that reconfigures a circuit, the schedule management circuit 50 enables accurate schedule management, so that the processing efficiency of the third coprocessor 20 can be improved.

  Further, the schedule management circuit 50 can accurately execute the on / off control of the clock supply by the clock control circuit 40. Thereby, the power saving of the apparatus or system in which the signal processing apparatus 100 is incorporated can be executed efficiently. In particular, when configured as a mobile terminal device, the remaining battery time can be extended by achieving efficient power saving.

  In the above, this invention was demonstrated based on the Example. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. .

It is a figure which shows the structure of the conventional signal processing apparatus. It is a figure which shows the flowchart of the signal processing by the conventional signal processing apparatus. It is a figure which shows the structure of the signal processing apparatus concerning the Example of this invention. It is a figure which shows the structure of a schedule management circuit. It is a figure which shows the flowchart of the signal processing by the signal processing apparatus concerning an Example.

Explanation of symbols

2 ... bus, 10 ... DSP, 12 ... first coprocessor, 14 ... memory, 16 ... second coprocessor, 18 ... memory, 20 ... third coprocessor , 22 ... Memory, 30 ... DMAC, 40 ... Clock control circuit, 50 ... Schedule management circuit, 100 ... Signal processing device, 110 ... Setting register, 112 ... Free run Counter ... 114 Time adjustment circuit 116 ... First offset counter 118 ... Second offset counter 120 ... Timing circuit 130 ... Output circuit

Claims (3)

A master processor that mainly executes various processes in the device;
A slave processor that executes a specific unit process in response to an execution start instruction;
A schedule management circuit for issuing the execution start instruction instead of the master processor;
With
The schedule management circuit includes:
A timing circuit having a register for recording a start time for each unit process, a first time counter, and a second time counter ;
The arrival of the start time of the unit process is detected based on the start time recorded in the register and the count value of the first time counter or the second time counter , and the unit process is executed. An output circuit for outputting an execution start instruction to the slave processor to be
The master processor executes communication control processing,
The first time point measurement counter outputs a count value indicating a timing to be a reference in the timing circuit,
The second time counting counter has a count value that is offset from a reference timing generated by the first time counting counter by a time according to the communication operation timing by the communication control processing of the master processor. A signal processing device for outputting. The signal processing device according to claim 1,
The signal processing device, wherein the timing circuit further includes an adjustment circuit that adjusts a count value of the second timekeeping counter in accordance with a communication operation timing in a communication control process of the master processor. The signal processing device according to claim 1 or 2,
The timing circuit records information designating whether or not to issue an end notification signal for each unit process in the register,
The output circuit is designated to detect the arrival of the end time for each unit process and issue the end notification signal for each unit process based on the count value of the first time counter or the second time counter. A signal processing device that issues an end notification signal to the master processor when the end time of the unit processing has arrived.

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