JP4377268B2 - Linearity correction method for current cell type D / A converter and current cell type D / A converter - Google Patents

Description

  The present invention comprises a current cell type comprising a plurality of current cells arranged two-dimensionally in a matrix, and generating an analog signal corresponding to the digital data by generating a current corresponding to the digital data using the current cells. The present invention relates to a linearity correction method for a D / A converter and a current cell type D / A converter.

  Conventionally, a current cell type D / A converter is widely known. This current cell type D / A converter includes a large number of current cells arranged two-dimensionally, generates a current with the number of current cells corresponding to the digital data, and a total value of the currents generated by these current cells. The D / A converter is a type that generates an analog signal corresponding to the digital data.

  FIG. 1 is a diagram showing a two-dimensional arrangement of current cells.

  Here, each rectangle surrounded by lines drawn vertically and horizontally represents each current cell. In FIG. 1, 15 current cells are arranged vertically and 17 horizontally. Here, for later explanation, the current cells arranged vertically in the center are named “S7 S6 S5... S1 S0 S1... S5 S6 S7” in order from the top, and the centers are arranged on both sides of the current cells arranged vertically. The current cell group (excluding the current cells arranged vertically in the center) is named “L7 L6 L5... L1 L0 L1... L5 L6 L7” in order from the top.

  FIG. 2 is a circuit diagram showing a configuration for one current cell.

  Here, two P-channel transistors 11 and 12 are arranged in series between a power supply Vdd and the ground, and a connection point (node a) between the two P-channel transistors 11 and 12 and a signal output terminal Iout, Another P-channel transistor 13 is connected between the two. Further, a resistor R for current / voltage conversion is connected between the signal output terminal Iout and the ground.

  All of the transistors corresponding to the P-channel transistor 13 in FIG. 2 in a large number of two-dimensionally arranged current cells shown in FIG. 1 are connected to a common signal output terminal Iout.

  Here, in the current cell of FIG. 2, a predetermined constant voltage VG is applied to the gate of the P channel transistor 11, and the amount of current flowing through the P channel transistor 11 is defined by the constant voltage VG. At the gate of the P-channel transistor 12, a signal S obtained by decoding digital data (a signal for controlling whether or not current is generated in this current cell. When current is generated in this current cell, a signal of "H" level) And an inverted signal S ′ of the signal S is input to the gate of another P-channel transistor 13. When this current cell is a current cell that should generate current according to digital data, the signal S is at the “H” level, the signal S ′ is at the “L” level, the P-channel transistor 12 is in the cutoff state, and the P-channel The transistor 13 becomes conductive, and the current flowing through the P channel transistor 11 flows into the signal output terminal Iout through the P channel transistor 13. Here, the state of the current cell at this time is referred to as “on state”, and turning on the current cell is referred to as “turning on”. On the other hand, when this current cell is a current cell that does not generate a current according to digital data, signal S becomes' L 'level, signal S' becomes' H 'level, and P channel transistor 12 becomes conductive. In this state, the P channel transistor 13 is cut off, and the current flowing through the P channel transistor 11 flows through the P channel transistor 12 and does not contribute to the current flowing into the signal output terminal Iout. Here, the state of the current cell at this time is referred to as “off state”, and turning the current cell into “off state” is referred to as “turning off”.

  As shown in FIG. 1, among the many current cells arranged two-dimensionally, by turning on the current cell corresponding to the digital data, the current generated in the current cell in the on state is the signal output terminal. As the total current flows through the resistor R and flows through the resistor R, an analog signal having a voltage corresponding to the digital data appears at the signal output terminal Iout.

  Here, it has been described that the inverted signal S ′ of the decode signal S is input to the P-channel transistor 13, but the P-channel transistor 13 includes a type of current cell that inputs a certain reference voltage, Various current cells having a completely different structure from that shown in FIG. 2 are also known. However, the configuration of the current cell is not a problem here, and further detailed description of the current cell is omitted.

  Here, the current cell type D / A converter needs to have all the characteristics of a large number of two-dimensionally arranged current cells as shown in FIG. This adversely affects the linearity of / A conversion.

  On the other hand, since this D / A converter is manufactured through an LSI manufacturing process, it is not possible to eliminate variations in characteristics depending on the location of current cells. Generally, it is known that adjacent current cells have almost the same characteristics, and current cells separated from each other have different characteristics. For this reason, for example, when increasing the value of digital data bit by bit, in what order to turn on a number of two-dimensionally arranged current cells in order to minimize the linearity error. This is important, and several methods have been proposed (see Patent Documents 1 and 2).

  Here, a method according to Patent Document 1 will be described.

  Here, the digital data is composed of 8 bits, and the 8-bit digital data is divided into upper 4 bits and lower 4 bits.

  For the lower 4 bits, the current cells arranged in a central vertical row among the many two-dimensionally arranged current cells shown in FIG. 1 are used according to Table 1.

  For the upper 4 bits, according to Table 2, all the current cells shown in FIG. 1 except for the current cells arranged in a central vertical row are used.

Japanese Patent Laid-Open No. 6-204879 JP-A-8-330966

  According to the methods shown in Tables 1 and 2, linearity is almost ensured when digital data is converted into an analog signal even if the characteristics of the current cells vary to some extent.

  However, when the digital data changes from “XXX01111” (XXX represents that each bit may be 1 or 0) to “XXX10000”, the center of the data is “XXX01111”. When all of the current cells in one vertical column are turned on, and all the current cells in the current cell group L0 except the current cell S0 among the current cell group arranged in a horizontal row in the center are in the off state and changed to “XXX10000”, All the current cells in the central vertical column change from the on state to the off state, and all the current cell groups L0 in the central horizontal row (except for the current cell S0) change from the off state to the on state. There is a large deviation in current value due to manufacturing variations between the central vertical row and the current cell group L0, and linearity (differential linearity) is large. If there are many that would be.

  In view of the above circumstances, the present invention provides a linearity correction method for correcting linearity of a current cell type D / A converter configured as a semiconductor integrated circuit, and a current cell type D / A converter with corrected linearity. The purpose is to provide.

  A linearity correction method for a current cell type D / A converter according to the present invention that achieves the above object comprises a plurality of current cells arranged two-dimensionally in a matrix, and a center of the plurality of current cells is defined at a predetermined position. A current corresponding to the lower bits of the digital data is generated by a row of current cells extending in the direction, and a current corresponding to the upper bits of the digital data by current cells arranged two-dimensionally on both sides sandwiching the current cell of the row Is a linearity correction method for a current cell type D / A converter that generates an analog signal corresponding to digital data by the total current of the currents, and a current corresponding to the upper bits of the digital data Among a plurality of sub-current cells for generating a small current per current cell. The combination of the plurality of sub-current cells that minimizes the linearity error is detected, and the combination is used in actual use of the current cell type D / A converter. To do.

  The current cell type D / A converter of the present invention that achieves the above object includes a plurality of current cells arranged two-dimensionally in a matrix, and extends in the predetermined direction at the center of the plurality of current cells. A current cell corresponding to the lower bits of the digital data is generated by one row of current cells, and a current corresponding to the upper bits of the digital data is generated by current cells arranged two-dimensionally on both sides sandwiching the current cell of one row. Thus, in the current cell type D / A converter that generates an analog signal corresponding to the digital data by the total current of the currents, the current cell that generates a current corresponding to the upper bits of the digital data A plurality of sub-current cells for generating a small current for each current cell, the predetermined number of current cells being parallel to the one row; Combinations linearity error of the flow cell is minimized, characterized by comprising the actual use.

  In the present invention, a current cell type D / A converter that constitutes a current cell and generates a current corresponding to an upper bit of digital data, and parallel to a column of current cells corresponding to a lower bit of digital data, A predetermined, at least one row of current cells is configured with a plurality of sub-current cells for generating a small current per current cell, and a combination that minimizes the linearity error among the plurality of sub-current cells for adjustment is selected. In detection and actual use, since the combination that minimizes the linearity error is used, the linearity error can be greatly improved compared to the conventional case.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 3 is a diagram showing an arrangement example of current cells in the current cell type D / A converter of the present invention.

  Compared with the conventional arrangement shown in FIG. 1, one current cell is arranged vertically at both left and right ends in FIG. 1, and in the embodiment shown in FIG. 3, three sub current cells A, B, and C are configured. It is. These three sub-current cells A, B, and C are one current cell shown in FIG. 1 or other current cells excluding the current cell composed of the sub-current cells A, B, and C shown in FIG. Is called a “standard size current cell”). Specifically, each of the sub-current cells A and B has the same structure as the standard-size current cell, and is a sub-current cell that has a small transistor size and flows half the current of the standard-size current cell. The current cell C is a sub-current cell having the same structure as that of a standard size current cell, but having a smaller transistor size and passing a current that is 1/4 that of the standard size current cell. Therefore, here, each of the sub-current cells A and B is referred to as a “½-size sub-current cell”, and the current cell C is referred to as a “¼-size sub-current cell”.

  FIG. 4 is a diagram showing a calibration circuit incorporated together in the D / A converter having the current cell arrangement shown in FIG.

  FIG. 4 shows a calibration pattern generation unit 21 that generates a calibration pattern for performing calibration (correction of linearity), a calibration pattern generated by the calibration pattern generation unit 21, and an analog signal during normal use. A multiplexer 22 which switches digital data (normal signal) to be converted into a normal signal in accordance with a calibration control signal and transmits it to a subsequent stage, and a current cell group having a structure shown in FIG. 3 based on a signal output from the multiplexer 22 A logic unit 23 that generates a control signal for controlling on / off of each current cell (including three sub-current cells A, B, and C for each current cell that constitutes current cells at both ends) 3 and the DA core 10 having the current cell group of the arrangement shown in FIG. Comparator 24 for comparing, as will be described later by monitoring the analog output is shown from 10. The comparison result in the comparator 24 is input to the logic unit 23. In the calibration mode, the logic unit 23 changes the control signal according to the comparison result.

  Here, the following processing is performed in the calibration mode.

  First, among the many current cells shown in FIG. 3, the current cells corresponding to the digital data “00001111” (all 15 current cells S0 to S7) are turned on (all other current cells are turned off). The voltage at the signal output terminal Iout is taken into the comparator 24 and temporarily stored (here, the voltage at the signal output terminal Iout is referred to as “comparison reference voltage V0”), and then corresponds to the digital data “00010000”. The current cell (16 current cells constituting the current cell group L0) is turned on (all other current cells are turned off). At this time, for the current cells at the left and right ends, the ½-size sub-current cell A and the ¼-size sub-current cell C are turned on, and the ½-size sub-current cell B is kept off. At this time, the voltage V1 appearing at the output signal terminal Iout is compared with the comparison reference voltage V0 previously taken into the comparator 24. At this time, if V0 <V1, the current cells corresponding to the digital data “00010000” (16 current cells constituting the current cell group L0) are present in the current cells at both the left and right ends. Of the three sub-current cells A, B, and C, only the ¼-size sub-current cell C is turned on, and the other two ½-size sub-current cells A and B are kept off. At this time, the voltage V2 appearing at the output signal terminal Iout is taken into the comparator 24 and compared with the comparison reference voltage V0.

From the above two comparison results, the logic unit 23 controls the three sub current cells A, B, and C as follows for each current cell constituting the current cells at the left and right ends in actual use.
(A) When V0 ≧ V1 In actual use, all three sub-current cells A, B, C are used (turned on / off simultaneously).
(B) When V0 <V1 and V0 ≧ V2 During actual use, among the three sub-current cells A, B, C, the quarter-size sub-current cell C is not used (always off). The remaining two 1/2 size sub-current cells A and B are simultaneously used (ON / OFF).
(C) When V0 <V2 In actual use, one of the two sub-current cells A, B of the ½ size among the three sub-current cells A, B, C (for example, 1 / 2 size sub current cell A) and another 1/4 size sub current cell C are used (on / off at the same time), and the remaining half size sub current cell (for example 1/2 here) The size of the sub-current cell B) is not used (always off).

  In this way, a combination with the smallest linearity error is detected for the three sub-current cells A, B, and C, and a D / A converter with good linearity is realized by using the combination in actual use. To do.

  In the configuration shown in FIG. 4, the information on which pattern (a) to (c) is to be used in actual use is stored in the logic unit 23 with a non-volatile memory. Alternatively, a fuse or an antifuse may be incorporated and stored in a fixed manner, or information may be transmitted to the inside by connecting an external pin to a power source or a ground.

  In the above embodiment, each row of current cells at the left and right ends in FIG. 3 is composed of two ½-size sub-current cells A and B and one ¼-size sub-current cell C. The combination of the sub-current cells constituting the adjustment current cell is not limited to these three sub-current cells A, B, C, and a plurality of sub-current cells may be prepared according to the required accuracy. That's fine. Moreover, the current cell for adjustment does not need to be a current cell at both ends of the left and right, may be a current cell at one of the left and right, and need not be a current cell at the left or right end, It may be a current cell at another location.

It is a figure which shows the conventional two-dimensional arrangement | positioning of the current cell. It is the circuit diagram which showed the structure for one current cell. It is a figure which shows the example of arrangement | positioning of the current cell in the current cell type D / A converter of this invention. It is a figure which shows the calibration circuit integrated together in the D / A converter with the arrangement | sequence of the current cell shown in FIG.

Explanation of symbols

10 DA core 11, 12, 13 P-channel transistor 21 Calibrated pattern generation unit 22 Multiplexer 23 Logic unit 24 Comparator

Claims (2)

A plurality of current cells arranged two-dimensionally in a matrix, and a current corresponding to the lower bits of the digital data is generated by a row of current cells extending in a predetermined direction at the center of the plurality of current cells; By generating current corresponding to the upper bits of the digital data with current cells that are two-dimensionally arranged on both sides of a row of current cells, an analog signal corresponding to the digital data is generated based on the total current of those currents. A linearity correction method for a current cell type D / A converter,
Among the current cells that generate a current corresponding to the upper bits of the digital data, a predetermined, at least one row of current cells parallel to the one row is a plurality of sub-current cells for generating a small current for each current cell. Configure
The combination that minimizes the linearity error among these sub-current cells is detected,
A method for correcting the linearity of a current cell type D / A converter, wherein the combination is used in actual use of the current cell type D / A converter. A plurality of current cells arranged two-dimensionally in a matrix, and a current corresponding to the lower bits of the digital data is generated by a row of current cells extending in a predetermined direction at the center of the plurality of current cells; By generating current corresponding to the upper bits of the digital data with current cells that are two-dimensionally arranged on both sides of a row of current cells, an analog signal corresponding to the digital data is generated based on the total current of those currents. In the current cell type D / A converter
Among the current cells that generate a current corresponding to the upper bits of the digital data, at least one row of current cells parallel to the one row, and a plurality of sub-current cells for generating a small current per current cell. Prepared,
A current cell type D / A converter characterized in that a combination that minimizes the linearity error among the plurality of sub-current cells is actually used.

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