JP4370524B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a page size can be changed by an aluminum master slice.

  Semiconductor memory devices have been increased in capacity and speed, and 1 Gbit DRAM has been put to practical use in dynamic random access memory (hereinafter abbreviated as DRAM). However, although the transfer speed in these semiconductor memory devices is increased, the current speed is considerably slower than the operation speed of the CPU. Therefore, in DRAM, a multi-bit data width, a prefetch method, or a multi-bank method is adopted for speeding up. The DRAM access is a multi-address method, in which a word line in the X direction is activated by a row address, and then a column system in the Y direction is operated by a column address. For this purpose, the row address is fixed and the column system is accessed continuously to increase the speed. By continuously accessing the data of the memory cells activated by one word line access, the data can be accessed only with the column delay time, and the data transfer time is increased.

  The number of memory cells or the number of bytes activated by one word line access is called a page size. If the page size is increased, the number of memory cells activated by one access increases. Therefore, if the page size is increased, the number of bits that can be accessed continuously increases, and the data access speed is increased. However, on the other hand, since many memory cells are activated, there is a drawback that current consumption increases. Therefore, the required page size varies depending on the field and system in which the semiconductor memory device is used. In a large-capacity storage system, the number of continuously processed data per time is large, and the page size is set large by placing importance on the data transfer speed. In a mobile storage system such as a cellular phone, the number of continuous processing data per time is relatively small, and the page size is set small by placing importance on current consumption.

  Therefore, semiconductor memory devices with different page sizes are required depending on the user's application, and semiconductor memory device manufacturers need to prepare semiconductor memory devices with different page sizes. As a result, the semiconductor storage device manufacturer has a problem that the man-hours for developing the two types are enormous. There is also a problem that the production system for supplying the quantity requested by the user on time is a heavy burden. For this reason, an aluminum master slice type product configuration in which the page size can be easily changed is desired.

  The following conventional page size configuration will be described. FIG. 1 is an overall configuration diagram of a 256 Mb DRAM, FIG. 4 is a data allocation (A) at a page size of 256 bytes, a data I / O line configuration diagram (B), and FIG. 5 is a connection diagram of a data I / O line at a page size of 256 bytes. FIG. 6 shows data allocation (A) with a page size of 512 bytes, data I / O line configuration diagram (B), and FIG. 7 shows a connection diagram of data I / O lines with a page size of 512 bytes.

  The 256 Mb DRAM of FIG. 1 is a 32-bit product of double data rate (DDR) system with two prefetches. This is a four-bank configuration of banks A, B, C, and D each including four blocks each having a memory capacity of 16 Mb in the horizontal direction. Each block includes 16 Mb memory cells, and outputs 32 bits, 8 bits each of DQ0 to 7, DQ8 to 15, DQ16 to 23, and DQ24 to 31. A row decoder (XDEC) is provided for each block, and a column decoder is provided for two blocks. The memory cells 16Mb in each block are arranged in a word line (including sub word lines) 8K, and the column system is arranged in 2K. Each block is further composed of a plurality of MATs.

  Access to the memory cell is performed as follows. A word line is selected by a signal from XDEC, a memory cell on the selected word line is activated, and data stored in the memory cell is read to a bit line pair and amplified by a sense amplifier. The output of the sense amplifier selected by the column selection signal (YSW) is transmitted to the local I / O line pair (LIO) and further transmitted to the main I / O line pair (MIO). A signal from the MIO is transmitted to the data amplifier (DAMP) of the input / output circuit via the global I / O line pair (GIO) and output as data to the outside. On the contrary, at the time of writing, input data is written into the memory cell via the write amplifier (WAMP), GIO, LIO, sense amplifier, and bit line of the input / output circuit. Here, for easy understanding, LIO is first aluminum, MIO is second aluminum, and GIO is third aluminum for easy understanding.

  FIG. 4A shows data allocation for a page size of 256 bytes. One block has a 16 Mb memory cell configuration, 8192 word lines, and 2048 column systems. Hereinafter, the column system is expressed as the number of YSW lines for selecting bit lines from each memory cell. Since one YSW line can activate data from four memory cells, 2048/4 = 512 lines are divided into four, and 128 lines are arranged. This is an 8-bit output of DQ0 to DQ7, and the page size is 256 bytes with EVEN128 and ODD128.

  As shown in the figure, the block is divided into two groups of 4 bits each for DQ 8 bits, and further divided into EVEN and ODD for a DDR prefetch number of 2. The data structure is DVEN, DQ0, 2, 4, 6 EVEN, DQ1, 3, 5, 7 EVEN, DQ0, 2, 4, 6 ODD, and DQ1, 3, 5, 7 ODD. . Eight bits of DQ0 to DQ7 are continuous with EVEN and ODD, and by switching 128 YSWs, the page size becomes 256 bytes in total.

  FIG. 4B shows a data IO line configuration diagram in one block. It consists of 120 MATs divided into 24 in the X direction and 5 in the Y direction. MAT is a memory cell array arranged in a matrix, and sense amplifier regions are arranged on both sides of these memory cell arrays. The sense amplifier area includes a sense amplifier, an LIO, a YSW for switching connection to the LIO, and an LIO selection SW for switching connection to the MIO. In the sense amplifier area, for example, MAT1 and 24 are dedicated areas at the end of the block. However, the sense amplifier area between MAT1 and MAT2 in the middle part operates for MAT1 when MAT1 is activated. On the contrary, when MAT2 is activated, it operates for MAT2 and is shared.

  As for data from the sense amplifier, LIO arranged in the Y direction, MIO arranged in the X direction, and GIO (not shown) in the Y direction are arranged. The bit line signal from each MAT is transmitted to the MIO via the LIO in the sense amplifier area. MIO is arranged between each MAT, 4 pairs for EVEN data of DQ0, 2, 4 and 6, 2 pairs for EVEN data of DQ3 and 7, 2 pairs for EVEN data of DQ1 and 5, DQ0 and 4 Two pairs for ODD data, two pairs for ODD data of DQ2, 6 and four pairs for ODD data of DQ1, 3, 5, and 7 are arranged. Sixteen data line pairs for EVEN and ODD up to a total of DQ0 to DQ7 are arranged. The MIO is connected to the data input / output circuit in the central part of the semiconductor via the GIO.

  Here, reading from the memory cell will be described. A memory cell connected to the selected word line is activated by a signal from XDEC. For example, the memory cells of MAT1, 25, 49, 73, and 97 are activated. Data from each memory cell is amplified by sense amplifiers arranged on both sides of each MAT and transmitted to LIO, MIO, and GIO (not shown). A total of 16-bit data of EVEN and ODD of DQ0 to 7 is read. At this time, 256-byte data is read by further switching the column system YSW.

  Refer to the connection to the data IO line shown in FIG. A memory cell connected to the selected word line is accessed. Each sense amplifier SA1, SA2, SA3, and SA4 connected to the bit line pair of the memory cell is activated, and the data of the memory cell is amplified. YSW is activated by the YSW selection signal, and the data of the sense amplifier is transmitted to LIO. Further, the LIO selection SW is activated by the LIO selection signal, and the data is transmitted to the MIO. At this time, the data from the sense amplifier SA1 on the MAT left side of MAT1 is the MIO DQ2, the data from the sense amplifier SA2 is the MIO DQ0, and the data from the opposite sense right SA3 sense amplifier SA3 is the data from the MIO DQ6 and the data from the sense amplifier SA4. Is transmitted to DIO 4 of MIO. Similarly, data from each MAT is transmitted to the corresponding MIO line by the YSW selection signal and the LIO selection signal, respectively.

  In the rows of MAT1, 25, 49, 73, 97, 128 YSWs from the top of the figure cause EVEN of DQ0, 2 from the left sense amplifier region, and EVEN of DQ4, 6 from the right sense amplifier region. For the next 128 YSWs, DQ1, 3 EVEN from the left, DQ5, 7 EVEN from the right, and for the next 128 YSWs, DQ0, 2 ODD from the left, DQ4, 6 from the right For the next 128 YSWs, the ODDs of DQ1 and 3 from the left side and the ODDs of DQ5 and 7 from the right side are connected to the MIO line.

  Data from each MAT is transmitted as 16 data of MIO DQ0-7 and ENEN / ODD. Further, it is transmitted to the data input / output circuit via the GIO. Similarly, data is transferred from other blocks in the bank to the respective input / output circuits as DQ8-15, DQ16-23, and DQ24-31. Further, by switching the YSW selection signal, the memory cell data amplified by the sense amplifier is sequentially read. With 128 YSW selection signals, 256 bytes of 128-byte EVEN ODD can be read as data.

  FIGS. 6 and 7 show semiconductor memory devices in which the semiconductor memory device having a page size of 256 bytes is expanded to a page size of 512 bytes without changing the basic configuration. FIG. 6A shows data allocation. The memory cell connected to one word line in the block is 2K bits, and if it is divided into EVEN and ODD, it becomes 256 bytes. Therefore, by simultaneously activating two word lines, the page size is 512 bytes. Realize. The block is divided into four, and EVEN and ODD of the first data group (DQ0, 2, 4, 6) are assigned to the left side, and EVEN and ODD of the second data group (DQ1, 3, 5, 7) are assigned to the right side. Of the 8192 word lines, one on each of the left and right sides is activated to make 4096 words x 2 so that the page size is 512 bytes. By activating two word lines, for example, in the MAT1 column of MAT1, 25, 49, 73, 97 on the left side and the MAT13 column of MAT13, 37, 61, 85, 109 on the right side shown by diagonal lines, Each of the word lines is activated.

  FIG. 6B shows a data IO line configuration diagram. The arrangement of MIO is the same as in the case of a page size of 256 bytes. Two sense amplifier regions are separately arranged at the boundary between the first data group DQ0, 2, 4, 6 and the second data group DQ1, 3, 5, 7. In the MAT1 column, the upper YSW is 256, the left sense amplifier area is DQ0, 2 EVEN, the right is DQ4, 6 EVEN, and the lower YSW 256 is the left sense amplifier area from the left sense amplifier area. The ODDs of DQ0 and DQ2, and the EVENs of DQ4 and 6 from the right side are connected to the MIO. Further, ENEN and ODD of DQ1, 3, 5, and 7 are similarly connected from the column of MAT13. By activating one word line from each of the first data group and the second data group, the page size becomes 512 bytes.

  FIG. 7 shows the connection to the data IO line. From the sense amplifier SA5 on the right side of MAT12 to MIODQ6 via LIO, from the sense amplifier SA6 to MIODQ4 via LIO, from the sense amplifier SA7 on the left side of MAT13 to MIODQ3 via LIO, to sense amplifier SA8. Is connected to MIODQ1 via LIO.

  Thus, two MAT configurations are arranged at the boundary of the data group. Since the sense amplifier region between the MATs 12 and 13 is not shared with the MATs 12 and 13 at the boundary of the data group, two sense amplifier regions are required. Therefore, in order to change the page size, it is necessary to change the formation of the isolation region and the diffusion layer forming pattern constituting the sense amplifier. Therefore, in this case, there is a problem that the page size cannot be changed by changing only the wiring process.

  There are many configurations of these memories, which are described in the following patent documents. In Patent Document 1, when the page size is 1K, the page size is changed to an 8-bank configuration, and when the page size is set to 2K, the page size is changed to a 4-bank configuration. In Patent Document 2, the page size is changed in the line mode or the box mode by specifying the word line mode. In Patent Document 3, the speed is increased by connecting mats at both ends to the same input / output line in a shared sense amplifier configuration. However, none of these patent documents recognizes a problem related to a method for achieving a page size desired by a user with a simple method, and does not describe a solution method. Therefore, it is desired to develop a method that enables a variety of aluminum master slice types that can be easily changed in page size.

JP 2003-178580 A JP 2001-312885 A JP 05-234377 A

  As described above, the optimum page size for the system differs depending on the system using the semiconductor memory device. However, there is no method for easily changing the page size, and a semiconductor memory device that matches each user's request is developed. Thus, there is a problem that the manufacturer has to bear enormous development costs.

  In view of the above problems, an object of the present application is to provide a semiconductor memory device using a technique capable of easily changing the page size in an aluminum master slice method in which only a wiring process is changed without a significant change in the semiconductor memory device. It is.

A semiconductor memory device of the present application includes a memory cell array, a row decoder, a column decoder, and a sense amplifier arranged in a matrix, and a local I / O (LIO) line and a main I / O (MIO) connected to the sense amplifier. The page size of the memory block can be changed by switching the connection to the line with an aluminum master slice .

  In the semiconductor memory device of the present application, the page size of the memory block is increased by activating a plurality of word lines selected from the row decoder of the memory block.

  In the semiconductor memory device of the present application, the local I / O (LIO) line is formed by a first wiring layer, the main I / O (MIO) line is formed by a second wiring layer, and the global I / O (GIO) line is the first wiring layer. 3 wiring layers.

In the semiconductor memory device of the present application, the memory block in which the connection between the local I / O (LIO) line and the main I / O (MIO) line is switched by the aluminum master slice is composed of a plurality of MAT columns, and the first data group is A plurality of first MAT columns to be output, a plurality of second MAT columns to output a second data group, half of the data in the first data group, and half of the data in the second data group. It is composed of a third MAT sequence to be output, and a fourth MAT sequence for outputting the remaining half of the data in the first data group and the remaining half of the data in the second data group. .

  In the semiconductor memory device of the present application, a plurality of the first MAT columns are arranged adjacent to each other, a plurality of the second MAT columns are arranged adjacent to each other, and the first MAT column and the second MAT column are arranged. The third MAT row is arranged at the boundary of the second MAT row, and the fourth MAT row is arranged at the other end of the second MAT row.

  In the semiconductor memory device of the present application, one word line is activated in the group composed of the first MAT column and the third MAT column, and the second MAT column and the fourth MAT column are activated. One word line is activated in a group composed of MAT columns.

In the semiconductor memory device of the present application, the memory block in which the connection between the local I / O (LIO) line and the main I / O (MIO) line is switched by the aluminum master slice is composed of a plurality of MAT columns, and the first data group is A plurality of first MAT columns to be output and a plurality of second MAT columns to output a second data group; and a MAT shared by the first data group and the second data group. As a boundary, a plurality of second MAT columns for outputting the second data group are inserted between a plurality of first MAT columns for outputting the first data group.

  The semiconductor memory device according to the present application is capable of obtaining a semiconductor memory device capable of changing the page size by the aluminum master slice method by changing the connection from the sense amplifier to the local I / O (LIO) and from the LIO to the main I / O (MIO). There is.

  The present invention will be described in detail below with reference to the drawings.

  A first embodiment will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of 256 MDRAM, FIG. 2 is a data allocation (A) and data I / O line configuration diagram (B) at a page size of 512 bytes, and FIG. 3 is a connection diagram of data I / O lines at a page size of 512 bytes. Indicates. In the present embodiment, in the 256 MDRAM of FIG. 1 described above, the semiconductor memory device having the page size of 256 bytes shown in FIGS. 4 and 5 is changed to the page size of 512 bytes by the aluminum master slice method that changes only the wiring process. It is an example.

  The semiconductor memory device 1 in FIG. 1 is a 256 Mb DRAM. The 256 Mb DRAM is a 32-bit product having a double data rate (DDR) type 32-bit DQ pin with two prefetch numbers. A four-bank configuration of banks A, B, C, and D each having four blocks 2 each having a memory capacity of 16 Mb in the horizontal direction. Each block includes 16 Mb memory cells, and outputs 32 bits each including 8 bits of DQ0 to 7, DQ8 to 15, DQ16 to 23, and DQ24 to 32. A row decoder (XDEC) is provided for each block and selects a word line. A column decoder is provided in units of two blocks and selects YSW. The memory cell 16Mb of each block has a word line (including sub word lines) 8K, and the column system has a 2K structure. Each block is further composed of a plurality of MATs.

  A word line is selected by a signal from the row decoder (XDEC), a memory cell on the selected word line is activated, and data stored in the memory cell is read to a bit line pair and amplified by a sense amplifier. . The output of the sense amplifier selected by YSW is transmitted to the local I / O line pair (LIO) and further to the main I / O line pair (MIO). A signal from the MIO is transmitted to the data amplifier (DAMP) of the input / output circuit via the global I / O line pair (GIO) and output as data to the outside. On the contrary, at the time of writing, the input data is written into the memory cell via the write amplifier (WAMP), GIO, MIO, LIO, sense amplifier and bit line of the input / output circuit. Here, for each metal wiring, LIO is a first aluminum, MIO is a second aluminum, and GIO is a third aluminum.

  FIG. 2A shows data allocation in a page size of 512 bytes, and FIG. 2B shows a configuration diagram of data IO lines. In the following description, since each 16M block has the same configuration except for data (DQ0-7, 8-15, 16-23, 24-31), one block that outputs DQ0-7 Only do with respect. The configuration of these MATs and the configuration of the main I / O (MIO) line are the same as those in FIG. 4, and the connection of the local I / O (LIO) line is different. Only by these changes, the page size can be changed from 256 bytes to 512 bytes. The LIO lines are wired in units of 256 YSW and are connected to the switching MIO by the LIO selection SW.

  A memory cell connected to one word line in the block is 2K bits, and if divided into 8 bits of DQ, EVEN, and ODD, it becomes 256 bytes. Therefore, by simultaneously activating two word lines, the memory cell to be accessed becomes 4K bits, and a page size of 512 bytes is realized. The block is divided into four, and EVEN and ODD of DQ0, 2, 4, 6 are assigned to the left side, and EVEN and ODD of DQ1, 3, 5, and 7 are assigned to the right side. Of the 8192 word lines, one each of the left 4096 word line and the right 4096 word line is activated to have a page size of 512 bytes. By activating two word lines, for example, one word line in each of the MAT columns of the left MATs 1, 25, 49, 73, and 97 and the MAT columns of the right MATs 13, 37, 61, 85, and 109, respectively. Is activated.

  In the MAT1 column, MAT1, MAT25, and half of the MAT49 corresponding to 256 upper YSWs are connected to EVEN of MIO DQ0 and 2 in the left sense amplifier region, and MIO in the right sense amplifier region. DQ4 and 6 are connected to EVEN. The other half of the MAT 49 corresponding to 256 lower YSWs, the memory cells of the MAT 73 and the MAT 97 are connected to the MDDs DQ0 and ODD in the left sense amplifier region, and the MIO DQ4 in the right sense amplifier region. , 6 ODD.

  In the column of MAT1, EVEN and ODD of DQ0, 2, 4 and 6 which are half of 8 bits are output. Here, the EVEN and ODD data of DQ0, 2 are extracted from the left sense amplifier area, and the EVEN and ODD data of DQ4, 6 are extracted from the right sense amplifier area. Therefore, it is only necessary to extract data in a relationship complemented by the left and right sense amplifier regions. In the columns MAT2 to MAT11, since the sense amplifier regions are shared by adjacent MATs, the data array is alternately repeated as understood from the drawing, and the data paths of the memory cells and LIO are connected.

  In the row of MAT13 accessed at the same time, MAT13 corresponding to 256 upper YSW, MAT37, and half of the memory cells of MAT61 are connected to EVEN of MIO DQ1 and 3 in the left sense amplifier region. Are connected to EVEN of MIO's DQ5 and 7 in the sense amplifier region. The remaining half of the MAT 61 corresponding to 256 YSWs on the lower side, the memory cells of the MAT 85, and the MAT 109 are connected to the ODDs of the MIO DQ1 and 3 in the left sense amplifier region, and the MIO DQ5 in the right sense amplifier region. , 7 are connected to the ODD. With these connections, EVEN and ODD data of DQ1, 3, 5, and 7 are output. In the rows of MATs 14 to 23, the left and right data arrays are alternately repeated, and the data paths of the memory cells and LIO are similarly connected.

  By combining the data group read in the MAT1 column and the data group read in the MAT13 column, the EVEN and ODD data of DQ0 to DQ7 are read from the memory cells. A page size of 512 bytes is obtained by selecting and switching with 256 YSW.

  However, the data arrangement in the column of MAT12 and the column of MAT24 to be the last of these data groups is the first data group (DQ0, 2, 4, 6) and the second data group (DQ1, 3, 5, 5). Different from the data array of 7). In the MATs 36, 60, 84, and 108 arranged in the row of the MAT 12, the memory cells of the MAT 12, MAT 36, and half of the MAT 60 are connected to the EVENs of the DQs 4 and 6 in the left sense amplifier region. In the region, it is connected to EVEN of DQ1,3. Half of the MAT 60, the memory cells of the MAT 84, and the MAT 108 are connected to the ODDs of DQ4 and 6 in the left sense amplifier region, and are connected to the ODDs of DQ1 and 3 in the right sense amplifier region. In the column of MAT12, EVEN and ODD data of DQ1, 3, 4, 6 are extracted.

  Further, the column of the MAT 24 accessed simultaneously with the column of the MAT 12 will be described. Half of the memory cells of MAT24, MAT48, and MAT72 are connected to EVEN of DQ5 and DQ7 in the left sense amplifier region, and are connected to EVEN of DQ0 and DQ2 in the right sense amplifier region. Half of the MAT 72, the memory cells of the MAT 96, and the MAT 120 are connected to the ODDs of DQ5 and DQ5 in the left sense amplifier region, and are connected to the ODDs of DQ0 and DQ2 in the right sense amplifier region. In the column of MAT24, EVEN and ODD data of DQ0, 2, 5, and 7 are extracted. Therefore, the EVEN and ODD data of DQ0 to DQ7 are output by the column of MAT12 and the column of MAT24.

  Thus, the data arrangement of the MAT columns of MAT12 and MAT24 is different from the other MAT columns. In the MAT 12, half the data of the first data group is output in the left sense amplifier area, and half the data of the second data group is output in the right sense amplifier area. In the MAT 24, the remaining half of the second data group is output in the left sense amplifier area, and the remaining half of the first data group is output in the right sense amplifier area. In this configuration, EVEN and ODD data of DQ0 to DQ7 are output in the MAT12 column and the MAT24 column.

  A connection diagram of the data IO shown in FIG. 3 will be described. FIG. 3 shows a row of MAT12. The word line is activated and the memory cell is activated. The data in the memory cell is amplified by the sense amplifier, and the data from the four sense amplifiers SA1, 2, 3, 4 selected by the YSW selection signal is transmitted to the LIO line. Data from SA1 is transmitted to MIODQ6 via LIO by LIO selection SW. Similarly, the data is transmitted from the sense amplifier SA2 to LIO and MIODQ4, from the sense amplifier SA3 to LIO and MIODQ3, and from the sense amplifier SA4 to LIO4 and MIODQ1, respectively. Here, for each metal wiring, LIO is first aluminum, MIO is second aluminum, and GIO is third aluminum. By changing the wiring layers in this way, it is easy to change each wiring layer and the through hole connecting the wiring layers, and the page size can be easily changed by the aluminum master slice.

  When comparing the configuration of the present application with the 512-byte page size of the conventional example, in the conventional example, two sense amplifier regions are required at the boundary of the data group. Has been. Therefore, the page size is the same as that shown in FIG. 4 and the page size can be changed by the aluminum master slice method in the wiring process.

  The column of the MAT 12 at the boundary of the data group and the column of the MAT 24 at the extreme end have a data structure different from that of the other MAT columns. That is, a plurality of MATs that output the first data group are arranged adjacent to each other, a plurality of MATs that output the second data group are arranged adjacently, and the MAT that outputs the first data group; A MAT that outputs half of the data of the first data group and half of the data of the second data group is arranged at the boundary with the MAT that outputs the second data group. Further, the MAT for outputting half the data of the first data group and half the data of the second data group at the end of the plurality of MATs that output the second data group arranged adjacent to each other. Has been placed.

  In the present embodiment, the data extraction from the sense amplifier regions on both sides of the MAT may be a relationship in which half of the data group is extracted and complemented in the left and right regions. In the MAT arrangement, the left and right sense amplifier areas are alternately arranged so as to maintain a complementary relationship. Therefore, the data extraction of the first and last MAT columns in the MAT array may be performed in the same way when the number of even MATs is used, and when the number of odd MATs is used, the opposite ends may be complemented.

  Therefore, in this embodiment, the data groups are switched with the MATs 12 and 24 as the boundary and the MATs 12 and 24 sharing the two data groups, but the data groups can be switched at any MAT position. For example, MAT10 and MAT22 are used as a boundary, and are shared by the first and second data groups. The first data group can be output from MAT1 to 10 and MAT22 to 24, and the second data group can be output from MAT10 to 22. In this way, data groups can be switched in any MAT. In the present application, the page size is doubled, but if the third and fourth data groups are further added as the second data group, the page size can be expanded to four times.

  In this embodiment, the page size can be changed by changing the LIO by the aluminum master slice method. Therefore, there is no increase in the chip size, and the effects can be obtained because the development man-hours can be reduced and the production process can be easily changed.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

It is a whole block diagram of 256MDRAM in this invention. It is a data allocation (A) in page size 512 bytes, and a block diagram (B) of a data IO line. It is a connection diagram of data IO in a page size of 512 bytes. It is a block diagram (B) of the data allocation (A) and data IO line in the page size 256 bytes of a prior art example. It is a connection diagram of data IO in a conventional page size of 256 bytes. It is a data allocation (A) in the page size of 512 bytes of a prior art example, and a block diagram (B) of a data IO line. It is a connection diagram of data IO in a conventional page size of 512 bytes.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Block SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8 Sense amplifier

Claims (7)

A semiconductor memory device includes a memory cell array arranged in a matrix, a row decoder, a column decoder, and a sense amplifier.
A semiconductor memory device characterized in that a page size of a memory block can be changed by switching connection between a local I / O (LIO) line and a main I / O (MIO) line connected to the sense amplifier by an aluminum master slice .   2. The semiconductor memory device according to claim 1, wherein the page size of the memory block is increased by activating a plurality of word lines selected from the row decoder of the memory block. The local I / O (LIO) line is formed by a first wiring layer, the main I / O (MIO) line is formed by a second wiring layer, and the global I / O (GIO) line is formed by a third wiring layer. The semiconductor memory device according to claim 1 , wherein: A memory block in which the connection between the local I / O (LIO) line and the main I / O (MIO) line is switched and connected by an aluminum master slice is composed of a plurality of MAT columns, and a plurality of first blocks that output a first data group. A MAT column, a plurality of second MAT columns for outputting a second data group, and a third MAT column for outputting half of the data of the first data group and half of the data of the second data group 2. The semiconductor according to claim 1, further comprising: a remaining half of the first data group and a fourth MAT column that outputs the remaining half of the second data group. Storage device. A plurality of the first MAT columns are arranged adjacent to each other, a plurality of the second MAT columns are arranged adjacent to each other, and the third MAT column is arranged at the boundary between the first MAT column and the second MAT column. 5. The semiconductor memory device according to claim 4, wherein a MAT column is disposed, and the fourth MAT column is disposed at the other end of the second MAT column. A group consisting of the second MAT column and the fourth MAT column when one word line is activated among the group consisting of the first MAT column and the third MAT column. 6. The semiconductor memory device according to claim 4 , wherein one of the word lines is activated. A memory block in which the connection between the local I / O (LIO) line and the main I / O (MIO) line is switched and connected by an aluminum master slice is composed of a plurality of MAT columns, and a plurality of first blocks that output a first data group. A MAT string and a plurality of second MAT strings for outputting a second data group, and the first data group and the second data group share the MAT as a boundary. 2. The semiconductor memory device according to claim 1, wherein a plurality of second MAT columns for outputting the second data group are inserted between a plurality of first MAT columns for outputting a data group.

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