JP4368477B2 - Mute circuit, electronic device and mute method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mute circuit, and more particularly to a mute circuit of a digital device, and more particularly to a mute circuit applied to an electronic device in which a digital part and an analog part are mixed. The present invention preferably relates to a mute circuit applied to an oversampling D / A converter that converts a digital signal into an analog signal.
[0002]
[Prior art]
In recent years, audio D / A converters are mainly D / A converters using oversampling techniques because of their good linearity, smooth waveforms, and high S / N ratio.
This oversampling D / A converter, for example, increases the sampling frequency of an input 16-bit digital signal by a digital filter or a sample and hold circuit to 8 times or 64 times, and converts the digital signal into a digital delta signal. Noise shaping with a sigma (ΔΣ) modulation circuit to quantize noise in the high frequency range, convert it to a 1-bit or several-bit signal, convert this signal to an analog signal, and then convert the high-frequency noise contained in the analog signal Is cut with an analog low-pass filter.
[0003]
Conventionally, when such an oversampling D / A converter is muted, for example, an output terminal connected to an analog ground terminal with a switch or the like, a digital signal multiplied by zero to attenuate the signal, or A device that attenuates the level of a signal using an up / down counter is known.
[0004]
[Problems to be solved by the invention]
By the way, when the D / A converter as described above is driven by a battery, it is necessary to reduce power consumption in order to use it for a long time. In order to reduce the power consumption, there are cases where power is supplied from the power supply for each block and power is not supplied to unnecessary blocks, or power is not consumed (power down mode).
[0005]
In the former case, if the supply of power from the power supply is suddenly stopped, the signal state changes abruptly, and a click sound (abnormal sound called a “bottom”) is generated.
For example, even if the output terminal of the D / A converter is fixed to a predetermined level, if the former power supply cut or the latter power down mode is entered, the output terminal level cannot be controlled and the voltage fluctuates. As a result, the click sound cannot be eliminated.
[0006]
Further, even when a digital code that becomes 0V is input to the D / A converter, a voltage of several mV may be output, which may cause a click sound when the power is turned off or in the power down mode.
Furthermore, even if the level is lowered while the input signal is fluctuating, the input signal may fluctuate abruptly. In this case, there is an inconvenience that a click sound is similarly generated.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a mute circuit and an electronic device that do not generate a click sound even when the power is turned off.
Another object of the present invention is to provide a mute circuit and an electronic device that do not generate click sound or noise even when an input signal fluctuates.
Furthermore, another object of the present invention is to provide a mute circuit and an electronic device that can be smoothly changed when the signal level is lowered to suppress the generation of noise.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, each invention described in claims 1 to 7 is configured as follows.
The invention according to claim 1 is used in an electronic apparatus for handling a coded digital signal, and the level of the digital signal is Down In a mute circuit that performs muting, the code range of the digital signal is made wider than that during normal operation. The electric It is characterized in that it is lowered to a code below the voltage level when the source is off.
[0009]
As described above, according to the first aspect of the present invention, during normal operation, for example, a digital signal corresponding to ± 0.5 V centered on 0.6 V is output. On the other hand, at the time of mute, the level of the digital signal is set higher than that at the time of normal operation, for example, 0 V or less. For this reason, since the output can be fixed to the ground potential when muted, the click sound can be prevented even if the power is turned off during the mute, and the click sound and noise associated with the fluctuation can be prevented even if the input signal fluctuates. Occurrence can be prevented.
[0010]
According to a second aspect of the present invention, a gain mute circuit for performing mute by multiplying an input digital signal by a coefficient and gradually making the coefficient zero, and an output from the gain mute circuit are input. The level of the digital signal multiplied by the zero voltage level when the power is turned off Lower level And a level mute circuit for performing mute by subtracting up to.
[0011]
Thus, in the second aspect of the invention, the gain mute circuit performs muting by multiplying the input digital signal by the coefficient and gradually reducing the coefficient to zero. The level mute circuit receives the output from the gain mute circuit, and sets the digital signal level multiplied by zero to the voltage level when the power is turned off. Lower level Subtract until mute.
[0012]
For this reason, when the present invention is applied to a D / A converter or the like, the output can be fixed to the ground potential or lower during mute, so that a click sound can be prevented even when the power is turned off during mute. Even if the input signal fluctuates, it is possible to prevent the occurrence of click sound and noise associated with the fluctuation.
Further, according to a third aspect of the present invention, in the mute circuit according to the second aspect, the digital signal is complemented by increasing a sampling frequency of the digital signal between the gain mute circuit and the level mute circuit. An interpolation filter is provided.
[0013]
Thus, according to the third aspect of the present invention, an interpolation filter is provided between the gain mute circuit and the level mute circuit, and the output level is changed by the level mute circuit after increasing the sampling rate. Yes. For this reason, the step width of the digital signal is reduced, and when the signal level is gradually lowered, the occurrence of noise can be suppressed by smoothly changing.
[0014]
According to a fourth aspect of the present invention, there is provided an electronic apparatus including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal. The digital unit reads the code of the digital signal into a voltage level when the electronic device is turned off. Lower code The analog unit includes an analog mute circuit that performs mute to fix the output terminal of the analog unit to the voltage level when the power is turned off, and performs the mute. The digital mute circuit includes a mute control unit that performs a mute operation and performs a mute operation of the analog mute circuit after the completion of the operation.
[0015]
Thus, in the invention according to claim 4, the digital mute circuit converts the code of the digital signal into the voltage level when the power source of the electronic device is turned off. Lower code The analog mute circuit mutes the output terminal of the analog unit at the voltage level when the power is turned off. For this reason, even when the power is turned off in the mute state, the generation of a click sound can be reliably prevented, and the generation of a click sound and noise associated with the fluctuation can be prevented even if the input signal fluctuates.
[0016]
Further, the invention described in claim 5 is an electronic device including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal. The digital unit inputs a gain mute circuit that performs muting by multiplying the input digital signal by a coefficient and gradually sets the coefficient to zero, and an output from the gain mute circuit. The level of the multiplied digital signal is the voltage level when the power is turned off. Lower level A level mute circuit that performs mute by gradually lowering to a level, and the analog unit includes an analog mute circuit that performs mute to fix the output terminal of the analog unit to a voltage level when the power is turned off, and mute In operation, a mute control unit is provided for performing each mute operation in the order of the gain mute circuit, the level mute circuit, and the analog mute circuit, and then turning off the power to the analog unit. It is a feature.
[0017]
Thus, in the fifth aspect of the present invention, the gain mute circuit performs muting by multiplying the input digital signal by a coefficient and gradually reducing the coefficient to zero, and the level mute circuit includes the gain mute circuit. Input the output from the digital signal level multiplied by its zero voltage level when the power is off Lower level Mute by gradually lowering until. The analog mute circuit performs mute to fix the output terminal of the analog unit to the voltage level when the power is turned off. Further, the mute control unit performs the mute operation in the order of the gain mute circuit, the level mute circuit, and the analog mute circuit in the mute operation, and then turns off the power to the analog unit.
[0018]
Therefore, according to the present invention, even when the analog section is turned off in the mute state, the generation of a click sound can be reliably prevented, and even if the input signal fluctuates, the click sound and noise associated with the fluctuation are generated. Can be prevented.
According to a sixth aspect of the present invention, in the electronic device according to the fifth aspect, the digital unit increases the sampling frequency of the digital signal between the gain mute circuit and the level mute circuit. An interpolation filter for complementing the digital signal is provided.
[0019]
Thus, according to the sixth aspect of the present invention, the interpolation filter is provided between the gain mute circuit and the level mute circuit, and the output level is changed by the level mute circuit after increasing the sampling rate. Yes. For this reason, the step width of the signal is reduced, and when the signal level is gradually lowered, the occurrence of noise can be suppressed by smoothly changing. The present invention is preferably applied to an oversampling D / A converter.
[0020]
Furthermore, the invention according to claim 7 is input to an electronic device including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal. A method for muting an electronic device that performs muting of a digital signal, wherein a gain is obtained by multiplying a digital signal input to the digital unit by a coefficient and gradually reducing the coefficient to zero during a mute operation. The step of performing the mute and the level of the digital signal after the gain mute is set to the voltage level when the electronic device is turned off Lower level The mute operation is canceled by the step of gradually lowering the output to the analog unit, the step of performing analog mute to fix the output terminal of the analog unit to the voltage level when the power is turned off, and the step of turning off the power of the analog unit. When turning on, the step of turning on the power of the analog unit, the step of releasing the output terminal of the analog unit from the fixed voltage level, and the step of releasing the level mute by gradually increasing the level of the digital signal And a step of gradually increasing a coefficient to be multiplied with the digital signal to cancel the gain mute.
[0021]
Thus, according to the method of the invention described in claim 7, even if the power supply of the power supply analog unit is turned off in the mute state, the generation of the click sound can be surely prevented, and even if the input signal fluctuates, It is possible to reliably prevent the generation of click sounds and noise associated with fluctuations.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
A case where the mute circuit of the present invention is applied to an oversampling D / A converter which is an electronic device will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an oversampling D / A converter.
[0023]
As shown in FIG. 1, the D / A converter receives a digital part 1 that receives a digital signal and performs a predetermined process, and inputs a digital signal output from the digital part 1 to convert it into an analog signal. An analog unit 2, a mute control unit 3 that controls the mute operation as described later, a power source 4 that supplies power to the digital unit 1 and the analog unit 2, and a power source that controls connection between the analog unit 2 and the power source 4 And at least a supply control unit 5. In the following example, the power supply 4 is assumed to output a voltage Vdd with reference to the ground potential Vss.
[0024]
As shown in FIG. 1, the digital unit 1 includes at least a gain mute circuit 11, a digital filter 12, a level mute circuit 13, a sample hold circuit 14, and a delta sigma modulation circuit 15.
As shown in FIG. 1, the analog unit 2 includes at least a switched capacitor D / A conversion circuit 21, an analog signal low-pass filter (LPF) 22, and an analog mute circuit 23.
[0025]
The mute control unit 3 controls the mute operation of the gain mute circuit 11, the level mute circuit 13, and the analog mute circuit 23, and the power supply control unit 5 connects the analog unit 2 to the power source 4 as will be described later. Instructions are given when doing.
The power supply 4 is for supplying electric power to each part of the digital part 1 and the analog part 2. The power supply control unit 5 controls the connection between the analog unit 2 and the power supply 4 based on an instruction from the mute control unit 3.
[0026]
The gain mute circuit 11 passes the input digital signal as it is in the next stage during normal operation, and performs muting by multiplying the digital signal by a coefficient and gradually reducing the coefficient to zero during the mute operation. It has become.
Here, the digital signal input to the gain mute circuit 11 is, for example, 20-bit data with a sampling frequency Fs of 48 KHz.
[0027]
The digital filter 12 is an interpolation that complements the digital signal by multiplying the sampling frequency Fs of the digital signal output from the gain mute circuit 11 by eight.
The level mute circuit 13 passes the input digital signal as it is to the next stage during normal operation, and subtracts the level of the digital signal to the voltage level when the power is turned off during the mute operation.
[0028]
The sample hold circuit 14 further increases the output of the digital filter 13 by 8 times, and outputs a digital signal having a sampling frequency Fs of 64 times.
The delta sigma modulation circuit 15 quantizes the digital signal from the sample hold circuit 14. The switched capacitor D / A conversion circuit 21 converts the digital signal quantized by the delta-sigma modulation circuit 15 into an analog signal. Here, the analog signal converted by the delta-sigma modulation circuit 15 has quantization noise in a high frequency region due to noise shaping. Therefore, the low pass filter 22 cuts the quantization noise.
[0029]
The analog mute circuit 23 is composed of a switch 231 provided between the output terminal of the analog unit 2 and the ground potential, and closes the contact and fixes the output terminal of the analog unit 2 to the ground potential Vss during the mute operation. It has become.
Next, the configuration of the gain mute circuit 11, the level mute circuit 13, and the low-pass filter 22 will be described with reference to FIGS.
[0030]
The gain mute circuit 11 includes a multiplier circuit 111 and a gain mute coefficient generation circuit 112 as shown in FIG. During the mute operation, the gain mute coefficient generation circuit 112 generates a predetermined coefficient, and the multiplication circuit 11 multiplies the generated digital signal by the generated coefficient and outputs the multiplication result. It has become.
[0031]
As shown in FIG. 3, the level mute circuit 13 includes an addition / subtraction circuit 131 and a level mute value generation circuit 132. During the mute operation, the level mute value generation circuit 132 generates a predetermined level mute value, and the addition / subtraction circuit 131 adds or subtracts the generated level mute value to the input digital signal. Yes.
[0032]
As shown in FIG. 4, the low-pass filter 22 includes an operational amplifier 221, resistors R1 and R2, a capacitor C1, and the like, and a switch 231 of an analog mute circuit 23 is connected to an output terminal thereof.
Next, an example of the operation of the D / A converter according to this embodiment having such a configuration will be described with reference to the drawings.
[0033]
First, the case of normal operation will be described. During this normal operation, the gain mute circuit 11 and the level mute circuit 13 do not perform the mute operation, so that the input digital signal is output as it is in both circuits 11 and 13. Further, the contact of the switch 231 of the gain mute circuit 23 remains open as shown in FIG.
[0034]
When a digital signal is input to the gain mute circuit 11 during normal operation, the digital signal is output from the gain mute circuit 11 as it is and input to the digital filter 12, and the sample frequency Fs is interpolated (digital). Complemented). When this interpolated signal is input to the level mute circuit 13, it is output as it is, and the sampling and holding circuit 14 further multiplies the sampling frequency Fs by 8 and outputs a digital signal having a sampling frequency Fs of 64 times. .
[0035]
The digital signal output from the sample hold circuit 14 is quantized by the delta sigma modulation circuit 15. The quantized digital signal is converted into an analog signal by the switched capacitor D / A conversion circuit 21. Quantization noise included in the analog signal is cut by the low-pass filter 22 and a desired analog signal is output.
[0036]
Next, the operation of each unit during the mute operation will be described with reference to FIGS.
As shown in FIG. 5, before the time t1, the above-mentioned normal operation is performed, and when a full-scale sine wave is output (for example, ± 0.5V output centering on 0.6V). As shown in FIG. 5A, the output of the level mute circuit 13 generates digital values (data corresponding to 16 bits) of +340902 to -340903, for example. Note that FIG. 5A should be expressed as a digital value, but an analog waveform is used for easy explanation.
[0037]
When the mute signal output from the mute controller 3 changes from the “L” level to the “H” level at time t1, the mute operation starts. First, in the period T1 from time t1 to time t2, the gain mute circuit 11 Gain mute is performed. That is, the gain mute circuit 11 gradually decreases the digital value (amplitude level) corresponding to the input full-scale sine wave during the period T1 (for example, 25 mSec), and sets the digital code to “0” (FIG. 5 (A)).
[0038]
More specifically, as shown in FIG. 2, the gain mute coefficient generation circuit 112 generates a gain mute coefficient and gradually reduces the generated gain mute coefficient. " The multiplication circuit 111 multiplies the code of the input digital signal by the gain mute coefficient, and the digital code finally becomes “0”.
[0039]
Next, at time t2, the level mute circuit 13 starts a level mute operation, and this level mute operation is performed during a period T2 (eg, 500 mSec) from time t2 to time t3. That is, the level mute circuit 13 subtracts the level of the input digital signal to a level lower than the voltage level when the power is turned off during the period T2.
[0040]
More specifically, as shown in FIG. 3, the level mute value generation circuit 132 generates a level mute value, and this level mute value is input to the addition / subtraction circuit 131. The addition / subtraction circuit 131 subtracts the level mute value from the input digital signal data “0” (this subtraction value gradually increases). As shown in FIG. The value of the output data finally becomes “−480560”. This final value corresponds to an analog value of −0.1 V, for example.
[0041]
Next, when the time t3 is reached, the contact of the switch 231 of the analog mute circuit 23 is closed and the analog mute operation state is entered, whereby the output terminal of the analog unit 2 becomes the ground potential Vss. When the contact of the switch 231 is closed, the output of the analog unit 2 is at the ground potential Vss, so that no noise is generated from the speaker connected to the subsequent stage of the analog unit 2.
[0042]
After the contact of the switch 231 of the analog mute circuit 23 is closed, the power supply control unit 5 releases the electrical connection between the power source 4 and the analog unit 2 based on an instruction from the mute control unit 3. Turn off the power. At this time, since the output of the analog unit 2 is fixed to the ground potential Vss, no click sound (abnormal sound) is generated from the speaker connected to the subsequent stage of the analog unit 2.
[0043]
The procedure during the mute operation described above is summarized as steps S1 to S4 in the flowchart shown in FIG.
Next, the mute release operation will be described with reference to FIGS.
When the mute signal output from the mute controller 3 changes from the “H” level to the “L” level at time t4, the mute release operation is started. First, based on an instruction from the mute control unit 3, the power supply control unit 5 performs electrical connection between the power source 4 and the analog unit 2, and turns the power of the analog unit 2 from off to on. After the analog unit 2 is turned on, the contact of the switch 231 of the analog mute circuit 23 is opened to release the analog mute.
[0044]
Next, when the analog mute is released, in a period T3 from time t4 to time t5, the level mute circuit 13 gradually increases the level of the digital signal and performs the level mute release operation. That is, the level mute value generation circuit 132 generates a level mute value, and this level mute value is input to the addition / subtraction circuit 131. The addition / subtraction circuit 131 adds the level mute value to the input digital signal data “0” (this addition value gradually decreases). For this reason, as shown in FIG. 5B, the value of the output data of the addition / subtraction circuit 131 gradually increases from “−450560” and finally becomes “0”.
[0045]
Next, when the level mute is released, in a period T4 from time t5 to time t6, the gain mute circuit 11 gradually increases the coefficient by which the digital signal is multiplied to release the gain mute. That is, the gain mute coefficient generation circuit 112 gradually increases the coefficient, and this coefficient is input to the multiplication circuit 111. The multiplier circuit 111 multiplies the code of the input digital signal by its coefficient, and the digital code finally becomes a predetermined value. When the time t6 is reached, the mute release operation is completed and the normal operation is resumed.
[0046]
The procedure of the mute release operation described above is summarized as steps S11 to S14 of the flowchart shown in FIG.
As described above, in the D / A converter according to this embodiment, the range of the code of the digital signal is set wider than that during normal operation, and the code of the digital signal is set higher than the voltage level when the power is turned off during the mute operation. I try to lower the code below. That is, the analog unit 2 outputs ± 0.5 V, for example, centering on 0.6 V during normal operation. On the other hand, at the time of mute operation, the code of the digital signal is made larger than that at the time of normal operation, and the output level of the digital signal is lowered to 0V or lower (for example, −0.1V). For this reason, the output can be fixed to the ground potential when muted, so that it is possible to reliably prevent the occurrence of a clicking sound even when the power is turned off during muting. Occurrence can be reliably prevented.
[0047]
In the D / A converter according to this embodiment, the digital unit 1 includes a gain mute circuit 11 and a level mute circuit 13 as mute circuits, and the gain mute circuit 11 and the level mute circuit 13 are interpolated. A digital filter 12 is provided to increase the sampling frequency of the digital signal, and then the level of the digital signal is decreased by the level mute circuit 13. For this reason, the step width of the digital signal is reduced, and the level can be smoothly lowered.
[0048]
In the above description, the power supply is turned off. However, the same operation can be performed when the power down mode is set.
[0049]
【The invention's effect】
As described above, according to the mute circuit of the present invention, the output at the time of mute can be fixed to the ground potential. Therefore, even when the power is turned off at the time of mute, the generation of the click sound can be prevented and the input signal fluctuates. However, it is possible to prevent the generation of click sound and noise associated with the fluctuation.
[0050]
Further, in the mute circuit of the present invention, when an interpolation filter is provided between the gain mute circuit and the level mute circuit, the step width of the digital signal becomes small, and when the signal level is gradually lowered, The occurrence of noise can be suppressed by changing to.
According to the electronic device of the present invention, since the output at the time of mute can be fixed to the ground potential, it is possible to reliably prevent the generation of a click sound even when the analog unit is turned off in the mute state, and the input signal fluctuates. However, it is possible to prevent the generation of click sound and noise associated with the fluctuation.
[0051]
Further, in the electronic device of the present invention, when an interpolation filter is provided between the gain mute circuit and the level mute circuit, the signal step width is reduced, and when the signal level is gradually lowered, The noise can be suppressed by changing.
According to the mute method of the present invention, even when the power supply of the power supply analog unit is turned off in the mute state, it is possible to reliably prevent the generation of a click sound, and also the click sound and noise associated with the fluctuation even if the input signal fluctuates. Can be reliably prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram of an oversampling D / A converter to which an embodiment of a mute circuit of the present invention is applied.
FIG. 2 is a block diagram showing a configuration of a gain mute circuit.
FIG. 3 is a block diagram showing a configuration of a level mute circuit.
FIG. 4 is a circuit diagram showing a configuration of a low-pass filter and an analog mute circuit.
FIG. 5 is a waveform diagram for explaining operations of a gain mute circuit and a level mute circuit.
FIG. 6 is a flowchart illustrating an example of a mute operation.
FIG. 7 is a flowchart illustrating an example of a mute release operation.
[Explanation of symbols]
1 Digital part
2 Analog part
3 Mute controller
4 Power supply
5 Power supply control unit
11 Gain mute circuit
12 Digital filter
13 level mute circuit
14 Sample hold circuit
15 Delta-sigma modulation circuit
21 Switched capacitor D / A converter circuit
22 Low-pass filter
23 Analog mute circuit
111 Multiplier circuit
112 Gain mute coefficient generation circuit
131 Addition / subtraction circuit
132 level mute value generation circuit

Claims (7)

Is used in an electronic device handling the coded digital signal, the mute circuit that performs down Gaité muting the level of the digital signal,
The scope of the code of the digital signal leave wider than the normal operation, when performing the muting, that it has to be lowered until the code below the voltage level in the off code the power of the digital signal A featured mute circuit. A gain mute circuit that performs muting by multiplying the input digital signal by a coefficient and gradually reducing the coefficient to zero;
A level mute circuit for inputting the output from the gain mute circuit and subtracting the level of the digital signal multiplied by zero to a level lower than the voltage level when the power is turned off. A mute circuit characterized by   3. The mute circuit according to claim 2, further comprising an interpolation filter between the gain mute circuit and the level mute circuit to increase the sampling frequency of the digital signal and complement the digital signal. . An electronic device including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal,
The digital unit includes a digital mute circuit that performs mute by lowering the code of the digital signal to a code lower than the voltage level when the electronic device is powered off,
The analog unit includes an analog mute circuit that performs mute to fix an output terminal of the analog unit to a voltage level when the power is turned off.
An electronic apparatus comprising: a mute control unit that performs a mute operation of the digital mute circuit when the mute is performed and performs a mute operation of the analog mute circuit after the operation is completed. An electronic device including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal,
The digital unit multiplies the input digital signal by multiplying the coefficient and gradually mutes the coefficient by zeroing the gain mute circuit that receives the output from the gain mute circuit. A level mute circuit that performs mute by gradually lowering the level of the digital signal to a level below the voltage level when the power is turned off,
The analog unit includes an analog mute circuit that performs mute to fix an output terminal of the analog unit to a voltage level when the power is turned off.
In addition, a mute control unit is provided for causing the mute operation to be performed in the order of the gain mute circuit, the level mute circuit, and the analog mute circuit in the mute operation, and then turning off the power to the analog unit. An electronic device characterized by comprising:   The digital unit includes an interpolation filter between the gain mute circuit and the level mute circuit to increase the sampling frequency of the digital signal and complement the digital signal. 5. The electronic device according to 5. An electronic device for muting a digital signal input to an electronic device including a digital unit that processes a coded digital signal and an analog unit that converts the digital signal processed by the digital unit into an analog signal A mute method,
In the mute operation, a step of performing gain mute by multiplying a digital signal input to the digital unit by a coefficient and gradually reducing the coefficient to zero, and a level of the gain-muted digital signal is set to the electronic A step of gradually lowering to a level lower than a voltage level at the time of power-off of the device; a step of performing analog mute for fixing an output terminal of the analog unit at a voltage level at the time of power-off; and a power source of the analog unit And the step of turning off
When releasing the mute operation, a step of turning on the power supply of the analog unit, a step of releasing the output terminal of the analog unit from the fixed voltage level, and a level mute by gradually increasing the level of the digital signal And a step of releasing gain mute by gradually increasing a coefficient to be multiplied by the digital signal.

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