JP4363965B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a BGA (Ball Grid Array) type semiconductor device having ball-shaped conductive terminals.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and as a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When this BGA type semiconductor device is incorporated into an electronic device, each conductive terminal is crimped to a wiring layer pattern on the printed circuit board to electrically connect the semiconductor chip and the external circuit mounted on the printed circuit board. Connected to.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 10 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 10A is a perspective view of the surface side of this BGA type semiconductor device. FIG. 10B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. On one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101, a plurality of ball-shaped terminals (hereinafter referred to as conductive terminals 106) are arranged in a lattice pattern.

  The conductive terminal 106 is connected to the semiconductor chip 104 through the second wiring layer 110. An aluminum wiring layer drawn from the inside of the semiconductor chip 104 is connected to each of the plurality of second wiring layers 110, and electrical connection between each conductive terminal 106 and the semiconductor chip 104 is made.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 11 shows a cross-sectional view of a BGA type semiconductor device 101 divided into individual chips along a dicing line.

  A first wiring layer 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 with a resin 105a. The back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 with a resin 105b.

One end of the first wiring layer 107 is connected to the second wiring layer 110. The second wiring layer 110 extends from one end of the first wiring layer 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring layer 110 extending on the second glass substrate 103.
Patent Publication 2002-512436

  In the BGA type semiconductor device 101 described above, the protective film 111 is formed on the surface of the semiconductor device having the V-shaped groove VG using an organic resin before the dicing step (FIG. 12A). reference). As a method of forming the protective film 111, the semiconductor wafer 104 is rotated by podding (dropping) a thermosetting organic resin from above with the back side of the semiconductor chip 104 facing upward. A method has been adopted in which the protective film 111 is formed on the surface of the second wiring layer 110 using centrifugal force.

However, in this method, as shown in FIG. 12A, the thermosetting organic resin accumulates more than necessary at the bottom of the V-shaped groove VG of the dicing line (broken line in the figure). This is because the organic resin has a viscous paste property. Therefore, the protective film 11
When 1 is thermally cured by baking (heat treatment), the organic resin accumulated in the V-shaped groove VG contracts more than the organic resin covering the other part of the semiconductor device 101. As a result, the V-shaped groove VG is further contracted, and there is a problem that a semiconductor wafer that becomes an individual semiconductor chip later warps (warping occurs in the arrow direction in FIG. 12B). .

  A semiconductor wafer having such a warp has hindered subsequent manufacturing processes. In particular, in the process of reflowing (high-temperature treatment) the conductive terminal 106 (so-called bump electrode) made of a conductive material having heat fluidity such as solder, the entire semiconductor wafer cannot be heated uniformly, causing a problem in reliability. There was a fear.

  For example, as shown in FIG. 13, when the conductive terminal 106 is reflowed, the warped semiconductor wafer 124 is mounted on the stage 123 in the reflow apparatus 120. The reflow apparatus 120 is adjusted to a predetermined temperature by the downward heat radiation line a from the IR heater 121 provided on the ceiling and the upward heat radiation line b from the hot plate 122 provided under the stage 123. Maintained. The arrows in FIG. 13 schematically represent the heat radiation line a and the heat radiation line b. A broken-line circle in the figure shows the warp formed at the end of the semiconductor wafer 124, and FIG. 14 shows an enlarged view in the broken-line circle.

  As shown in FIG. 14, the semiconductor wafer 124 includes a flat portion (hereinafter referred to as a flat portion 125) and a warped portion (hereinafter referred to as a warped portion 126) at the end thereof. The flat portion 125 is in direct contact with the lower stage 123 (hereinafter referred to as a direct contact portion 127). On the other hand, since the warped portion 126 is warped, it does not directly contact the stage 123. If the reflow of the conductive terminal 106 is performed in this state, the direct contact portion 127 may be heated to a temperature higher than necessary by the hot plate 122.

  On the other hand, in the curvature part 126, the thermal radiation a1 and the thermal radiation a2 from IR heater (infrared heater) arrange | positioned upwards are applied. The heat radiation line a1 heats the end of the semiconductor wafer 124, and the heat radiation line a2 heats the inner part. A slight intensity difference is generated between the heat radiation a1 and the heat radiation a2, and it is difficult to heat the semiconductor wafer 124 uniformly.

  Further, a slight difference in intensity occurs between the thermal radiation b1 and the thermal radiation b2 from below. The thermal radiation b1 is applied below the end of the semiconductor wafer 124, and the thermal radiation b2 is applied below the semiconductor wafer 124 close to the flat portion 125.

  For this reason, a temperature difference occurs between the warped portion 126 and the flat portion 125 of the semiconductor wafer 124. As described above, when a temperature difference occurs depending on the location of the semiconductor wafer 124, it becomes difficult to form the plurality of conductive terminals 106 having a uniform shape on the semiconductor wafer 124. As a result, the yield and reliability of the semiconductor device are increased. The performance was significantly reduced.

  The present invention eliminates the influence of the warpage of the semiconductor wafer that occurs during the manufacturing process of the BGA type semiconductor device on the reflow process of the conductive terminals, and improves the yield and reliability of the semiconductor device.

Accordingly, a method for manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor wafer having a first wiring layer formed on a surface thereof, and affixing a first support substrate to the surface of the semiconductor wafer, and the semiconductor wafer. Attaching a second support substrate to the back surface of the semiconductor wafer, forming a groove on the back surface of the semiconductor wafer, partially exposing the first wiring layer, and exposing an exposed portion of the first wiring layer Forming a second wiring layer connected to and extending on a surface of the second support substrate; forming a conductive terminal having heat fluidity on the second wiring layer; and the semiconductor wafer. And a reflow step of reflowing the conductive terminals by supporting the surface of the semiconductor wafer by a plurality of pins erected from the heating stage and making the first heater face the back surface of the semiconductor wafer. When That.
In the reflow process, the heating stage is heated by a heating plate in contact with a lower surface thereof.
Further, in the reflow step, a second heater is opposed to the side surface of the semiconductor wafer, and the semiconductor wafer is heated by the second heater.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor wafer having a first wiring layer formed on a surface thereof; attaching a support substrate to the surface of the semiconductor wafer; Forming a groove to partially expose the first wiring layer; and forming a second wiring layer connected to the exposed portion of the first wiring layer and extending to the back surface of the semiconductor wafer. A step of forming a conductive terminal having heat fluidity on the second wiring layer, a surface of the semiconductor wafer supported by a plurality of pins erected from a heating stage, and a back surface of the semiconductor wafer And a reflow step of reflowing the conductive terminal by making the first heater face the surface.
Furthermore, in the reflow step, the heating stage is heated by a heating plate in contact with the lower surface thereof.
In the reflow process, a second heater is opposed to the side surface of the semiconductor wafer, and the semiconductor wafer is heated by the second heater.

  According to such a configuration, even if the semiconductor wafer is warped, the entire semiconductor wafer can be heated uniformly, and a plurality of conductive terminals having a uniform shape can be formed over the entire surface of the semiconductor wafer. . Thus, the yield and reliability of the BGA type semiconductor device can be improved.

  According to the present invention, a plurality of conductive terminals on a warped semiconductor wafer can be uniformly reflowed. Thus, the yield and reliability of the BGA type semiconductor device can be improved.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, a semiconductor wafer 1a is prepared. The semiconductor wafer 1a is divided into a plurality of semiconductor chips 1 along a boundary line S (called a dicing line or a scribe line).

  These semiconductor chips 1 are, for example, chips for CCD image sensors, and are formed by a semiconductor wafer process. An insulating film 2 is formed on the semiconductor wafer 1 a, and a pair of first wiring layers 3 are formed on the insulating film 2. The pair of first wiring layers 3 is formed by sputtering a metal layer on the entire surface and selectively etching the metal layer. The thickness of the pair of first wiring layers 3 is about 1 μm.

  The pair of first wiring layers 3 are formed to face both sides of the boundary line S. The pair of first wiring layers 3 are pads extended from the bonding pad of the semiconductor chip 1 to the boundary line S. That is, the pair of first wiring layers 3 are external connection pads and are electrically connected to a circuit (not shown) of the semiconductor chip 1.

  Next, as shown in FIG. 2, a first glass substrate 4 as a support substrate having a thickness of about 200 μm is formed on a surface of the semiconductor wafer 1a on which the first wiring layer 3 is formed from a transparent epoxy material. The resulting resin layer 5a is attached as an adhesive. Then, the back surface of the semiconductor wafer 1a is back-ground to reduce the chip thickness to about 100 μm, and then the semiconductor wafer 1a is dry-etched along the boundary line S from the back surface side to expose the insulating film 2.

  The semiconductor wafer 1a is once separated into individual semiconductor chips 1 by this dry etching, but these semiconductor chips 1 are supported by a first glass substrate 4 and form a single semiconductor wafer 1a as a whole. Have.

  Next, as shown in FIG. 3, a second glass substrate 6 as a supporting substrate having a film thickness of about 100 μm is attached to the back side of the semiconductor chip 1 using the resin layer 5b as an adhesive. Note that the second glass substrate 6 may not be attached. Note that the support substrate may be made of a material other than glass.

  Next, as shown in FIG. 4A, a buffer member 7 made of a photosensitive organic film having flexibility is formed at a predetermined position on the flat portion of the second glass substrate 6. This buffer member 7 is for absorbing the force applied to the conductive terminal 9 to be described later and preventing the glass substrate from cracking.

  When the second glass substrate 6 is not attached to the back surface of the semiconductor chip 1, the buffer member 7 is formed on the back surface of the semiconductor chip 1. Thereafter, notching is performed along the boundary line S from the back surface side of the semiconductor chip 1. This notching is to perform cutting using a saw-like tool such as a blade from the back side of the semiconductor chip 1.

  This notching is performed from the second glass substrate 6 to the first glass substrate 4 to such an extent that the first glass substrate 4 is somewhat cut to expose the side surface portion of the first wiring layer 3. . By this notching, a V-shaped groove VG is formed along the boundary line S. At this time, the exposed surface may be contaminated by notching. Therefore, the exposed surface may be cleaned by dry etching or the like as necessary.

  Next, as shown in FIG. 4B, an aluminum layer having a thickness of about 3 μm is formed by sputtering so as to cover the second glass substrate 6 and the V-shaped groove VG formed by notching. To do. Thereafter, the aluminum layer is patterned into a predetermined wiring layer pattern to form a second wiring layer 8 that is electrically connected to the exposed side surface portion of the first wiring layer 3.

  The second wiring layer 8 extends on the surface of the second glass substrate 6 on the back surface of the semiconductor chip 1. On the second wiring layer 8 extending on the surface of the second glass substrate 6, a conductive terminal 9 described later is formed. When the second glass substrate 6 is not attached to the back surface of the semiconductor chip 1, the second wiring layer 8 extends to the back surface of the semiconductor chip 1.

  Next, as shown in FIG. 5, a protective film 10 is formed on the second wiring layer 8. The protective film 10 functions as a solder mask in a later screen printing process. As a method of forming the protective film 10, the semiconductor chip 1 is rotated by podding (dropping) a thermosetting organic resin from above with the back side of the semiconductor chip 1 facing upward. A protective film 10 is formed on the surface of the second wiring layer 8 using centrifugal force. This is the same process as that shown in FIG. The protective film 10 may be formed of a resist material.

  Thereafter, the protective film 10 is thermally cured by baking (heat treatment). By this baking, the semiconductor wafer is warped at its end. Next, an opening is formed in the protective film 10 so that the second wiring layer 8 is exposed in order to form a conductive terminal 9 to be described later at a predetermined position of the protective film 10 above the second glass substrate 6. . When the buffer member 7 is present, the opening is formed at a position corresponding to the buffer member 7.

  Thereafter, a conductive terminal 9 made of a material having heat fluidity, for example, solder is formed in the screen printing process, and the process proceeds to the next reflow process. The reflow process will be described with reference to FIGS. The conductive terminal 9 is fluidized by being subjected to a high temperature treatment by a reflow process described below. This is performed in order to process it into a spherical shape by utilizing the surface tension of the conductive terminal 9.

  As shown in FIGS. 6A and 6B, a stage 20 is prepared, and a plurality of pins 21 are erected on the stage 20. The semiconductor wafer 1a is mounted on the tips of these pins 21 so that the surface side is in contact therewith. These pins 21 all have the same length, and support the semiconductor wafer 1a along its edge. FIG. 6A is a perspective view showing the state, and FIG. 6B is a front view. As a result, the semiconductor wafer 1a is separated from the stage 20 by the length of the pins 21, and heat generated from the stage 20 is prevented from being directly applied to the semiconductor wafer 1a. An appropriate length of the pin 21 is about 1 mm.

  Next, as illustrated in FIG. 7A, the stage 20 on which the semiconductor wafer 1 a illustrated in FIGS. 6A and 6B is mounted is transferred into the reflow processing box 40 of the reflow apparatus 30. Here, a rotating belt 31 is provided below the reflow processing box 40, and a pair of pulleys (belt wheels) 32 are provided to rotate the rotating belt 31. A stage 20 on which the semiconductor wafer 1 a is mounted is placed on the belt 31. Then, by driving the pulley 32, the stage 20 on which the semiconductor wafer 1 a is mounted is conveyed into the reflow processing box 40 by the rotating belt 31.

The reflow process box 40 is formed of a heating zone 41 from the cooling zone 42. A plurality of IR heaters (infrared heaters) 45 are arranged on the ceiling of the heating zone 41. A plurality of hot plates 46 are arranged under the belt 31. FIG. 7B is a side view of FIG. 7A viewed from the arrow X side, and is an enlarged view of the inside of the reflow processing box 40.

  As shown in FIG. 7B, a plurality of side heaters 47 are arranged on both side surfaces of the reflow processing box 40. The side heater 47 faces the side surface of the semiconductor wafer 1a. The cooling zone 42 is a zone for cooling the semiconductor wafer 1a heated in the heating zone 41, and the IR heater 45, the hot plate 46, and the side heater 47 are not provided.

  Here, the example in which the semiconductor wafer 1a is transported integrally with the plurality of pins 21 has been disclosed, but these pins 21 may be installed in the heating zone 41. In this case, when the semiconductor wafer 1a is transported from the outside of the reflow processing box 40 and reaches the position on the pin 21, the pin 21 rises to lift the semiconductor wafer 1a. Then, the semiconductor wafer 1 a is heated in the heating zone 41 while being lifted on the pins 21. Thereafter, the pins 21 are lowered, and the semiconductor wafer 1 a is separated from the pins 21 and transferred to the cooling zone 42.

  Next, a reflow process using the reflow apparatus 30 will be described. As shown in FIGS. 7A and 7B, the semiconductor wafer 1a mounted on the stage 20 via the pins 21 is mounted on the belt 31 from the direction of the arrow X in the figure, and is a reflow processing box. It is conveyed into 40.

  As a result, the semiconductor wafer 1a is moved in three directions in the heating zone 41 of the reflow processing box 40 by three types of heaters: an IR heater 45 provided on the ceiling, a hot plate 46 provided below the belt 31, and a side heater 47. It will be heated from. Here, although the stage 20 is conveyed on the belt 31, it is heated by the hot plate 46 arrange | positioned under it. The time for the stage 20 to pass through the heating zone 41 is about 1 minute, and the heating temperature is about 220 ° C.

  After passing through the heating zone 41, the semiconductor wafer 1 a is cooled by the cooling zone 42. At this time, in the cooling zone 42, a device that actively cools, for example, an air cooling device may be provided. Thereafter, the semiconductor wafer 1a is unloaded from the reflow processing box 40 and then transferred to a dicing process.

  FIG. 8 is an enlarged view of the inside of the broken-line circle in FIG. The arrows in the figure schematically show a state in which the semiconductor wafer 1a is heated from three types of heaters. As shown in FIG. 8, in the heating zone 41, heat radiation rays A, B, C, D, and E are applied to the end of the semiconductor wafer 1a. The thermal radiation A is radiated from an IR heater installed above the box 40, the thermal radiation B and the thermal radiation C are radiated from the side heater 47, and the thermal radiation D is heated by the hot plate 46. Radiated from. Further, the heat radiation E is a heat radiation emitted from the side heater 47 reflected by the stage 20 and the belt 31.

  In the present embodiment, by providing side heaters 47 on both side surfaces of the reflow processing box 40, the surface of the warped portion of the semiconductor wafer 1a is heated by thermal radiation C (the right side heater 47 in FIG. 7B). The Similarly, the back surface of the semiconductor wafer 1a is heated by the heat radiation B (the left side heater 47 in FIG. 7B) and the heat radiation D (the lower hot plate 46 in FIG. 7B). Is done.

  The back surface side of the warped portion of the semiconductor wafer 1 a is heated by the heat radiation line E reflected from the stage 20 by the heat radiation line B emitted from the left side heater 47 in FIG. Conventionally, it has been difficult to heat this portion in the same manner as the flat portion of the semiconductor wafer 1a. However, this portion can be achieved by using the heat radiation E.

As described above, in this embodiment, the semiconductor wafer 1a is separated from the stage 20, and uniform radiation heat is applied to the entire warped semiconductor wafer 1a, so that the entire semiconductor wafer 1a has a uniform temperature. To be heated. Thereby, the reflow of the conductive terminals 9 formed over the entire surface of the semiconductor wafer 1a is performed uniformly, and the shape thereof is also uniform.
After the reflow process of the conductive terminal 9, dicing is performed along the boundary line S as shown in FIG. Thus, a BGA type semiconductor device is completed.

  According to the embodiment of the present invention, when the reflow (high heat treatment) process is performed after the conductive terminals 9 are formed by screen printing, the plurality of pins 21 are arranged on the stage 20 of the reflow apparatus 30, and the semiconductor wafer 1a is heated with these pins 21 being supported.

Thereby, the semiconductor wafer 1a is not directly heated by the hot plate 46 under the stage 20, and the heating state of the semiconductor wafer 1a can be made uniform. In addition, by arranging the side heaters 47 on both side surfaces of the reflow processing box 40 of the reflow apparatus 30, the front surface side and the back surface side of the warped portion of the end portion of the semiconductor wafer 1a can be uniformly heated.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is the perspective view and side view of the reflow apparatus which concern on embodiment of this invention. It is a side view of the reflow apparatus which concerns on embodiment of this invention. It is a figure which shows the heating state by the reflow apparatus which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a perspective view which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the heating state of the reflow apparatus of the conventional semiconductor device. It is an expanded sectional view which shows the reflow apparatus of the conventional semiconductor device.

Claims (6)

Preparing a semiconductor wafer having a first wiring layer formed on the surface;
Attaching a first support substrate to the surface of the semiconductor wafer;
Attaching a second support substrate to the back surface of the semiconductor wafer;
Forming a groove on a back surface of the semiconductor wafer to partially expose the first wiring layer;
Forming a second wiring layer connected to an exposed portion of the first wiring layer and extending to a surface of the second support substrate;
Forming a conductive terminal having heat fluidity on the second wiring layer;
A reflow process for supporting the surface of the semiconductor wafer by a plurality of pins erected from a heating stage and reflowing the conductive terminals by making a first heater face the back surface of the semiconductor wafer. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1, wherein in the reflow step, the heating stage is heated by a heating plate in contact with a lower surface thereof. 3. The manufacturing of a semiconductor device according to claim 1, wherein in the reflow step, a second heater is opposed to a side surface of the semiconductor wafer, and the semiconductor wafer is heated by the second heater. Method. Preparing a semiconductor wafer having a first wiring layer formed on the surface;
Attaching a support substrate to the surface of the semiconductor wafer;
Forming a groove on a back surface of the semiconductor wafer to partially expose the first wiring layer;
Forming a second wiring layer connected to the exposed portion of the first wiring layer and extending to the back surface of the semiconductor wafer;
Forming a conductive terminal having heat fluidity on the second wiring layer;
A reflow process for supporting the surface of the semiconductor wafer by a plurality of pins erected from a heating stage and reflowing the conductive terminals by making a first heater face the back surface of the semiconductor wafer. A method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the reflow step, the heating stage is heated by a heating plate in contact with a lower surface thereof. 6. The semiconductor device manufacturing method according to claim 4, wherein, in the reflow process, a second heater is opposed to a side surface of the semiconductor wafer, and the semiconductor wafer is heated by the second heater. Method.

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