JP4357691B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus that generates a JPEG encoded signal from an output signal of a CCD solid-state imaging device.
[0002]
[Prior art]
In recent years, in the digital still camera industry, the demand for high-speed JPEG encoding processing of high-pixel images accompanying the increase in the number of pixels of a CCD solid-state imaging device and the continuous shooting function similar to that of a silver salt camera are increasing for digital still cameras. Yes. Further, if the continuous shooting function increases the number of continuous shots and performs processing at high speed, it is becoming a problem that a memory area proportional to the number of continuous shots in the system is required.
[0003]
Hereinafter, the configuration of a conventional imaging device will be described. FIG. 15 is a block diagram showing a process for generating a JPEG encoded signal from an output signal of a CCD solid-state imaging device in a conventional imaging apparatus. In FIG. 15, 101 is a timing generator, 102 is a CCD solid-state imaging device, 103 is a correlated double sampling circuit, 104 is an A / D conversion circuit, 200 is a memory controller, 300 is a memory such as a DRAM, 400 is a Y / C signal A generation unit (hereinafter referred to as “Y / C processing unit”), 500 is a JPEG compression / decompression processing unit (hereinafter referred to as “JPEG processing unit”), and 501 is a JPEG block read control unit. The memory controller 200 includes a memory write controller 201 and a memory read controller 202.
[0004]
The operation of generating a JPEG encoded signal from the output signal of the CCD solid-state image sensor 102 in the conventional imaging apparatus configured as described above will be described.
[0005]
First, the vertical transfer CCD and horizontal transfer CCD in the CCD solid-state imaging device 102 are continuously driven by the vertical transfer pulse and horizontal transfer pulse of the timing generator 101. The horizontal transfer pulse output from the timing generator 101 is directly input to the CCD solid-state image sensor 102, but the vertical transfer pulse is subjected to high level conversion by the V driver 105 and input to the CCD solid-state image sensor 102. When the timing generator 101 receives an “acquisition command signal” which is an external input signal such as a shutter in a silver halide camera, a photodiode readout pulse (hereinafter referred to as “PD readout”) after an exposure period corresponding to a predetermined shutter speed. 7) is output to the V driver 105. Therefore, the timing generator 101 outputs the PD read pulse 7 and the vertical transfer pulse to the V driver 105 when receiving the fetch command signal. In the V driver 105, the vertical transfer pulse and the PD read pulse 7 are synthesized and output to the CCD solid-state imaging device 102.
[0006]
The configuration of the CCD solid-state imaging device 102 is shown in FIG. When the CCD solid-state imaging device 102 receives the PD readout pulse 7 (superimposed on the vertical transfer pulse) from the V driver 105, the CCD solid-state image sensor 102 moves the pixel charge from each photodiode 2 to the vertical transfer CCD 1. By the transfer pulse 6, it is sequentially sent to the horizontal transfer CCD 3 below the last row. Thereafter, the charges for one horizontal line sent to the horizontal transfer CCD 3 are sequentially sent to the charge detection circuit 4 by the horizontal transfer pulse 5 from the timing generator 101, and the charge for one pixel is converted into a potential signal and output. Is done. When all the charges for one horizontal row are sent to the charge detection circuit 4 and converted into potential signals by the horizontal transfer CCD 3, the charges in the vertical transfer CCD 1 adjacent to the horizontal transfer CCD 3 are sent to the horizontal transfer CCD 3. This operation is repeated to convert the charge signal of the pixels constituting one screen into a potential signal and output it.
[0007]
The pixel potential signal output from the CCD solid-state imaging device 102 is input to the correlated double sampling circuit 103, subjected to noise reduction, and output as a pixel signal quantized by the A / D conversion circuit 104. Thereafter, the data is output to the memory write controller 201 in the memory controller 200.
[0008]
As indicated by arrows in the memory 300 in FIG. 17, the pixel signals output to the memory writing controller 201 are written in order from the memory writing start address. The position where the pixel data is written in the memory 300 is similar to the positional relationship of the pixels of the CCD solid-state imaging device 102. When writing for one horizontal line is completed, the vertical position is changed, the horizontal position is returned to the start position, and the horizontal line is written. Follow the order of writing minutes. This writing process is performed until all image data for one screen is completely developed in the memory 300.
[0009]
As shown in FIG. 19B, the minimum unit block for JPEG encoding has a luminance signal Y of 16 [pixels] × 16 [pixels] and a color difference signal Cr · Cb of M ′ [pixels] × N ′ [ Pixel] block. The signal of the minimum unit block is generated by inputting the Bayer array pixel signal or the complementary color array pixel signal in the memory 300 to the Y / C processing unit 400, and is shown in FIG. 19A necessary for generating the signal. The size (M [pixels] × N [pixels]) of the YC processing read block on the memory 300 differs depending on the block spatial filter used in the Y / C processing method.
[0010]
When all image data for one screen is written in the memory 300 by the memory writing process, the memory reading controller 202 in the memory controller 200 performs YC as shown by a square (block) in the memory 300 in FIG. Read out in units of processing read blocks, output to Y / C processing unit 400 to generate luminance signal Y and color difference signals Cr and Cb, output the signals to JPEG processing unit 500, and perform JPEG processing in JPEG processing unit 500 When the luminance signal Y (16 [pixels] × 16 [pixels]) and the color difference signals Cr and Cb (which differ depending on the format) are accumulated in units of blocks, the JPEG processing unit 500 starts the encoding process and outputs the encoded signal. Output.
[0011]
However, the time required for the encoding process of the JPEG processing unit 500 varies depending on the contents of the luminance signal and the color difference signal for each JPEG processing block. Therefore, the JPEG block read control unit 501 generates a stop signal so as to stop the read process for the memory read controller 202 in accordance with the encoding process load of the JPEG processing unit 500. When the memory read controller 202 receives the stop signal, the memory read controller 202 temporarily stops the reading process from the memory 300. However, the YC process read block of the read process from the memory 300 moves horizontally each time the Y / C process for the read block is completed, and when there are no more blocks to be processed in the horizontal direction, the YC process read block is equal to the vertical size of the YC process read block. Move in the vertical direction and return to the original address in the horizontal direction. In this way, the YC processing read block continues to move as soon as the Y / C processing is completed until the processing of one screen is completed. In this way, JPEG processing is also continuously performed in units of blocks.
[0012]
[Problems to be solved by the invention]
According to the above-described conventional configuration, since the reading process is started after the writing of all image data for one screen in the memory 300 is completed, a JPEG encoded signal is generated from the output signal of the CCD solid-state imaging device 102. There was a problem that it took a long time to process.
[0013]
Here, it is assumed that the writing process and the reading process for the memory 300 are performed in parallel. If it is performed in parallel as shown in the timing of the first “one screen process” in FIG. 13A, a read process is performed on an area where the write process is not completed as shown in FIG. There was a possibility.
[0014]
Further, assuming that the area for image development in the memory 300 is smaller than one screen and that the writing process and the reading process for the memory 300 are performed in parallel, the following points (1) and (2) There is a possibility that the data of the writing process is overwritten in the area where the reading process is not completed.
[0015]
(1) When the CCD solid-state imaging device 102 receives the PD read pulse 7 from the timing generator 101 via the V driver 105, the CCD horizontal transfer pulse 5 and the CCD vertical transfer pulse 6 are always driven. Until the output of the effective pixel data is finished, it cannot be stopped during the output.
[0016]
(2) The JPEG processing unit 500 has a different processing time depending on the information amount of data in the input YC processing read block.
[0017]
In this case, for example, as shown in FIG. 21, if the entire area of the memory 300 corresponds to one screen, the area narrower than that is set as an image development area, and the writing process is performed as an image development area. Are written sequentially from the writing start point, and when the writing process at the writing end point is completed, the processing returns to the writing start point and data for one screen is written sequentially. Also, as shown in FIG. 22, the reading process is performed in units of YC processing reading blocks, and when the reading process of the last reading block in the image development area is completed, the process returns to the reading start block, and data for one screen is read. Are sequentially read for each block. If the processing shown in FIGS. 20 and 21 is performed in parallel as shown in the timing of the first “one-screen processing” in FIG. 13A, the data of the writing process is read out as shown in FIG. There is a possibility that the YC processing read block being processed is overwritten. Therefore, with the conventional configuration, the area for image development in the memory 300 cannot be made smaller than one screen and read / write parallel processing cannot be performed.
[0018]
An object of the present invention is to provide an imaging apparatus capable of shortening the processing time required to generate an encoded signal from an output signal of a CCD solid-state imaging device and enabling high-speed processing.
[0019]
Still another object of the present invention is to provide an imaging apparatus that can reduce the storage area of a memory.
[0020]
[Means for Solving the Problems]
  The imaging device according to claim 1 outputs a timing generator that outputs a vertical transfer pulse and a horizontal transfer pulse, and charges accumulated during an exposure period of a photodiode (photoelectric conversion element) based on the vertical transfer pulse and the horizontal transfer pulse. CCD solid-state imaging device, a memory in which storage areas are arranged in the row and column directions and output data of the CCD solid-state imaging device is written, and data read out from the memory are input, luminance signal and color difference for encoding processing Y / C processing means for generating a signal, encoding means for performing encoding processing on the luminance signal and the color difference signal generated by the Y / C processing means, and outputting an encoded signal, and encoding by the encoding means Read stop signal generation means for outputting a read stop signal according to the processing load, and the output data of the CCD solid-state imaging device are sequentially written to the memory in the row direction. Reads data from the memory in units of blocks having a predetermined column width and outputs data to the Y / C processing means, and stops reading from the memory in response to a read stop signal from the read stop signal generating means The memory controller performs parallel processing of memory writing and reading, and writing of a row included in block unit data to be read from the memory has not been completed. Sometimes stop reading and start reading when writing is completeThen, when writing to the memory, after the last line of the storage area, return to the start line and write, and then the reading of the written block unit data including the line to be written to the memory is completed. If not, the vertical transfer pulse of the timing generator is stopped, and when the reading is completed, the stop of the vertical transfer pulse is released.
[0021]
According to this configuration, by performing parallel processing of memory writing and reading, it is possible to shorten the processing time until the encoded signal is generated from the output data of the CCD solid-state imaging device. In that case, if the writing of the row included in the block unit data to be read from the memory is not completed, the reading is stopped, so that the memory writing process is not completed. It is possible to prevent the reading process from being performed.
[0023]
  Also,The storage area of the memory for storing the output data of the CCD solid-state imaging device can be reduced. In this case, when the reading of the written block unit data including the row to be written next in the memory is not completed, the vertical transfer pulse of the timing generator is stopped, thereby substantially reducing the CCD. It is possible to stop the output of the solid-state imaging device and prevent overwriting to an area where the memory reading process is not completed.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration from generation of a JPEG encoded signal from an output signal of a CCD solid-state imaging device in an imaging apparatus according to an embodiment of the present invention. In FIG. 1, 601 is a timing generator with a built-in vertical transfer pulse stop function, 602 is a CCD solid-state imaging device that outputs data corresponding to a subject as a pixel potential signal, 603 is a double correlation sampling circuit, and 604 is an A / D. Conversion circuit, 700 is a memory controller, 800 is a memory such as a DRAM, 900 is a Y / C signal generation unit (hereinafter referred to as “Y / C processing unit”) that is a Y / C processing unit, and 1000 is a JPEG that is an encoding unit A compression / expansion processing unit (hereinafter referred to as “JPEG processing unit”) 1001 is a JPEG block read control unit which is a read stop signal generating unit.
[0025]
In this embodiment, the memory controller 700 is provided with a stop controller 703 in addition to the memory write controller 701 and the memory read controller 702.
[0026]
The stop control controller 703 receives a stop signal output from the JPEG block read control unit 1001 according to the encoding processing load of the JPEG processing unit 1000, and performs read processing to the memory read controller 702 in response to the stop signal. Stop.
[0027]
The stop control controller 703 also executes an execution address where the memory write controller 701 performs a write process and an execution area of a YC process read block (M [pixel] × N [pixel]) where the memory read controller 702 performs a read process. And instructing the memory write controller 701 the execution address for performing the write process and the memory read controller 702 for the execution area for performing the read process. Regardless of the presence / absence of a stop signal from the JPEG block read control unit 1001, the memory read controller 702 is informed until the memory write processing for the read block minimum row area including the YC process read block to be read is completed. In response to this, a stop signal is issued to stop the memory reading process. Here, in the memory 800 as shown in FIG. 2, an area having a horizontal effective pixel size l of an image generated by the CCD solid-state imaging device 602 in the vertical direction is called a read block minimum row area. To. ... (1), (2)... Indicate YC processing read blocks.
[0028]
Further, when the write process is being performed on the memory 800, the stop controller 703, when the read process of the written YC process read block including the next row to be written is not completed, A signal for stopping the vertical transfer pulse is issued to the timing generator 601 until the reading process is completed.
[0029]
The timing generator 601 is provided with a terminal for inputting a vertical transfer pulse stop signal from the stop control controller 703, and can temporarily stop the vertical transfer pulse in response to a signal from the stop control controller 703. Thus, the vertical transfer of charges of the CCD solid-state imaging device 602 can be stopped, and the transfer to the horizontal transfer CCD is temporarily stopped. When the output of the potential signal for one horizontal line immediately before the pause is finished, the vertical transfer pulse is stopped, but the horizontal transfer pulse continues to be driven, so that a signal (invalid from the signal output terminal of the CCD solid-state imaging device 602). Data) continues to be output. However, since the output of invalid data continues when the output of the potential signal for one horizontal line immediately before the pause is finished, the output of the potential signal of the effective pixels constituting one screen is temporarily stopped in units of one line. Will be. With such a function, the output of the potential signal of the pixels constituting one screen can be stopped in units of rows in the middle of the output of one screen.
[0030]
In the imaging apparatus according to the present embodiment, an operation from generation of a JPEG encoded signal from an output signal of the CCD solid-state imaging device 602 will be described.
[0031]
First, as a first example, the size of the area in the memory 800 used for writing the data output from the CCD solid-state image sensor 602 is the effective image size for one screen (the vertical direction is that of the CCD solid-state image sensor 602). It is assumed that the number of effective vertical pixels and the horizontal direction can store the number of effective horizontal pixels of the CCD solid-state imaging device 602), and the operation in the case of performing the encoding process in the read / write parallel processing will be described. In the case of this first example, control and configuration for temporarily stopping the vertical transfer pulse of the timing generator 601 by the stop controller 703 are unnecessary and are not provided.
[0032]
As in the conventional example, the horizontal transfer pulse output from the timing generator 601 is directly input to the CCD solid-state image sensor 602, but the vertical transfer pulse is input to the CCD solid-state image sensor 602 via the V driver 605. When the timing generator 601 receives an “input command signal” which is an external input signal, it outputs a vertical transfer pulse and a PD read pulse to the V driver 605, and the V driver 605 combines the vertical transfer pulse and the PD read pulse. And output to the CCD solid-state imaging device 602.
[0033]
When the CCD solid-state image sensor 602 receives a PD read pulse (superimposed on the vertical transfer pulse) from the V driver 605, the CCD solid-state image sensor 602 moves the pixel charge from each photodiode to the vertical transfer CCD. The vertical transfer CCD / horizontal transfer CCD is driven in the same manner as the conventional example by vertical transfer pulses / horizontal transfer pulses, and converts the charge signals of the pixels constituting one screen into potential signals and outputs them.
[0034]
The pixel potential signal output from the CCD solid-state imaging device 602 is input to the correlated double sampling circuit 603, subjected to noise reduction, and output as a pixel signal quantized by the A / D conversion circuit 604. Thereafter, the data is output to the memory write controller 701 in the memory controller 700.
[0035]
As shown in FIG. 3, the pixel signals output to the memory writing controller 701 are sequentially written to the addresses of the memory 800 designated by the stop control controller 703. At the time of the first memory write processing as shown in FIG. 3, the stop control controller 703 sends a stop signal to the memory read controller 702 until the memory write processing for the first read block minimum row area is completed. The memory read processing is stopped.
[0036]
Memory reading processing for JPEG processing reads a YC processing reading block (M [pixel] × N [pixel]) on the memory 800 necessary for signal generation of the minimum unit block, and reads the reading position in the horizontal direction in units of the block. When the horizontal processing is completed, the vertical position is changed and the processing is advanced again in the horizontal direction. This is repeated to generate an encoded signal.
[0037]
Then, as shown in FIG. 4, when the first read block minimum row area in the memory 800 is filled with pixel data by the memory write process, the memory read controller 702 in the memory controller 700 reads the YC process read block unit. Is output to the Y / C processing unit 900 to generate a luminance signal and a color difference signal, output the signal to the JPEG processing unit 1000, and the luminance signal in units of JPEG processing blocks as shown in FIG. When Y (16 [pixel] × 16 [pixel]) and the color difference signal Cr · Cb (M ′ [pixel] × N ′ [pixel]) are accumulated, the JPEG processing unit 1000 starts the encoding process, Outputs the digitized signal.
[0038]
However, the time required for the encoding process of the JPEG processing unit 1000 varies depending on the contents of the luminance signal and the color difference signal in units of JPEG processing blocks. Therefore, according to the encoding processing load of the JPEG processing unit 1000, the JPEG block read control unit 1001 generates a stop signal to stop the read processing to the memory read controller 702 via the stop control controller 703. When the memory read controller 702 receives the stop signal, the read process from the memory 800 is temporarily stopped.
[0039]
Note that the JPEG block read control unit 1001 monitors the status of whether or not unprocessed data remains in the input data storage unit of the JPEG processing unit 1000, as shown in FIG. When the load on the JPEG encoding process is heavy, that is, when there is a large amount of picture information corresponding to the process (there is a lot of small changes in the YC of the picture), the output code quantity increases and more time is required for the coding process. Become. Therefore, if the processing is not completed within a predetermined period, unprocessed data remains in the input data storage unit. In this case, the JPEG block read control unit 1001 generates a stop signal.
[0040]
When the read process and the write process are performed in parallel as shown in FIG. 4, the last YC process read block in the read block minimum row area is read by the read process as shown in FIG. 5, and the Y / C process ends. At this point, if the memory write processing for the next read block minimum row area has not been completed, it is likely to read the YC process read block for which the write processing has not been completed. However, in the present embodiment, when the memory write process is in the middle of the next read block minimum row area write process, the stop control controller 703 issues a stop signal to the memory read controller 702 to read The processing stops moving to the next read block minimum row area. Then, as shown in FIG. 6, when the writing process of the next read block minimum row area is completed, the processing target of the read process is shifted to the next read block minimum row area and the process is continued. Thereafter, processing for one screen is performed in the same manner.
[0041]
Therefore, according to the first example described above, the processing time can be shortened and high-speed processing can be performed by performing the writing process to the memory 800 and the reading process in parallel. Further, unlike the case of FIG. 20, the read process is not performed on the area where the write process is not completed. In particular, the effect of shortening the processing time during continuous shooting is increased, and high-speed processing can be realized compared to conventional processing.
[0042]
Next, as a second example, the size of an area in the memory 800 used for writing data output from the CCD solid-state imaging device 602 (an area for image development) is the minimum of the read block as shown in FIG. When two rows are used (the vertical direction is twice the vertical size of the YC processing read block size, the horizontal direction is the number of effective horizontal pixels of the CCD solid-state image sensor 602), and the encoding processing is performed by read / write parallel processing. The operation of will be described. Here, it is assumed that the number of effective pixels in the vertical direction of the CCD solid-state imaging device 602 is much larger than the vertical size of the YC processing readout block size. In the following, the case of continuous shooting will be described, but the processing for the first screen (first image) is the same when only one image or one image is taken at a certain time.
[0043]
As in the case of FIG. 21, the position at which the pixel data is written in the memory 800 is changed in the vertical position after the writing for one horizontal line is completed, similarly to the positional relationship of the pixels of the CCD solid-state imaging device 602, and again for one horizontal line. Follow the order of writing. When the memory writing process is completed for the area used for image processing in the memory 800, the writing operation is returned to the address where the writing is started.
[0044]
Similarly to the case of FIG. 22, the read process is also performed horizontally each time the Y / C process for the read block is completed (when there is no data in the process data storage unit in the Y / C processing unit 900 of FIG. 14). When the block to be processed disappears in the horizontal direction, the block moves in the vertical direction by the vertical size of the YC processing read block, and the horizontal direction returns to the original address. When the processing is completed for two read block minimum row areas, the processing returns to the position where the read processing is started again, and the read processing is resumed.
[0045]
As described above, the order in which the quantized signal output from the CCD solid-state imaging device 602 is written to the memory 800 is written in units of horizontal lines as shown in FIG. 7, and at the first point of processing of the first screen. Until the write processing for the first read block minimum row area is completed, the stop control controller 703 issues a stop signal to the memory read controller 702 to stop the read processing.
[0046]
When the write processing for the first read block minimum row area is completed, the stop signal from the stop control controller 703 to the memory read controller 702 is canceled as shown in FIG. 8, and the read processing from the memory 800 is performed as described above. The reading process and the writing process are performed in parallel.
[0047]
If this parallel processing is continued, as shown in FIG. 9, the last YC processing read block in the read block minimum row area is read by read processing, and when the Y / C processing is completed, the next read block minimum row is read. When the memory writing process for the area has not been completed, the YC process reading block in which the writing process has not been completed will be read. However, as in the first example, when the memory write process is in the process of writing the next read block minimum row area, the stop control controller 703 issues a stop signal to the memory read controller 702. The reading process stops moving to the next read block minimum row area. Then, as shown in FIG. 10, when the writing process of the next read block minimum row area is completed, the processing target of the read process is shifted to the next read block minimum row area and the process is continued. Thereafter, processing for one screen is performed in the same manner.
[0048]
When the image development area in the memory 800 is smaller than the area necessary for data development for one screen as in the second example, JPEG processing depends on the information amount of the input block data. Since the processing load (time) is different, depending on the data, there is a possibility that the data of the writing process is likely to be overwritten on the YC processing reading block that is performing the reading process. In such a case, for example, as shown in FIG. 11, the stop control controller 703 performs vertical transfer to the timing generator 601 at the time when the write process is being performed on the line before the next read block reaches the minimum row area. A pulse stop signal is issued, the vertical CCD transfer of the CCD solid-state imaging device 602 is stopped, and control is performed so that the data in the read block minimum row area in which the read process is performed with the write process data is not overwritten (overwrite prevention function). .
[0049]
The write process is stopped until the process of the minimum row area of the read block that is performing the read process is completed and the process moves to the next row block. When the process is shifted, the vertical transfer pulse stop signal of the stop controller 703 is released. And processing is resumed. The stop control controller 703 issues a write stop signal to the memory write controller 701 and prohibits writing while issuing a vertical transfer pulse stop signal to the timing generator 601. For example, at the timing shown in FIG. 12, writing of all data for 1H output from the CCD solid-state imaging device 602 is prohibited during the horizontal effective period in which the vertical transfer is stopped.
[0050]
As described above, Y / C processing or JPEG processing for one screen can be realized if there is at least two minimum read block row areas without requiring the memory 800 to develop all image data for one screen. Therefore, the memory consumption area can be drastically reduced.
[0051]
The above processing is the same for both continuous shooting and single shooting. In the case of continuous shooting, when the writing of one screen is completed, the stop control controller 703 issues a write stop signal to the memory writing controller 701, and the CCD output signal is output until the minimum row area of the read block is completed for both the writing process and the reading process. The read block minimum row area where both the writing process and the reading process are completed is completed, and the process is paused until the data output signal of the next screen is output. Then, when the output of the next screen data is started from the CCD solid-state imaging device 602, the writing is immediately resumed with respect to the read block minimum row area where both the writing process and the reading are completed. That is, the next screen writing process is performed without waiting for the previous screen encoding process to be completed. The timing of the writing process and the reading process in the case of continuous shooting is as shown in FIG.
[0052]
On the other hand, when continuous shooting is performed in the first example, it is shown at the timing of FIG. 13A, and after the reading process of the screen being processed is completed, the writing process of the next screen is performed. Is called. This is because, in the case of the first example, there is no overwriting prevention function in the second example, and an area for image development is required in the memory 800 for one screen.
[0053]
According to the second example, as compared with the first example, the storage area of the memory 800 used for the image development area can be significantly reduced, and the continuous shooting can be performed at a higher speed.
[0054]
【The invention's effect】
As described above, according to the present invention, the parallel processing of memory writing and reading is performed by the memory controller, thereby shortening the processing time until the encoded signal is generated from the output data of the CCD solid-state imaging device, and high speed. Processing is possible. In that case, if the writing of the row included in the block unit data to be read from the memory is not completed, the reading is stopped, so that the memory writing process is not completed. It is possible to prevent the reading process from being performed.
[0055]
Furthermore, the storage area of the memory can be reduced as an area corresponding to output data of less than one screen of the CCD solid-state imaging device. In that case, when writing to the memory by the memory controller, after the last row of the storage area, writing is performed after returning to the start row, and then including the row to be written to the memory. When the data reading is not completed, the vertical transfer pulse of the timing generator is stopped to substantially stop the output of the CCD solid-state imaging device and overwrite the area where the memory reading process has not been completed. Can be prevented.
[0056]
In particular, during continuous shooting, the writing process and reading process of the data of the CCD solid-state imaging device data can be performed in parallel, thereby realizing a higher-speed process than the conventional process, and with a significantly smaller memory area. The high pixel image encoding process can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main configuration of an imaging apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a read block minimum row area according to the embodiment of the present invention.
FIG. 3 is a diagram showing an operation of a first example in the embodiment of the present invention.
FIG. 4 is a diagram showing an operation of the first example in the embodiment of the present invention.
FIG. 5 is a diagram showing an operation of the first example in the embodiment of the present invention.
FIG. 6 is a diagram showing an operation of the first example in the embodiment of the present invention.
FIG. 7 is a diagram showing an operation of a second example in the embodiment of the present invention.
FIG. 8 is a diagram showing an operation of a second example in the embodiment of the present invention.
FIG. 9 is a diagram showing the operation of the second example in the embodiment of the present invention.
FIG. 10 is a diagram showing an operation of the second example in the embodiment of the present invention.
FIG. 11 is a diagram showing the operation of the second example in the embodiment of the present invention.
FIG. 12 is a timing chart showing the operation of the second example in the embodiment of the present invention.
FIG. 13 is a timing chart of operations during continuous shooting in the first example and the second example in the embodiment of the present invention.
FIG. 14 is a block diagram showing an internal configuration of a part of the imaging apparatus according to the embodiment of the present invention.
FIG. 15 is a block diagram illustrating a main configuration of a conventional imaging apparatus.
FIG. 16 is a diagram showing a configuration of a CCD solid-state imaging device.
FIG. 17 is a block diagram showing the operation of a conventional imaging apparatus.
FIG. 18 is a block diagram showing the operation of a conventional imaging apparatus.
FIG. 19 is a diagram showing a minimum unit block for read processing and a minimum unit block for JPEG encoding.
FIG. 20 is a diagram for explaining a conventional problem.
FIG. 21 is a diagram for explaining a conventional problem.
FIG. 22 is a diagram for explaining a conventional problem.
FIG. 23 is a diagram for explaining a conventional problem.
[Explanation of symbols]
601 Timing generator
602 CCD solid-state imaging device
700 Memory controller
800 memory
900 Y / C signal generator (Y / C processor)
1000 JPEG compression / decompression processing unit (JPEG processing unit)
1001 JPEG block read control unit

Claims (1)

A timing generator that outputs vertical and horizontal transfer pulses;
A CCD solid-state imaging device that outputs signal charges accumulated in a photoelectric conversion element during an exposure period based on the vertical transfer pulse and the horizontal transfer pulse;
A memory in which storage areas are arranged in a row and column direction and output data of the CCD solid-state imaging device is written;
Y / C processing means for inputting data read from the memory and generating a luminance signal and a color difference signal for encoding processing;
Encoding means for performing an encoding process on the luminance signal and the color difference signal generated by the Y / C processing means and outputting an encoded signal;
A read stop signal generating means for outputting a read stop signal in accordance with the load of the encoding process of the encoding means;
The output data of the CCD solid-state imaging device is sequentially written to the memory in the row direction, the data is read out from the memory in units of blocks having a predetermined column width across a plurality of predetermined rows, and is output to the Y / C processing means. An imaging device comprising: a memory controller that stops reading from the memory in response to a read stop signal from the read stop signal generating means;
The memory controller performs parallel processing of writing to and reading from the memory. When writing of a row included in block unit data to be read from the memory is not completed, reading is stopped, and the writing is stopped. When reading is completed, when writing to the memory, writing is performed after returning to the starting row after the last row of the storage area, and then including the row to be written to the memory. An image pickup apparatus , wherein when the reading of data in block units is not completed, the vertical transfer pulse of the timing generator is stopped, and when the reading is completed, the stop of the vertical transfer pulse is released .

Images